2 * Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_crtc_helper.h>
14 #include <drm/drm_fb_cma_helper.h>
15 #include <drm/drm_gem_cma_helper.h>
16 #include <drm/drm_plane_helper.h>
19 #include "sun8i_vi_layer.h"
20 #include "sun8i_mixer.h"
21 #include "sun8i_vi_scaler.h"
23 static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
24 int overlay, bool enable, unsigned int zpos,
25 unsigned int old_zpos)
29 DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
30 enable ? "En" : "Dis", channel, overlay);
33 val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
37 regmap_update_bits(mixer->engine.regs,
38 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
39 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
41 if (!enable || zpos != old_zpos) {
42 regmap_update_bits(mixer->engine.regs,
43 SUN8I_MIXER_BLEND_PIPE_CTL,
44 SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
47 regmap_update_bits(mixer->engine.regs,
48 SUN8I_MIXER_BLEND_ROUTE,
49 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
54 val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
56 regmap_update_bits(mixer->engine.regs,
57 SUN8I_MIXER_BLEND_PIPE_CTL, val, val);
59 val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
61 regmap_update_bits(mixer->engine.regs,
62 SUN8I_MIXER_BLEND_ROUTE,
63 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
68 static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
69 int overlay, struct drm_plane *plane,
72 struct drm_plane_state *state = plane->state;
73 const struct drm_format_info *format = state->fb->format;
74 u32 src_w, src_h, dst_w, dst_h;
79 DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
82 src_w = drm_rect_width(&state->src) >> 16;
83 src_h = drm_rect_height(&state->src) >> 16;
84 dst_w = drm_rect_width(&state->dst);
85 dst_h = drm_rect_height(&state->dst);
87 hphase = state->src.x1 & 0xffff;
88 vphase = state->src.y1 & 0xffff;
90 /* make coordinates dividable by subsampling factor */
91 if (format->hsub > 1) {
94 mask = format->hsub - 1;
95 remainder = (state->src.x1 >> 16) & mask;
96 src_w = (src_w + remainder) & ~mask;
97 hphase += remainder << 16;
100 if (format->vsub > 1) {
103 mask = format->vsub - 1;
104 remainder = (state->src.y1 >> 16) & mask;
105 src_h = (src_h + remainder) & ~mask;
106 vphase += remainder << 16;
109 insize = SUN8I_MIXER_SIZE(src_w, src_h);
110 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
112 /* Set height and width */
113 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
114 (state->src.x1 >> 16) & ~(format->hsub - 1),
115 (state->src.y1 >> 16) & ~(format->vsub - 1));
116 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
117 regmap_write(mixer->engine.regs,
118 SUN8I_MIXER_CHAN_VI_LAYER_SIZE(channel, overlay),
120 regmap_write(mixer->engine.regs,
121 SUN8I_MIXER_CHAN_VI_OVL_SIZE(channel),
125 * Scaler must be enabled for subsampled formats, so it scales
126 * chroma to same size as luma.
128 subsampled = format->hsub > 1 || format->vsub > 1;
130 if (insize != outsize || subsampled || hphase || vphase) {
133 DRM_DEBUG_DRIVER("HW scaling is enabled\n");
135 hscale = state->src_w / state->crtc_w;
136 vscale = state->src_h / state->crtc_h;
138 sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,
139 dst_h, hscale, vscale, hphase, vphase,
141 sun8i_vi_scaler_enable(mixer, channel, true);
143 DRM_DEBUG_DRIVER("HW scaling is not needed\n");
144 sun8i_vi_scaler_enable(mixer, channel, false);
147 /* Set base coordinates */
148 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
149 state->dst.x1, state->dst.y1);
150 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
151 regmap_write(mixer->engine.regs,
152 SUN8I_MIXER_BLEND_ATTR_COORD(zpos),
153 SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
154 regmap_write(mixer->engine.regs,
155 SUN8I_MIXER_BLEND_ATTR_INSIZE(zpos),
161 static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
162 int overlay, struct drm_plane *plane)
164 struct drm_plane_state *state = plane->state;
165 const struct de2_fmt_info *fmt_info;
168 fmt_info = sun8i_mixer_format_info(state->fb->format->format);
170 DRM_DEBUG_DRIVER("Invalid format\n");
174 val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
175 regmap_update_bits(mixer->engine.regs,
176 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
177 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
179 if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
180 sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
181 sun8i_csc_enable_ccsc(mixer, channel, true);
183 sun8i_csc_enable_ccsc(mixer, channel, false);
187 val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
191 regmap_update_bits(mixer->engine.regs,
192 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
193 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
198 static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
199 int overlay, struct drm_plane *plane)
201 struct drm_plane_state *state = plane->state;
202 struct drm_framebuffer *fb = state->fb;
203 const struct drm_format_info *format = fb->format;
204 struct drm_gem_cma_object *gem;
205 u32 dx, dy, src_x, src_y;
209 /* Adjust x and y to be dividable by subsampling factor */
210 src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
211 src_y = (state->src.y1 >> 16) & ~(format->vsub - 1);
213 for (i = 0; i < format->num_planes; i++) {
214 /* Get the physical address of the buffer in memory */
215 gem = drm_fb_cma_get_gem_obj(fb, i);
217 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
219 /* Compute the start of the displayed memory */
220 paddr = gem->paddr + fb->offsets[i];
230 /* Fixup framebuffer address for src coordinates */
231 paddr += dx * format->cpp[i];
232 paddr += dy * fb->pitches[i];
234 /* Set the line width */
235 DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
236 i + 1, fb->pitches[i]);
237 regmap_write(mixer->engine.regs,
238 SUN8I_MIXER_CHAN_VI_LAYER_PITCH(channel,
242 DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
245 regmap_write(mixer->engine.regs,
246 SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(channel,
248 lower_32_bits(paddr));
254 static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
255 struct drm_plane_state *state)
257 struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
258 struct drm_crtc *crtc = state->crtc;
259 struct drm_crtc_state *crtc_state;
260 int min_scale, max_scale;
265 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
266 if (WARN_ON(!crtc_state))
269 min_scale = DRM_PLANE_HELPER_NO_SCALING;
270 max_scale = DRM_PLANE_HELPER_NO_SCALING;
272 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
273 min_scale = SUN8I_VI_SCALER_SCALE_MIN;
274 max_scale = SUN8I_VI_SCALER_SCALE_MAX;
277 return drm_atomic_helper_check_plane_state(state, crtc_state,
278 min_scale, max_scale,
282 static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
283 struct drm_plane_state *old_state)
285 struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
286 unsigned int old_zpos = old_state->normalized_zpos;
287 struct sun8i_mixer *mixer = layer->mixer;
289 sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
293 static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
294 struct drm_plane_state *old_state)
296 struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
297 unsigned int zpos = plane->state->normalized_zpos;
298 unsigned int old_zpos = old_state->normalized_zpos;
299 struct sun8i_mixer *mixer = layer->mixer;
301 if (!plane->state->visible) {
302 sun8i_vi_layer_enable(mixer, layer->channel,
303 layer->overlay, false, 0, old_zpos);
307 sun8i_vi_layer_update_coord(mixer, layer->channel,
308 layer->overlay, plane, zpos);
309 sun8i_vi_layer_update_formats(mixer, layer->channel,
310 layer->overlay, plane);
311 sun8i_vi_layer_update_buffer(mixer, layer->channel,
312 layer->overlay, plane);
313 sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
314 true, zpos, old_zpos);
317 static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
318 .atomic_check = sun8i_vi_layer_atomic_check,
319 .atomic_disable = sun8i_vi_layer_atomic_disable,
320 .atomic_update = sun8i_vi_layer_atomic_update,
323 static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
324 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
325 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
326 .destroy = drm_plane_cleanup,
327 .disable_plane = drm_atomic_helper_disable_plane,
328 .reset = drm_atomic_helper_plane_reset,
329 .update_plane = drm_atomic_helper_update_plane,
333 * While DE2 VI layer supports same RGB formats as UI layer, alpha
334 * channel is ignored. This structure lists all unique variants
335 * where alpha channel is replaced with "don't care" (X) channel.
337 static const u32 sun8i_vi_layer_formats[] = {
371 struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
372 struct sun8i_mixer *mixer,
375 struct sun8i_vi_layer *layer;
376 unsigned int plane_cnt;
379 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
381 return ERR_PTR(-ENOMEM);
383 /* possible crtcs are set later */
384 ret = drm_universal_plane_init(drm, &layer->plane, 0,
385 &sun8i_vi_layer_funcs,
386 sun8i_vi_layer_formats,
387 ARRAY_SIZE(sun8i_vi_layer_formats),
388 NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
390 dev_err(drm->dev, "Couldn't initialize layer\n");
394 plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
396 ret = drm_plane_create_zpos_property(&layer->plane, index,
399 dev_err(drm->dev, "Couldn't add zpos property\n");
403 drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
404 layer->mixer = mixer;
405 layer->channel = index;