drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
   4  */
   5
   6 #include <linux/delay.h>
   7 #include <linux/of_address.h>
   8
   9 #include "sun8i_dw_hdmi.h"
  10
  11 /*
  12  * Address can be actually any value. Here is set to same value as
  13  * it is set in BSP driver.
  14  */
  15 #define I2C_ADDR        0x69
  16
  17 static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
  18                                       struct sun8i_hdmi_phy *phy,
  19                                       unsigned int clk_rate)
  20 {
  21         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
  22                            SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
  23                            SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
  24
  25         /* power down */
  26         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
  27         dw_hdmi_phy_gen2_pddq(hdmi, 1);
  28
  29         dw_hdmi_phy_reset(hdmi);
  30
  31         dw_hdmi_phy_gen2_pddq(hdmi, 0);
  32
  33         dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
  34
  35         /*
  36          * Values are taken from BSP HDMI driver. Although AW didn't
  37          * release any documentation, explanation of this values can
  38          * be found in i.MX 6Dual/6Quad Reference Manual.
  39          */
  40         if (clk_rate <= 27000000) {
  41                 dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
  42                 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
  43                 dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
  44                 dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
  45                 dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
  46                 dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
  47         } else if (clk_rate <= 74250000) {
  48                 dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
  49                 dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
  50                 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
  51                 dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
  52                 dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
  53                 dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
  54         } else if (clk_rate <= 148500000) {
  55                 dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
  56                 dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
  57                 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
  58                 dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
  59                 dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
  60                 dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
  61         } else {
  62                 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
  63                 dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
  64                 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
  65                 dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
  66                 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
  67                 dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
  68         }
  69
  70         dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
  71         dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
  72         dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
  73
  74         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
  75
  76         return 0;
  77 }
  78
  79 static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
  80                                     struct sun8i_hdmi_phy *phy,
  81                                     unsigned int clk_rate)
  82 {
  83         u32 pll_cfg1_init;
  84         u32 pll_cfg2_init;
  85         u32 ana_cfg1_end;
  86         u32 ana_cfg2_init;
  87         u32 ana_cfg3_init;
  88         u32 b_offset = 0;
  89         u32 val;
  90
  91         /* bandwidth / frequency independent settings */
  92
  93         pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN |
  94                         SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN |
  95                         SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) |
  96                         SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) |
  97                         SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN |
  98                         SUN8I_HDMI_PHY_PLL_CFG1_CS |
  99                         SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) |
 100                         SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) |
 101                         SUN8I_HDMI_PHY_PLL_CFG1_BWS;
 102
 103         pll_cfg2_init = SUN8I_HDMI_PHY_PLL_CFG2_SV_H |
 104                         SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN |
 105                         SUN8I_HDMI_PHY_PLL_CFG2_SDIV2;
 106
 107         ana_cfg1_end = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) |
 108                        SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT |
 109                        SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT |
 110                        SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT |
 111                        SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT |
 112                        SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL |
 113                        SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG |
 114                        SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS |
 115                        SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN |
 116                        SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK |
 117                        SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL |
 118                        SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK |
 119                        SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
 120                        SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
 121                        SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
 122                        SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 |
 123                        SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
 124                        SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
 125                        SUN8I_HDMI_PHY_ANA_CFG1_CKEN |
 126                        SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
 127                        SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
 128                        SUN8I_HDMI_PHY_ANA_CFG1_ENBI;
 129
 130         ana_cfg2_init = SUN8I_HDMI_PHY_ANA_CFG2_M_EN |
 131                         SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK |
 132                         SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN |
 133                         SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) |
 134                         SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1);
 135
 136         ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) |
 137                         SUN8I_HDMI_PHY_ANA_CFG3_SDAEN |
 138                         SUN8I_HDMI_PHY_ANA_CFG3_SCLEN;
 139
 140         /* bandwidth / frequency dependent settings */
 141         if (clk_rate <= 27000000) {
 142                 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
 143                                  SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
 144                 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
 145                                  SUN8I_HDMI_PHY_PLL_CFG2_S(4);
 146                 ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
 147                 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
 148                                  SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
 149                 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) |
 150                                  SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5);
 151         } else if (clk_rate <= 74250000) {
 152                 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
 153                                  SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
 154                 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
 155                                  SUN8I_HDMI_PHY_PLL_CFG2_S(5);
 156                 ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
 157                 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
 158                                  SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
 159                 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) |
 160                                  SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7);
 161         } else if (clk_rate <= 148500000) {
 162                 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
 163                                  SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
 164                 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
 165                                  SUN8I_HDMI_PHY_PLL_CFG2_S(6);
 166                 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
 167                                  SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
 168                                  SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2);
 169                 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) |
 170                                  SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9);
 171         } else {
 172                 b_offset = 2;
 173                 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63);
 174                 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) |
 175                                  SUN8I_HDMI_PHY_PLL_CFG2_S(7);
 176                 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
 177                                  SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
 178                                  SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
 179                 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
 180                                  SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
 181                                  SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
 182         }
 183
 184         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 185                            SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
 186
 187         /*
 188          * NOTE: We have to be careful not to overwrite PHY parent
 189          * clock selection bit and clock divider.
 190          */
 191         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
 192                            (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
 193                            pll_cfg1_init);
 194         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
 195                            (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
 196                            pll_cfg2_init);
 197         usleep_range(10000, 15000);
 198         regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG,
 199                      SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2);
 200         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
 201                            SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,
 202                            SUN8I_HDMI_PHY_PLL_CFG1_PLLEN);
 203         msleep(100);
 204
 205         /* get B value */
 206         regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
 207         val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >>
 208                 SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT;
 209         val = min(val + b_offset, (u32)0x3f);
 210
 211         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
 212                            SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
 213                            SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,
 214                            SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
 215                            SUN8I_HDMI_PHY_PLL_CFG1_REG_OD);
 216         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
 217                            SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,
 218                            val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT);
 219         msleep(100);
 220         regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end);
 221         regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init);
 222         regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init);
 223
 224         return 0;
 225 }
 226
 227 static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
 228                                  struct drm_display_mode *mode)
 229 {
 230         struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
 231         u32 val = 0;
 232
 233         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 234                 val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
 235
 236         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 237                 val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
 238
 239         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
 240                            SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
 241
 242         if (phy->variant->has_phy_clk)
 243                 clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
 244
 245         return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
 246 };
 247
 248 static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi,
 249                                         struct sun8i_hdmi_phy *phy)
 250 {
 251         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 252         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 253
 254         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
 255                            SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
 256 }
 257
 258 static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi,
 259                                       struct sun8i_hdmi_phy *phy)
 260 {
 261         regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 262                      SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
 263                      SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
 264                      SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
 265         regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
 266 }
 267
 268 static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
 269 {
 270         struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
 271
 272         phy->variant->phy_disable(hdmi, phy);
 273 }
 274
 275 static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
 276         .init = &sun8i_hdmi_phy_config,
 277         .disable = &sun8i_hdmi_phy_disable,
 278         .read_hpd = &dw_hdmi_phy_read_hpd,
 279         .update_hpd = &dw_hdmi_phy_update_hpd,
 280         .setup_hpd = &dw_hdmi_phy_setup_hpd,
 281 };
 282
 283 static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
 284 {
 285         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
 286                            SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
 287                            SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
 288
 289         /*
 290          * Set PHY I2C address. It must match to the address set by
 291          * dw_hdmi_phy_set_slave_addr().
 292          */
 293         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
 294                            SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
 295                            SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
 296 }
 297
 298 static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
 299 {
 300         unsigned int val;
 301
 302         regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);
 303         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 304                            SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
 305                            SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
 306         udelay(5);
 307         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 308                            SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,
 309                            SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN);
 310         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 311                            SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,
 312                            SUN8I_HDMI_PHY_ANA_CFG1_ENVBS);
 313         usleep_range(10, 20);
 314         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 315                            SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,
 316                            SUN8I_HDMI_PHY_ANA_CFG1_LDOEN);
 317         udelay(5);
 318         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 319                            SUN8I_HDMI_PHY_ANA_CFG1_CKEN,
 320                            SUN8I_HDMI_PHY_ANA_CFG1_CKEN);
 321         usleep_range(40, 100);
 322         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 323                            SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,
 324                            SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL);
 325         usleep_range(100, 200);
 326         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 327                            SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,
 328                            SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG);
 329         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 330                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
 331                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
 332                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,
 333                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
 334                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
 335                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2);
 336
 337         /* wait for calibration to finish */
 338         regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val,
 339                                  (val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D),
 340                                  100, 2000);
 341
 342         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 343                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,
 344                            SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK);
 345         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
 346                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
 347                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
 348                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
 349                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,
 350                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
 351                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
 352                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
 353                            SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK);
 354
 355         /* enable DDC communication */
 356         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG,
 357                            SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
 358                            SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,
 359                            SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
 360                            SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
 361
 362         /* reset PHY PLL clock parent */
 363         regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
 364                            SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0);
 365
 366         /* set HW control of CEC pins */
 367         regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
 368
 369         /* read calibration data */
 370         regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
 371         phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2;
 372 }
 373
 374 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
 375 {
 376         /* enable read access to HDMI controller */
 377         regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
 378                      SUN8I_HDMI_PHY_READ_EN_MAGIC);
 379
 380         /* unscramble register offsets */
 381         regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
 382                      SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
 383
 384         phy->variant->phy_init(phy);
 385 }
 386
 387 const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void)
 388 {
 389         return &sun8i_hdmi_phy_ops;
 390 }
 391
 392 static struct regmap_config sun8i_hdmi_phy_regmap_config = {
 393         .reg_bits       = 32,
 394         .val_bits       = 32,
 395         .reg_stride     = 4,
 396         .max_register   = SUN8I_HDMI_PHY_CEC_REG,
 397         .name           = "phy"
 398 };
 399
 400 static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
 401         .has_phy_clk = true,
 402         .phy_init = &sun8i_hdmi_phy_init_h3,
 403         .phy_disable = &sun8i_hdmi_phy_disable_h3,
 404         .phy_config = &sun8i_hdmi_phy_config_h3,
 405 };
 406
 407 static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
 408         .phy_init = &sun8i_hdmi_phy_init_a83t,
 409         .phy_disable = &sun8i_hdmi_phy_disable_a83t,
 410         .phy_config = &sun8i_hdmi_phy_config_a83t,
 411 };
 412
 413 static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
 414         .has_phy_clk = true,
 415         .phy_init = &sun8i_hdmi_phy_init_h3,
 416         .phy_disable = &sun8i_hdmi_phy_disable_h3,
 417         .phy_config = &sun8i_hdmi_phy_config_h3,
 418 };
 419
 420 static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
 421         {
 422                 .compatible = "allwinner,sun50i-a64-hdmi-phy",
 423                 .data = &sun50i_a64_hdmi_phy,
 424         },
 425         {
 426                 .compatible = "allwinner,sun8i-a83t-hdmi-phy",
 427                 .data = &sun8i_a83t_hdmi_phy,
 428         },
 429         {
 430                 .compatible = "allwinner,sun8i-h3-hdmi-phy",
 431                 .data = &sun8i_h3_hdmi_phy,
 432         },
 433         { /* sentinel */ }
 434 };
 435
 436 int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
 437 {
 438         const struct of_device_id *match;
 439         struct device *dev = hdmi->dev;
 440         struct sun8i_hdmi_phy *phy;
 441         struct resource res;
 442         void __iomem *regs;
 443         int ret;
 444
 445         match = of_match_node(sun8i_hdmi_phy_of_table, node);
 446         if (!match) {
 447                 dev_err(dev, "Incompatible HDMI PHY\n");
 448                 return -EINVAL;
 449         }
 450
 451         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 452         if (!phy)
 453                 return -ENOMEM;
 454
 455         phy->variant = (struct sun8i_hdmi_phy_variant *)match->data;
 456
 457         ret = of_address_to_resource(node, 0, &res);
 458         if (ret) {
 459                 dev_err(dev, "phy: Couldn't get our resources\n");
 460                 return ret;
 461         }
 462
 463         regs = devm_ioremap_resource(dev, &res);
 464         if (IS_ERR(regs)) {
 465                 dev_err(dev, "Couldn't map the HDMI PHY registers\n");
 466                 return PTR_ERR(regs);
 467         }
 468
 469         phy->regs = devm_regmap_init_mmio(dev, regs,
 470                                           &sun8i_hdmi_phy_regmap_config);
 471         if (IS_ERR(phy->regs)) {
 472                 dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
 473                 return PTR_ERR(phy->regs);
 474         }
 475
 476         phy->clk_bus = of_clk_get_by_name(node, "bus");
 477         if (IS_ERR(phy->clk_bus)) {
 478                 dev_err(dev, "Could not get bus clock\n");
 479                 return PTR_ERR(phy->clk_bus);
 480         }
 481
 482         phy->clk_mod = of_clk_get_by_name(node, "mod");
 483         if (IS_ERR(phy->clk_mod)) {
 484                 dev_err(dev, "Could not get mod clock\n");
 485                 ret = PTR_ERR(phy->clk_mod);
 486                 goto err_put_clk_bus;
 487         }
 488
 489         if (phy->variant->has_phy_clk) {
 490                 phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
 491                 if (IS_ERR(phy->clk_pll0)) {
 492                         dev_err(dev, "Could not get pll-0 clock\n");
 493                         ret = PTR_ERR(phy->clk_pll0);
 494                         goto err_put_clk_mod;
 495                 }
 496
 497                 if (phy->variant->has_second_pll) {
 498                         phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
 499                         if (IS_ERR(phy->clk_pll1)) {
 500                                 dev_err(dev, "Could not get pll-1 clock\n");
 501                                 ret = PTR_ERR(phy->clk_pll1);
 502                                 goto err_put_clk_pll0;
 503                         }
 504                 }
 505         }
 506
 507         phy->rst_phy = of_reset_control_get_shared(node, "phy");
 508         if (IS_ERR(phy->rst_phy)) {
 509                 dev_err(dev, "Could not get phy reset control\n");
 510                 ret = PTR_ERR(phy->rst_phy);
 511                 goto err_put_clk_pll1;
 512         }
 513
 514         ret = reset_control_deassert(phy->rst_phy);
 515         if (ret) {
 516                 dev_err(dev, "Cannot deassert phy reset control: %d\n", ret);
 517                 goto err_put_rst_phy;
 518         }
 519
 520         ret = clk_prepare_enable(phy->clk_bus);
 521         if (ret) {
 522                 dev_err(dev, "Cannot enable bus clock: %d\n", ret);
 523                 goto err_deassert_rst_phy;
 524         }
 525
 526         ret = clk_prepare_enable(phy->clk_mod);
 527         if (ret) {
 528                 dev_err(dev, "Cannot enable mod clock: %d\n", ret);
 529                 goto err_disable_clk_bus;
 530         }
 531
 532         if (phy->variant->has_phy_clk) {
 533                 ret = sun8i_phy_clk_create(phy, dev,
 534                                            phy->variant->has_second_pll);
 535                 if (ret) {
 536                         dev_err(dev, "Couldn't create the PHY clock\n");
 537                         goto err_disable_clk_mod;
 538                 }
 539
 540                 clk_prepare_enable(phy->clk_phy);
 541         }
 542
 543         hdmi->phy = phy;
 544
 545         return 0;
 546
 547 err_disable_clk_mod:
 548         clk_disable_unprepare(phy->clk_mod);
 549 err_disable_clk_bus:
 550         clk_disable_unprepare(phy->clk_bus);
 551 err_deassert_rst_phy:
 552         reset_control_assert(phy->rst_phy);
 553 err_put_rst_phy:
 554         reset_control_put(phy->rst_phy);
 555 err_put_clk_pll1:
 556         clk_put(phy->clk_pll1);
 557 err_put_clk_pll0:
 558         clk_put(phy->clk_pll0);
 559 err_put_clk_mod:
 560         clk_put(phy->clk_mod);
 561 err_put_clk_bus:
 562         clk_put(phy->clk_bus);
 563
 564         return ret;
 565 }
 566
 567 void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
 568 {
 569         struct sun8i_hdmi_phy *phy = hdmi->phy;
 570
 571         clk_disable_unprepare(phy->clk_mod);
 572         clk_disable_unprepare(phy->clk_bus);
 573         clk_disable_unprepare(phy->clk_phy);
 574
 575         reset_control_assert(phy->rst_phy);
 576
 577         reset_control_put(phy->rst_phy);
 578
 579         clk_put(phy->clk_pll0);
 580         clk_put(phy->clk_pll1);
 581         clk_put(phy->clk_mod);
 582         clk_put(phy->clk_bus);
 583 }