1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
6 #include <linux/component.h>
7 #include <linux/module.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
11 #include <drm/drm_crtc_helper.h>
12 #include <drm/drm_of.h>
13 #include <drm/drm_simple_kms_helper.h>
15 #include "sun8i_dw_hdmi.h"
16 #include "sun8i_tcon_top.h"
18 static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
19 struct drm_display_mode *mode,
20 struct drm_display_mode *adj_mode)
22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
27 static const struct drm_encoder_helper_funcs
28 sun8i_dw_hdmi_encoder_helper_funcs = {
29 .mode_set = sun8i_dw_hdmi_encoder_mode_set,
32 static enum drm_mode_status
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data,
34 const struct drm_display_info *info,
35 const struct drm_display_mode *mode)
37 if (mode->clock > 297000)
38 return MODE_CLOCK_HIGH;
43 static enum drm_mode_status
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data,
45 const struct drm_display_info *info,
46 const struct drm_display_mode *mode)
49 * Controller support maximum of 594 MHz, which correlates to
50 * 4K@60Hz 4:4:4 or RGB.
52 if (mode->clock > 594000)
53 return MODE_CLOCK_HIGH;
58 static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node)
60 return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
61 !!of_match_node(sun8i_tcon_top_of_table, node);
64 static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm,
65 struct device_node *node)
67 struct device_node *port, *ep, *remote, *remote_port;
70 remote = of_graph_get_remote_node(node, 0, -1);
74 if (sun8i_dw_hdmi_node_is_tcon_top(remote)) {
75 port = of_graph_get_port_by_id(remote, 4);
79 for_each_child_of_node(port, ep) {
80 remote_port = of_graph_get_remote_port(ep);
82 crtcs |= drm_of_crtc_port_mask(drm, remote_port);
83 of_node_put(remote_port);
87 crtcs = drm_of_find_possible_crtcs(drm, node);
96 static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
99 struct platform_device *pdev = to_platform_device(dev);
100 struct dw_hdmi_plat_data *plat_data;
101 struct drm_device *drm = data;
102 struct device_node *phy_node;
103 struct drm_encoder *encoder;
104 struct sun8i_dw_hdmi *hdmi;
107 if (!pdev->dev.of_node)
110 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
114 plat_data = &hdmi->plat_data;
115 hdmi->dev = &pdev->dev;
116 encoder = &hdmi->encoder;
118 hdmi->quirks = of_device_get_match_data(dev);
120 encoder->possible_crtcs =
121 sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node);
123 * If we failed to find the CRTC(s) which this encoder is
124 * supposed to be connected to, it's because the CRTC has
125 * not been registered yet. Defer probing, and hope that
126 * the required CRTC is added later.
128 if (encoder->possible_crtcs == 0)
129 return -EPROBE_DEFER;
131 hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
132 if (IS_ERR(hdmi->rst_ctrl))
133 return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
134 "Could not get ctrl reset control\n");
136 hdmi->clk_tmds = devm_clk_get(dev, "tmds");
137 if (IS_ERR(hdmi->clk_tmds))
138 return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
139 "Couldn't get the tmds clock\n");
141 hdmi->regulator = devm_regulator_get(dev, "hvcc");
142 if (IS_ERR(hdmi->regulator))
143 return dev_err_probe(dev, PTR_ERR(hdmi->regulator),
144 "Couldn't get regulator\n");
146 ret = regulator_enable(hdmi->regulator);
148 dev_err(dev, "Failed to enable regulator\n");
152 ret = reset_control_deassert(hdmi->rst_ctrl);
154 dev_err(dev, "Could not deassert ctrl reset control\n");
155 goto err_disable_regulator;
158 ret = clk_prepare_enable(hdmi->clk_tmds);
160 dev_err(dev, "Could not enable tmds clock\n");
161 goto err_assert_ctrl_reset;
164 phy_node = of_parse_phandle(dev->of_node, "phys", 0);
166 dev_err(dev, "Can't found PHY phandle\n");
168 goto err_disable_clk_tmds;
171 ret = sun8i_hdmi_phy_get(hdmi, phy_node);
172 of_node_put(phy_node);
174 dev_err(dev, "Couldn't get the HDMI PHY\n");
175 goto err_disable_clk_tmds;
178 ret = sun8i_hdmi_phy_init(hdmi->phy);
180 goto err_disable_clk_tmds;
182 drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
183 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
185 plat_data->mode_valid = hdmi->quirks->mode_valid;
186 plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe;
187 sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data);
189 platform_set_drvdata(pdev, hdmi);
191 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
194 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
195 * which would have called the encoder cleanup. Do it manually.
197 if (IS_ERR(hdmi->hdmi)) {
198 ret = PTR_ERR(hdmi->hdmi);
199 goto cleanup_encoder;
205 drm_encoder_cleanup(encoder);
206 err_disable_clk_tmds:
207 clk_disable_unprepare(hdmi->clk_tmds);
208 err_assert_ctrl_reset:
209 reset_control_assert(hdmi->rst_ctrl);
210 err_disable_regulator:
211 regulator_disable(hdmi->regulator);
216 static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
219 struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);
221 dw_hdmi_unbind(hdmi->hdmi);
222 sun8i_hdmi_phy_deinit(hdmi->phy);
223 clk_disable_unprepare(hdmi->clk_tmds);
224 reset_control_assert(hdmi->rst_ctrl);
225 regulator_disable(hdmi->regulator);
228 static const struct component_ops sun8i_dw_hdmi_ops = {
229 .bind = sun8i_dw_hdmi_bind,
230 .unbind = sun8i_dw_hdmi_unbind,
233 static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
235 return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
238 static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
240 component_del(&pdev->dev, &sun8i_dw_hdmi_ops);
245 static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
246 .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
249 static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
250 .mode_valid = sun8i_dw_hdmi_mode_valid_h6,
251 .use_drm_infoframe = true,
254 static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
256 .compatible = "allwinner,sun8i-a83t-dw-hdmi",
257 .data = &sun8i_a83t_quirks,
260 .compatible = "allwinner,sun50i-h6-dw-hdmi",
261 .data = &sun50i_h6_quirks,
265 MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
267 static struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
268 .probe = sun8i_dw_hdmi_probe,
269 .remove = sun8i_dw_hdmi_remove,
271 .name = "sun8i-dw-hdmi",
272 .of_match_table = sun8i_dw_hdmi_dt_ids,
276 static int __init sun8i_dw_hdmi_init(void)
280 ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver);
284 ret = platform_driver_register(&sun8i_hdmi_phy_driver);
286 platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
293 static void __exit sun8i_dw_hdmi_exit(void)
295 platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
296 platform_driver_unregister(&sun8i_hdmi_phy_driver);
299 module_init(sun8i_dw_hdmi_init);
300 module_exit(sun8i_dw_hdmi_exit);
302 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
303 MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
304 MODULE_LICENSE("GPL");