2 * Copyright (C) 2015 Free Electrons
3 * Copyright (C) 2015 NextThing Co
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_modes.h>
18 #include <drm/drm_of.h>
20 #include <linux/component.h>
21 #include <linux/ioport.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
28 #include "sun4i_crtc.h"
29 #include "sun4i_dotclock.h"
30 #include "sun4i_drv.h"
31 #include "sun4i_rgb.h"
32 #include "sun4i_tcon.h"
33 #include "sunxi_engine.h"
35 void sun4i_tcon_disable(struct sun4i_tcon *tcon)
37 DRM_DEBUG_DRIVER("Disabling TCON\n");
39 /* Disable the TCON */
40 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
41 SUN4I_TCON_GCTL_TCON_ENABLE, 0);
43 EXPORT_SYMBOL(sun4i_tcon_disable);
45 void sun4i_tcon_enable(struct sun4i_tcon *tcon)
47 DRM_DEBUG_DRIVER("Enabling TCON\n");
50 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
51 SUN4I_TCON_GCTL_TCON_ENABLE,
52 SUN4I_TCON_GCTL_TCON_ENABLE);
54 EXPORT_SYMBOL(sun4i_tcon_enable);
56 void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
58 DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
60 /* Disable the TCON's channel */
62 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
63 SUN4I_TCON0_CTL_TCON_ENABLE, 0);
64 clk_disable_unprepare(tcon->dclk);
68 WARN_ON(!tcon->quirks->has_channel_1);
69 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
70 SUN4I_TCON1_CTL_TCON_ENABLE, 0);
71 clk_disable_unprepare(tcon->sclk1);
73 EXPORT_SYMBOL(sun4i_tcon_channel_disable);
75 void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
77 DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
79 /* Enable the TCON's channel */
81 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
82 SUN4I_TCON0_CTL_TCON_ENABLE,
83 SUN4I_TCON0_CTL_TCON_ENABLE);
84 clk_prepare_enable(tcon->dclk);
88 WARN_ON(!tcon->quirks->has_channel_1);
89 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
90 SUN4I_TCON1_CTL_TCON_ENABLE,
91 SUN4I_TCON1_CTL_TCON_ENABLE);
92 clk_prepare_enable(tcon->sclk1);
94 EXPORT_SYMBOL(sun4i_tcon_channel_enable);
96 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
100 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
102 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
103 SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
108 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
110 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
112 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
113 struct drm_encoder *encoder)
117 if (!tcon->quirks->has_unknown_mux)
123 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
129 * FIXME: Undocumented bits
131 regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
133 EXPORT_SYMBOL(sun4i_tcon_set_mux);
135 static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
138 int delay = mode->vtotal - mode->vdisplay;
140 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
146 delay = min(delay, 30);
148 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
153 void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
154 struct drm_display_mode *mode)
156 unsigned int bp, hsync, vsync;
160 /* Configure the dot clock */
161 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
163 /* Adjust clock delay */
164 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
165 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
166 SUN4I_TCON0_CTL_CLK_DELAY_MASK,
167 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
169 /* Set the resolution */
170 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
171 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
172 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
175 * This is called a backporch in the register documentation,
176 * but it really is the back porch + hsync
178 bp = mode->crtc_htotal - mode->crtc_hsync_start;
179 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
180 mode->crtc_htotal, bp);
182 /* Set horizontal display timings */
183 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
184 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
185 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
188 * This is called a backporch in the register documentation,
189 * but it really is the back porch + hsync
191 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
192 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
193 mode->crtc_vtotal, bp);
195 /* Set vertical display timings */
196 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
197 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
198 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
200 /* Set Hsync and Vsync length */
201 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
202 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
203 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
204 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
205 SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
206 SUN4I_TCON0_BASIC3_H_SYNC(hsync));
208 /* Setup the polarity of the various signals */
209 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
210 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
212 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
213 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
215 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
216 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
219 /* Map output pins to channel 0 */
220 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
221 SUN4I_TCON_GCTL_IOMAP_MASK,
222 SUN4I_TCON_GCTL_IOMAP_TCON0);
224 /* Enable the output on the pins */
225 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
227 EXPORT_SYMBOL(sun4i_tcon0_mode_set);
229 void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
230 struct drm_display_mode *mode)
232 unsigned int bp, hsync, vsync, vtotal;
236 WARN_ON(!tcon->quirks->has_channel_1);
238 /* Configure the dot clock */
239 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
241 /* Adjust clock delay */
242 clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
243 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
244 SUN4I_TCON1_CTL_CLK_DELAY_MASK,
245 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
247 /* Set interlaced mode */
248 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
249 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
252 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
253 SUN4I_TCON1_CTL_INTERLACE_ENABLE,
256 /* Set the input resolution */
257 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
258 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
259 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
261 /* Set the upscaling resolution */
262 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
263 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
264 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
266 /* Set the output resolution */
267 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
268 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
269 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
271 /* Set horizontal display timings */
272 bp = mode->crtc_htotal - mode->crtc_hsync_start;
273 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
275 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
276 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
277 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
279 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
280 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
281 mode->crtc_vtotal, bp);
284 * The vertical resolution needs to be doubled in all
285 * cases. We could use crtc_vtotal and always multiply by two,
286 * but that leads to a rounding error in interlace when vtotal
289 * This happens with TV's PAL for example, where vtotal will
290 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
291 * 624, which apparently confuses the hardware.
293 * To work around this, we will always use vtotal, and
294 * multiply by two only if we're not in interlace.
296 vtotal = mode->vtotal;
297 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
300 /* Set vertical display timings */
301 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
302 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
303 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
305 /* Set Hsync and Vsync length */
306 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
307 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
308 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
309 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
310 SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
311 SUN4I_TCON1_BASIC5_H_SYNC(hsync));
313 /* Map output pins to channel 1 */
314 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
315 SUN4I_TCON_GCTL_IOMAP_MASK,
316 SUN4I_TCON_GCTL_IOMAP_TCON1);
318 EXPORT_SYMBOL(sun4i_tcon1_mode_set);
320 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
321 struct sun4i_crtc *scrtc)
325 spin_lock_irqsave(&dev->event_lock, flags);
327 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
328 drm_crtc_vblank_put(&scrtc->crtc);
331 spin_unlock_irqrestore(&dev->event_lock, flags);
334 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
336 struct sun4i_tcon *tcon = private;
337 struct drm_device *drm = tcon->drm;
338 struct sun4i_crtc *scrtc = tcon->crtc;
341 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
343 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
344 SUN4I_TCON_GINT0_VBLANK_INT(1))))
347 drm_crtc_handle_vblank(&scrtc->crtc);
348 sun4i_tcon_finish_page_flip(drm, scrtc);
350 /* Acknowledge the interrupt */
351 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
352 SUN4I_TCON_GINT0_VBLANK_INT(0) |
353 SUN4I_TCON_GINT0_VBLANK_INT(1),
359 static int sun4i_tcon_init_clocks(struct device *dev,
360 struct sun4i_tcon *tcon)
362 tcon->clk = devm_clk_get(dev, "ahb");
363 if (IS_ERR(tcon->clk)) {
364 dev_err(dev, "Couldn't get the TCON bus clock\n");
365 return PTR_ERR(tcon->clk);
367 clk_prepare_enable(tcon->clk);
369 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
370 if (IS_ERR(tcon->sclk0)) {
371 dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
372 return PTR_ERR(tcon->sclk0);
374 clk_prepare_enable(tcon->sclk0);
376 if (tcon->quirks->has_channel_1) {
377 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
378 if (IS_ERR(tcon->sclk1)) {
379 dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
380 return PTR_ERR(tcon->sclk1);
387 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
389 clk_disable_unprepare(tcon->sclk0);
390 clk_disable_unprepare(tcon->clk);
393 static int sun4i_tcon_init_irq(struct device *dev,
394 struct sun4i_tcon *tcon)
396 struct platform_device *pdev = to_platform_device(dev);
399 irq = platform_get_irq(pdev, 0);
401 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
405 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
406 dev_name(dev), tcon);
408 dev_err(dev, "Couldn't request the IRQ\n");
415 static struct regmap_config sun4i_tcon_regmap_config = {
419 .max_register = 0x800,
422 static int sun4i_tcon_init_regmap(struct device *dev,
423 struct sun4i_tcon *tcon)
425 struct platform_device *pdev = to_platform_device(dev);
426 struct resource *res;
429 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 regs = devm_ioremap_resource(dev, res);
432 return PTR_ERR(regs);
434 tcon->regs = devm_regmap_init_mmio(dev, regs,
435 &sun4i_tcon_regmap_config);
436 if (IS_ERR(tcon->regs)) {
437 dev_err(dev, "Couldn't create the TCON regmap\n");
438 return PTR_ERR(tcon->regs);
441 /* Make sure the TCON is disabled and all IRQs are off */
442 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
443 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
444 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
446 /* Disable IO lines and set them to tristate */
447 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
448 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
454 * On SoCs with the old display pipeline design (Display Engine 1.0),
455 * the TCON is always tied to just one backend. Hence we can traverse
456 * the of_graph upwards to find the backend our tcon is connected to,
457 * and take its ID as our own.
459 * We can either identify backends from their compatible strings, which
460 * means maintaining a large list of them. Or, since the backend is
461 * registered and binded before the TCON, we can just go through the
462 * list of registered backends and compare the device node.
464 * As the structures now store engines instead of backends, here this
465 * function in fact searches the corresponding engine, and the ID is
466 * requested via the get_id function of the engine.
468 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
469 struct device_node *node)
471 struct device_node *port, *ep, *remote;
472 struct sunxi_engine *engine;
474 port = of_graph_get_port_by_id(node, 0);
476 return ERR_PTR(-EINVAL);
478 for_each_available_child_of_node(port, ep) {
479 remote = of_graph_get_remote_port_parent(ep);
483 /* does this node match any registered engines? */
484 list_for_each_entry(engine, &drv->engine_list, list) {
485 if (remote == engine->node) {
492 /* keep looking through upstream ports */
493 engine = sun4i_tcon_find_engine(drv, remote);
494 if (!IS_ERR(engine)) {
501 return ERR_PTR(-EINVAL);
504 static int sun4i_tcon_bind(struct device *dev, struct device *master,
507 struct drm_device *drm = data;
508 struct sun4i_drv *drv = drm->dev_private;
509 struct sunxi_engine *engine;
510 struct sun4i_tcon *tcon;
513 engine = sun4i_tcon_find_engine(drv, dev->of_node);
514 if (IS_ERR(engine)) {
515 dev_err(dev, "Couldn't find matching engine\n");
516 return -EPROBE_DEFER;
519 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
522 dev_set_drvdata(dev, tcon);
525 tcon->id = engine->id;
526 tcon->quirks = of_device_get_match_data(dev);
528 tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
529 if (IS_ERR(tcon->lcd_rst)) {
530 dev_err(dev, "Couldn't get our reset line\n");
531 return PTR_ERR(tcon->lcd_rst);
534 /* Make sure our TCON is reset */
535 if (!reset_control_status(tcon->lcd_rst))
536 reset_control_assert(tcon->lcd_rst);
538 ret = reset_control_deassert(tcon->lcd_rst);
540 dev_err(dev, "Couldn't deassert our reset line\n");
544 ret = sun4i_tcon_init_clocks(dev, tcon);
546 dev_err(dev, "Couldn't init our TCON clocks\n");
547 goto err_assert_reset;
550 ret = sun4i_tcon_init_regmap(dev, tcon);
552 dev_err(dev, "Couldn't init our TCON regmap\n");
553 goto err_free_clocks;
556 ret = sun4i_dclk_create(dev, tcon);
558 dev_err(dev, "Couldn't create our TCON dot clock\n");
559 goto err_free_clocks;
562 ret = sun4i_tcon_init_irq(dev, tcon);
564 dev_err(dev, "Couldn't init our TCON interrupts\n");
565 goto err_free_dotclock;
568 tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
569 if (IS_ERR(tcon->crtc)) {
570 dev_err(dev, "Couldn't create our CRTC\n");
571 ret = PTR_ERR(tcon->crtc);
572 goto err_free_dotclock;
575 ret = sun4i_rgb_init(drm, tcon);
577 goto err_free_dotclock;
579 list_add_tail(&tcon->list, &drv->tcon_list);
584 sun4i_dclk_free(tcon);
586 sun4i_tcon_free_clocks(tcon);
588 reset_control_assert(tcon->lcd_rst);
592 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
595 struct sun4i_tcon *tcon = dev_get_drvdata(dev);
597 list_del(&tcon->list);
598 sun4i_dclk_free(tcon);
599 sun4i_tcon_free_clocks(tcon);
602 static const struct component_ops sun4i_tcon_ops = {
603 .bind = sun4i_tcon_bind,
604 .unbind = sun4i_tcon_unbind,
607 static int sun4i_tcon_probe(struct platform_device *pdev)
609 struct device_node *node = pdev->dev.of_node;
610 struct drm_bridge *bridge;
611 struct drm_panel *panel;
614 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
615 if (ret == -EPROBE_DEFER)
618 return component_add(&pdev->dev, &sun4i_tcon_ops);
621 static int sun4i_tcon_remove(struct platform_device *pdev)
623 component_del(&pdev->dev, &sun4i_tcon_ops);
628 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
629 .has_unknown_mux = true,
630 .has_channel_1 = true,
633 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
634 .has_channel_1 = true,
637 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
638 .has_channel_1 = true,
641 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
642 /* nothing is supported */
645 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
646 /* nothing is supported */
649 static const struct of_device_id sun4i_tcon_of_table[] = {
650 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
651 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
652 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
653 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
654 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
657 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
659 static struct platform_driver sun4i_tcon_platform_driver = {
660 .probe = sun4i_tcon_probe,
661 .remove = sun4i_tcon_remove,
663 .name = "sun4i-tcon",
664 .of_match_table = sun4i_tcon_of_table,
667 module_platform_driver(sun4i_tcon_platform_driver);
669 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
670 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
671 MODULE_LICENSE("GPL");