2 * Copyright (C) 2016 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_edid.h>
16 #include <drm/drm_encoder.h>
17 #include <drm/drm_of.h>
18 #include <drm/drm_panel.h>
20 #include <linux/clk.h>
21 #include <linux/component.h>
22 #include <linux/iopoll.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
29 #include "sun4i_backend.h"
30 #include "sun4i_crtc.h"
31 #include "sun4i_drv.h"
32 #include "sun4i_hdmi.h"
34 static inline struct sun4i_hdmi *
35 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
37 return container_of(encoder, struct sun4i_hdmi,
41 static inline struct sun4i_hdmi *
42 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
44 return container_of(connector, struct sun4i_hdmi,
48 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
49 struct drm_display_mode *mode)
51 struct hdmi_avi_infoframe frame;
55 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
57 DRM_ERROR("Failed to get infoframes from mode\n");
61 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
63 DRM_ERROR("Failed to pack infoframes\n");
67 for (i = 0; i < sizeof(buffer); i++)
68 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
73 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
74 struct drm_crtc_state *crtc_state,
75 struct drm_connector_state *conn_state)
77 struct drm_display_mode *mode = &crtc_state->mode;
79 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
85 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
87 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
90 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
92 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
93 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
94 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
96 clk_disable_unprepare(hdmi->tmds_clk);
99 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
101 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
102 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
105 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
107 clk_prepare_enable(hdmi->tmds_clk);
109 sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
110 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
111 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
112 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
114 val = SUN4I_HDMI_VID_CTRL_ENABLE;
115 if (hdmi->hdmi_monitor)
116 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
118 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
121 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
122 struct drm_display_mode *mode,
123 struct drm_display_mode *adjusted_mode)
125 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
129 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
130 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
132 /* Set input sync enable */
133 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
134 hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
137 * Setup output pad (?) controls
139 * This is done here instead of at probe/bind time because
140 * the controller seems to toggle some of the bits on its own.
142 * We can't just initialize the register there, we need to
143 * protect the clock bits that have already been read out and
144 * cached by the clock framework.
146 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
147 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
148 val |= hdmi->variant->pad_ctrl1_init_val;
149 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
150 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
152 /* Setup timing registers */
153 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
154 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
155 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
157 x = mode->htotal - mode->hsync_start;
158 y = mode->vtotal - mode->vsync_start;
159 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
160 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
162 x = mode->hsync_start - mode->hdisplay;
163 y = mode->vsync_start - mode->vdisplay;
164 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
165 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
167 x = mode->hsync_end - mode->hsync_start;
168 y = mode->vsync_end - mode->vsync_start;
169 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
170 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
172 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
173 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
174 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
176 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
177 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
179 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
182 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
183 const struct drm_display_mode *mode)
185 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
186 unsigned long rate = mode->clock * 1000;
187 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
190 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
191 if (rate > 165000000)
192 return MODE_CLOCK_HIGH;
193 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
194 if (rounded_rate > 0 &&
195 max_t(unsigned long, rounded_rate, rate) -
196 min_t(unsigned long, rounded_rate, rate) < diff)
201 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
202 .atomic_check = sun4i_hdmi_atomic_check,
203 .disable = sun4i_hdmi_disable,
204 .enable = sun4i_hdmi_enable,
205 .mode_set = sun4i_hdmi_mode_set,
206 .mode_valid = sun4i_hdmi_mode_valid,
209 static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
210 .destroy = drm_encoder_cleanup,
213 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
215 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
219 edid = drm_get_edid(connector, hdmi->i2c);
223 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
224 DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
225 hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
227 drm_connector_update_edid_property(connector, edid);
228 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
229 ret = drm_add_edid_modes(connector, edid);
235 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
236 .get_modes = sun4i_hdmi_get_modes,
239 static enum drm_connector_status
240 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
242 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
245 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG);
246 if (!(reg & SUN4I_HDMI_HPD_HIGH)) {
247 cec_phys_addr_invalidate(hdmi->cec_adap);
248 return connector_status_disconnected;
251 return connector_status_connected;
254 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
255 .detect = sun4i_hdmi_connector_detect,
256 .fill_modes = drm_helper_probe_single_connector_modes,
257 .destroy = drm_connector_cleanup,
258 .reset = drm_atomic_helper_connector_reset,
259 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
260 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
263 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
264 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
266 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
268 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
271 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
273 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
275 /* Start driving the CEC pin low */
276 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
279 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
281 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
284 * Stop driving the CEC pin, the pull up will take over
285 * unless another CEC device is driving the pin low.
287 writel(0, hdmi->base + SUN4I_HDMI_CEC);
290 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
291 .read = sun4i_hdmi_cec_pin_read,
292 .low = sun4i_hdmi_cec_pin_low,
293 .high = sun4i_hdmi_cec_pin_high,
297 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0))
298 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))
300 /* Only difference from sun5i is AMP is 4 instead of 6 */
301 static const struct sun4i_hdmi_variant sun4i_variant = {
302 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
303 SUN4I_HDMI_PAD_CTRL0_CKEN |
304 SUN4I_HDMI_PAD_CTRL0_PWENG |
305 SUN4I_HDMI_PAD_CTRL0_PWEND |
306 SUN4I_HDMI_PAD_CTRL0_PWENC |
307 SUN4I_HDMI_PAD_CTRL0_LDODEN |
308 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
309 SUN4I_HDMI_PAD_CTRL0_BIASEN,
310 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
311 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
312 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
313 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
314 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
315 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
316 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
317 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
318 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
319 SUN4I_HDMI_PLL_CTRL_CS(7) |
320 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
321 SUN4I_HDMI_PLL_CTRL_S(7) |
322 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
323 SUN4I_HDMI_PLL_CTRL_SDIV2 |
324 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
325 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
326 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
327 SUN4I_HDMI_PLL_CTRL_BWS |
328 SUN4I_HDMI_PLL_CTRL_PLL_EN,
330 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
331 .ddc_clk_pre_divider = 2,
332 .ddc_clk_m_offset = 1,
334 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
335 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
336 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
337 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
338 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
339 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
340 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
341 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
342 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
343 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
344 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
345 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
346 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
348 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
349 .ddc_fifo_has_dir = true,
352 static const struct sun4i_hdmi_variant sun5i_variant = {
353 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
354 SUN4I_HDMI_PAD_CTRL0_CKEN |
355 SUN4I_HDMI_PAD_CTRL0_PWENG |
356 SUN4I_HDMI_PAD_CTRL0_PWEND |
357 SUN4I_HDMI_PAD_CTRL0_PWENC |
358 SUN4I_HDMI_PAD_CTRL0_LDODEN |
359 SUN4I_HDMI_PAD_CTRL0_LDOCEN |
360 SUN4I_HDMI_PAD_CTRL0_BIASEN,
361 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
362 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
363 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
364 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
365 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
366 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
367 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
368 SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
369 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
370 SUN4I_HDMI_PLL_CTRL_CS(7) |
371 SUN4I_HDMI_PLL_CTRL_CP_S(15) |
372 SUN4I_HDMI_PLL_CTRL_S(7) |
373 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
374 SUN4I_HDMI_PLL_CTRL_SDIV2 |
375 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
376 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
377 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
378 SUN4I_HDMI_PLL_CTRL_BWS |
379 SUN4I_HDMI_PLL_CTRL_PLL_EN,
381 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
382 .ddc_clk_pre_divider = 2,
383 .ddc_clk_m_offset = 1,
385 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
386 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
387 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
388 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
389 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
390 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
391 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
392 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
393 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
394 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
395 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
396 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
397 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
399 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG,
400 .ddc_fifo_has_dir = true,
403 static const struct sun4i_hdmi_variant sun6i_variant = {
404 .has_ddc_parent_clk = true,
405 .has_reset_control = true,
406 .pad_ctrl0_init_val = 0xff |
407 SUN4I_HDMI_PAD_CTRL0_TXEN |
408 SUN4I_HDMI_PAD_CTRL0_CKEN |
409 SUN4I_HDMI_PAD_CTRL0_PWENG |
410 SUN4I_HDMI_PAD_CTRL0_PWEND |
411 SUN4I_HDMI_PAD_CTRL0_PWENC |
412 SUN4I_HDMI_PAD_CTRL0_LDODEN |
413 SUN4I_HDMI_PAD_CTRL0_LDOCEN,
414 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
415 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
416 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
417 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
418 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
419 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
420 SUN4I_HDMI_PAD_CTRL1_PWSDT |
421 SUN4I_HDMI_PAD_CTRL1_PWSCK |
422 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
423 SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
424 SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
425 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
426 SUN4I_HDMI_PLL_CTRL_CS(3) |
427 SUN4I_HDMI_PLL_CTRL_CP_S(10) |
428 SUN4I_HDMI_PLL_CTRL_S(4) |
429 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
430 SUN4I_HDMI_PLL_CTRL_SDIV2 |
431 SUN4I_HDMI_PLL_CTRL_LDO2_EN |
432 SUN4I_HDMI_PLL_CTRL_LDO1_EN |
433 SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
434 SUN4I_HDMI_PLL_CTRL_PLL_EN,
436 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
437 .ddc_clk_pre_divider = 1,
438 .ddc_clk_m_offset = 2,
440 .tmds_clk_div_offset = 1,
442 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
443 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
444 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
445 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
446 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
447 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
448 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
449 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
450 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
451 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
452 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
453 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
454 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
456 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG,
457 .ddc_fifo_thres_incl = true,
460 static const struct regmap_config sun4i_hdmi_regmap_config = {
464 .max_register = 0x580,
467 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
470 struct platform_device *pdev = to_platform_device(dev);
471 struct drm_device *drm = data;
472 struct sun4i_drv *drv = drm->dev_private;
473 struct sun4i_hdmi *hdmi;
474 struct resource *res;
478 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
481 dev_set_drvdata(dev, hdmi);
485 hdmi->variant = of_device_get_match_data(dev);
489 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
490 hdmi->base = devm_ioremap_resource(dev, res);
491 if (IS_ERR(hdmi->base)) {
492 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
493 return PTR_ERR(hdmi->base);
496 if (hdmi->variant->has_reset_control) {
497 hdmi->reset = devm_reset_control_get(dev, NULL);
498 if (IS_ERR(hdmi->reset)) {
499 dev_err(dev, "Couldn't get the HDMI reset control\n");
500 return PTR_ERR(hdmi->reset);
503 ret = reset_control_deassert(hdmi->reset);
505 dev_err(dev, "Couldn't deassert HDMI reset\n");
510 hdmi->bus_clk = devm_clk_get(dev, "ahb");
511 if (IS_ERR(hdmi->bus_clk)) {
512 dev_err(dev, "Couldn't get the HDMI bus clock\n");
513 ret = PTR_ERR(hdmi->bus_clk);
514 goto err_assert_reset;
516 clk_prepare_enable(hdmi->bus_clk);
518 hdmi->mod_clk = devm_clk_get(dev, "mod");
519 if (IS_ERR(hdmi->mod_clk)) {
520 dev_err(dev, "Couldn't get the HDMI mod clock\n");
521 ret = PTR_ERR(hdmi->mod_clk);
522 goto err_disable_bus_clk;
524 clk_prepare_enable(hdmi->mod_clk);
526 hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
527 if (IS_ERR(hdmi->pll0_clk)) {
528 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
529 ret = PTR_ERR(hdmi->pll0_clk);
530 goto err_disable_mod_clk;
533 hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
534 if (IS_ERR(hdmi->pll1_clk)) {
535 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
536 ret = PTR_ERR(hdmi->pll1_clk);
537 goto err_disable_mod_clk;
540 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
541 &sun4i_hdmi_regmap_config);
542 if (IS_ERR(hdmi->regmap)) {
543 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
544 ret = PTR_ERR(hdmi->regmap);
545 goto err_disable_mod_clk;
548 ret = sun4i_tmds_create(hdmi);
550 dev_err(dev, "Couldn't create the TMDS clock\n");
551 goto err_disable_mod_clk;
554 if (hdmi->variant->has_ddc_parent_clk) {
555 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
556 if (IS_ERR(hdmi->ddc_parent_clk)) {
557 dev_err(dev, "Couldn't get the HDMI DDC clock\n");
558 ret = PTR_ERR(hdmi->ddc_parent_clk);
559 goto err_disable_mod_clk;
562 hdmi->ddc_parent_clk = hdmi->tmds_clk;
565 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
567 writel(hdmi->variant->pad_ctrl0_init_val,
568 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
570 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
571 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
572 reg |= hdmi->variant->pll_ctrl_init_val;
573 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
575 ret = sun4i_hdmi_i2c_create(dev, hdmi);
577 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
578 goto err_disable_mod_clk;
581 drm_encoder_helper_add(&hdmi->encoder,
582 &sun4i_hdmi_helper_funcs);
583 ret = drm_encoder_init(drm,
586 DRM_MODE_ENCODER_TMDS,
589 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
590 goto err_del_i2c_adapter;
593 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
595 if (!hdmi->encoder.possible_crtcs) {
597 goto err_del_i2c_adapter;
600 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
601 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
602 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
603 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
604 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
606 goto err_cleanup_connector;
607 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
608 hdmi->base + SUN4I_HDMI_CEC);
611 drm_connector_helper_add(&hdmi->connector,
612 &sun4i_hdmi_connector_helper_funcs);
613 ret = drm_connector_init(drm, &hdmi->connector,
614 &sun4i_hdmi_connector_funcs,
615 DRM_MODE_CONNECTOR_HDMIA);
618 "Couldn't initialise the HDMI connector\n");
619 goto err_cleanup_connector;
622 /* There is no HPD interrupt, so we need to poll the controller */
623 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
624 DRM_CONNECTOR_POLL_DISCONNECT;
626 ret = cec_register_adapter(hdmi->cec_adap, dev);
628 goto err_cleanup_connector;
629 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
633 err_cleanup_connector:
634 cec_delete_adapter(hdmi->cec_adap);
635 drm_encoder_cleanup(&hdmi->encoder);
637 i2c_del_adapter(hdmi->i2c);
639 clk_disable_unprepare(hdmi->mod_clk);
641 clk_disable_unprepare(hdmi->bus_clk);
643 reset_control_assert(hdmi->reset);
647 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
650 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
652 cec_unregister_adapter(hdmi->cec_adap);
653 i2c_del_adapter(hdmi->i2c);
654 clk_disable_unprepare(hdmi->mod_clk);
655 clk_disable_unprepare(hdmi->bus_clk);
658 static const struct component_ops sun4i_hdmi_ops = {
659 .bind = sun4i_hdmi_bind,
660 .unbind = sun4i_hdmi_unbind,
663 static int sun4i_hdmi_probe(struct platform_device *pdev)
665 return component_add(&pdev->dev, &sun4i_hdmi_ops);
668 static int sun4i_hdmi_remove(struct platform_device *pdev)
670 component_del(&pdev->dev, &sun4i_hdmi_ops);
675 static const struct of_device_id sun4i_hdmi_of_table[] = {
676 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
677 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
678 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
681 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
683 static struct platform_driver sun4i_hdmi_driver = {
684 .probe = sun4i_hdmi_probe,
685 .remove = sun4i_hdmi_remove,
687 .name = "sun4i-hdmi",
688 .of_match_table = sun4i_hdmi_of_table,
691 module_platform_driver(sun4i_hdmi_driver);
693 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
694 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
695 MODULE_LICENSE("GPL");