drivers/gpu/drm/stm/ltdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <philippe.cornu@st.com>
   6  *          Yannick Fertre <yannick.fertre@st.com>
   7  *          Fabien Dessenne <fabien.dessenne@st.com>
   8  *          Mickael Reulier <mickael.reulier@st.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/module.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23
  24 #include <drm/drm_atomic.h>
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/drm_bridge.h>
  27 #include <drm/drm_device.h>
  28 #include <drm/drm_fb_cma_helper.h>
  29 #include <drm/drm_fourcc.h>
  30 #include <drm/drm_gem_atomic_helper.h>
  31 #include <drm/drm_gem_cma_helper.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_plane_helper.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/drm_simple_kms_helper.h>
  36 #include <drm/drm_vblank.h>
  37
  38 #include <video/videomode.h>
  39
  40 #include "ltdc.h"
  41
  42 #define NB_CRTC 1
  43 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
  44
  45 #define MAX_IRQ 4
  46
  47 #define HWVER_10200 0x010200
  48 #define HWVER_10300 0x010300
  49 #define HWVER_20101 0x020101
  50 #define HWVER_40100 0x040100
  51
  52 /*
  53  * The address of some registers depends on the HW version: such registers have
  54  * an extra offset specified with layer_ofs.
  55  */
  56 #define LAY_OFS_0       0x80
  57 #define LAY_OFS_1       0x100
  58 #define LAY_OFS (ldev->caps.layer_ofs)
  59
  60 /* Global register offsets */
  61 #define LTDC_IDR        0x0000          /* IDentification */
  62 #define LTDC_LCR        0x0004          /* Layer Count */
  63 #define LTDC_SSCR       0x0008          /* Synchronization Size Configuration */
  64 #define LTDC_BPCR       0x000C          /* Back Porch Configuration */
  65 #define LTDC_AWCR       0x0010          /* Active Width Configuration */
  66 #define LTDC_TWCR       0x0014          /* Total Width Configuration */
  67 #define LTDC_GCR        0x0018          /* Global Control */
  68 #define LTDC_GC1R       0x001C          /* Global Configuration 1 */
  69 #define LTDC_GC2R       0x0020          /* Global Configuration 2 */
  70 #define LTDC_SRCR       0x0024          /* Shadow Reload Configuration */
  71 #define LTDC_GACR       0x0028          /* GAmma Correction */
  72 #define LTDC_BCCR       0x002C          /* Background Color Configuration */
  73 #define LTDC_IER        0x0034          /* Interrupt Enable */
  74 #define LTDC_ISR        0x0038          /* Interrupt Status */
  75 #define LTDC_ICR        0x003C          /* Interrupt Clear */
  76 #define LTDC_LIPCR      0x0040          /* Line Interrupt Position Conf. */
  77 #define LTDC_CPSR       0x0044          /* Current Position Status */
  78 #define LTDC_CDSR       0x0048          /* Current Display Status */
  79 #define LTDC_EDCR       0x0060          /* External Display Control */
  80 #define LTDC_CCRCR      0x007C          /* Computed CRC value */
  81 #define LTDC_FUT        0x0090          /* Fifo underrun Threshold */
  82
  83 /* Layer register offsets */
  84 #define LTDC_L1C0R      (ldev->caps.layer_regs[0])      /* L1 configuration 0 */
  85 #define LTDC_L1C1R      (ldev->caps.layer_regs[1])      /* L1 configuration 1 */
  86 #define LTDC_L1RCR      (ldev->caps.layer_regs[2])      /* L1 reload control */
  87 #define LTDC_L1CR       (ldev->caps.layer_regs[3])      /* L1 control register */
  88 #define LTDC_L1WHPCR    (ldev->caps.layer_regs[4])      /* L1 window horizontal position configuration */
  89 #define LTDC_L1WVPCR    (ldev->caps.layer_regs[5])      /* L1 window vertical position configuration */
  90 #define LTDC_L1CKCR     (ldev->caps.layer_regs[6])      /* L1 color keying configuration */
  91 #define LTDC_L1PFCR     (ldev->caps.layer_regs[7])      /* L1 pixel format configuration */
  92 #define LTDC_L1CACR     (ldev->caps.layer_regs[8])      /* L1 constant alpha configuration */
  93 #define LTDC_L1DCCR     (ldev->caps.layer_regs[9])      /* L1 default color configuration */
  94 #define LTDC_L1BFCR     (ldev->caps.layer_regs[10])     /* L1 blending factors configuration */
  95 #define LTDC_L1BLCR     (ldev->caps.layer_regs[11])     /* L1 burst length configuration */
  96 #define LTDC_L1PCR      (ldev->caps.layer_regs[12])     /* L1 planar configuration */
  97 #define LTDC_L1CFBAR    (ldev->caps.layer_regs[13])     /* L1 color frame buffer address */
  98 #define LTDC_L1CFBLR    (ldev->caps.layer_regs[14])     /* L1 color frame buffer length */
  99 #define LTDC_L1CFBLNR   (ldev->caps.layer_regs[15])     /* L1 color frame buffer line number */
 100 #define LTDC_L1AFBA0R   (ldev->caps.layer_regs[16])     /* L1 auxiliary frame buffer address 0 */
 101 #define LTDC_L1AFBA1R   (ldev->caps.layer_regs[17])     /* L1 auxiliary frame buffer address 1 */
 102 #define LTDC_L1AFBLR    (ldev->caps.layer_regs[18])     /* L1 auxiliary frame buffer length */
 103 #define LTDC_L1AFBLNR   (ldev->caps.layer_regs[19])     /* L1 auxiliary frame buffer line number */
 104 #define LTDC_L1CLUTWR   (ldev->caps.layer_regs[20])     /* L1 CLUT write */
 105 #define LTDC_L1CYR0R    (ldev->caps.layer_regs[21])     /* L1 Conversion YCbCr RGB 0 */
 106 #define LTDC_L1CYR1R    (ldev->caps.layer_regs[22])     /* L1 Conversion YCbCr RGB 1 */
 107 #define LTDC_L1FPF0R    (ldev->caps.layer_regs[23])     /* L1 Flexible Pixel Format 0 */
 108 #define LTDC_L1FPF1R    (ldev->caps.layer_regs[24])     /* L1 Flexible Pixel Format 1 */
 109
 110 /* Bit definitions */
 111 #define SSCR_VSH        GENMASK(10, 0)  /* Vertical Synchronization Height */
 112 #define SSCR_HSW        GENMASK(27, 16) /* Horizontal Synchronization Width */
 113
 114 #define BPCR_AVBP       GENMASK(10, 0)  /* Accumulated Vertical Back Porch */
 115 #define BPCR_AHBP       GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
 116
 117 #define AWCR_AAH        GENMASK(10, 0)  /* Accumulated Active Height */
 118 #define AWCR_AAW        GENMASK(27, 16) /* Accumulated Active Width */
 119
 120 #define TWCR_TOTALH     GENMASK(10, 0)  /* TOTAL Height */
 121 #define TWCR_TOTALW     GENMASK(27, 16) /* TOTAL Width */
 122
 123 #define GCR_LTDCEN      BIT(0)          /* LTDC ENable */
 124 #define GCR_DEN         BIT(16)         /* Dither ENable */
 125 #define GCR_CRCEN       BIT(19)         /* CRC ENable */
 126 #define GCR_PCPOL       BIT(28)         /* Pixel Clock POLarity-Inverted */
 127 #define GCR_DEPOL       BIT(29)         /* Data Enable POLarity-High */
 128 #define GCR_VSPOL       BIT(30)         /* Vertical Synchro POLarity-High */
 129 #define GCR_HSPOL       BIT(31)         /* Horizontal Synchro POLarity-High */
 130
 131 #define GC1R_WBCH       GENMASK(3, 0)   /* Width of Blue CHannel output */
 132 #define GC1R_WGCH       GENMASK(7, 4)   /* Width of Green Channel output */
 133 #define GC1R_WRCH       GENMASK(11, 8)  /* Width of Red Channel output */
 134 #define GC1R_PBEN       BIT(12)         /* Precise Blending ENable */
 135 #define GC1R_DT         GENMASK(15, 14) /* Dithering Technique */
 136 #define GC1R_GCT        GENMASK(19, 17) /* Gamma Correction Technique */
 137 #define GC1R_SHREN      BIT(21)         /* SHadow Registers ENabled */
 138 #define GC1R_BCP        BIT(22)         /* Background Colour Programmable */
 139 #define GC1R_BBEN       BIT(23)         /* Background Blending ENabled */
 140 #define GC1R_LNIP       BIT(24)         /* Line Number IRQ Position */
 141 #define GC1R_TP         BIT(25)         /* Timing Programmable */
 142 #define GC1R_IPP        BIT(26)         /* IRQ Polarity Programmable */
 143 #define GC1R_SPP        BIT(27)         /* Sync Polarity Programmable */
 144 #define GC1R_DWP        BIT(28)         /* Dither Width Programmable */
 145 #define GC1R_STREN      BIT(29)         /* STatus Registers ENabled */
 146 #define GC1R_BMEN       BIT(31)         /* Blind Mode ENabled */
 147
 148 #define GC2R_EDCA       BIT(0)          /* External Display Control Ability  */
 149 #define GC2R_STSAEN     BIT(1)          /* Slave Timing Sync Ability ENabled */
 150 #define GC2R_DVAEN      BIT(2)          /* Dual-View Ability ENabled */
 151 #define GC2R_DPAEN      BIT(3)          /* Dual-Port Ability ENabled */
 152 #define GC2R_BW         GENMASK(6, 4)   /* Bus Width (log2 of nb of bytes) */
 153 #define GC2R_EDCEN      BIT(7)          /* External Display Control ENabled */
 154
 155 #define SRCR_IMR        BIT(0)          /* IMmediate Reload */
 156 #define SRCR_VBR        BIT(1)          /* Vertical Blanking Reload */
 157
 158 #define BCCR_BCBLACK    0x00            /* Background Color BLACK */
 159 #define BCCR_BCBLUE     GENMASK(7, 0)   /* Background Color BLUE */
 160 #define BCCR_BCGREEN    GENMASK(15, 8)  /* Background Color GREEN */
 161 #define BCCR_BCRED      GENMASK(23, 16) /* Background Color RED */
 162 #define BCCR_BCWHITE    GENMASK(23, 0)  /* Background Color WHITE */
 163
 164 #define IER_LIE         BIT(0)          /* Line Interrupt Enable */
 165 #define IER_FUIE        BIT(1)          /* Fifo Underrun Interrupt Enable */
 166 #define IER_TERRIE      BIT(2)          /* Transfer ERRor Interrupt Enable */
 167 #define IER_RRIE        BIT(3)          /* Register Reload Interrupt enable */
 168
 169 #define CPSR_CYPOS      GENMASK(15, 0)  /* Current Y position */
 170
 171 #define ISR_LIF         BIT(0)          /* Line Interrupt Flag */
 172 #define ISR_FUIF        BIT(1)          /* Fifo Underrun Interrupt Flag */
 173 #define ISR_TERRIF      BIT(2)          /* Transfer ERRor Interrupt Flag */
 174 #define ISR_RRIF        BIT(3)          /* Register Reload Interrupt Flag */
 175
 176 #define EDCR_OCYEN      BIT(25)         /* Output Conversion to YCbCr 422: ENable */
 177 #define EDCR_OCYSEL     BIT(26)         /* Output Conversion to YCbCr 422: SELection of the CCIR */
 178 #define EDCR_OCYCO      BIT(27)         /* Output Conversion to YCbCr 422: Chrominance Order */
 179
 180 #define LXCR_LEN        BIT(0)          /* Layer ENable */
 181 #define LXCR_COLKEN     BIT(1)          /* Color Keying Enable */
 182 #define LXCR_CLUTEN     BIT(4)          /* Color Look-Up Table ENable */
 183
 184 #define LXWHPCR_WHSTPOS GENMASK(11, 0)  /* Window Horizontal StarT POSition */
 185 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
 186
 187 #define LXWVPCR_WVSTPOS GENMASK(10, 0)  /* Window Vertical StarT POSition */
 188 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
 189
 190 #define LXPFCR_PF       GENMASK(2, 0)   /* Pixel Format */
 191 #define PF_FLEXIBLE     0x7             /* Flexible Pixel Format selected */
 192
 193 #define LXCACR_CONSTA   GENMASK(7, 0)   /* CONSTant Alpha */
 194
 195 #define LXBFCR_BF2      GENMASK(2, 0)   /* Blending Factor 2 */
 196 #define LXBFCR_BF1      GENMASK(10, 8)  /* Blending Factor 1 */
 197
 198 #define LXCFBLR_CFBLL   GENMASK(12, 0)  /* Color Frame Buffer Line Length */
 199 #define LXCFBLR_CFBP    GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
 200
 201 #define LXCFBLNR_CFBLN  GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 202
 203 #define LXCR_C1R_YIA    BIT(0)          /* Ycbcr 422 Interleaved Ability */
 204 #define LXCR_C1R_YSPA   BIT(1)          /* Ycbcr 420 Semi-Planar Ability */
 205 #define LXCR_C1R_YFPA   BIT(2)          /* Ycbcr 420 Full-Planar Ability */
 206 #define LXCR_C1R_SCA    BIT(31)         /* SCaling Ability*/
 207
 208 #define LxPCR_YREN      BIT(9)          /* Y Rescale Enable for the color dynamic range */
 209 #define LxPCR_OF        BIT(8)          /* Odd pixel First */
 210 #define LxPCR_CBF       BIT(7)          /* CB component First */
 211 #define LxPCR_YF        BIT(6)          /* Y component First */
 212 #define LxPCR_YCM       GENMASK(5, 4)   /* Ycbcr Conversion Mode */
 213 #define YCM_I           0x0             /* Interleaved 422 */
 214 #define YCM_SP          0x1             /* Semi-Planar 420 */
 215 #define YCM_FP          0x2             /* Full-Planar 420 */
 216 #define LxPCR_YCEN      BIT(3)          /* YCbCr-to-RGB Conversion Enable */
 217
 218 #define LXRCR_IMR       BIT(0)          /* IMmediate Reload */
 219 #define LXRCR_VBR       BIT(1)          /* Vertical Blanking Reload */
 220 #define LXRCR_GRMSK     BIT(2)          /* Global (centralized) Reload MaSKed */
 221
 222 #define CLUT_SIZE       256
 223
 224 #define CONSTA_MAX      0xFF            /* CONSTant Alpha MAX= 1.0 */
 225 #define BF1_PAXCA       0x600           /* Pixel Alpha x Constant Alpha */
 226 #define BF1_CA          0x400           /* Constant Alpha */
 227 #define BF2_1PAXCA      0x007           /* 1 - (Pixel Alpha x Constant Alpha) */
 228 #define BF2_1CA         0x005           /* 1 - Constant Alpha */
 229
 230 #define NB_PF           8               /* Max nb of HW pixel format */
 231
 232 /*
 233  * Skip the first value and the second in case CRC was enabled during
 234  * the thread irq. This is to be sure CRC value is relevant for the
 235  * frame.
 236  */
 237 #define CRC_SKIP_FRAMES 2
 238
 239 enum ltdc_pix_fmt {
 240         PF_NONE,
 241         /* RGB formats */
 242         PF_ARGB8888,            /* ARGB [32 bits] */
 243         PF_RGBA8888,            /* RGBA [32 bits] */
 244         PF_ABGR8888,            /* ABGR [32 bits] */
 245         PF_BGRA8888,            /* BGRA [32 bits] */
 246         PF_RGB888,              /* RGB [24 bits] */
 247         PF_BGR888,              /* BGR [24 bits] */
 248         PF_RGB565,              /* RGB [16 bits] */
 249         PF_BGR565,              /* BGR [16 bits] */
 250         PF_ARGB1555,            /* ARGB A:1 bit RGB:15 bits [16 bits] */
 251         PF_ARGB4444,            /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
 252         /* Indexed formats */
 253         PF_L8,                  /* Indexed 8 bits [8 bits] */
 254         PF_AL44,                /* Alpha:4 bits + indexed 4 bits [8 bits] */
 255         PF_AL88                 /* Alpha:8 bits + indexed 8 bits [16 bits] */
 256 };
 257
 258 /* The index gives the encoding of the pixel format for an HW version */
 259 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
 260         PF_ARGB8888,            /* 0x00 */
 261         PF_RGB888,              /* 0x01 */
 262         PF_RGB565,              /* 0x02 */
 263         PF_ARGB1555,            /* 0x03 */
 264         PF_ARGB4444,            /* 0x04 */
 265         PF_L8,                  /* 0x05 */
 266         PF_AL44,                /* 0x06 */
 267         PF_AL88                 /* 0x07 */
 268 };
 269
 270 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
 271         PF_ARGB8888,            /* 0x00 */
 272         PF_RGB888,              /* 0x01 */
 273         PF_RGB565,              /* 0x02 */
 274         PF_RGBA8888,            /* 0x03 */
 275         PF_AL44,                /* 0x04 */
 276         PF_L8,                  /* 0x05 */
 277         PF_ARGB1555,            /* 0x06 */
 278         PF_ARGB4444             /* 0x07 */
 279 };
 280
 281 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = {
 282         PF_ARGB8888,            /* 0x00 */
 283         PF_ABGR8888,            /* 0x01 */
 284         PF_RGBA8888,            /* 0x02 */
 285         PF_BGRA8888,            /* 0x03 */
 286         PF_RGB565,              /* 0x04 */
 287         PF_BGR565,              /* 0x05 */
 288         PF_RGB888,              /* 0x06 */
 289         PF_NONE                 /* 0x07 */
 290 };
 291
 292 static const u32 ltdc_drm_fmt_a0[] = {
 293         DRM_FORMAT_ARGB8888,
 294         DRM_FORMAT_XRGB8888,
 295         DRM_FORMAT_RGB888,
 296         DRM_FORMAT_RGB565,
 297         DRM_FORMAT_ARGB1555,
 298         DRM_FORMAT_XRGB1555,
 299         DRM_FORMAT_ARGB4444,
 300         DRM_FORMAT_XRGB4444,
 301         DRM_FORMAT_C8
 302 };
 303
 304 static const u32 ltdc_drm_fmt_a1[] = {
 305         DRM_FORMAT_ARGB8888,
 306         DRM_FORMAT_XRGB8888,
 307         DRM_FORMAT_RGB888,
 308         DRM_FORMAT_RGB565,
 309         DRM_FORMAT_RGBA8888,
 310         DRM_FORMAT_RGBX8888,
 311         DRM_FORMAT_ARGB1555,
 312         DRM_FORMAT_XRGB1555,
 313         DRM_FORMAT_ARGB4444,
 314         DRM_FORMAT_XRGB4444,
 315         DRM_FORMAT_C8
 316 };
 317
 318 static const u32 ltdc_drm_fmt_a2[] = {
 319         DRM_FORMAT_ARGB8888,
 320         DRM_FORMAT_XRGB8888,
 321         DRM_FORMAT_ABGR8888,
 322         DRM_FORMAT_XBGR8888,
 323         DRM_FORMAT_RGBA8888,
 324         DRM_FORMAT_RGBX8888,
 325         DRM_FORMAT_BGRA8888,
 326         DRM_FORMAT_BGRX8888,
 327         DRM_FORMAT_RGB565,
 328         DRM_FORMAT_BGR565,
 329         DRM_FORMAT_RGB888,
 330         DRM_FORMAT_BGR888,
 331         DRM_FORMAT_ARGB1555,
 332         DRM_FORMAT_XRGB1555,
 333         DRM_FORMAT_ARGB4444,
 334         DRM_FORMAT_XRGB4444,
 335         DRM_FORMAT_C8
 336 };
 337
 338 static const u32 ltdc_drm_fmt_ycbcr_cp[] = {
 339         DRM_FORMAT_YUYV,
 340         DRM_FORMAT_YVYU,
 341         DRM_FORMAT_UYVY,
 342         DRM_FORMAT_VYUY
 343 };
 344
 345 static const u32 ltdc_drm_fmt_ycbcr_sp[] = {
 346         DRM_FORMAT_NV12,
 347         DRM_FORMAT_NV21
 348 };
 349
 350 static const u32 ltdc_drm_fmt_ycbcr_fp[] = {
 351         DRM_FORMAT_YUV420,
 352         DRM_FORMAT_YVU420
 353 };
 354
 355 /* Layer register offsets */
 356 static const u32 ltdc_layer_regs_a0[] = {
 357         0x80,   /* L1 configuration 0 */
 358         0x00,   /* not available */
 359         0x00,   /* not available */
 360         0x84,   /* L1 control register */
 361         0x88,   /* L1 window horizontal position configuration */
 362         0x8c,   /* L1 window vertical position configuration */
 363         0x90,   /* L1 color keying configuration */
 364         0x94,   /* L1 pixel format configuration */
 365         0x98,   /* L1 constant alpha configuration */
 366         0x9c,   /* L1 default color configuration */
 367         0xa0,   /* L1 blending factors configuration */
 368         0x00,   /* not available */
 369         0x00,   /* not available */
 370         0xac,   /* L1 color frame buffer address */
 371         0xb0,   /* L1 color frame buffer length */
 372         0xb4,   /* L1 color frame buffer line number */
 373         0x00,   /* not available */
 374         0x00,   /* not available */
 375         0x00,   /* not available */
 376         0x00,   /* not available */
 377         0xc4,   /* L1 CLUT write */
 378         0x00,   /* not available */
 379         0x00,   /* not available */
 380         0x00,   /* not available */
 381         0x00    /* not available */
 382 };
 383
 384 static const u32 ltdc_layer_regs_a1[] = {
 385         0x80,   /* L1 configuration 0 */
 386         0x84,   /* L1 configuration 1 */
 387         0x00,   /* L1 reload control */
 388         0x88,   /* L1 control register */
 389         0x8c,   /* L1 window horizontal position configuration */
 390         0x90,   /* L1 window vertical position configuration */
 391         0x94,   /* L1 color keying configuration */
 392         0x98,   /* L1 pixel format configuration */
 393         0x9c,   /* L1 constant alpha configuration */
 394         0xa0,   /* L1 default color configuration */
 395         0xa4,   /* L1 blending factors configuration */
 396         0xa8,   /* L1 burst length configuration */
 397         0x00,   /* not available */
 398         0xac,   /* L1 color frame buffer address */
 399         0xb0,   /* L1 color frame buffer length */
 400         0xb4,   /* L1 color frame buffer line number */
 401         0xb8,   /* L1 auxiliary frame buffer address 0 */
 402         0xbc,   /* L1 auxiliary frame buffer address 1 */
 403         0xc0,   /* L1 auxiliary frame buffer length */
 404         0xc4,   /* L1 auxiliary frame buffer line number */
 405         0xc8,   /* L1 CLUT write */
 406         0x00,   /* not available */
 407         0x00,   /* not available */
 408         0x00,   /* not available */
 409         0x00    /* not available */
 410 };
 411
 412 static const u32 ltdc_layer_regs_a2[] = {
 413         0x100,  /* L1 configuration 0 */
 414         0x104,  /* L1 configuration 1 */
 415         0x108,  /* L1 reload control */
 416         0x10c,  /* L1 control register */
 417         0x110,  /* L1 window horizontal position configuration */
 418         0x114,  /* L1 window vertical position configuration */
 419         0x118,  /* L1 color keying configuration */
 420         0x11c,  /* L1 pixel format configuration */
 421         0x120,  /* L1 constant alpha configuration */
 422         0x124,  /* L1 default color configuration */
 423         0x128,  /* L1 blending factors configuration */
 424         0x12c,  /* L1 burst length configuration */
 425         0x130,  /* L1 planar configuration */
 426         0x134,  /* L1 color frame buffer address */
 427         0x138,  /* L1 color frame buffer length */
 428         0x13c,  /* L1 color frame buffer line number */
 429         0x140,  /* L1 auxiliary frame buffer address 0 */
 430         0x144,  /* L1 auxiliary frame buffer address 1 */
 431         0x148,  /* L1 auxiliary frame buffer length */
 432         0x14c,  /* L1 auxiliary frame buffer line number */
 433         0x150,  /* L1 CLUT write */
 434         0x16c,  /* L1 Conversion YCbCr RGB 0 */
 435         0x170,  /* L1 Conversion YCbCr RGB 1 */
 436         0x174,  /* L1 Flexible Pixel Format 0 */
 437         0x178   /* L1 Flexible Pixel Format 1 */
 438 };
 439
 440 static const u64 ltdc_format_modifiers[] = {
 441         DRM_FORMAT_MOD_LINEAR,
 442         DRM_FORMAT_MOD_INVALID
 443 };
 444
 445 static const struct regmap_config stm32_ltdc_regmap_cfg = {
 446         .reg_bits = 32,
 447         .val_bits = 32,
 448         .reg_stride = sizeof(u32),
 449         .max_register = 0x400,
 450         .use_relaxed_mmio = true,
 451         .cache_type = REGCACHE_NONE,
 452 };
 453
 454 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = {
 455         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 456                 0x02040199,     /* (b_cb = 516 / r_cr = 409) */
 457                 0x006400D0      /* (g_cb = 100 / g_cr = 208) */
 458         },
 459         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
 460                 0x01C60167,     /* (b_cb = 454 / r_cr = 359) */
 461                 0x005800B7      /* (g_cb = 88 / g_cr = 183) */
 462         },
 463         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 464                 0x021D01CB,     /* (b_cb = 541 / r_cr = 459) */
 465                 0x00370089      /* (g_cb = 55 / g_cr = 137) */
 466         },
 467         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
 468                 0x01DB0193,     /* (b_cb = 475 / r_cr = 403) */
 469                 0x00300078      /* (g_cb = 48 / g_cr = 120) */
 470         }
 471         /* BT2020 not supported */
 472 };
 473
 474 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
 475 {
 476         return (struct ltdc_device *)crtc->dev->dev_private;
 477 }
 478
 479 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
 480 {
 481         return (struct ltdc_device *)plane->dev->dev_private;
 482 }
 483
 484 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
 485 {
 486         return (struct ltdc_device *)enc->dev->dev_private;
 487 }
 488
 489 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 490 {
 491         enum ltdc_pix_fmt pf;
 492
 493         switch (drm_fmt) {
 494         case DRM_FORMAT_ARGB8888:
 495         case DRM_FORMAT_XRGB8888:
 496                 pf = PF_ARGB8888;
 497                 break;
 498         case DRM_FORMAT_ABGR8888:
 499         case DRM_FORMAT_XBGR8888:
 500                 pf = PF_ABGR8888;
 501                 break;
 502         case DRM_FORMAT_RGBA8888:
 503         case DRM_FORMAT_RGBX8888:
 504                 pf = PF_RGBA8888;
 505                 break;
 506         case DRM_FORMAT_BGRA8888:
 507         case DRM_FORMAT_BGRX8888:
 508                 pf = PF_BGRA8888;
 509                 break;
 510         case DRM_FORMAT_RGB888:
 511                 pf = PF_RGB888;
 512                 break;
 513         case DRM_FORMAT_BGR888:
 514                 pf = PF_BGR888;
 515                 break;
 516         case DRM_FORMAT_RGB565:
 517                 pf = PF_RGB565;
 518                 break;
 519         case DRM_FORMAT_BGR565:
 520                 pf = PF_BGR565;
 521                 break;
 522         case DRM_FORMAT_ARGB1555:
 523         case DRM_FORMAT_XRGB1555:
 524                 pf = PF_ARGB1555;
 525                 break;
 526         case DRM_FORMAT_ARGB4444:
 527         case DRM_FORMAT_XRGB4444:
 528                 pf = PF_ARGB4444;
 529                 break;
 530         case DRM_FORMAT_C8:
 531                 pf = PF_L8;
 532                 break;
 533         default:
 534                 pf = PF_NONE;
 535                 break;
 536                 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
 537         }
 538
 539         return pf;
 540 }
 541
 542 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt)
 543 {
 544         struct ltdc_device *ldev = plane_to_ltdc(plane);
 545         u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE;
 546         int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos;
 547
 548         switch (pix_fmt) {
 549         case PF_BGR888:
 550                 psize = 3;
 551                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 552                 glen = 8; gpos = 8; blen = 8; bpos = 16;
 553         break;
 554         case PF_ARGB1555:
 555                 psize = 2;
 556                 alen = 1; apos = 15; rlen = 5; rpos = 10;
 557                 glen = 5; gpos = 5;  blen = 5; bpos = 0;
 558         break;
 559         case PF_ARGB4444:
 560                 psize = 2;
 561                 alen = 4; apos = 12; rlen = 4; rpos = 8;
 562                 glen = 4; gpos = 4; blen = 4; bpos = 0;
 563         break;
 564         case PF_L8:
 565                 psize = 1;
 566                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 567                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 568         break;
 569         case PF_AL44:
 570                 psize = 1;
 571                 alen = 4; apos = 4; rlen = 4; rpos = 0;
 572                 glen = 4; gpos = 0; blen = 4; bpos = 0;
 573         break;
 574         case PF_AL88:
 575                 psize = 2;
 576                 alen = 8; apos = 8; rlen = 8; rpos = 0;
 577                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 578         break;
 579         default:
 580                 ret = NB_PF; /* error case, trace msg is handled by the caller */
 581         break;
 582         }
 583
 584         if (ret == PF_FLEXIBLE) {
 585                 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
 586                              (rlen << 14)  + (rpos << 9) + (alen << 5) + apos);
 587
 588                 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
 589                              (psize << 18) + (blen << 14)  + (bpos << 9) + (glen << 5) + gpos);
 590         }
 591
 592         return ret;
 593 }
 594
 595 /*
 596  * All non-alpha color formats derived from native alpha color formats are
 597  * either characterized by a FourCC format code
 598  */
 599 static inline u32 is_xrgb(u32 drm)
 600 {
 601         return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
 602 }
 603
 604 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
 605 {
 606         struct ltdc_device *ldev = plane_to_ltdc(plane);
 607         struct drm_plane_state *state = plane->state;
 608         u32 lofs = plane->index * LAY_OFS;
 609         u32 val;
 610
 611         switch (drm_pix_fmt) {
 612         case DRM_FORMAT_YUYV:
 613                 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF;
 614                 break;
 615         case DRM_FORMAT_YVYU:
 616                 val = (YCM_I << 4) | LxPCR_YF;
 617                 break;
 618         case DRM_FORMAT_UYVY:
 619                 val = (YCM_I << 4) | LxPCR_CBF;
 620                 break;
 621         case DRM_FORMAT_VYUY:
 622                 val = (YCM_I << 4);
 623                 break;
 624         case DRM_FORMAT_NV12:
 625                 val = (YCM_SP << 4) | LxPCR_CBF;
 626                 break;
 627         case DRM_FORMAT_NV21:
 628                 val = (YCM_SP << 4);
 629                 break;
 630         case DRM_FORMAT_YUV420:
 631         case DRM_FORMAT_YVU420:
 632                 val = (YCM_FP << 4);
 633                 break;
 634         default:
 635                 /* RGB or not a YCbCr supported format */
 636                 DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt);
 637                 return;
 638         }
 639
 640         /* Enable limited range */
 641         if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
 642                 val |= LxPCR_YREN;
 643
 644         /* enable ycbcr conversion */
 645         val |= LxPCR_YCEN;
 646
 647         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val);
 648 }
 649
 650 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane)
 651 {
 652         struct ltdc_device *ldev = plane_to_ltdc(plane);
 653         struct drm_plane_state *state = plane->state;
 654         enum drm_color_encoding enc = state->color_encoding;
 655         enum drm_color_range ran = state->color_range;
 656         u32 lofs = plane->index * LAY_OFS;
 657
 658         if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) {
 659                 DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc);
 660                 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */
 661                 enc = DRM_COLOR_YCBCR_BT601;
 662         }
 663
 664         if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) {
 665                 DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
 666                 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
 667                 ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
 668         }
 669
 670         DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
 671         regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
 672                      ltdc_ycbcr2rgb_coeffs[enc][ran][0]);
 673         regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
 674                      ltdc_ycbcr2rgb_coeffs[enc][ran][1]);
 675 }
 676
 677 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev,
 678                                        struct drm_crtc *crtc)
 679 {
 680         u32 crc;
 681         int ret;
 682
 683         if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
 684                 ldev->crc_skip_count++;
 685                 return;
 686         }
 687
 688         /* Get the CRC of the frame */
 689         ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
 690         if (ret)
 691                 return;
 692
 693         /* Report to DRM the CRC (hw dependent feature) */
 694         drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc);
 695 }
 696
 697 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
 698 {
 699         struct drm_device *ddev = arg;
 700         struct ltdc_device *ldev = ddev->dev_private;
 701         struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
 702
 703         /* Line IRQ : trigger the vblank event */
 704         if (ldev->irq_status & ISR_LIF) {
 705                 drm_crtc_handle_vblank(crtc);
 706
 707                 /* Early return if CRC is not active */
 708                 if (ldev->crc_active)
 709                         ltdc_irq_crc_handle(ldev, crtc);
 710         }
 711
 712         /* Save FIFO Underrun & Transfer Error status */
 713         mutex_lock(&ldev->err_lock);
 714         if (ldev->irq_status & ISR_FUIF)
 715                 ldev->error_status |= ISR_FUIF;
 716         if (ldev->irq_status & ISR_TERRIF)
 717                 ldev->error_status |= ISR_TERRIF;
 718         mutex_unlock(&ldev->err_lock);
 719
 720         return IRQ_HANDLED;
 721 }
 722
 723 static irqreturn_t ltdc_irq(int irq, void *arg)
 724 {
 725         struct drm_device *ddev = arg;
 726         struct ltdc_device *ldev = ddev->dev_private;
 727
 728         /*
 729          *  Read & Clear the interrupt status
 730          *  In order to write / read registers in this critical section
 731          *  very quickly, the regmap functions are not used.
 732          */
 733         ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR);
 734         writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
 735
 736         return IRQ_WAKE_THREAD;
 737 }
 738
 739 /*
 740  * DRM_CRTC
 741  */
 742
 743 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
 744 {
 745         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 746         struct drm_color_lut *lut;
 747         u32 val;
 748         int i;
 749
 750         if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
 751                 return;
 752
 753         lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
 754
 755         for (i = 0; i < CLUT_SIZE; i++, lut++) {
 756                 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
 757                         (lut->blue >> 8) | (i << 24);
 758                 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val);
 759         }
 760 }
 761
 762 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
 763                                     struct drm_atomic_state *state)
 764 {
 765         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 766         struct drm_device *ddev = crtc->dev;
 767
 768         DRM_DEBUG_DRIVER("\n");
 769
 770         pm_runtime_get_sync(ddev->dev);
 771
 772         /* Sets the background color value */
 773         regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK);
 774
 775         /* Enable IRQ */
 776         regmap_set_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 777
 778         /* Commit shadow registers = update planes at next vblank */
 779         if (!ldev->caps.plane_reg_shadow)
 780                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
 781
 782         drm_crtc_vblank_on(crtc);
 783 }
 784
 785 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
 786                                      struct drm_atomic_state *state)
 787 {
 788         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 789         struct drm_device *ddev = crtc->dev;
 790
 791         DRM_DEBUG_DRIVER("\n");
 792
 793         drm_crtc_vblank_off(crtc);
 794
 795         /* disable IRQ */
 796         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 797
 798         /* immediately commit disable of layers before switching off LTDC */
 799         if (!ldev->caps.plane_reg_shadow)
 800                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
 801
 802         pm_runtime_put_sync(ddev->dev);
 803 }
 804
 805 #define CLK_TOLERANCE_HZ 50
 806
 807 static enum drm_mode_status
 808 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
 809                      const struct drm_display_mode *mode)
 810 {
 811         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 812         int target = mode->clock * 1000;
 813         int target_min = target - CLK_TOLERANCE_HZ;
 814         int target_max = target + CLK_TOLERANCE_HZ;
 815         int result;
 816
 817         result = clk_round_rate(ldev->pixel_clk, target);
 818
 819         DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
 820
 821         /* Filter modes according to the max frequency supported by the pads */
 822         if (result > ldev->caps.pad_max_freq_hz)
 823                 return MODE_CLOCK_HIGH;
 824
 825         /*
 826          * Accept all "preferred" modes:
 827          * - this is important for panels because panel clock tolerances are
 828          *   bigger than hdmi ones and there is no reason to not accept them
 829          *   (the fps may vary a little but it is not a problem).
 830          * - the hdmi preferred mode will be accepted too, but userland will
 831          *   be able to use others hdmi "valid" modes if necessary.
 832          */
 833         if (mode->type & DRM_MODE_TYPE_PREFERRED)
 834                 return MODE_OK;
 835
 836         /*
 837          * Filter modes according to the clock value, particularly useful for
 838          * hdmi modes that require precise pixel clocks.
 839          */
 840         if (result < target_min || result > target_max)
 841                 return MODE_CLOCK_RANGE;
 842
 843         return MODE_OK;
 844 }
 845
 846 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
 847                                  const struct drm_display_mode *mode,
 848                                  struct drm_display_mode *adjusted_mode)
 849 {
 850         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 851         int rate = mode->clock * 1000;
 852
 853         if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
 854                 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
 855                 return false;
 856         }
 857
 858         adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
 859
 860         DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
 861                          mode->clock, adjusted_mode->clock);
 862
 863         return true;
 864 }
 865
 866 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 867 {
 868         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 869         struct drm_device *ddev = crtc->dev;
 870         struct drm_connector_list_iter iter;
 871         struct drm_connector *connector = NULL;
 872         struct drm_encoder *encoder = NULL, *en_iter;
 873         struct drm_bridge *bridge = NULL, *br_iter;
 874         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 875         u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
 876         u32 total_width, total_height;
 877         u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24;
 878         u32 bus_flags = 0;
 879         u32 val;
 880         int ret;
 881
 882         /* get encoder from crtc */
 883         drm_for_each_encoder(en_iter, ddev)
 884                 if (en_iter->crtc == crtc) {
 885                         encoder = en_iter;
 886                         break;
 887                 }
 888
 889         if (encoder) {
 890                 /* get bridge from encoder */
 891                 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node)
 892                         if (br_iter->encoder == encoder) {
 893                                 bridge = br_iter;
 894                                 break;
 895                         }
 896
 897                 /* Get the connector from encoder */
 898                 drm_connector_list_iter_begin(ddev, &iter);
 899                 drm_for_each_connector_iter(connector, &iter)
 900                         if (connector->encoder == encoder)
 901                                 break;
 902                 drm_connector_list_iter_end(&iter);
 903         }
 904
 905         if (bridge && bridge->timings)
 906                 bus_flags = bridge->timings->input_bus_flags;
 907         else if (connector) {
 908                 bus_flags = connector->display_info.bus_flags;
 909                 if (connector->display_info.num_bus_formats)
 910                         bus_formats = connector->display_info.bus_formats[0];
 911         }
 912
 913         if (!pm_runtime_active(ddev->dev)) {
 914                 ret = pm_runtime_get_sync(ddev->dev);
 915                 if (ret) {
 916                         DRM_ERROR("Failed to set mode, cannot get sync\n");
 917                         return;
 918                 }
 919         }
 920
 921         DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
 922         DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay);
 923         DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
 924                          mode->hsync_start - mode->hdisplay,
 925                          mode->htotal - mode->hsync_end,
 926                          mode->hsync_end - mode->hsync_start,
 927                          mode->vsync_start - mode->vdisplay,
 928                          mode->vtotal - mode->vsync_end,
 929                          mode->vsync_end - mode->vsync_start);
 930
 931         /* Convert video timings to ltdc timings */
 932         hsync = mode->hsync_end - mode->hsync_start - 1;
 933         vsync = mode->vsync_end - mode->vsync_start - 1;
 934         accum_hbp = mode->htotal - mode->hsync_start - 1;
 935         accum_vbp = mode->vtotal - mode->vsync_start - 1;
 936         accum_act_w = accum_hbp + mode->hdisplay;
 937         accum_act_h = accum_vbp + mode->vdisplay;
 938         total_width = mode->htotal - 1;
 939         total_height = mode->vtotal - 1;
 940
 941         /* Configures the HS, VS, DE and PC polarities. Default Active Low */
 942         val = 0;
 943
 944         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 945                 val |= GCR_HSPOL;
 946
 947         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 948                 val |= GCR_VSPOL;
 949
 950         if (bus_flags & DRM_BUS_FLAG_DE_LOW)
 951                 val |= GCR_DEPOL;
 952
 953         if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 954                 val |= GCR_PCPOL;
 955
 956         regmap_update_bits(ldev->regmap, LTDC_GCR,
 957                            GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
 958
 959         /* Set Synchronization size */
 960         val = (hsync << 16) | vsync;
 961         regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
 962
 963         /* Set Accumulated Back porch */
 964         val = (accum_hbp << 16) | accum_vbp;
 965         regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
 966
 967         /* Set Accumulated Active Width */
 968         val = (accum_act_w << 16) | accum_act_h;
 969         regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
 970
 971         /* Set total width & height */
 972         val = (total_width << 16) | total_height;
 973         regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 974
 975         regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
 976
 977         /* Configure the output format (hw version dependent) */
 978         if (ldev->caps.ycbcr_output) {
 979                 /* Input video dynamic_range & colorimetry */
 980                 int vic = drm_match_cea_mode(mode);
 981                 u32 val;
 982
 983                 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||
 984                     vic == 2 || vic == 3 || vic == 17 || vic == 18)
 985                         /* ITU-R BT.601 */
 986                         val = 0;
 987                 else
 988                         /* ITU-R BT.709 */
 989                         val = EDCR_OCYSEL;
 990
 991                 switch (bus_formats) {
 992                 case MEDIA_BUS_FMT_YUYV8_1X16:
 993                         /* enable ycbcr output converter */
 994                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val);
 995                         break;
 996                 case MEDIA_BUS_FMT_YVYU8_1X16:
 997                         /* enable ycbcr output converter & invert chrominance order */
 998                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val);
 999                         break;
1000                 default:
1001                         /* disable ycbcr output converter */
1002                         regmap_write(ldev->regmap, LTDC_EDCR, 0);
1003                         break;
1004                 }
1005         }
1006 }
1007
1008 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
1009                                    struct drm_atomic_state *state)
1010 {
1011         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1012         struct drm_device *ddev = crtc->dev;
1013         struct drm_pending_vblank_event *event = crtc->state->event;
1014
1015         DRM_DEBUG_ATOMIC("\n");
1016
1017         ltdc_crtc_update_clut(crtc);
1018
1019         /* Commit shadow registers = update planes at next vblank */
1020         if (!ldev->caps.plane_reg_shadow)
1021                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
1022
1023         if (event) {
1024                 crtc->state->event = NULL;
1025
1026                 spin_lock_irq(&ddev->event_lock);
1027                 if (drm_crtc_vblank_get(crtc) == 0)
1028                         drm_crtc_arm_vblank_event(crtc, event);
1029                 else
1030                         drm_crtc_send_vblank_event(crtc, event);
1031                 spin_unlock_irq(&ddev->event_lock);
1032         }
1033 }
1034
1035 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
1036                                            bool in_vblank_irq,
1037                                            int *vpos, int *hpos,
1038                                            ktime_t *stime, ktime_t *etime,
1039                                            const struct drm_display_mode *mode)
1040 {
1041         struct drm_device *ddev = crtc->dev;
1042         struct ltdc_device *ldev = ddev->dev_private;
1043         int line, vactive_start, vactive_end, vtotal;
1044
1045         if (stime)
1046                 *stime = ktime_get();
1047
1048         /* The active area starts after vsync + front porch and ends
1049          * at vsync + front porc + display size.
1050          * The total height also include back porch.
1051          * We have 3 possible cases to handle:
1052          * - line < vactive_start: vpos = line - vactive_start and will be
1053          * negative
1054          * - vactive_start < line < vactive_end: vpos = line - vactive_start
1055          * and will be positive
1056          * - line > vactive_end: vpos = line - vtotal - vactive_start
1057          * and will negative
1058          *
1059          * Computation for the two first cases are identical so we can
1060          * simplify the code and only test if line > vactive_end
1061          */
1062         if (pm_runtime_active(ddev->dev)) {
1063                 regmap_read(ldev->regmap, LTDC_CPSR, &line);
1064                 line &= CPSR_CYPOS;
1065                 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start);
1066                 vactive_start &= BPCR_AVBP;
1067                 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end);
1068                 vactive_end &= AWCR_AAH;
1069                 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal);
1070                 vtotal &= TWCR_TOTALH;
1071
1072                 if (line > vactive_end)
1073                         *vpos = line - vtotal - vactive_start;
1074                 else
1075                         *vpos = line - vactive_start;
1076         } else {
1077                 *vpos = 0;
1078         }
1079
1080         *hpos = 0;
1081
1082         if (etime)
1083                 *etime = ktime_get();
1084
1085         return true;
1086 }
1087
1088 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
1089         .mode_valid = ltdc_crtc_mode_valid,
1090         .mode_fixup = ltdc_crtc_mode_fixup,
1091         .mode_set_nofb = ltdc_crtc_mode_set_nofb,
1092         .atomic_flush = ltdc_crtc_atomic_flush,
1093         .atomic_enable = ltdc_crtc_atomic_enable,
1094         .atomic_disable = ltdc_crtc_atomic_disable,
1095         .get_scanout_position = ltdc_crtc_get_scanout_position,
1096 };
1097
1098 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
1099 {
1100         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1101         struct drm_crtc_state *state = crtc->state;
1102
1103         DRM_DEBUG_DRIVER("\n");
1104
1105         if (state->enable)
1106                 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
1107         else
1108                 return -EPERM;
1109
1110         return 0;
1111 }
1112
1113 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
1114 {
1115         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1116
1117         DRM_DEBUG_DRIVER("\n");
1118         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
1119 }
1120
1121 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source)
1122 {
1123         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1124         int ret;
1125
1126         DRM_DEBUG_DRIVER("\n");
1127
1128         if (!crtc)
1129                 return -ENODEV;
1130
1131         if (source && strcmp(source, "auto") == 0) {
1132                 ldev->crc_active = true;
1133                 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1134         } else if (!source) {
1135                 ldev->crc_active = false;
1136                 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1137         } else {
1138                 ret = -EINVAL;
1139         }
1140
1141         ldev->crc_skip_count = 0;
1142         return ret;
1143 }
1144
1145 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc,
1146                                        const char *source, size_t *values_cnt)
1147 {
1148         DRM_DEBUG_DRIVER("\n");
1149
1150         if (!crtc)
1151                 return -ENODEV;
1152
1153         if (source && strcmp(source, "auto") != 0) {
1154                 DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n",
1155                                  source, crtc->name);
1156                 return -EINVAL;
1157         }
1158
1159         *values_cnt = 1;
1160         return 0;
1161 }
1162
1163 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
1164         .destroy = drm_crtc_cleanup,
1165         .set_config = drm_atomic_helper_set_config,
1166         .page_flip = drm_atomic_helper_page_flip,
1167         .reset = drm_atomic_helper_crtc_reset,
1168         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1169         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1170         .enable_vblank = ltdc_crtc_enable_vblank,
1171         .disable_vblank = ltdc_crtc_disable_vblank,
1172         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1173 };
1174
1175 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = {
1176         .destroy = drm_crtc_cleanup,
1177         .set_config = drm_atomic_helper_set_config,
1178         .page_flip = drm_atomic_helper_page_flip,
1179         .reset = drm_atomic_helper_crtc_reset,
1180         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1181         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1182         .enable_vblank = ltdc_crtc_enable_vblank,
1183         .disable_vblank = ltdc_crtc_disable_vblank,
1184         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1185         .set_crc_source = ltdc_crtc_set_crc_source,
1186         .verify_crc_source = ltdc_crtc_verify_crc_source,
1187 };
1188
1189 /*
1190  * DRM_PLANE
1191  */
1192
1193 static int ltdc_plane_atomic_check(struct drm_plane *plane,
1194                                    struct drm_atomic_state *state)
1195 {
1196         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1197                                                                                  plane);
1198         struct drm_framebuffer *fb = new_plane_state->fb;
1199         u32 src_w, src_h;
1200
1201         DRM_DEBUG_DRIVER("\n");
1202
1203         if (!fb)
1204                 return 0;
1205
1206         /* convert src_ from 16:16 format */
1207         src_w = new_plane_state->src_w >> 16;
1208         src_h = new_plane_state->src_h >> 16;
1209
1210         /* Reject scaling */
1211         if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
1212                 DRM_ERROR("Scaling is not supported");
1213                 return -EINVAL;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static void ltdc_plane_atomic_update(struct drm_plane *plane,
1220                                      struct drm_atomic_state *state)
1221 {
1222         struct ltdc_device *ldev = plane_to_ltdc(plane);
1223         struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
1224                                                                           plane);
1225         struct drm_framebuffer *fb = newstate->fb;
1226         u32 lofs = plane->index * LAY_OFS;
1227         u32 x0 = newstate->crtc_x;
1228         u32 x1 = newstate->crtc_x + newstate->crtc_w - 1;
1229         u32 y0 = newstate->crtc_y;
1230         u32 y1 = newstate->crtc_y + newstate->crtc_h - 1;
1231         u32 src_x, src_y, src_w, src_h;
1232         u32 val, pitch_in_bytes, line_length, line_number, paddr, ahbp, avbp, bpcr;
1233         enum ltdc_pix_fmt pf;
1234
1235         if (!newstate->crtc || !fb) {
1236                 DRM_DEBUG_DRIVER("fb or crtc NULL");
1237                 return;
1238         }
1239
1240         /* convert src_ from 16:16 format */
1241         src_x = newstate->src_x >> 16;
1242         src_y = newstate->src_y >> 16;
1243         src_w = newstate->src_w >> 16;
1244         src_h = newstate->src_h >> 16;
1245
1246         DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
1247                          plane->base.id, fb->base.id,
1248                          src_w, src_h, src_x, src_y,
1249                          newstate->crtc_w, newstate->crtc_h,
1250                          newstate->crtc_x, newstate->crtc_y);
1251
1252         regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
1253
1254         ahbp = (bpcr & BPCR_AHBP) >> 16;
1255         avbp = bpcr & BPCR_AVBP;
1256
1257         /* Configures the horizontal start and stop position */
1258         val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
1259         regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs,
1260                           LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
1261
1262         /* Configures the vertical start and stop position */
1263         val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
1264         regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs,
1265                           LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
1266
1267         /* Specifies the pixel format */
1268         pf = to_ltdc_pixelformat(fb->format->format);
1269         for (val = 0; val < NB_PF; val++)
1270                 if (ldev->caps.pix_fmt_hw[val] == pf)
1271                         break;
1272
1273         /* Use the flexible color format feature if necessary and available */
1274         if (ldev->caps.pix_fmt_flex && val == NB_PF)
1275                 val = ltdc_set_flexible_pixel_format(plane, pf);
1276
1277         if (val == NB_PF) {
1278                 DRM_ERROR("Pixel format %.4s not supported\n",
1279                           (char *)&fb->format->format);
1280                 val = 0;        /* set by default ARGB 32 bits */
1281         }
1282         regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
1283
1284         /* Configures the color frame buffer pitch in bytes & line length */
1285         pitch_in_bytes = fb->pitches[0];
1286         line_length = fb->format->cpp[0] *
1287                       (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
1288         val = ((pitch_in_bytes << 16) | line_length);
1289         regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
1290
1291         /* Specifies the constant alpha value */
1292         val = newstate->alpha >> 8;
1293         regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
1294
1295         /* Specifies the blending factors */
1296         val = BF1_PAXCA | BF2_1PAXCA;
1297         if (!fb->format->has_alpha)
1298                 val = BF1_CA | BF2_1CA;
1299
1300         /* Manage hw-specific capabilities */
1301         if (ldev->caps.non_alpha_only_l1 &&
1302             plane->type != DRM_PLANE_TYPE_PRIMARY)
1303                 val = BF1_PAXCA | BF2_1PAXCA;
1304
1305         regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, LXBFCR_BF2 | LXBFCR_BF1, val);
1306
1307         /* Configures the frame buffer line number */
1308         line_number = y1 - y0 + 1;
1309         regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number);
1310
1311         /* Sets the FB address */
1312         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 0);
1313
1314         DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
1315         regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
1316
1317         if (ldev->caps.ycbcr_input) {
1318                 if (fb->format->is_yuv) {
1319                         switch (fb->format->format) {
1320                         case DRM_FORMAT_NV12:
1321                         case DRM_FORMAT_NV21:
1322                         /* Configure the auxiliary frame buffer address 0 & 1 */
1323                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
1324                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr);
1325                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr + 1);
1326
1327                         /* Configure the buffer length */
1328                         val = ((pitch_in_bytes << 16) | line_length);
1329                         regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1330
1331                         /* Configure the frame buffer line number */
1332                         val = (line_number >> 1);
1333                         regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1334                         break;
1335                         case DRM_FORMAT_YUV420:
1336                         /* Configure the auxiliary frame buffer address 0 */
1337                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
1338                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr);
1339
1340                         /* Configure the auxiliary frame buffer address 1 */
1341                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2);
1342                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr);
1343
1344                         line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) +
1345                                       (ldev->caps.bus_width >> 3) - 1;
1346
1347                         /* Configure the buffer length */
1348                         val = (((pitch_in_bytes >> 1) << 16) | line_length);
1349                         regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1350
1351                         /* Configure the frame buffer line number */
1352                         val = (line_number >> 1);
1353                         regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1354                         break;
1355                         case DRM_FORMAT_YVU420:
1356                         /* Configure the auxiliary frame buffer address 0 */
1357                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2);
1358                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr);
1359
1360                         /* Configure the auxiliary frame buffer address 1 */
1361                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
1362                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr);
1363
1364                         line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) +
1365                                       (ldev->caps.bus_width >> 3) - 1;
1366
1367                         /* Configure the buffer length */
1368                         val = (((pitch_in_bytes >> 1) << 16) | line_length);
1369                         regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1370
1371                         /* Configure the frame buffer line number */
1372                         val = (line_number >> 1);
1373                         regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1374                         break;
1375                         }
1376
1377                         /* Configure YCbC conversion coefficient */
1378                         ltdc_set_ycbcr_coeffs(plane);
1379
1380                         /* Configure YCbCr format and enable/disable conversion */
1381                         ltdc_set_ycbcr_config(plane, fb->format->format);
1382                 } else {
1383                         /* disable ycbcr conversion */
1384                         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0);
1385                 }
1386         }
1387
1388         /* Enable layer and CLUT if needed */
1389         val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
1390         val |= LXCR_LEN;
1391         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN, val);
1392
1393         /* Commit shadow registers = update plane at next vblank */
1394         if (ldev->caps.plane_reg_shadow)
1395                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1396                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1397
1398         ldev->plane_fpsi[plane->index].counter++;
1399
1400         mutex_lock(&ldev->err_lock);
1401         if (ldev->error_status & ISR_FUIF) {
1402                 DRM_WARN("ltdc fifo underrun: please verify display mode\n");
1403                 ldev->error_status &= ~ISR_FUIF;
1404         }
1405         if (ldev->error_status & ISR_TERRIF) {
1406                 DRM_WARN("ltdc transfer error\n");
1407                 ldev->error_status &= ~ISR_TERRIF;
1408         }
1409         mutex_unlock(&ldev->err_lock);
1410 }
1411
1412 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
1413                                       struct drm_atomic_state *state)
1414 {
1415         struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
1416                                                                           plane);
1417         struct ltdc_device *ldev = plane_to_ltdc(plane);
1418         u32 lofs = plane->index * LAY_OFS;
1419
1420         /* disable layer */
1421         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN, 0);
1422
1423         /* Commit shadow registers = update plane at next vblank */
1424         if (ldev->caps.plane_reg_shadow)
1425                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1426                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1427
1428         DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
1429                          oldstate->crtc->base.id, plane->base.id);
1430 }
1431
1432 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
1433                                           const struct drm_plane_state *state)
1434 {
1435         struct drm_plane *plane = state->plane;
1436         struct ltdc_device *ldev = plane_to_ltdc(plane);
1437         struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
1438         int ms_since_last;
1439         ktime_t now;
1440
1441         now = ktime_get();
1442         ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
1443
1444         drm_printf(p, "\tuser_updates=%dfps\n",
1445                    DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
1446
1447         fpsi->last_timestamp = now;
1448         fpsi->counter = 0;
1449 }
1450
1451 static const struct drm_plane_funcs ltdc_plane_funcs = {
1452         .update_plane = drm_atomic_helper_update_plane,
1453         .disable_plane = drm_atomic_helper_disable_plane,
1454         .destroy = drm_plane_cleanup,
1455         .reset = drm_atomic_helper_plane_reset,
1456         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1457         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1458         .atomic_print_state = ltdc_plane_atomic_print_state,
1459 };
1460
1461 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
1462         .atomic_check = ltdc_plane_atomic_check,
1463         .atomic_update = ltdc_plane_atomic_update,
1464         .atomic_disable = ltdc_plane_atomic_disable,
1465 };
1466
1467 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
1468                                            enum drm_plane_type type,
1469                                            int index)
1470 {
1471         unsigned long possible_crtcs = CRTC_MASK;
1472         struct ltdc_device *ldev = ddev->dev_private;
1473         struct device *dev = ddev->dev;
1474         struct drm_plane *plane;
1475         unsigned int i, nb_fmt = 0;
1476         u32 *formats;
1477         u32 drm_fmt;
1478         const u64 *modifiers = ltdc_format_modifiers;
1479         u32 lofs = index * LAY_OFS;
1480         u32 val;
1481         int ret;
1482
1483         /* Allocate the biggest size according to supported color formats */
1484         formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
1485                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) +
1486                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) +
1487                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) *
1488                                sizeof(*formats), GFP_KERNEL);
1489
1490         for (i = 0; i < ldev->caps.pix_fmt_nb; i++) {
1491                 drm_fmt = ldev->caps.pix_fmt_drm[i];
1492
1493                 /* Manage hw-specific capabilities */
1494                 if (ldev->caps.non_alpha_only_l1)
1495                         /* XR24 & RX24 like formats supported only on primary layer */
1496                         if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt))
1497                                 continue;
1498
1499                 formats[nb_fmt++] = drm_fmt;
1500         }
1501
1502         /* Add YCbCr supported pixel formats */
1503         if (ldev->caps.ycbcr_input) {
1504                 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
1505                 if (val & LXCR_C1R_YIA) {
1506                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp,
1507                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats));
1508                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp);
1509                 }
1510                 if (val & LXCR_C1R_YSPA) {
1511                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp,
1512                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats));
1513                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp);
1514                 }
1515                 if (val & LXCR_C1R_YFPA) {
1516                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp,
1517                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats));
1518                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp);
1519                 }
1520         }
1521
1522         plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
1523         if (!plane)
1524                 return NULL;
1525
1526         ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
1527                                        &ltdc_plane_funcs, formats, nb_fmt,
1528                                        modifiers, type, NULL);
1529         if (ret < 0)
1530                 return NULL;
1531
1532         if (ldev->caps.ycbcr_input) {
1533                 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA))
1534                         drm_plane_create_color_properties(plane,
1535                                                           BIT(DRM_COLOR_YCBCR_BT601) |
1536                                                           BIT(DRM_COLOR_YCBCR_BT709),
1537                                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1538                                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1539                                                           DRM_COLOR_YCBCR_BT601,
1540                                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1541         }
1542
1543         drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
1544
1545         drm_plane_create_alpha_property(plane);
1546
1547         DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
1548
1549         return plane;
1550 }
1551
1552 static void ltdc_plane_destroy_all(struct drm_device *ddev)
1553 {
1554         struct drm_plane *plane, *plane_temp;
1555
1556         list_for_each_entry_safe(plane, plane_temp,
1557                                  &ddev->mode_config.plane_list, head)
1558                 drm_plane_cleanup(plane);
1559 }
1560
1561 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
1562 {
1563         struct ltdc_device *ldev = ddev->dev_private;
1564         struct drm_plane *primary, *overlay;
1565         unsigned int i;
1566         int ret;
1567
1568         primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0);
1569         if (!primary) {
1570                 DRM_ERROR("Can not create primary plane\n");
1571                 return -EINVAL;
1572         }
1573
1574         drm_plane_create_zpos_immutable_property(primary, 0);
1575
1576         /* Init CRTC according to its hardware features */
1577         if (ldev->caps.crc)
1578                 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1579                                                 &ltdc_crtc_with_crc_support_funcs, NULL);
1580         else
1581                 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1582                                                 &ltdc_crtc_funcs, NULL);
1583         if (ret) {
1584                 DRM_ERROR("Can not initialize CRTC\n");
1585                 goto cleanup;
1586         }
1587
1588         drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
1589
1590         drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1591         drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1592
1593         DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1594
1595         /* Add planes. Note : the first layer is used by primary plane */
1596         for (i = 1; i < ldev->caps.nb_layers; i++) {
1597                 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i);
1598                 if (!overlay) {
1599                         ret = -ENOMEM;
1600                         DRM_ERROR("Can not create overlay plane %d\n", i);
1601                         goto cleanup;
1602                 }
1603                 drm_plane_create_zpos_immutable_property(overlay, i);
1604         }
1605
1606         return 0;
1607
1608 cleanup:
1609         ltdc_plane_destroy_all(ddev);
1610         return ret;
1611 }
1612
1613 static void ltdc_encoder_disable(struct drm_encoder *encoder)
1614 {
1615         struct drm_device *ddev = encoder->dev;
1616         struct ltdc_device *ldev = ddev->dev_private;
1617
1618         DRM_DEBUG_DRIVER("\n");
1619
1620         /* Disable LTDC */
1621         regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1622
1623         /* Set to sleep state the pinctrl whatever type of encoder */
1624         pinctrl_pm_select_sleep_state(ddev->dev);
1625 }
1626
1627 static void ltdc_encoder_enable(struct drm_encoder *encoder)
1628 {
1629         struct drm_device *ddev = encoder->dev;
1630         struct ltdc_device *ldev = ddev->dev_private;
1631
1632         DRM_DEBUG_DRIVER("\n");
1633
1634         /* Enable LTDC */
1635         regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1636 }
1637
1638 static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
1639                                   struct drm_display_mode *mode,
1640                                   struct drm_display_mode *adjusted_mode)
1641 {
1642         struct drm_device *ddev = encoder->dev;
1643
1644         DRM_DEBUG_DRIVER("\n");
1645
1646         /*
1647          * Set to default state the pinctrl only with DPI type.
1648          * Others types like DSI, don't need pinctrl due to
1649          * internal bridge (the signals do not come out of the chipset).
1650          */
1651         if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
1652                 pinctrl_pm_select_default_state(ddev->dev);
1653 }
1654
1655 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
1656         .disable = ltdc_encoder_disable,
1657         .enable = ltdc_encoder_enable,
1658         .mode_set = ltdc_encoder_mode_set,
1659 };
1660
1661 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
1662 {
1663         struct drm_encoder *encoder;
1664         int ret;
1665
1666         encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
1667         if (!encoder)
1668                 return -ENOMEM;
1669
1670         encoder->possible_crtcs = CRTC_MASK;
1671         encoder->possible_clones = 0;   /* No cloning support */
1672
1673         drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI);
1674
1675         drm_encoder_helper_add(encoder, &ltdc_encoder_helper_funcs);
1676
1677         ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1678         if (ret) {
1679                 if (ret != -EPROBE_DEFER)
1680                         drm_encoder_cleanup(encoder);
1681                 return ret;
1682         }
1683
1684         DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1685
1686         return 0;
1687 }
1688
1689 static int ltdc_get_caps(struct drm_device *ddev)
1690 {
1691         struct ltdc_device *ldev = ddev->dev_private;
1692         u32 bus_width_log2, lcr, gc2r;
1693
1694         /*
1695          * at least 1 layer must be managed & the number of layers
1696          * must not exceed LTDC_MAX_LAYER
1697          */
1698         regmap_read(ldev->regmap, LTDC_LCR, &lcr);
1699
1700         ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1701
1702         /* set data bus width */
1703         regmap_read(ldev->regmap, LTDC_GC2R, &gc2r);
1704         bus_width_log2 = (gc2r & GC2R_BW) >> 4;
1705         ldev->caps.bus_width = 8 << bus_width_log2;
1706         regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
1707
1708         switch (ldev->caps.hw_version) {
1709         case HWVER_10200:
1710         case HWVER_10300:
1711                 ldev->caps.layer_ofs = LAY_OFS_0;
1712                 ldev->caps.layer_regs = ltdc_layer_regs_a0;
1713                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1714                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0;
1715                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0);
1716                 ldev->caps.pix_fmt_flex = false;
1717                 /*
1718                  * Hw older versions support non-alpha color formats derived
1719                  * from native alpha color formats only on the primary layer.
1720                  * For instance, RG16 native format without alpha works fine
1721                  * on 2nd layer but XR24 (derived color format from AR24)
1722                  * does not work on 2nd layer.
1723                  */
1724                 ldev->caps.non_alpha_only_l1 = true;
1725                 ldev->caps.pad_max_freq_hz = 90000000;
1726                 if (ldev->caps.hw_version == HWVER_10200)
1727                         ldev->caps.pad_max_freq_hz = 65000000;
1728                 ldev->caps.nb_irq = 2;
1729                 ldev->caps.ycbcr_input = false;
1730                 ldev->caps.ycbcr_output = false;
1731                 ldev->caps.plane_reg_shadow = false;
1732                 ldev->caps.crc = false;
1733                 break;
1734         case HWVER_20101:
1735                 ldev->caps.layer_ofs = LAY_OFS_0;
1736                 ldev->caps.layer_regs = ltdc_layer_regs_a1;
1737                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1738                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1;
1739                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1);
1740                 ldev->caps.pix_fmt_flex = false;
1741                 ldev->caps.non_alpha_only_l1 = false;
1742                 ldev->caps.pad_max_freq_hz = 150000000;
1743                 ldev->caps.nb_irq = 4;
1744                 ldev->caps.ycbcr_input = false;
1745                 ldev->caps.ycbcr_output = false;
1746                 ldev->caps.plane_reg_shadow = false;
1747                 ldev->caps.crc = false;
1748                 break;
1749         case HWVER_40100:
1750                 ldev->caps.layer_ofs = LAY_OFS_1;
1751                 ldev->caps.layer_regs = ltdc_layer_regs_a2;
1752                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
1753                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2;
1754                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
1755                 ldev->caps.pix_fmt_flex = true;
1756                 ldev->caps.non_alpha_only_l1 = false;
1757                 ldev->caps.pad_max_freq_hz = 90000000;
1758                 ldev->caps.nb_irq = 2;
1759                 ldev->caps.ycbcr_input = true;
1760                 ldev->caps.ycbcr_output = true;
1761                 ldev->caps.plane_reg_shadow = true;
1762                 ldev->caps.crc = true;
1763                 break;
1764         default:
1765                 return -ENODEV;
1766         }
1767
1768         return 0;
1769 }
1770
1771 void ltdc_suspend(struct drm_device *ddev)
1772 {
1773         struct ltdc_device *ldev = ddev->dev_private;
1774
1775         DRM_DEBUG_DRIVER("\n");
1776         clk_disable_unprepare(ldev->pixel_clk);
1777 }
1778
1779 int ltdc_resume(struct drm_device *ddev)
1780 {
1781         struct ltdc_device *ldev = ddev->dev_private;
1782         int ret;
1783
1784         DRM_DEBUG_DRIVER("\n");
1785
1786         ret = clk_prepare_enable(ldev->pixel_clk);
1787         if (ret) {
1788                 DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1789                 return ret;
1790         }
1791
1792         return 0;
1793 }
1794
1795 int ltdc_load(struct drm_device *ddev)
1796 {
1797         struct platform_device *pdev = to_platform_device(ddev->dev);
1798         struct ltdc_device *ldev = ddev->dev_private;
1799         struct device *dev = ddev->dev;
1800         struct device_node *np = dev->of_node;
1801         struct drm_bridge *bridge;
1802         struct drm_panel *panel;
1803         struct drm_crtc *crtc;
1804         struct reset_control *rstc;
1805         struct resource *res;
1806         int irq, i, nb_endpoints;
1807         int ret = -ENODEV;
1808
1809         DRM_DEBUG_DRIVER("\n");
1810
1811         /* Get number of endpoints */
1812         nb_endpoints = of_graph_get_endpoint_count(np);
1813         if (!nb_endpoints)
1814                 return -ENODEV;
1815
1816         ldev->pixel_clk = devm_clk_get(dev, "lcd");
1817         if (IS_ERR(ldev->pixel_clk)) {
1818                 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1819                         DRM_ERROR("Unable to get lcd clock\n");
1820                 return PTR_ERR(ldev->pixel_clk);
1821         }
1822
1823         if (clk_prepare_enable(ldev->pixel_clk)) {
1824                 DRM_ERROR("Unable to prepare pixel clock\n");
1825                 return -ENODEV;
1826         }
1827
1828         /* Get endpoints if any */
1829         for (i = 0; i < nb_endpoints; i++) {
1830                 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
1831
1832                 /*
1833                  * If at least one endpoint is -ENODEV, continue probing,
1834                  * else if at least one endpoint returned an error
1835                  * (ie -EPROBE_DEFER) then stop probing.
1836                  */
1837                 if (ret == -ENODEV)
1838                         continue;
1839                 else if (ret)
1840                         goto err;
1841
1842                 if (panel) {
1843                         bridge = drm_panel_bridge_add_typed(panel,
1844                                                             DRM_MODE_CONNECTOR_DPI);
1845                         if (IS_ERR(bridge)) {
1846                                 DRM_ERROR("panel-bridge endpoint %d\n", i);
1847                                 ret = PTR_ERR(bridge);
1848                                 goto err;
1849                         }
1850                 }
1851
1852                 if (bridge) {
1853                         ret = ltdc_encoder_init(ddev, bridge);
1854                         if (ret) {
1855                                 if (ret != -EPROBE_DEFER)
1856                                         DRM_ERROR("init encoder endpoint %d\n", i);
1857                                 goto err;
1858                         }
1859                 }
1860         }
1861
1862         rstc = devm_reset_control_get_exclusive(dev, NULL);
1863
1864         mutex_init(&ldev->err_lock);
1865
1866         if (!IS_ERR(rstc)) {
1867                 reset_control_assert(rstc);
1868                 usleep_range(10, 20);
1869                 reset_control_deassert(rstc);
1870         }
1871
1872         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1873         ldev->regs = devm_ioremap_resource(dev, res);
1874         if (IS_ERR(ldev->regs)) {
1875                 DRM_ERROR("Unable to get ltdc registers\n");
1876                 ret = PTR_ERR(ldev->regs);
1877                 goto err;
1878         }
1879
1880         ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
1881         if (IS_ERR(ldev->regmap)) {
1882                 DRM_ERROR("Unable to regmap ltdc registers\n");
1883                 ret = PTR_ERR(ldev->regmap);
1884                 goto err;
1885         }
1886
1887         /* Disable interrupts */
1888         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1889
1890         ret = ltdc_get_caps(ddev);
1891         if (ret) {
1892                 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1893                           ldev->caps.hw_version);
1894                 goto err;
1895         }
1896
1897         DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1898
1899         for (i = 0; i < ldev->caps.nb_irq; i++) {
1900                 irq = platform_get_irq(pdev, i);
1901                 if (irq < 0) {
1902                         ret = irq;
1903                         goto err;
1904                 }
1905
1906                 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1907                                                 ltdc_irq_thread, IRQF_ONESHOT,
1908                                                 dev_name(dev), ddev);
1909                 if (ret) {
1910                         DRM_ERROR("Failed to register LTDC interrupt\n");
1911                         goto err;
1912                 }
1913
1914         }
1915
1916         crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1917         if (!crtc) {
1918                 DRM_ERROR("Failed to allocate crtc\n");
1919                 ret = -ENOMEM;
1920                 goto err;
1921         }
1922
1923         ret = ltdc_crtc_init(ddev, crtc);
1924         if (ret) {
1925                 DRM_ERROR("Failed to init crtc\n");
1926                 goto err;
1927         }
1928
1929         ret = drm_vblank_init(ddev, NB_CRTC);
1930         if (ret) {
1931                 DRM_ERROR("Failed calling drm_vblank_init()\n");
1932                 goto err;
1933         }
1934
1935         clk_disable_unprepare(ldev->pixel_clk);
1936
1937         pinctrl_pm_select_sleep_state(ddev->dev);
1938
1939         pm_runtime_enable(ddev->dev);
1940
1941         return 0;
1942 err:
1943         for (i = 0; i < nb_endpoints; i++)
1944                 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1945
1946         clk_disable_unprepare(ldev->pixel_clk);
1947
1948         return ret;
1949 }
1950
1951 void ltdc_unload(struct drm_device *ddev)
1952 {
1953         struct device *dev = ddev->dev;
1954         int nb_endpoints, i;
1955
1956         DRM_DEBUG_DRIVER("\n");
1957
1958         nb_endpoints = of_graph_get_endpoint_count(dev->of_node);
1959
1960         for (i = 0; i < nb_endpoints; i++)
1961                 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1962
1963         pm_runtime_disable(ddev->dev);
1964 }
1965
1966 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1967 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1968 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1969 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1970 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1971 MODULE_LICENSE("GPL v2");