drivers/gpu/drm/sti/sti_hdmi.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
   4  * License terms:  GNU General Public License (GPL), version 2
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/module.h>
  12 #include <linux/of_gpio.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_edid.h>
  20
  21 #include <sound/hdmi-codec.h>
  22
  23 #include "sti_hdmi.h"
  24 #include "sti_hdmi_tx3g4c28phy.h"
  25 #include "sti_vtg.h"
  26
  27 #define HDMI_CFG                        0x0000
  28 #define HDMI_INT_EN                     0x0004
  29 #define HDMI_INT_STA                    0x0008
  30 #define HDMI_INT_CLR                    0x000C
  31 #define HDMI_STA                        0x0010
  32 #define HDMI_ACTIVE_VID_XMIN            0x0100
  33 #define HDMI_ACTIVE_VID_XMAX            0x0104
  34 #define HDMI_ACTIVE_VID_YMIN            0x0108
  35 #define HDMI_ACTIVE_VID_YMAX            0x010C
  36 #define HDMI_DFLT_CHL0_DAT              0x0110
  37 #define HDMI_DFLT_CHL1_DAT              0x0114
  38 #define HDMI_DFLT_CHL2_DAT              0x0118
  39 #define HDMI_AUDIO_CFG                  0x0200
  40 #define HDMI_SPDIF_FIFO_STATUS          0x0204
  41 #define HDMI_SW_DI_1_HEAD_WORD          0x0210
  42 #define HDMI_SW_DI_1_PKT_WORD0          0x0214
  43 #define HDMI_SW_DI_1_PKT_WORD1          0x0218
  44 #define HDMI_SW_DI_1_PKT_WORD2          0x021C
  45 #define HDMI_SW_DI_1_PKT_WORD3          0x0220
  46 #define HDMI_SW_DI_1_PKT_WORD4          0x0224
  47 #define HDMI_SW_DI_1_PKT_WORD5          0x0228
  48 #define HDMI_SW_DI_1_PKT_WORD6          0x022C
  49 #define HDMI_SW_DI_CFG                  0x0230
  50 #define HDMI_SAMPLE_FLAT_MASK           0x0244
  51 #define HDMI_AUDN                       0x0400
  52 #define HDMI_AUD_CTS                    0x0404
  53 #define HDMI_SW_DI_2_HEAD_WORD          0x0600
  54 #define HDMI_SW_DI_2_PKT_WORD0          0x0604
  55 #define HDMI_SW_DI_2_PKT_WORD1          0x0608
  56 #define HDMI_SW_DI_2_PKT_WORD2          0x060C
  57 #define HDMI_SW_DI_2_PKT_WORD3          0x0610
  58 #define HDMI_SW_DI_2_PKT_WORD4          0x0614
  59 #define HDMI_SW_DI_2_PKT_WORD5          0x0618
  60 #define HDMI_SW_DI_2_PKT_WORD6          0x061C
  61 #define HDMI_SW_DI_3_HEAD_WORD          0x0620
  62 #define HDMI_SW_DI_3_PKT_WORD0          0x0624
  63 #define HDMI_SW_DI_3_PKT_WORD1          0x0628
  64 #define HDMI_SW_DI_3_PKT_WORD2          0x062C
  65 #define HDMI_SW_DI_3_PKT_WORD3          0x0630
  66 #define HDMI_SW_DI_3_PKT_WORD4          0x0634
  67 #define HDMI_SW_DI_3_PKT_WORD5          0x0638
  68 #define HDMI_SW_DI_3_PKT_WORD6          0x063C
  69
  70 #define HDMI_IFRAME_SLOT_AVI            1
  71 #define HDMI_IFRAME_SLOT_AUDIO          2
  72 #define HDMI_IFRAME_SLOT_VENDOR         3
  73
  74 #define  XCAT(prefix, x, suffix)        prefix ## x ## suffix
  75 #define  HDMI_SW_DI_N_HEAD_WORD(x)      XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  76 #define  HDMI_SW_DI_N_PKT_WORD0(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  77 #define  HDMI_SW_DI_N_PKT_WORD1(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  78 #define  HDMI_SW_DI_N_PKT_WORD2(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  79 #define  HDMI_SW_DI_N_PKT_WORD3(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  80 #define  HDMI_SW_DI_N_PKT_WORD4(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  81 #define  HDMI_SW_DI_N_PKT_WORD5(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  82 #define  HDMI_SW_DI_N_PKT_WORD6(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  83
  84 #define HDMI_SW_DI_MAX_WORD             7
  85
  86 #define HDMI_IFRAME_DISABLED            0x0
  87 #define HDMI_IFRAME_SINGLE_SHOT         0x1
  88 #define HDMI_IFRAME_FIELD               0x2
  89 #define HDMI_IFRAME_FRAME               0x3
  90 #define HDMI_IFRAME_MASK                0x3
  91 #define HDMI_IFRAME_CFG_DI_N(x, n)       ((x) << ((n-1)*4)) /* n from 1 to 6 */
  92
  93 #define HDMI_CFG_DEVICE_EN              BIT(0)
  94 #define HDMI_CFG_HDMI_NOT_DVI           BIT(1)
  95 #define HDMI_CFG_HDCP_EN                BIT(2)
  96 #define HDMI_CFG_ESS_NOT_OESS           BIT(3)
  97 #define HDMI_CFG_H_SYNC_POL_NEG         BIT(4)
  98 #define HDMI_CFG_V_SYNC_POL_NEG         BIT(6)
  99 #define HDMI_CFG_422_EN                 BIT(8)
 100 #define HDMI_CFG_FIFO_OVERRUN_CLR       BIT(12)
 101 #define HDMI_CFG_FIFO_UNDERRUN_CLR      BIT(13)
 102 #define HDMI_CFG_SW_RST_EN              BIT(31)
 103
 104 #define HDMI_INT_GLOBAL                 BIT(0)
 105 #define HDMI_INT_SW_RST                 BIT(1)
 106 #define HDMI_INT_PIX_CAP                BIT(3)
 107 #define HDMI_INT_HOT_PLUG               BIT(4)
 108 #define HDMI_INT_DLL_LCK                BIT(5)
 109 #define HDMI_INT_NEW_FRAME              BIT(6)
 110 #define HDMI_INT_GENCTRL_PKT            BIT(7)
 111 #define HDMI_INT_AUDIO_FIFO_XRUN        BIT(8)
 112 #define HDMI_INT_SINK_TERM_PRESENT      BIT(11)
 113
 114 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
 115                         | HDMI_INT_DLL_LCK \
 116                         | HDMI_INT_HOT_PLUG \
 117                         | HDMI_INT_GLOBAL)
 118
 119 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
 120                         | HDMI_INT_AUDIO_FIFO_XRUN \
 121                         | HDMI_INT_GENCTRL_PKT \
 122                         | HDMI_INT_NEW_FRAME \
 123                         | HDMI_INT_DLL_LCK \
 124                         | HDMI_INT_HOT_PLUG \
 125                         | HDMI_INT_PIX_CAP \
 126                         | HDMI_INT_SW_RST \
 127                         | HDMI_INT_GLOBAL)
 128
 129 #define HDMI_STA_SW_RST                 BIT(1)
 130
 131 #define HDMI_AUD_CFG_8CH                BIT(0)
 132 #define HDMI_AUD_CFG_SPDIF_DIV_2        BIT(1)
 133 #define HDMI_AUD_CFG_SPDIF_DIV_3        BIT(2)
 134 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4    (BIT(1) | BIT(2))
 135 #define HDMI_AUD_CFG_CTS_CLK_256FS      BIT(12)
 136 #define HDMI_AUD_CFG_DTS_INVALID        BIT(16)
 137 #define HDMI_AUD_CFG_ONE_BIT_INVALID    (BIT(18) | BIT(19) | BIT(20) |  BIT(21))
 138 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
 139 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
 140 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
 141 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
 142
 143 /* sample flat mask */
 144 #define HDMI_SAMPLE_FLAT_NO      0
 145 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
 146 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
 147 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
 148 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
 149 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
 150                               HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
 151
 152 #define HDMI_INFOFRAME_HEADER_TYPE(x)    (((x) & 0xff) <<  0)
 153 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) <<  8)
 154 #define HDMI_INFOFRAME_HEADER_LEN(x)     (((x) & 0x0f) << 16)
 155
 156 struct sti_hdmi_connector {
 157         struct drm_connector drm_connector;
 158         struct drm_encoder *encoder;
 159         struct sti_hdmi *hdmi;
 160         struct drm_property *colorspace_property;
 161 };
 162
 163 #define to_sti_hdmi_connector(x) \
 164         container_of(x, struct sti_hdmi_connector, drm_connector)
 165
 166 u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
 167 {
 168         return readl(hdmi->regs + offset);
 169 }
 170
 171 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
 172 {
 173         writel(val, hdmi->regs + offset);
 174 }
 175
 176 /**
 177  * HDMI interrupt handler threaded
 178  *
 179  * @irq: irq number
 180  * @arg: connector structure
 181  */
 182 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
 183 {
 184         struct sti_hdmi *hdmi = arg;
 185
 186         /* Hot plug/unplug IRQ */
 187         if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
 188                 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
 189                 if (hdmi->drm_dev)
 190                         drm_helper_hpd_irq_event(hdmi->drm_dev);
 191         }
 192
 193         /* Sw reset and PLL lock are exclusive so we can use the same
 194          * event to signal them
 195          */
 196         if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
 197                 hdmi->event_received = true;
 198                 wake_up_interruptible(&hdmi->wait_event);
 199         }
 200
 201         /* Audio FIFO underrun IRQ */
 202         if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
 203                 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
 204
 205         return IRQ_HANDLED;
 206 }
 207
 208 /**
 209  * HDMI interrupt handler
 210  *
 211  * @irq: irq number
 212  * @arg: connector structure
 213  */
 214 static irqreturn_t hdmi_irq(int irq, void *arg)
 215 {
 216         struct sti_hdmi *hdmi = arg;
 217
 218         /* read interrupt status */
 219         hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
 220
 221         /* clear interrupt status */
 222         hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
 223
 224         /* force sync bus write */
 225         hdmi_read(hdmi, HDMI_INT_STA);
 226
 227         return IRQ_WAKE_THREAD;
 228 }
 229
 230 /**
 231  * Set hdmi active area depending on the drm display mode selected
 232  *
 233  * @hdmi: pointer on the hdmi internal structure
 234  */
 235 static void hdmi_active_area(struct sti_hdmi *hdmi)
 236 {
 237         u32 xmin, xmax;
 238         u32 ymin, ymax;
 239
 240         xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
 241         xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
 242         ymin = sti_vtg_get_line_number(hdmi->mode, 0);
 243         ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
 244
 245         hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
 246         hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
 247         hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
 248         hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
 249 }
 250
 251 /**
 252  * Overall hdmi configuration
 253  *
 254  * @hdmi: pointer on the hdmi internal structure
 255  */
 256 static void hdmi_config(struct sti_hdmi *hdmi)
 257 {
 258         u32 conf;
 259
 260         DRM_DEBUG_DRIVER("\n");
 261
 262         /* Clear overrun and underrun fifo */
 263         conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
 264
 265         /* Select encryption type and the framing mode */
 266         conf |= HDMI_CFG_ESS_NOT_OESS;
 267         if (hdmi->hdmi_monitor)
 268                 conf |= HDMI_CFG_HDMI_NOT_DVI;
 269
 270         /* Set Hsync polarity */
 271         if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
 272                 DRM_DEBUG_DRIVER("H Sync Negative\n");
 273                 conf |= HDMI_CFG_H_SYNC_POL_NEG;
 274         }
 275
 276         /* Set Vsync polarity */
 277         if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
 278                 DRM_DEBUG_DRIVER("V Sync Negative\n");
 279                 conf |= HDMI_CFG_V_SYNC_POL_NEG;
 280         }
 281
 282         /* Enable HDMI */
 283         conf |= HDMI_CFG_DEVICE_EN;
 284
 285         hdmi_write(hdmi, conf, HDMI_CFG);
 286 }
 287
 288 /*
 289  * Helper to reset info frame
 290  *
 291  * @hdmi: pointer on the hdmi internal structure
 292  * @slot: infoframe to reset
 293  */
 294 static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
 295                                  u32 slot)
 296 {
 297         u32 val, i;
 298         u32 head_offset, pack_offset;
 299
 300         switch (slot) {
 301         case HDMI_IFRAME_SLOT_AVI:
 302                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
 303                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
 304                 break;
 305         case HDMI_IFRAME_SLOT_AUDIO:
 306                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
 307                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
 308                 break;
 309         case HDMI_IFRAME_SLOT_VENDOR:
 310                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
 311                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
 312                 break;
 313         default:
 314                 DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
 315                 return;
 316         }
 317
 318         /* Disable transmission for the selected slot */
 319         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 320         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
 321         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 322
 323         /* Reset info frame registers */
 324         hdmi_write(hdmi, 0x0, head_offset);
 325         for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
 326                 hdmi_write(hdmi, 0x0, pack_offset + i);
 327 }
 328
 329 /**
 330  * Helper to concatenate infoframe in 32 bits word
 331  *
 332  * @ptr: pointer on the hdmi internal structure
 333  * @data: infoframe to write
 334  * @size: size to write
 335  */
 336 static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
 337 {
 338         unsigned long value = 0;
 339         size_t i;
 340
 341         for (i = size; i > 0; i--)
 342                 value = (value << 8) | ptr[i - 1];
 343
 344         return value;
 345 }
 346
 347 /**
 348  * Helper to write info frame
 349  *
 350  * @hdmi: pointer on the hdmi internal structure
 351  * @data: infoframe to write
 352  * @size: size to write
 353  */
 354 static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
 355                                           const u8 *data,
 356                                           size_t size)
 357 {
 358         const u8 *ptr = data;
 359         u32 val, slot, mode, i;
 360         u32 head_offset, pack_offset;
 361
 362         switch (*ptr) {
 363         case HDMI_INFOFRAME_TYPE_AVI:
 364                 slot = HDMI_IFRAME_SLOT_AVI;
 365                 mode = HDMI_IFRAME_FIELD;
 366                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
 367                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
 368                 break;
 369         case HDMI_INFOFRAME_TYPE_AUDIO:
 370                 slot = HDMI_IFRAME_SLOT_AUDIO;
 371                 mode = HDMI_IFRAME_FRAME;
 372                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
 373                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
 374                 break;
 375         case HDMI_INFOFRAME_TYPE_VENDOR:
 376                 slot = HDMI_IFRAME_SLOT_VENDOR;
 377                 mode = HDMI_IFRAME_FRAME;
 378                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
 379                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
 380                 break;
 381         default:
 382                 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
 383                 return;
 384         }
 385
 386         /* Disable transmission slot for updated infoframe */
 387         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 388         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
 389         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 390
 391         val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
 392         val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
 393         val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
 394         writel(val, hdmi->regs + head_offset);
 395
 396         /*
 397          * Each subpack contains 4 bytes
 398          * The First Bytes of the first subpacket must contain the checksum
 399          * Packet size is increase by one.
 400          */
 401         size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
 402         for (i = 0; i < size; i += sizeof(u32)) {
 403                 size_t num;
 404
 405                 num = min_t(size_t, size - i, sizeof(u32));
 406                 val = hdmi_infoframe_subpack(ptr, num);
 407                 ptr += sizeof(u32);
 408                 writel(val, hdmi->regs + pack_offset + i);
 409         }
 410
 411         /* Enable transmission slot for updated infoframe */
 412         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 413         val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
 414         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 415 }
 416
 417 /**
 418  * Prepare and configure the AVI infoframe
 419  *
 420  * AVI infoframe are transmitted at least once per two video field and
 421  * contains information about HDMI transmission mode such as color space,
 422  * colorimetry, ...
 423  *
 424  * @hdmi: pointer on the hdmi internal structure
 425  *
 426  * Return negative value if error occurs
 427  */
 428 static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
 429 {
 430         struct drm_display_mode *mode = &hdmi->mode;
 431         struct hdmi_avi_infoframe infoframe;
 432         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 433         int ret;
 434
 435         DRM_DEBUG_DRIVER("\n");
 436
 437         ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode, false);
 438         if (ret < 0) {
 439                 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
 440                 return ret;
 441         }
 442
 443         /* fixed infoframe configuration not linked to the mode */
 444         infoframe.colorspace = hdmi->colorspace;
 445         infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 446         infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
 447
 448         ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
 449         if (ret < 0) {
 450                 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
 451                 return ret;
 452         }
 453
 454         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 455
 456         return 0;
 457 }
 458
 459 /**
 460  * Prepare and configure the AUDIO infoframe
 461  *
 462  * AUDIO infoframe are transmitted once per frame and
 463  * contains information about HDMI transmission mode such as audio codec,
 464  * sample size, ...
 465  *
 466  * @hdmi: pointer on the hdmi internal structure
 467  *
 468  * Return negative value if error occurs
 469  */
 470 static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
 471 {
 472         struct hdmi_audio_params *audio = &hdmi->audio;
 473         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
 474         int ret, val;
 475
 476         DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
 477                          audio->enabled ? "enable" : "disable");
 478         if (audio->enabled) {
 479                 /* set audio parameters stored*/
 480                 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
 481                                                 sizeof(buffer));
 482                 if (ret < 0) {
 483                         DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
 484                         return ret;
 485                 }
 486                 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 487         } else {
 488                 /*disable audio info frame transmission */
 489                 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 490                 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
 491                                              HDMI_IFRAME_SLOT_AUDIO);
 492                 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 493         }
 494
 495         return 0;
 496 }
 497
 498 /*
 499  * Prepare and configure the VS infoframe
 500  *
 501  * Vendor Specific infoframe are transmitted once per frame and
 502  * contains vendor specific information.
 503  *
 504  * @hdmi: pointer on the hdmi internal structure
 505  *
 506  * Return negative value if error occurs
 507  */
 508 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
 509 static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
 510 {
 511         struct drm_display_mode *mode = &hdmi->mode;
 512         struct hdmi_vendor_infoframe infoframe;
 513         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
 514         int ret;
 515
 516         DRM_DEBUG_DRIVER("\n");
 517
 518         ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe, mode);
 519         if (ret < 0) {
 520                 /*
 521                  * Going into that statement does not means vendor infoframe
 522                  * fails. It just informed us that vendor infoframe is not
 523                  * needed for the selected mode. Only  4k or stereoscopic 3D
 524                  * mode requires vendor infoframe. So just simply return 0.
 525                  */
 526                 return 0;
 527         }
 528
 529         ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
 530         if (ret < 0) {
 531                 DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
 532                 return ret;
 533         }
 534
 535         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 536
 537         return 0;
 538 }
 539
 540 /**
 541  * Software reset of the hdmi subsystem
 542  *
 543  * @hdmi: pointer on the hdmi internal structure
 544  *
 545  */
 546 #define HDMI_TIMEOUT_SWRESET  100   /*milliseconds */
 547 static void hdmi_swreset(struct sti_hdmi *hdmi)
 548 {
 549         u32 val;
 550
 551         DRM_DEBUG_DRIVER("\n");
 552
 553         /* Enable hdmi_audio clock only during hdmi reset */
 554         if (clk_prepare_enable(hdmi->clk_audio))
 555                 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
 556
 557         /* Sw reset */
 558         hdmi->event_received = false;
 559
 560         val = hdmi_read(hdmi, HDMI_CFG);
 561         val |= HDMI_CFG_SW_RST_EN;
 562         hdmi_write(hdmi, val, HDMI_CFG);
 563
 564         /* Wait reset completed */
 565         wait_event_interruptible_timeout(hdmi->wait_event,
 566                                          hdmi->event_received,
 567                                          msecs_to_jiffies
 568                                          (HDMI_TIMEOUT_SWRESET));
 569
 570         /*
 571          * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
 572          * set to '1' and clk_audio is running.
 573          */
 574         if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
 575                 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
 576
 577         val = hdmi_read(hdmi, HDMI_CFG);
 578         val &= ~HDMI_CFG_SW_RST_EN;
 579         hdmi_write(hdmi, val, HDMI_CFG);
 580
 581         /* Disable hdmi_audio clock. Not used anymore for drm purpose */
 582         clk_disable_unprepare(hdmi->clk_audio);
 583 }
 584
 585 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
 586 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
 587 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s  %-25s 0x%08X", str, #reg, \
 588                                         hdmi_read(hdmi, reg))
 589 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
 590
 591 static void hdmi_dbg_cfg(struct seq_file *s, int val)
 592 {
 593         int tmp;
 594
 595         seq_putc(s, '\t');
 596         tmp = val & HDMI_CFG_HDMI_NOT_DVI;
 597         DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
 598         seq_puts(s, "\t\t\t\t\t");
 599         tmp = val & HDMI_CFG_HDCP_EN;
 600         DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
 601         seq_puts(s, "\t\t\t\t\t");
 602         tmp = val & HDMI_CFG_ESS_NOT_OESS;
 603         DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
 604         seq_puts(s, "\t\t\t\t\t");
 605         tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
 606         DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
 607         seq_puts(s, "\t\t\t\t\t");
 608         tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
 609         DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
 610         seq_puts(s, "\t\t\t\t\t");
 611         tmp = val & HDMI_CFG_422_EN;
 612         DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
 613 }
 614
 615 static void hdmi_dbg_sta(struct seq_file *s, int val)
 616 {
 617         int tmp;
 618
 619         seq_putc(s, '\t');
 620         tmp = (val & HDMI_STA_DLL_LCK);
 621         DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
 622         seq_puts(s, "\t\t\t\t\t");
 623         tmp = (val & HDMI_STA_HOT_PLUG);
 624         DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
 625 }
 626
 627 static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
 628 {
 629         int tmp;
 630         char *const en_di[] = {"no transmission",
 631                                "single transmission",
 632                                "once every field",
 633                                "once every frame"};
 634
 635         seq_putc(s, '\t');
 636         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
 637         DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
 638         seq_puts(s, "\t\t\t\t\t");
 639         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
 640         DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
 641         seq_puts(s, "\t\t\t\t\t");
 642         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
 643         DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
 644         seq_puts(s, "\t\t\t\t\t");
 645         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
 646         DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
 647         seq_puts(s, "\t\t\t\t\t");
 648         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
 649         DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
 650         seq_puts(s, "\t\t\t\t\t");
 651         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
 652         DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
 653 }
 654
 655 static int hdmi_dbg_show(struct seq_file *s, void *data)
 656 {
 657         struct drm_info_node *node = s->private;
 658         struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
 659
 660         seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
 661         DBGFS_DUMP("\n", HDMI_CFG);
 662         hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
 663         DBGFS_DUMP("", HDMI_INT_EN);
 664         DBGFS_DUMP("\n", HDMI_STA);
 665         hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
 666         DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
 667         seq_putc(s, '\t');
 668         DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
 669         DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
 670         seq_putc(s, '\t');
 671         DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
 672         DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
 673         seq_putc(s, '\t');
 674         DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
 675         DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
 676         seq_putc(s, '\t');
 677         DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
 678         DBGFS_DUMP("", HDMI_SW_DI_CFG);
 679         hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
 680
 681         DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
 682         DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
 683         DBGFS_DUMP("\n", HDMI_AUDN);
 684
 685         seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
 686                    HDMI_IFRAME_SLOT_AVI);
 687         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
 688         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
 689         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
 690         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
 691         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
 692         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
 693         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
 694         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
 695         seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
 696                    HDMI_IFRAME_SLOT_AUDIO);
 697         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
 698         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
 699         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
 700         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
 701         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
 702         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
 703         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
 704         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
 705         seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
 706                    HDMI_IFRAME_SLOT_VENDOR);
 707         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
 708         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
 709         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
 710         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
 711         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
 712         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
 713         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
 714         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
 715         seq_putc(s, '\n');
 716         return 0;
 717 }
 718
 719 static struct drm_info_list hdmi_debugfs_files[] = {
 720         { "hdmi", hdmi_dbg_show, 0, NULL },
 721 };
 722
 723 static int hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
 724 {
 725         unsigned int i;
 726
 727         for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
 728                 hdmi_debugfs_files[i].data = hdmi;
 729
 730         return drm_debugfs_create_files(hdmi_debugfs_files,
 731                                         ARRAY_SIZE(hdmi_debugfs_files),
 732                                         minor->debugfs_root, minor);
 733 }
 734
 735 static void sti_hdmi_disable(struct drm_bridge *bridge)
 736 {
 737         struct sti_hdmi *hdmi = bridge->driver_private;
 738
 739         u32 val = hdmi_read(hdmi, HDMI_CFG);
 740
 741         if (!hdmi->enabled)
 742                 return;
 743
 744         DRM_DEBUG_DRIVER("\n");
 745
 746         /* Disable HDMI */
 747         val &= ~HDMI_CFG_DEVICE_EN;
 748         hdmi_write(hdmi, val, HDMI_CFG);
 749
 750         hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
 751
 752         /* Stop the phy */
 753         hdmi->phy_ops->stop(hdmi);
 754
 755         /* Reset info frame transmission */
 756         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
 757         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
 758         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
 759
 760         /* Set the default channel data to be a dark red */
 761         hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
 762         hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
 763         hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
 764
 765         /* Disable/unprepare hdmi clock */
 766         clk_disable_unprepare(hdmi->clk_phy);
 767         clk_disable_unprepare(hdmi->clk_tmds);
 768         clk_disable_unprepare(hdmi->clk_pix);
 769
 770         hdmi->enabled = false;
 771
 772         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
 773 }
 774
 775 /**
 776  * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
 777  * clocks. None-coherent clocks means that audio and TMDS clocks have not the
 778  * same source (drifts between clocks). In this case assumption is that CTS is
 779  * automatically calculated by hardware.
 780  *
 781  * @audio_fs: audio frame clock frequency in Hz
 782  *
 783  * Values computed are based on table described in HDMI specification 1.4b
 784  *
 785  * Returns n value.
 786  */
 787 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
 788 {
 789         unsigned int n;
 790
 791         switch (audio_fs) {
 792         case 32000:
 793                 n = 4096;
 794                 break;
 795         case 44100:
 796                 n = 6272;
 797                 break;
 798         case 48000:
 799                 n = 6144;
 800                 break;
 801         case 88200:
 802                 n = 6272 * 2;
 803                 break;
 804         case 96000:
 805                 n = 6144 * 2;
 806                 break;
 807         case 176400:
 808                 n = 6272 * 4;
 809                 break;
 810         case 192000:
 811                 n = 6144 * 4;
 812                 break;
 813         default:
 814                 /* Not pre-defined, recommended value: 128 * fs / 1000 */
 815                 n = (audio_fs * 128) / 1000;
 816         }
 817
 818         return n;
 819 }
 820
 821 static int hdmi_audio_configure(struct sti_hdmi *hdmi)
 822 {
 823         int audio_cfg, n;
 824         struct hdmi_audio_params *params = &hdmi->audio;
 825         struct hdmi_audio_infoframe *info = &params->cea;
 826
 827         DRM_DEBUG_DRIVER("\n");
 828
 829         if (!hdmi->enabled)
 830                 return 0;
 831
 832         /* update N parameter */
 833         n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
 834
 835         DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
 836                          params->sample_rate, hdmi->mode.clock * 1000, n);
 837         hdmi_write(hdmi, n, HDMI_AUDN);
 838
 839         /* update HDMI registers according to configuration */
 840         audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
 841                     HDMI_AUD_CFG_ONE_BIT_INVALID;
 842
 843         switch (info->channels) {
 844         case 8:
 845                 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
 846         case 6:
 847                 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
 848         case 4:
 849                 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
 850         case 2:
 851                 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
 852                 break;
 853         default:
 854                 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
 855                           info->channels);
 856                 return -EINVAL;
 857         }
 858
 859         hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
 860
 861         return hdmi_audio_infoframe_config(hdmi);
 862 }
 863
 864 static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
 865 {
 866         struct sti_hdmi *hdmi = bridge->driver_private;
 867
 868         DRM_DEBUG_DRIVER("\n");
 869
 870         if (hdmi->enabled)
 871                 return;
 872
 873         /* Prepare/enable clocks */
 874         if (clk_prepare_enable(hdmi->clk_pix))
 875                 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
 876         if (clk_prepare_enable(hdmi->clk_tmds))
 877                 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
 878         if (clk_prepare_enable(hdmi->clk_phy))
 879                 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
 880
 881         hdmi->enabled = true;
 882
 883         /* Program hdmi serializer and start phy */
 884         if (!hdmi->phy_ops->start(hdmi)) {
 885                 DRM_ERROR("Unable to start hdmi phy\n");
 886                 return;
 887         }
 888
 889         /* Program hdmi active area */
 890         hdmi_active_area(hdmi);
 891
 892         /* Enable working interrupts */
 893         hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
 894
 895         /* Program hdmi config */
 896         hdmi_config(hdmi);
 897
 898         /* Program AVI infoframe */
 899         if (hdmi_avi_infoframe_config(hdmi))
 900                 DRM_ERROR("Unable to configure AVI infoframe\n");
 901
 902         if (hdmi->audio.enabled) {
 903                 if (hdmi_audio_configure(hdmi))
 904                         DRM_ERROR("Unable to configure audio\n");
 905         } else {
 906                 hdmi_audio_infoframe_config(hdmi);
 907         }
 908
 909         /* Program VS infoframe */
 910         if (hdmi_vendor_infoframe_config(hdmi))
 911                 DRM_ERROR("Unable to configure VS infoframe\n");
 912
 913         /* Sw reset */
 914         hdmi_swreset(hdmi);
 915 }
 916
 917 static void sti_hdmi_set_mode(struct drm_bridge *bridge,
 918                 struct drm_display_mode *mode,
 919                 struct drm_display_mode *adjusted_mode)
 920 {
 921         struct sti_hdmi *hdmi = bridge->driver_private;
 922         int ret;
 923
 924         DRM_DEBUG_DRIVER("\n");
 925
 926         /* Copy the drm display mode in the connector local structure */
 927         drm_mode_copy(&hdmi->mode, mode);
 928
 929         /* Update clock framerate according to the selected mode */
 930         ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
 931         if (ret < 0) {
 932                 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
 933                           mode->clock * 1000);
 934                 return;
 935         }
 936         ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
 937         if (ret < 0) {
 938                 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
 939                           mode->clock * 1000);
 940                 return;
 941         }
 942 }
 943
 944 static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
 945 {
 946         /* do nothing */
 947 }
 948
 949 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
 950         .pre_enable = sti_hdmi_pre_enable,
 951         .enable = sti_hdmi_bridge_nope,
 952         .disable = sti_hdmi_disable,
 953         .post_disable = sti_hdmi_bridge_nope,
 954         .mode_set = sti_hdmi_set_mode,
 955 };
 956
 957 static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
 958 {
 959         struct sti_hdmi_connector *hdmi_connector
 960                 = to_sti_hdmi_connector(connector);
 961         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
 962         struct edid *edid;
 963         int count;
 964
 965         DRM_DEBUG_DRIVER("\n");
 966
 967         edid = drm_get_edid(connector, hdmi->ddc_adapt);
 968         if (!edid)
 969                 goto fail;
 970
 971         hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 972         DRM_DEBUG_KMS("%s : %dx%d cm\n",
 973                       (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
 974                       edid->width_cm, edid->height_cm);
 975         cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
 976
 977         count = drm_add_edid_modes(connector, edid);
 978         drm_mode_connector_update_edid_property(connector, edid);
 979         drm_edid_to_eld(connector, edid);
 980
 981         kfree(edid);
 982         return count;
 983
 984 fail:
 985         DRM_ERROR("Can't read HDMI EDID\n");
 986         return 0;
 987 }
 988
 989 #define CLK_TOLERANCE_HZ 50
 990
 991 static enum drm_mode_status
 992 sti_hdmi_connector_mode_valid(struct drm_connector *connector,
 993                               struct drm_display_mode *mode)
 994 {
 995         int target = mode->clock * 1000;
 996         int target_min = target - CLK_TOLERANCE_HZ;
 997         int target_max = target + CLK_TOLERANCE_HZ;
 998         int result;
 999         struct sti_hdmi_connector *hdmi_connector
1000                 = to_sti_hdmi_connector(connector);
1001         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1002
1003
1004         result = clk_round_rate(hdmi->clk_pix, target);
1005
1006         DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1007                          target, result);
1008
1009         if ((result < target_min) || (result > target_max)) {
1010                 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1011                 return MODE_BAD;
1012         }
1013
1014         return MODE_OK;
1015 }
1016
1017 static const
1018 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
1019         .get_modes = sti_hdmi_connector_get_modes,
1020         .mode_valid = sti_hdmi_connector_mode_valid,
1021 };
1022
1023 /* get detection status of display device */
1024 static enum drm_connector_status
1025 sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1026 {
1027         struct sti_hdmi_connector *hdmi_connector
1028                 = to_sti_hdmi_connector(connector);
1029         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1030
1031         DRM_DEBUG_DRIVER("\n");
1032
1033         if (hdmi->hpd) {
1034                 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1035                 return connector_status_connected;
1036         }
1037
1038         DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1039         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1040         return connector_status_disconnected;
1041 }
1042
1043 static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1044                                              struct drm_connector *connector)
1045 {
1046         struct sti_hdmi_connector *hdmi_connector
1047                 = to_sti_hdmi_connector(connector);
1048         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1049         struct drm_property *prop;
1050
1051         /* colorspace property */
1052         hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1053         prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1054                                         colorspace_mode_names,
1055                                         ARRAY_SIZE(colorspace_mode_names));
1056         if (!prop) {
1057                 DRM_ERROR("fails to create colorspace property\n");
1058                 return;
1059         }
1060         hdmi_connector->colorspace_property = prop;
1061         drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1062 }
1063
1064 static int
1065 sti_hdmi_connector_set_property(struct drm_connector *connector,
1066                                 struct drm_connector_state *state,
1067                                 struct drm_property *property,
1068                                 uint64_t val)
1069 {
1070         struct sti_hdmi_connector *hdmi_connector
1071                 = to_sti_hdmi_connector(connector);
1072         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1073
1074         if (property == hdmi_connector->colorspace_property) {
1075                 hdmi->colorspace = val;
1076                 return 0;
1077         }
1078
1079         DRM_ERROR("failed to set hdmi connector property\n");
1080         return -EINVAL;
1081 }
1082
1083 static int
1084 sti_hdmi_connector_get_property(struct drm_connector *connector,
1085                                 const struct drm_connector_state *state,
1086                                 struct drm_property *property,
1087                                 uint64_t *val)
1088 {
1089         struct sti_hdmi_connector *hdmi_connector
1090                 = to_sti_hdmi_connector(connector);
1091         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1092
1093         if (property == hdmi_connector->colorspace_property) {
1094                 *val = hdmi->colorspace;
1095                 return 0;
1096         }
1097
1098         DRM_ERROR("failed to get hdmi connector property\n");
1099         return -EINVAL;
1100 }
1101
1102 static int sti_hdmi_late_register(struct drm_connector *connector)
1103 {
1104         struct sti_hdmi_connector *hdmi_connector
1105                 = to_sti_hdmi_connector(connector);
1106         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1107
1108         if (hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary)) {
1109                 DRM_ERROR("HDMI debugfs setup failed\n");
1110                 return -EINVAL;
1111         }
1112
1113         return 0;
1114 }
1115
1116 static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1117         .fill_modes = drm_helper_probe_single_connector_modes,
1118         .detect = sti_hdmi_connector_detect,
1119         .destroy = drm_connector_cleanup,
1120         .reset = drm_atomic_helper_connector_reset,
1121         .atomic_set_property = sti_hdmi_connector_set_property,
1122         .atomic_get_property = sti_hdmi_connector_get_property,
1123         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1124         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1125         .late_register = sti_hdmi_late_register,
1126 };
1127
1128 static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1129 {
1130         struct drm_encoder *encoder;
1131
1132         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1133                 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1134                         return encoder;
1135         }
1136
1137         return NULL;
1138 }
1139
1140 static void hdmi_audio_shutdown(struct device *dev, void *data)
1141 {
1142         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1143         int audio_cfg;
1144
1145         DRM_DEBUG_DRIVER("\n");
1146
1147         /* disable audio */
1148         audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1149                     HDMI_AUD_CFG_ONE_BIT_INVALID;
1150         hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1151
1152         hdmi->audio.enabled = false;
1153         hdmi_audio_infoframe_config(hdmi);
1154 }
1155
1156 static int hdmi_audio_hw_params(struct device *dev,
1157                                 void *data,
1158                                 struct hdmi_codec_daifmt *daifmt,
1159                                 struct hdmi_codec_params *params)
1160 {
1161         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1162         int ret;
1163
1164         DRM_DEBUG_DRIVER("\n");
1165
1166         if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1167             daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1168             daifmt->frame_clk_master) {
1169                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1170                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1171                         daifmt->bit_clk_master,
1172                         daifmt->frame_clk_master);
1173                 return -EINVAL;
1174         }
1175
1176         hdmi->audio.sample_width = params->sample_width;
1177         hdmi->audio.sample_rate = params->sample_rate;
1178         hdmi->audio.cea = params->cea;
1179
1180         hdmi->audio.enabled = true;
1181
1182         ret = hdmi_audio_configure(hdmi);
1183         if (ret < 0)
1184                 return ret;
1185
1186         return 0;
1187 }
1188
1189 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1190 {
1191         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1192
1193         DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1194
1195         if (enable)
1196                 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1197         else
1198                 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1199
1200         return 0;
1201 }
1202
1203 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1204 {
1205         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1206         struct drm_connector *connector = hdmi->drm_connector;
1207
1208         DRM_DEBUG_DRIVER("\n");
1209         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1210
1211         return 0;
1212 }
1213
1214 static const struct hdmi_codec_ops audio_codec_ops = {
1215         .hw_params = hdmi_audio_hw_params,
1216         .audio_shutdown = hdmi_audio_shutdown,
1217         .digital_mute = hdmi_audio_digital_mute,
1218         .get_eld = hdmi_audio_get_eld,
1219 };
1220
1221 static int sti_hdmi_register_audio_driver(struct device *dev,
1222                                           struct sti_hdmi *hdmi)
1223 {
1224         struct hdmi_codec_pdata codec_data = {
1225                 .ops = &audio_codec_ops,
1226                 .max_i2s_channels = 8,
1227                 .i2s = 1,
1228         };
1229
1230         DRM_DEBUG_DRIVER("\n");
1231
1232         hdmi->audio.enabled = false;
1233
1234         hdmi->audio_pdev = platform_device_register_data(
1235                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1236                 &codec_data, sizeof(codec_data));
1237
1238         if (IS_ERR(hdmi->audio_pdev))
1239                 return PTR_ERR(hdmi->audio_pdev);
1240
1241         DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1242
1243         return 0;
1244 }
1245
1246 static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1247 {
1248         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1249         struct drm_device *drm_dev = data;
1250         struct drm_encoder *encoder;
1251         struct sti_hdmi_connector *connector;
1252         struct drm_connector *drm_connector;
1253         struct drm_bridge *bridge;
1254         int err;
1255
1256         /* Set the drm device handle */
1257         hdmi->drm_dev = drm_dev;
1258
1259         encoder = sti_hdmi_find_encoder(drm_dev);
1260         if (!encoder)
1261                 return -EINVAL;
1262
1263         connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1264         if (!connector)
1265                 return -EINVAL;
1266
1267         connector->hdmi = hdmi;
1268
1269         bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1270         if (!bridge)
1271                 return -EINVAL;
1272
1273         bridge->driver_private = hdmi;
1274         bridge->funcs = &sti_hdmi_bridge_funcs;
1275         drm_bridge_attach(encoder, bridge, NULL);
1276
1277         connector->encoder = encoder;
1278
1279         drm_connector = (struct drm_connector *)connector;
1280
1281         drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1282
1283         drm_connector_init(drm_dev, drm_connector,
1284                         &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1285         drm_connector_helper_add(drm_connector,
1286                         &sti_hdmi_connector_helper_funcs);
1287
1288         /* initialise property */
1289         sti_hdmi_connector_init_property(drm_dev, drm_connector);
1290
1291         hdmi->drm_connector = drm_connector;
1292
1293         err = drm_mode_connector_attach_encoder(drm_connector, encoder);
1294         if (err) {
1295                 DRM_ERROR("Failed to attach a connector to a encoder\n");
1296                 goto err_sysfs;
1297         }
1298
1299         err = sti_hdmi_register_audio_driver(dev, hdmi);
1300         if (err) {
1301                 DRM_ERROR("Failed to attach an audio codec\n");
1302                 goto err_sysfs;
1303         }
1304
1305         /* Initialize audio infoframe */
1306         err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1307         if (err) {
1308                 DRM_ERROR("Failed to init audio infoframe\n");
1309                 goto err_sysfs;
1310         }
1311
1312         /* Enable default interrupts */
1313         hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1314
1315         return 0;
1316
1317 err_sysfs:
1318         hdmi->drm_connector = NULL;
1319         return -EINVAL;
1320 }
1321
1322 static void sti_hdmi_unbind(struct device *dev,
1323                 struct device *master, void *data)
1324 {
1325 }
1326
1327 static const struct component_ops sti_hdmi_ops = {
1328         .bind = sti_hdmi_bind,
1329         .unbind = sti_hdmi_unbind,
1330 };
1331
1332 static const struct of_device_id hdmi_of_match[] = {
1333         {
1334                 .compatible = "st,stih407-hdmi",
1335                 .data = &tx3g4c28phy_ops,
1336         }, {
1337                 /* end node */
1338         }
1339 };
1340 MODULE_DEVICE_TABLE(of, hdmi_of_match);
1341
1342 static int sti_hdmi_probe(struct platform_device *pdev)
1343 {
1344         struct device *dev = &pdev->dev;
1345         struct sti_hdmi *hdmi;
1346         struct device_node *np = dev->of_node;
1347         struct resource *res;
1348         struct device_node *ddc;
1349         int ret;
1350
1351         DRM_INFO("%s\n", __func__);
1352
1353         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1354         if (!hdmi)
1355                 return -ENOMEM;
1356
1357         ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1358         if (ddc) {
1359                 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
1360                 of_node_put(ddc);
1361                 if (!hdmi->ddc_adapt)
1362                         return -EPROBE_DEFER;
1363         }
1364
1365         hdmi->dev = pdev->dev;
1366
1367         /* Get resources */
1368         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1369         if (!res) {
1370                 DRM_ERROR("Invalid hdmi resource\n");
1371                 ret = -ENOMEM;
1372                 goto release_adapter;
1373         }
1374         hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
1375         if (!hdmi->regs) {
1376                 ret = -ENOMEM;
1377                 goto release_adapter;
1378         }
1379
1380         hdmi->phy_ops = (struct hdmi_phy_ops *)
1381                 of_match_node(hdmi_of_match, np)->data;
1382
1383         /* Get clock resources */
1384         hdmi->clk_pix = devm_clk_get(dev, "pix");
1385         if (IS_ERR(hdmi->clk_pix)) {
1386                 DRM_ERROR("Cannot get hdmi_pix clock\n");
1387                 ret = PTR_ERR(hdmi->clk_pix);
1388                 goto release_adapter;
1389         }
1390
1391         hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1392         if (IS_ERR(hdmi->clk_tmds)) {
1393                 DRM_ERROR("Cannot get hdmi_tmds clock\n");
1394                 ret = PTR_ERR(hdmi->clk_tmds);
1395                 goto release_adapter;
1396         }
1397
1398         hdmi->clk_phy = devm_clk_get(dev, "phy");
1399         if (IS_ERR(hdmi->clk_phy)) {
1400                 DRM_ERROR("Cannot get hdmi_phy clock\n");
1401                 ret = PTR_ERR(hdmi->clk_phy);
1402                 goto release_adapter;
1403         }
1404
1405         hdmi->clk_audio = devm_clk_get(dev, "audio");
1406         if (IS_ERR(hdmi->clk_audio)) {
1407                 DRM_ERROR("Cannot get hdmi_audio clock\n");
1408                 ret = PTR_ERR(hdmi->clk_audio);
1409                 goto release_adapter;
1410         }
1411
1412         hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
1413
1414         init_waitqueue_head(&hdmi->wait_event);
1415
1416         hdmi->irq = platform_get_irq_byname(pdev, "irq");
1417
1418         ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1419                         hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1420         if (ret) {
1421                 DRM_ERROR("Failed to register HDMI interrupt\n");
1422                 goto release_adapter;
1423         }
1424
1425         hdmi->notifier = cec_notifier_get(&pdev->dev);
1426         if (!hdmi->notifier)
1427                 goto release_adapter;
1428
1429         hdmi->reset = devm_reset_control_get(dev, "hdmi");
1430         /* Take hdmi out of reset */
1431         if (!IS_ERR(hdmi->reset))
1432                 reset_control_deassert(hdmi->reset);
1433
1434         platform_set_drvdata(pdev, hdmi);
1435
1436         return component_add(&pdev->dev, &sti_hdmi_ops);
1437
1438  release_adapter:
1439         i2c_put_adapter(hdmi->ddc_adapt);
1440
1441         return ret;
1442 }
1443
1444 static int sti_hdmi_remove(struct platform_device *pdev)
1445 {
1446         struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1447
1448         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1449
1450         i2c_put_adapter(hdmi->ddc_adapt);
1451         if (hdmi->audio_pdev)
1452                 platform_device_unregister(hdmi->audio_pdev);
1453         component_del(&pdev->dev, &sti_hdmi_ops);
1454
1455         cec_notifier_put(hdmi->notifier);
1456         return 0;
1457 }
1458
1459 struct platform_driver sti_hdmi_driver = {
1460         .driver = {
1461                 .name = "sti-hdmi",
1462                 .owner = THIS_MODULE,
1463                 .of_match_table = hdmi_of_match,
1464         },
1465         .probe = sti_hdmi_probe,
1466         .remove = sti_hdmi_remove,
1467 };
1468
1469 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1470 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1471 MODULE_LICENSE("GPL");