drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:Mark Yao <mark.yao@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/delay.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/overflow.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/reset.h>
  19
  20 #include <drm/drm.h>
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_uapi.h>
  23 #include <drm/drm_crtc.h>
  24 #include <drm/drm_flip_work.h>
  25 #include <drm/drm_fourcc.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27 #include <drm/drm_plane_helper.h>
  28 #include <drm/drm_probe_helper.h>
  29 #include <drm/drm_self_refresh_helper.h>
  30 #include <drm/drm_vblank.h>
  31
  32 #ifdef CONFIG_DRM_ANALOGIX_DP
  33 #include <drm/bridge/analogix_dp.h>
  34 #endif
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40 #include "rockchip_rgb.h"
  41
  42 #define VOP_WIN_SET(vop, win, name, v) \
  43                 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
  44 #define VOP_SCL_SET(vop, win, name, v) \
  45                 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
  46 #define VOP_SCL_SET_EXT(vop, win, name, v) \
  47                 vop_reg_set(vop, &win->phy->scl->ext->name, \
  48                             win->base, ~0, v, #name)
  49
  50 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
  51         do { \
  52                 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
  53                         vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
  54         } while (0)
  55
  56 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
  57         do { \
  58                 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
  59                         vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
  60         } while (0)
  61
  62 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  63                 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
  64
  65 #define VOP_REG_SET(vop, group, name, v) \
  66                     vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
  67
  68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  69         do { \
  70                 int i, reg = 0, mask = 0; \
  71                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  72                         if (vop->data->intr->intrs[i] & type) { \
  73                                 reg |= (v) << i; \
  74                                 mask |= 1 << i; \
  75                         } \
  76                 } \
  77                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
  78         } while (0)
  79 #define VOP_INTR_GET_TYPE(vop, name, type) \
  80                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  81
  82 #define VOP_WIN_GET(vop, win, name) \
  83                 vop_read_reg(vop, win->base, &win->phy->name)
  84
  85 #define VOP_WIN_HAS_REG(win, name) \
  86         (!!(win->phy->name.mask))
  87
  88 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  89                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  90
  91 #define VOP_WIN_TO_INDEX(vop_win) \
  92         ((vop_win) - (vop_win)->vop->win)
  93
  94 #define VOP_AFBC_SET(vop, name, v) \
  95         do { \
  96                 if ((vop)->data->afbc) \
  97                         vop_reg_set((vop), &(vop)->data->afbc->name, \
  98                                     0, ~0, v, #name); \
  99         } while (0)
 100
 101 #define to_vop(x) container_of(x, struct vop, crtc)
 102 #define to_vop_win(x) container_of(x, struct vop_win, base)
 103
 104 #define AFBC_FMT_RGB565         0x0
 105 #define AFBC_FMT_U8U8U8U8       0x5
 106 #define AFBC_FMT_U8U8U8         0x4
 107
 108 #define AFBC_TILE_16x16         BIT(4)
 109
 110 /*
 111  * The coefficients of the following matrix are all fixed points.
 112  * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
 113  * They are all represented in two's complement.
 114  */
 115 static const uint32_t bt601_yuv2rgb[] = {
 116         0x4A8, 0x0,    0x662,
 117         0x4A8, 0x1E6F, 0x1CBF,
 118         0x4A8, 0x812,  0x0,
 119         0x321168, 0x0877CF, 0x2EB127
 120 };
 121
 122 enum vop_pending {
 123         VOP_PENDING_FB_UNREF,
 124 };
 125
 126 struct vop_win {
 127         struct drm_plane base;
 128         const struct vop_win_data *data;
 129         const struct vop_win_yuv2yuv_data *yuv2yuv_data;
 130         struct vop *vop;
 131 };
 132
 133 struct rockchip_rgb;
 134 struct vop {
 135         struct drm_crtc crtc;
 136         struct device *dev;
 137         struct drm_device *drm_dev;
 138         bool is_enabled;
 139
 140         struct completion dsp_hold_completion;
 141         unsigned int win_enabled;
 142
 143         /* protected by dev->event_lock */
 144         struct drm_pending_vblank_event *event;
 145
 146         struct drm_flip_work fb_unref_work;
 147         unsigned long pending;
 148
 149         struct completion line_flag_completion;
 150
 151         const struct vop_data *data;
 152
 153         uint32_t *regsbak;
 154         void __iomem *regs;
 155         void __iomem *lut_regs;
 156
 157         /* physical map length of vop register */
 158         uint32_t len;
 159
 160         /* one time only one process allowed to config the register */
 161         spinlock_t reg_lock;
 162         /* lock vop irq reg */
 163         spinlock_t irq_lock;
 164         /* protects crtc enable/disable */
 165         struct mutex vop_lock;
 166
 167         unsigned int irq;
 168
 169         /* vop AHP clk */
 170         struct clk *hclk;
 171         /* vop dclk */
 172         struct clk *dclk;
 173         /* vop share memory frequency */
 174         struct clk *aclk;
 175
 176         /* vop dclk reset */
 177         struct reset_control *dclk_rst;
 178
 179         /* optional internal rgb encoder */
 180         struct rockchip_rgb *rgb;
 181
 182         struct vop_win win[];
 183 };
 184
 185 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 186 {
 187         writel(v, vop->regs + offset);
 188         vop->regsbak[offset >> 2] = v;
 189 }
 190
 191 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 192 {
 193         return readl(vop->regs + offset);
 194 }
 195
 196 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 197                                     const struct vop_reg *reg)
 198 {
 199         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 200 }
 201
 202 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
 203                         uint32_t _offset, uint32_t _mask, uint32_t v,
 204                         const char *reg_name)
 205 {
 206         int offset, mask, shift;
 207
 208         if (!reg || !reg->mask) {
 209                 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
 210                 return;
 211         }
 212
 213         offset = reg->offset + _offset;
 214         mask = reg->mask & _mask;
 215         shift = reg->shift;
 216
 217         if (reg->write_mask) {
 218                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 219         } else {
 220                 uint32_t cached_val = vop->regsbak[offset >> 2];
 221
 222                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 223                 vop->regsbak[offset >> 2] = v;
 224         }
 225
 226         if (reg->relaxed)
 227                 writel_relaxed(v, vop->regs + offset);
 228         else
 229                 writel(v, vop->regs + offset);
 230 }
 231
 232 static inline uint32_t vop_get_intr_type(struct vop *vop,
 233                                          const struct vop_reg *reg, int type)
 234 {
 235         uint32_t i, ret = 0;
 236         uint32_t regs = vop_read_reg(vop, 0, reg);
 237
 238         for (i = 0; i < vop->data->intr->nintrs; i++) {
 239                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 240                         ret |= vop->data->intr->intrs[i];
 241         }
 242
 243         return ret;
 244 }
 245
 246 static inline void vop_cfg_done(struct vop *vop)
 247 {
 248         VOP_REG_SET(vop, common, cfg_done, 1);
 249 }
 250
 251 static bool has_rb_swapped(uint32_t format)
 252 {
 253         switch (format) {
 254         case DRM_FORMAT_XBGR8888:
 255         case DRM_FORMAT_ABGR8888:
 256         case DRM_FORMAT_BGR888:
 257         case DRM_FORMAT_BGR565:
 258                 return true;
 259         default:
 260                 return false;
 261         }
 262 }
 263
 264 static enum vop_data_format vop_convert_format(uint32_t format)
 265 {
 266         switch (format) {
 267         case DRM_FORMAT_XRGB8888:
 268         case DRM_FORMAT_ARGB8888:
 269         case DRM_FORMAT_XBGR8888:
 270         case DRM_FORMAT_ABGR8888:
 271                 return VOP_FMT_ARGB8888;
 272         case DRM_FORMAT_RGB888:
 273         case DRM_FORMAT_BGR888:
 274                 return VOP_FMT_RGB888;
 275         case DRM_FORMAT_RGB565:
 276         case DRM_FORMAT_BGR565:
 277                 return VOP_FMT_RGB565;
 278         case DRM_FORMAT_NV12:
 279                 return VOP_FMT_YUV420SP;
 280         case DRM_FORMAT_NV16:
 281                 return VOP_FMT_YUV422SP;
 282         case DRM_FORMAT_NV24:
 283                 return VOP_FMT_YUV444SP;
 284         default:
 285                 DRM_ERROR("unsupported format[%08x]\n", format);
 286                 return -EINVAL;
 287         }
 288 }
 289
 290 static int vop_convert_afbc_format(uint32_t format)
 291 {
 292         switch (format) {
 293         case DRM_FORMAT_XRGB8888:
 294         case DRM_FORMAT_ARGB8888:
 295         case DRM_FORMAT_XBGR8888:
 296         case DRM_FORMAT_ABGR8888:
 297                 return AFBC_FMT_U8U8U8U8;
 298         case DRM_FORMAT_RGB888:
 299         case DRM_FORMAT_BGR888:
 300                 return AFBC_FMT_U8U8U8;
 301         case DRM_FORMAT_RGB565:
 302         case DRM_FORMAT_BGR565:
 303                 return AFBC_FMT_RGB565;
 304         /* either of the below should not be reachable */
 305         default:
 306                 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format);
 307                 return -EINVAL;
 308         }
 309
 310         return -EINVAL;
 311 }
 312
 313 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 314                                   uint32_t dst, bool is_horizontal,
 315                                   int vsu_mode, int *vskiplines)
 316 {
 317         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 318
 319         if (vskiplines)
 320                 *vskiplines = 0;
 321
 322         if (is_horizontal) {
 323                 if (mode == SCALE_UP)
 324                         val = GET_SCL_FT_BIC(src, dst);
 325                 else if (mode == SCALE_DOWN)
 326                         val = GET_SCL_FT_BILI_DN(src, dst);
 327         } else {
 328                 if (mode == SCALE_UP) {
 329                         if (vsu_mode == SCALE_UP_BIL)
 330                                 val = GET_SCL_FT_BILI_UP(src, dst);
 331                         else
 332                                 val = GET_SCL_FT_BIC(src, dst);
 333                 } else if (mode == SCALE_DOWN) {
 334                         if (vskiplines) {
 335                                 *vskiplines = scl_get_vskiplines(src, dst);
 336                                 val = scl_get_bili_dn_vskip(src, dst,
 337                                                             *vskiplines);
 338                         } else {
 339                                 val = GET_SCL_FT_BILI_DN(src, dst);
 340                         }
 341                 }
 342         }
 343
 344         return val;
 345 }
 346
 347 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 348                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 349                              uint32_t dst_h, const struct drm_format_info *info)
 350 {
 351         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 352         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 353         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 354         bool is_yuv = false;
 355         uint16_t cbcr_src_w = src_w / info->hsub;
 356         uint16_t cbcr_src_h = src_h / info->vsub;
 357         uint16_t vsu_mode;
 358         uint16_t lb_mode;
 359         uint32_t val;
 360         int vskiplines;
 361
 362         if (info->is_yuv)
 363                 is_yuv = true;
 364
 365         if (dst_w > 3840) {
 366                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 367                 return;
 368         }
 369
 370         if (!win->phy->scl->ext) {
 371                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 372                             scl_cal_scale2(src_w, dst_w));
 373                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 374                             scl_cal_scale2(src_h, dst_h));
 375                 if (is_yuv) {
 376                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 377                                     scl_cal_scale2(cbcr_src_w, dst_w));
 378                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 379                                     scl_cal_scale2(cbcr_src_h, dst_h));
 380                 }
 381                 return;
 382         }
 383
 384         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 385         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 386
 387         if (is_yuv) {
 388                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 389                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 390                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 391                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 392                 else
 393                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 394         } else {
 395                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 396                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 397                 else
 398                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 399         }
 400
 401         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 402         if (lb_mode == LB_RGB_3840X2) {
 403                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 404                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 405                         return;
 406                 }
 407                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 408                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 409                         return;
 410                 }
 411                 vsu_mode = SCALE_UP_BIL;
 412         } else if (lb_mode == LB_RGB_2560X4) {
 413                 vsu_mode = SCALE_UP_BIL;
 414         } else {
 415                 vsu_mode = SCALE_UP_BIC;
 416         }
 417
 418         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 419                                 true, 0, NULL);
 420         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 421         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 422                                 false, vsu_mode, &vskiplines);
 423         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 424
 425         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 426         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 427
 428         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 429         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 430         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 431         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 432         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 433         if (is_yuv) {
 434                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 435                                         dst_w, true, 0, NULL);
 436                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 437                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 438                                         dst_h, false, vsu_mode, &vskiplines);
 439                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 440
 441                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 442                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 443                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 444                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 445                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 446                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 447                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 448         }
 449 }
 450
 451 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 452 {
 453         unsigned long flags;
 454
 455         if (WARN_ON(!vop->is_enabled))
 456                 return;
 457
 458         spin_lock_irqsave(&vop->irq_lock, flags);
 459
 460         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 461         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 462
 463         spin_unlock_irqrestore(&vop->irq_lock, flags);
 464 }
 465
 466 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 467 {
 468         unsigned long flags;
 469
 470         if (WARN_ON(!vop->is_enabled))
 471                 return;
 472
 473         spin_lock_irqsave(&vop->irq_lock, flags);
 474
 475         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 476
 477         spin_unlock_irqrestore(&vop->irq_lock, flags);
 478 }
 479
 480 /*
 481  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 482  *     the "FRAME_SYNC" interrupt.
 483  * (2) the active data region of each frame ends at dsp_vact_end
 484  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 485  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 486  *
 487  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 488  * Interrupts
 489  * LINE_FLAG -------------------------------+
 490  * FRAME_SYNC ----+                         |
 491  *                |                         |
 492  *                v                         v
 493  *                | Vsync | Vbp |  Vactive  | Vfp |
 494  *                        ^     ^           ^     ^
 495  *                        |     |           |     |
 496  *                        |     |           |     |
 497  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 498  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 499  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 500  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 501  */
 502 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 503 {
 504         uint32_t line_flag_irq;
 505         unsigned long flags;
 506
 507         spin_lock_irqsave(&vop->irq_lock, flags);
 508
 509         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 510
 511         spin_unlock_irqrestore(&vop->irq_lock, flags);
 512
 513         return !!line_flag_irq;
 514 }
 515
 516 static void vop_line_flag_irq_enable(struct vop *vop)
 517 {
 518         unsigned long flags;
 519
 520         if (WARN_ON(!vop->is_enabled))
 521                 return;
 522
 523         spin_lock_irqsave(&vop->irq_lock, flags);
 524
 525         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 526         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 527
 528         spin_unlock_irqrestore(&vop->irq_lock, flags);
 529 }
 530
 531 static void vop_line_flag_irq_disable(struct vop *vop)
 532 {
 533         unsigned long flags;
 534
 535         if (WARN_ON(!vop->is_enabled))
 536                 return;
 537
 538         spin_lock_irqsave(&vop->irq_lock, flags);
 539
 540         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 541
 542         spin_unlock_irqrestore(&vop->irq_lock, flags);
 543 }
 544
 545 static int vop_core_clks_enable(struct vop *vop)
 546 {
 547         int ret;
 548
 549         ret = clk_enable(vop->hclk);
 550         if (ret < 0)
 551                 return ret;
 552
 553         ret = clk_enable(vop->aclk);
 554         if (ret < 0)
 555                 goto err_disable_hclk;
 556
 557         return 0;
 558
 559 err_disable_hclk:
 560         clk_disable(vop->hclk);
 561         return ret;
 562 }
 563
 564 static void vop_core_clks_disable(struct vop *vop)
 565 {
 566         clk_disable(vop->aclk);
 567         clk_disable(vop->hclk);
 568 }
 569
 570 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
 571 {
 572         const struct vop_win_data *win = vop_win->data;
 573
 574         if (win->phy->scl && win->phy->scl->ext) {
 575                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 576                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 577                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 578                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 579         }
 580
 581         VOP_WIN_SET(vop, win, enable, 0);
 582         vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
 583 }
 584
 585 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
 586 {
 587         struct vop *vop = to_vop(crtc);
 588         int ret, i;
 589
 590         ret = pm_runtime_get_sync(vop->dev);
 591         if (ret < 0) {
 592                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
 593                 return ret;
 594         }
 595
 596         ret = vop_core_clks_enable(vop);
 597         if (WARN_ON(ret < 0))
 598                 goto err_put_pm_runtime;
 599
 600         ret = clk_enable(vop->dclk);
 601         if (WARN_ON(ret < 0))
 602                 goto err_disable_core;
 603
 604         /*
 605          * Slave iommu shares power, irq and clock with vop.  It was associated
 606          * automatically with this master device via common driver code.
 607          * Now that we have enabled the clock we attach it to the shared drm
 608          * mapping.
 609          */
 610         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 611         if (ret) {
 612                 DRM_DEV_ERROR(vop->dev,
 613                               "failed to attach dma mapping, %d\n", ret);
 614                 goto err_disable_dclk;
 615         }
 616
 617         spin_lock(&vop->reg_lock);
 618         for (i = 0; i < vop->len; i += 4)
 619                 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
 620
 621         /*
 622          * We need to make sure that all windows are disabled before we
 623          * enable the crtc. Otherwise we might try to scan from a destroyed
 624          * buffer later.
 625          *
 626          * In the case of enable-after-PSR, we don't need to worry about this
 627          * case since the buffer is guaranteed to be valid and disabling the
 628          * window will result in screen glitches on PSR exit.
 629          */
 630         if (!old_state || !old_state->self_refresh_active) {
 631                 for (i = 0; i < vop->data->win_size; i++) {
 632                         struct vop_win *vop_win = &vop->win[i];
 633
 634                         vop_win_disable(vop, vop_win);
 635                 }
 636         }
 637
 638         if (vop->data->afbc) {
 639                 struct rockchip_crtc_state *s;
 640                 /*
 641                  * Disable AFBC and forget there was a vop window with AFBC
 642                  */
 643                 VOP_AFBC_SET(vop, enable, 0);
 644                 s = to_rockchip_crtc_state(crtc->state);
 645                 s->enable_afbc = false;
 646         }
 647
 648         vop_cfg_done(vop);
 649
 650         spin_unlock(&vop->reg_lock);
 651
 652         /*
 653          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 654          */
 655         vop->is_enabled = true;
 656
 657         spin_lock(&vop->reg_lock);
 658
 659         VOP_REG_SET(vop, common, standby, 1);
 660
 661         spin_unlock(&vop->reg_lock);
 662
 663         drm_crtc_vblank_on(crtc);
 664
 665         return 0;
 666
 667 err_disable_dclk:
 668         clk_disable(vop->dclk);
 669 err_disable_core:
 670         vop_core_clks_disable(vop);
 671 err_put_pm_runtime:
 672         pm_runtime_put_sync(vop->dev);
 673         return ret;
 674 }
 675
 676 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
 677 {
 678         struct vop *vop = to_vop(crtc);
 679         int i;
 680
 681         spin_lock(&vop->reg_lock);
 682
 683         for (i = 0; i < vop->data->win_size; i++) {
 684                 struct vop_win *vop_win = &vop->win[i];
 685                 const struct vop_win_data *win = vop_win->data;
 686
 687                 VOP_WIN_SET(vop, win, enable,
 688                             enabled && (vop->win_enabled & BIT(i)));
 689         }
 690         vop_cfg_done(vop);
 691
 692         spin_unlock(&vop->reg_lock);
 693 }
 694
 695 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 696                                     struct drm_crtc_state *old_state)
 697 {
 698         struct vop *vop = to_vop(crtc);
 699
 700         WARN_ON(vop->event);
 701
 702         if (crtc->state->self_refresh_active)
 703                 rockchip_drm_set_win_enabled(crtc, false);
 704
 705         mutex_lock(&vop->vop_lock);
 706
 707         drm_crtc_vblank_off(crtc);
 708
 709         if (crtc->state->self_refresh_active)
 710                 goto out;
 711
 712         /*
 713          * Vop standby will take effect at end of current frame,
 714          * if dsp hold valid irq happen, it means standby complete.
 715          *
 716          * we must wait standby complete when we want to disable aclk,
 717          * if not, memory bus maybe dead.
 718          */
 719         reinit_completion(&vop->dsp_hold_completion);
 720         vop_dsp_hold_valid_irq_enable(vop);
 721
 722         spin_lock(&vop->reg_lock);
 723
 724         VOP_REG_SET(vop, common, standby, 1);
 725
 726         spin_unlock(&vop->reg_lock);
 727
 728         wait_for_completion(&vop->dsp_hold_completion);
 729
 730         vop_dsp_hold_valid_irq_disable(vop);
 731
 732         vop->is_enabled = false;
 733
 734         /*
 735          * vop standby complete, so iommu detach is safe.
 736          */
 737         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 738
 739         clk_disable(vop->dclk);
 740         vop_core_clks_disable(vop);
 741         pm_runtime_put(vop->dev);
 742
 743 out:
 744         mutex_unlock(&vop->vop_lock);
 745
 746         if (crtc->state->event && !crtc->state->active) {
 747                 spin_lock_irq(&crtc->dev->event_lock);
 748                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 749                 spin_unlock_irq(&crtc->dev->event_lock);
 750
 751                 crtc->state->event = NULL;
 752         }
 753 }
 754
 755 static void vop_plane_destroy(struct drm_plane *plane)
 756 {
 757         drm_plane_cleanup(plane);
 758 }
 759
 760 static inline bool rockchip_afbc(u64 modifier)
 761 {
 762         return modifier == ROCKCHIP_AFBC_MOD;
 763 }
 764
 765 static bool rockchip_mod_supported(struct drm_plane *plane,
 766                                    u32 format, u64 modifier)
 767 {
 768         if (modifier == DRM_FORMAT_MOD_LINEAR)
 769                 return true;
 770
 771         if (!rockchip_afbc(modifier)) {
 772                 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
 773
 774                 return false;
 775         }
 776
 777         return vop_convert_afbc_format(format) >= 0;
 778 }
 779
 780 static int vop_plane_atomic_check(struct drm_plane *plane,
 781                            struct drm_plane_state *state)
 782 {
 783         struct drm_crtc *crtc = state->crtc;
 784         struct drm_crtc_state *crtc_state;
 785         struct drm_framebuffer *fb = state->fb;
 786         struct vop_win *vop_win = to_vop_win(plane);
 787         const struct vop_win_data *win = vop_win->data;
 788         int ret;
 789         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 790                                         DRM_PLANE_HELPER_NO_SCALING;
 791         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 792                                         DRM_PLANE_HELPER_NO_SCALING;
 793
 794         if (!crtc || WARN_ON(!fb))
 795                 return 0;
 796
 797         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 798         if (WARN_ON(!crtc_state))
 799                 return -EINVAL;
 800
 801         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 802                                                   min_scale, max_scale,
 803                                                   true, true);
 804         if (ret)
 805                 return ret;
 806
 807         if (!state->visible)
 808                 return 0;
 809
 810         ret = vop_convert_format(fb->format->format);
 811         if (ret < 0)
 812                 return ret;
 813
 814         /*
 815          * Src.x1 can be odd when do clip, but yuv plane start point
 816          * need align with 2 pixel.
 817          */
 818         if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
 819                 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
 820                 return -EINVAL;
 821         }
 822
 823         if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
 824                 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
 825                 return -EINVAL;
 826         }
 827
 828         if (rockchip_afbc(fb->modifier)) {
 829                 struct vop *vop = to_vop(crtc);
 830
 831                 if (!vop->data->afbc) {
 832                         DRM_ERROR("vop does not support AFBC\n");
 833                         return -EINVAL;
 834                 }
 835
 836                 ret = vop_convert_afbc_format(fb->format->format);
 837                 if (ret < 0)
 838                         return ret;
 839
 840                 if (state->src.x1 || state->src.y1) {
 841                         DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", state->src.x1, state->src.y1, fb->offsets[0]);
 842                         return -EINVAL;
 843                 }
 844
 845                 if (state->rotation && state->rotation != DRM_MODE_ROTATE_0) {
 846                         DRM_ERROR("No rotation support in AFBC, rotation=%d\n",
 847                                   state->rotation);
 848                         return -EINVAL;
 849                 }
 850         }
 851
 852         return 0;
 853 }
 854
 855 static void vop_plane_atomic_disable(struct drm_plane *plane,
 856                                      struct drm_plane_state *old_state)
 857 {
 858         struct vop_win *vop_win = to_vop_win(plane);
 859         struct vop *vop = to_vop(old_state->crtc);
 860
 861         if (!old_state->crtc)
 862                 return;
 863
 864         spin_lock(&vop->reg_lock);
 865
 866         vop_win_disable(vop, vop_win);
 867
 868         spin_unlock(&vop->reg_lock);
 869 }
 870
 871 static void vop_plane_atomic_update(struct drm_plane *plane,
 872                 struct drm_plane_state *old_state)
 873 {
 874         struct drm_plane_state *state = plane->state;
 875         struct drm_crtc *crtc = state->crtc;
 876         struct vop_win *vop_win = to_vop_win(plane);
 877         const struct vop_win_data *win = vop_win->data;
 878         const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
 879         struct vop *vop = to_vop(state->crtc);
 880         struct drm_framebuffer *fb = state->fb;
 881         unsigned int actual_w, actual_h;
 882         unsigned int dsp_stx, dsp_sty;
 883         uint32_t act_info, dsp_info, dsp_st;
 884         struct drm_rect *src = &state->src;
 885         struct drm_rect *dest = &state->dst;
 886         struct drm_gem_object *obj, *uv_obj;
 887         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 888         unsigned long offset;
 889         dma_addr_t dma_addr;
 890         uint32_t val;
 891         bool rb_swap;
 892         int win_index = VOP_WIN_TO_INDEX(vop_win);
 893         int format;
 894         int is_yuv = fb->format->is_yuv;
 895         int i;
 896
 897         /*
 898          * can't update plane when vop is disabled.
 899          */
 900         if (WARN_ON(!crtc))
 901                 return;
 902
 903         if (WARN_ON(!vop->is_enabled))
 904                 return;
 905
 906         if (!state->visible) {
 907                 vop_plane_atomic_disable(plane, old_state);
 908                 return;
 909         }
 910
 911         obj = fb->obj[0];
 912         rk_obj = to_rockchip_obj(obj);
 913
 914         actual_w = drm_rect_width(src) >> 16;
 915         actual_h = drm_rect_height(src) >> 16;
 916         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 917
 918         dsp_info = (drm_rect_height(dest) - 1) << 16;
 919         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 920
 921         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 922         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 923         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 924
 925         offset = (src->x1 >> 16) * fb->format->cpp[0];
 926         offset += (src->y1 >> 16) * fb->pitches[0];
 927         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 928
 929         /*
 930          * For y-mirroring we need to move address
 931          * to the beginning of the last line.
 932          */
 933         if (state->rotation & DRM_MODE_REFLECT_Y)
 934                 dma_addr += (actual_h - 1) * fb->pitches[0];
 935
 936         format = vop_convert_format(fb->format->format);
 937
 938         spin_lock(&vop->reg_lock);
 939
 940         if (rockchip_afbc(fb->modifier)) {
 941                 int afbc_format = vop_convert_afbc_format(fb->format->format);
 942
 943                 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
 944                 VOP_AFBC_SET(vop, hreg_block_split, 0);
 945                 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
 946                 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
 947                 VOP_AFBC_SET(vop, pic_size, act_info);
 948         }
 949
 950         VOP_WIN_SET(vop, win, format, format);
 951         VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 952         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 953         VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
 954         VOP_WIN_SET(vop, win, y_mir_en,
 955                     (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
 956         VOP_WIN_SET(vop, win, x_mir_en,
 957                     (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 958
 959         if (is_yuv) {
 960                 int hsub = fb->format->hsub;
 961                 int vsub = fb->format->vsub;
 962                 int bpp = fb->format->cpp[1];
 963
 964                 uv_obj = fb->obj[1];
 965                 rk_uv_obj = to_rockchip_obj(uv_obj);
 966
 967                 offset = (src->x1 >> 16) * bpp / hsub;
 968                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 969
 970                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 971                 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 972                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 973
 974                 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
 975                         VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
 976                                                         win_yuv2yuv,
 977                                                         y2r_coefficients[i],
 978                                                         bt601_yuv2rgb[i]);
 979                 }
 980         }
 981
 982         if (win->phy->scl)
 983                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 984                                     drm_rect_width(dest), drm_rect_height(dest),
 985                                     fb->format);
 986
 987         VOP_WIN_SET(vop, win, act_info, act_info);
 988         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 989         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 990
 991         rb_swap = has_rb_swapped(fb->format->format);
 992         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 993
 994         /*
 995          * Blending win0 with the background color doesn't seem to work
 996          * correctly. We only get the background color, no matter the contents
 997          * of the win0 framebuffer.  However, blending pre-multiplied color
 998          * with the default opaque black default background color is a no-op,
 999          * so we can just disable blending to get the correct result.
1000          */
1001         if (fb->format->has_alpha && win_index > 0) {
1002                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1003                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1004                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1005                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1006                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1007                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1008                         SRC_FACTOR_M0(ALPHA_ONE);
1009                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1010
1011                 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1012                 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1013                 VOP_WIN_SET(vop, win, alpha_en, 1);
1014         } else {
1015                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1016                 VOP_WIN_SET(vop, win, alpha_en, 0);
1017         }
1018
1019         VOP_WIN_SET(vop, win, enable, 1);
1020         vop->win_enabled |= BIT(win_index);
1021         spin_unlock(&vop->reg_lock);
1022 }
1023
1024 static int vop_plane_atomic_async_check(struct drm_plane *plane,
1025                                         struct drm_plane_state *state)
1026 {
1027         struct vop_win *vop_win = to_vop_win(plane);
1028         const struct vop_win_data *win = vop_win->data;
1029         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1030                                         DRM_PLANE_HELPER_NO_SCALING;
1031         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1032                                         DRM_PLANE_HELPER_NO_SCALING;
1033         struct drm_crtc_state *crtc_state;
1034
1035         if (plane != state->crtc->cursor)
1036                 return -EINVAL;
1037
1038         if (!plane->state)
1039                 return -EINVAL;
1040
1041         if (!plane->state->fb)
1042                 return -EINVAL;
1043
1044         if (state->state)
1045                 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
1046                                                                 state->crtc);
1047         else /* Special case for asynchronous cursor updates. */
1048                 crtc_state = plane->crtc->state;
1049
1050         return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1051                                                    min_scale, max_scale,
1052                                                    true, true);
1053 }
1054
1055 static void vop_plane_atomic_async_update(struct drm_plane *plane,
1056                                           struct drm_plane_state *new_state)
1057 {
1058         struct vop *vop = to_vop(plane->state->crtc);
1059         struct drm_framebuffer *old_fb = plane->state->fb;
1060
1061         plane->state->crtc_x = new_state->crtc_x;
1062         plane->state->crtc_y = new_state->crtc_y;
1063         plane->state->crtc_h = new_state->crtc_h;
1064         plane->state->crtc_w = new_state->crtc_w;
1065         plane->state->src_x = new_state->src_x;
1066         plane->state->src_y = new_state->src_y;
1067         plane->state->src_h = new_state->src_h;
1068         plane->state->src_w = new_state->src_w;
1069         swap(plane->state->fb, new_state->fb);
1070
1071         if (vop->is_enabled) {
1072                 vop_plane_atomic_update(plane, plane->state);
1073                 spin_lock(&vop->reg_lock);
1074                 vop_cfg_done(vop);
1075                 spin_unlock(&vop->reg_lock);
1076
1077                 /*
1078                  * A scanout can still be occurring, so we can't drop the
1079                  * reference to the old framebuffer. To solve this we get a
1080                  * reference to old_fb and set a worker to release it later.
1081                  * FIXME: if we perform 500 async_update calls before the
1082                  * vblank, then we can have 500 different framebuffers waiting
1083                  * to be released.
1084                  */
1085                 if (old_fb && plane->state->fb != old_fb) {
1086                         drm_framebuffer_get(old_fb);
1087                         WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1088                         drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1089                         set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1090                 }
1091         }
1092 }
1093
1094 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1095         .atomic_check = vop_plane_atomic_check,
1096         .atomic_update = vop_plane_atomic_update,
1097         .atomic_disable = vop_plane_atomic_disable,
1098         .atomic_async_check = vop_plane_atomic_async_check,
1099         .atomic_async_update = vop_plane_atomic_async_update,
1100         .prepare_fb = drm_gem_fb_prepare_fb,
1101 };
1102
1103 static const struct drm_plane_funcs vop_plane_funcs = {
1104         .update_plane   = drm_atomic_helper_update_plane,
1105         .disable_plane  = drm_atomic_helper_disable_plane,
1106         .destroy = vop_plane_destroy,
1107         .reset = drm_atomic_helper_plane_reset,
1108         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1109         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1110         .format_mod_supported = rockchip_mod_supported,
1111 };
1112
1113 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1114 {
1115         struct vop *vop = to_vop(crtc);
1116         unsigned long flags;
1117
1118         if (WARN_ON(!vop->is_enabled))
1119                 return -EPERM;
1120
1121         spin_lock_irqsave(&vop->irq_lock, flags);
1122
1123         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1124         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1125
1126         spin_unlock_irqrestore(&vop->irq_lock, flags);
1127
1128         return 0;
1129 }
1130
1131 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1132 {
1133         struct vop *vop = to_vop(crtc);
1134         unsigned long flags;
1135
1136         if (WARN_ON(!vop->is_enabled))
1137                 return;
1138
1139         spin_lock_irqsave(&vop->irq_lock, flags);
1140
1141         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1142
1143         spin_unlock_irqrestore(&vop->irq_lock, flags);
1144 }
1145
1146 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1147                                 const struct drm_display_mode *mode,
1148                                 struct drm_display_mode *adjusted_mode)
1149 {
1150         struct vop *vop = to_vop(crtc);
1151         unsigned long rate;
1152
1153         /*
1154          * Clock craziness.
1155          *
1156          * Key points:
1157          *
1158          * - DRM works in in kHz.
1159          * - Clock framework works in Hz.
1160          * - Rockchip's clock driver picks the clock rate that is the
1161          *   same _OR LOWER_ than the one requested.
1162          *
1163          * Action plan:
1164          *
1165          * 1. When DRM gives us a mode, we should add 999 Hz to it.  That way
1166          *    if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to
1167          *    make 60000 kHz then the clock framework will actually give us
1168          *    the right clock.
1169          *
1170          *    NOTE: if the PLL (maybe through a divider) could actually make
1171          *    a clock rate 999 Hz higher instead of the one we want then this
1172          *    could be a problem.  Unfortunately there's not much we can do
1173          *    since it's baked into DRM to use kHz.  It shouldn't matter in
1174          *    practice since Rockchip PLLs are controlled by tables and
1175          *    even if there is a divider in the middle I wouldn't expect PLL
1176          *    rates in the table that are just a few kHz different.
1177          *
1178          * 2. Get the clock framework to round the rate for us to tell us
1179          *    what it will actually make.
1180          *
1181          * 3. Store the rounded up rate so that we don't need to worry about
1182          *    this in the actual clk_set_rate().
1183          */
1184         rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999);
1185         adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1186
1187         return true;
1188 }
1189
1190 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1191 {
1192         return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1193 }
1194
1195 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1196 {
1197         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1198         unsigned int i;
1199
1200         for (i = 0; i < crtc->gamma_size; i++) {
1201                 u32 word;
1202
1203                 word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
1204                        (drm_color_lut_extract(lut[i].green, 10) << 10) |
1205                         drm_color_lut_extract(lut[i].blue, 10);
1206                 writel(word, vop->lut_regs + i * 4);
1207         }
1208 }
1209
1210 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1211                                struct drm_crtc_state *old_state)
1212 {
1213         struct drm_crtc_state *state = crtc->state;
1214         unsigned int idle;
1215         int ret;
1216
1217         if (!vop->lut_regs)
1218                 return;
1219         /*
1220          * To disable gamma (gamma_lut is null) or to write
1221          * an update to the LUT, clear dsp_lut_en.
1222          */
1223         spin_lock(&vop->reg_lock);
1224         VOP_REG_SET(vop, common, dsp_lut_en, 0);
1225         vop_cfg_done(vop);
1226         spin_unlock(&vop->reg_lock);
1227
1228         /*
1229          * In order to write the LUT to the internal memory,
1230          * we need to first make sure the dsp_lut_en bit is cleared.
1231          */
1232         ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1233                                  idle, !idle, 5, 30 * 1000);
1234         if (ret) {
1235                 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1236                 return;
1237         }
1238
1239         if (!state->gamma_lut)
1240                 return;
1241
1242         spin_lock(&vop->reg_lock);
1243         vop_crtc_write_gamma_lut(vop, crtc);
1244         VOP_REG_SET(vop, common, dsp_lut_en, 1);
1245         vop_cfg_done(vop);
1246         spin_unlock(&vop->reg_lock);
1247 }
1248
1249 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1250                                   struct drm_crtc_state *old_crtc_state)
1251 {
1252         struct vop *vop = to_vop(crtc);
1253
1254         /*
1255          * Only update GAMMA if the 'active' flag is not changed,
1256          * otherwise it's updated by .atomic_enable.
1257          */
1258         if (crtc->state->color_mgmt_changed &&
1259             !crtc->state->active_changed)
1260                 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1261 }
1262
1263 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1264                                    struct drm_crtc_state *old_state)
1265 {
1266         struct vop *vop = to_vop(crtc);
1267         const struct vop_data *vop_data = vop->data;
1268         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1269         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1270         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1271         u16 hdisplay = adjusted_mode->hdisplay;
1272         u16 htotal = adjusted_mode->htotal;
1273         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1274         u16 hact_end = hact_st + hdisplay;
1275         u16 vdisplay = adjusted_mode->vdisplay;
1276         u16 vtotal = adjusted_mode->vtotal;
1277         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1278         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1279         u16 vact_end = vact_st + vdisplay;
1280         uint32_t pin_pol, val;
1281         int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1282         int ret;
1283
1284         if (old_state && old_state->self_refresh_active) {
1285                 drm_crtc_vblank_on(crtc);
1286                 rockchip_drm_set_win_enabled(crtc, true);
1287                 return;
1288         }
1289
1290         /*
1291          * If we have a GAMMA LUT in the state, then let's make sure
1292          * it's updated. We might be coming out of suspend,
1293          * which means the LUT internal memory needs to be re-written.
1294          */
1295         if (crtc->state->gamma_lut)
1296                 vop_crtc_gamma_set(vop, crtc, old_state);
1297
1298         mutex_lock(&vop->vop_lock);
1299
1300         WARN_ON(vop->event);
1301
1302         ret = vop_enable(crtc, old_state);
1303         if (ret) {
1304                 mutex_unlock(&vop->vop_lock);
1305                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1306                 return;
1307         }
1308         pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1309                    BIT(HSYNC_POSITIVE) : 0;
1310         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1311                    BIT(VSYNC_POSITIVE) : 0;
1312         VOP_REG_SET(vop, output, pin_pol, pin_pol);
1313         VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1314
1315         switch (s->output_type) {
1316         case DRM_MODE_CONNECTOR_LVDS:
1317                 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1318                 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1319                 VOP_REG_SET(vop, output, rgb_en, 1);
1320                 break;
1321         case DRM_MODE_CONNECTOR_eDP:
1322                 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1323                 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1324                 VOP_REG_SET(vop, output, edp_en, 1);
1325                 break;
1326         case DRM_MODE_CONNECTOR_HDMIA:
1327                 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1328                 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1329                 VOP_REG_SET(vop, output, hdmi_en, 1);
1330                 break;
1331         case DRM_MODE_CONNECTOR_DSI:
1332                 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1333                 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1334                 VOP_REG_SET(vop, output, mipi_en, 1);
1335                 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1336                             !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1337                 break;
1338         case DRM_MODE_CONNECTOR_DisplayPort:
1339                 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1340                 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1341                 VOP_REG_SET(vop, output, dp_en, 1);
1342                 break;
1343         default:
1344                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1345                               s->output_type);
1346         }
1347
1348         /*
1349          * if vop is not support RGB10 output, need force RGB10 to RGB888.
1350          */
1351         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1352             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1353                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1354
1355         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1356                 VOP_REG_SET(vop, common, pre_dither_down, 1);
1357         else
1358                 VOP_REG_SET(vop, common, pre_dither_down, 0);
1359
1360         if (dither_bpc == 6) {
1361                 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1362                 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1363                 VOP_REG_SET(vop, common, dither_down_en, 1);
1364         } else {
1365                 VOP_REG_SET(vop, common, dither_down_en, 0);
1366         }
1367
1368         VOP_REG_SET(vop, common, out_mode, s->output_mode);
1369
1370         VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1371         val = hact_st << 16;
1372         val |= hact_end;
1373         VOP_REG_SET(vop, modeset, hact_st_end, val);
1374         VOP_REG_SET(vop, modeset, hpost_st_end, val);
1375
1376         VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1377         val = vact_st << 16;
1378         val |= vact_end;
1379         VOP_REG_SET(vop, modeset, vact_st_end, val);
1380         VOP_REG_SET(vop, modeset, vpost_st_end, val);
1381
1382         VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1383
1384         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1385
1386         VOP_REG_SET(vop, common, standby, 0);
1387         mutex_unlock(&vop->vop_lock);
1388 }
1389
1390 static bool vop_fs_irq_is_pending(struct vop *vop)
1391 {
1392         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1393 }
1394
1395 static void vop_wait_for_irq_handler(struct vop *vop)
1396 {
1397         bool pending;
1398         int ret;
1399
1400         /*
1401          * Spin until frame start interrupt status bit goes low, which means
1402          * that interrupt handler was invoked and cleared it. The timeout of
1403          * 10 msecs is really too long, but it is just a safety measure if
1404          * something goes really wrong. The wait will only happen in the very
1405          * unlikely case of a vblank happening exactly at the same time and
1406          * shouldn't exceed microseconds range.
1407          */
1408         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1409                                         !pending, 0, 10 * 1000);
1410         if (ret)
1411                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1412
1413         synchronize_irq(vop->irq);
1414 }
1415
1416 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1417                                  struct drm_crtc_state *crtc_state)
1418 {
1419         struct vop *vop = to_vop(crtc);
1420         struct drm_plane *plane;
1421         struct drm_plane_state *plane_state;
1422         struct rockchip_crtc_state *s;
1423         int afbc_planes = 0;
1424
1425         if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1426             crtc_state->gamma_lut) {
1427                 unsigned int len;
1428
1429                 len = drm_color_lut_size(crtc_state->gamma_lut);
1430                 if (len != crtc->gamma_size) {
1431                         DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1432                                       len, crtc->gamma_size);
1433                         return -EINVAL;
1434                 }
1435         }
1436
1437         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1438                 plane_state =
1439                         drm_atomic_get_plane_state(crtc_state->state, plane);
1440                 if (IS_ERR(plane_state)) {
1441                         DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1442                                       plane->name);
1443                         return PTR_ERR(plane_state);
1444                 }
1445
1446                 if (drm_is_afbc(plane_state->fb->modifier))
1447                         ++afbc_planes;
1448         }
1449
1450         if (afbc_planes > 1) {
1451                 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1452                 return -EINVAL;
1453         }
1454
1455         s = to_rockchip_crtc_state(crtc_state);
1456         s->enable_afbc = afbc_planes > 0;
1457
1458         return 0;
1459 }
1460
1461 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1462                                   struct drm_crtc_state *old_crtc_state)
1463 {
1464         struct drm_atomic_state *old_state = old_crtc_state->state;
1465         struct drm_plane_state *old_plane_state, *new_plane_state;
1466         struct vop *vop = to_vop(crtc);
1467         struct drm_plane *plane;
1468         struct rockchip_crtc_state *s;
1469         int i;
1470
1471         if (WARN_ON(!vop->is_enabled))
1472                 return;
1473
1474         spin_lock(&vop->reg_lock);
1475
1476         /* Enable AFBC if there is some AFBC window, disable otherwise. */
1477         s = to_rockchip_crtc_state(crtc->state);
1478         VOP_AFBC_SET(vop, enable, s->enable_afbc);
1479         vop_cfg_done(vop);
1480
1481         spin_unlock(&vop->reg_lock);
1482
1483         /*
1484          * There is a (rather unlikely) possiblity that a vblank interrupt
1485          * fired before we set the cfg_done bit. To avoid spuriously
1486          * signalling flip completion we need to wait for it to finish.
1487          */
1488         vop_wait_for_irq_handler(vop);
1489
1490         spin_lock_irq(&crtc->dev->event_lock);
1491         if (crtc->state->event) {
1492                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1493                 WARN_ON(vop->event);
1494
1495                 vop->event = crtc->state->event;
1496                 crtc->state->event = NULL;
1497         }
1498         spin_unlock_irq(&crtc->dev->event_lock);
1499
1500         for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1501                                        new_plane_state, i) {
1502                 if (!old_plane_state->fb)
1503                         continue;
1504
1505                 if (old_plane_state->fb == new_plane_state->fb)
1506                         continue;
1507
1508                 drm_framebuffer_get(old_plane_state->fb);
1509                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1510                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1511                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1512         }
1513 }
1514
1515 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1516         .mode_fixup = vop_crtc_mode_fixup,
1517         .atomic_check = vop_crtc_atomic_check,
1518         .atomic_begin = vop_crtc_atomic_begin,
1519         .atomic_flush = vop_crtc_atomic_flush,
1520         .atomic_enable = vop_crtc_atomic_enable,
1521         .atomic_disable = vop_crtc_atomic_disable,
1522 };
1523
1524 static void vop_crtc_destroy(struct drm_crtc *crtc)
1525 {
1526         drm_crtc_cleanup(crtc);
1527 }
1528
1529 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1530 {
1531         struct rockchip_crtc_state *rockchip_state;
1532
1533         if (WARN_ON(!crtc->state))
1534                 return NULL;
1535
1536         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1537         if (!rockchip_state)
1538                 return NULL;
1539
1540         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1541         return &rockchip_state->base;
1542 }
1543
1544 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1545                                    struct drm_crtc_state *state)
1546 {
1547         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1548
1549         __drm_atomic_helper_crtc_destroy_state(&s->base);
1550         kfree(s);
1551 }
1552
1553 static void vop_crtc_reset(struct drm_crtc *crtc)
1554 {
1555         struct rockchip_crtc_state *crtc_state =
1556                 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1557
1558         if (crtc->state)
1559                 vop_crtc_destroy_state(crtc, crtc->state);
1560
1561         __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1562 }
1563
1564 #ifdef CONFIG_DRM_ANALOGIX_DP
1565 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1566 {
1567         struct drm_connector *connector;
1568         struct drm_connector_list_iter conn_iter;
1569
1570         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1571         drm_for_each_connector_iter(connector, &conn_iter) {
1572                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1573                         drm_connector_list_iter_end(&conn_iter);
1574                         return connector;
1575                 }
1576         }
1577         drm_connector_list_iter_end(&conn_iter);
1578
1579         return NULL;
1580 }
1581
1582 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1583                                    const char *source_name)
1584 {
1585         struct vop *vop = to_vop(crtc);
1586         struct drm_connector *connector;
1587         int ret;
1588
1589         connector = vop_get_edp_connector(vop);
1590         if (!connector)
1591                 return -EINVAL;
1592
1593         if (source_name && strcmp(source_name, "auto") == 0)
1594                 ret = analogix_dp_start_crc(connector);
1595         else if (!source_name)
1596                 ret = analogix_dp_stop_crc(connector);
1597         else
1598                 ret = -EINVAL;
1599
1600         return ret;
1601 }
1602
1603 static int
1604 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1605                            size_t *values_cnt)
1606 {
1607         if (source_name && strcmp(source_name, "auto") != 0)
1608                 return -EINVAL;
1609
1610         *values_cnt = 3;
1611         return 0;
1612 }
1613
1614 #else
1615 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1616                                    const char *source_name)
1617 {
1618         return -ENODEV;
1619 }
1620
1621 static int
1622 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1623                            size_t *values_cnt)
1624 {
1625         return -ENODEV;
1626 }
1627 #endif
1628
1629 static const struct drm_crtc_funcs vop_crtc_funcs = {
1630         .set_config = drm_atomic_helper_set_config,
1631         .page_flip = drm_atomic_helper_page_flip,
1632         .destroy = vop_crtc_destroy,
1633         .reset = vop_crtc_reset,
1634         .atomic_duplicate_state = vop_crtc_duplicate_state,
1635         .atomic_destroy_state = vop_crtc_destroy_state,
1636         .enable_vblank = vop_crtc_enable_vblank,
1637         .disable_vblank = vop_crtc_disable_vblank,
1638         .set_crc_source = vop_crtc_set_crc_source,
1639         .verify_crc_source = vop_crtc_verify_crc_source,
1640         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1641 };
1642
1643 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1644 {
1645         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1646         struct drm_framebuffer *fb = val;
1647
1648         drm_crtc_vblank_put(&vop->crtc);
1649         drm_framebuffer_put(fb);
1650 }
1651
1652 static void vop_handle_vblank(struct vop *vop)
1653 {
1654         struct drm_device *drm = vop->drm_dev;
1655         struct drm_crtc *crtc = &vop->crtc;
1656
1657         spin_lock(&drm->event_lock);
1658         if (vop->event) {
1659                 drm_crtc_send_vblank_event(crtc, vop->event);
1660                 drm_crtc_vblank_put(crtc);
1661                 vop->event = NULL;
1662         }
1663         spin_unlock(&drm->event_lock);
1664
1665         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1666                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1667 }
1668
1669 static irqreturn_t vop_isr(int irq, void *data)
1670 {
1671         struct vop *vop = data;
1672         struct drm_crtc *crtc = &vop->crtc;
1673         uint32_t active_irqs;
1674         int ret = IRQ_NONE;
1675
1676         /*
1677          * The irq is shared with the iommu. If the runtime-pm state of the
1678          * vop-device is disabled the irq has to be targeted at the iommu.
1679          */
1680         if (!pm_runtime_get_if_in_use(vop->dev))
1681                 return IRQ_NONE;
1682
1683         if (vop_core_clks_enable(vop)) {
1684                 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1685                 goto out;
1686         }
1687
1688         /*
1689          * interrupt register has interrupt status, enable and clear bits, we
1690          * must hold irq_lock to avoid a race with enable/disable_vblank().
1691         */
1692         spin_lock(&vop->irq_lock);
1693
1694         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1695         /* Clear all active interrupt sources */
1696         if (active_irqs)
1697                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1698
1699         spin_unlock(&vop->irq_lock);
1700
1701         /* This is expected for vop iommu irqs, since the irq is shared */
1702         if (!active_irqs)
1703                 goto out_disable;
1704
1705         if (active_irqs & DSP_HOLD_VALID_INTR) {
1706                 complete(&vop->dsp_hold_completion);
1707                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1708                 ret = IRQ_HANDLED;
1709         }
1710
1711         if (active_irqs & LINE_FLAG_INTR) {
1712                 complete(&vop->line_flag_completion);
1713                 active_irqs &= ~LINE_FLAG_INTR;
1714                 ret = IRQ_HANDLED;
1715         }
1716
1717         if (active_irqs & FS_INTR) {
1718                 drm_crtc_handle_vblank(crtc);
1719                 vop_handle_vblank(vop);
1720                 active_irqs &= ~FS_INTR;
1721                 ret = IRQ_HANDLED;
1722         }
1723
1724         /* Unhandled irqs are spurious. */
1725         if (active_irqs)
1726                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1727                               active_irqs);
1728
1729 out_disable:
1730         vop_core_clks_disable(vop);
1731 out:
1732         pm_runtime_put(vop->dev);
1733         return ret;
1734 }
1735
1736 static void vop_plane_add_properties(struct drm_plane *plane,
1737                                      const struct vop_win_data *win_data)
1738 {
1739         unsigned int flags = 0;
1740
1741         flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1742         flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1743         if (flags)
1744                 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1745                                                    DRM_MODE_ROTATE_0 | flags);
1746 }
1747
1748 static int vop_create_crtc(struct vop *vop)
1749 {
1750         const struct vop_data *vop_data = vop->data;
1751         struct device *dev = vop->dev;
1752         struct drm_device *drm_dev = vop->drm_dev;
1753         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1754         struct drm_crtc *crtc = &vop->crtc;
1755         struct device_node *port;
1756         int ret;
1757         int i;
1758
1759         /*
1760          * Create drm_plane for primary and cursor planes first, since we need
1761          * to pass them to drm_crtc_init_with_planes, which sets the
1762          * "possible_crtcs" to the newly initialized crtc.
1763          */
1764         for (i = 0; i < vop_data->win_size; i++) {
1765                 struct vop_win *vop_win = &vop->win[i];
1766                 const struct vop_win_data *win_data = vop_win->data;
1767
1768                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1769                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1770                         continue;
1771
1772                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1773                                                0, &vop_plane_funcs,
1774                                                win_data->phy->data_formats,
1775                                                win_data->phy->nformats,
1776                                                win_data->phy->format_modifiers,
1777                                                win_data->type, NULL);
1778                 if (ret) {
1779                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1780                                       ret);
1781                         goto err_cleanup_planes;
1782                 }
1783
1784                 plane = &vop_win->base;
1785                 drm_plane_helper_add(plane, &plane_helper_funcs);
1786                 vop_plane_add_properties(plane, win_data);
1787                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1788                         primary = plane;
1789                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1790                         cursor = plane;
1791         }
1792
1793         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1794                                         &vop_crtc_funcs, NULL);
1795         if (ret)
1796                 goto err_cleanup_planes;
1797
1798         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1799         if (vop->lut_regs) {
1800                 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1801                 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1802         }
1803
1804         /*
1805          * Create drm_planes for overlay windows with possible_crtcs restricted
1806          * to the newly created crtc.
1807          */
1808         for (i = 0; i < vop_data->win_size; i++) {
1809                 struct vop_win *vop_win = &vop->win[i];
1810                 const struct vop_win_data *win_data = vop_win->data;
1811                 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1812
1813                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1814                         continue;
1815
1816                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1817                                                possible_crtcs,
1818                                                &vop_plane_funcs,
1819                                                win_data->phy->data_formats,
1820                                                win_data->phy->nformats,
1821                                                win_data->phy->format_modifiers,
1822                                                win_data->type, NULL);
1823                 if (ret) {
1824                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1825                                       ret);
1826                         goto err_cleanup_crtc;
1827                 }
1828                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1829                 vop_plane_add_properties(&vop_win->base, win_data);
1830         }
1831
1832         port = of_get_child_by_name(dev->of_node, "port");
1833         if (!port) {
1834                 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1835                               dev->of_node);
1836                 ret = -ENOENT;
1837                 goto err_cleanup_crtc;
1838         }
1839
1840         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1841                            vop_fb_unref_worker);
1842
1843         init_completion(&vop->dsp_hold_completion);
1844         init_completion(&vop->line_flag_completion);
1845         crtc->port = port;
1846
1847         ret = drm_self_refresh_helper_init(crtc);
1848         if (ret)
1849                 DRM_DEV_DEBUG_KMS(vop->dev,
1850                         "Failed to init %s with SR helpers %d, ignoring\n",
1851                         crtc->name, ret);
1852
1853         return 0;
1854
1855 err_cleanup_crtc:
1856         drm_crtc_cleanup(crtc);
1857 err_cleanup_planes:
1858         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1859                                  head)
1860                 drm_plane_cleanup(plane);
1861         return ret;
1862 }
1863
1864 static void vop_destroy_crtc(struct vop *vop)
1865 {
1866         struct drm_crtc *crtc = &vop->crtc;
1867         struct drm_device *drm_dev = vop->drm_dev;
1868         struct drm_plane *plane, *tmp;
1869
1870         drm_self_refresh_helper_cleanup(crtc);
1871
1872         of_node_put(crtc->port);
1873
1874         /*
1875          * We need to cleanup the planes now.  Why?
1876          *
1877          * The planes are "&vop->win[i].base".  That means the memory is
1878          * all part of the big "struct vop" chunk of memory.  That memory
1879          * was devm allocated and associated with this component.  We need to
1880          * free it ourselves before vop_unbind() finishes.
1881          */
1882         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1883                                  head)
1884                 vop_plane_destroy(plane);
1885
1886         /*
1887          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1888          * references the CRTC.
1889          */
1890         drm_crtc_cleanup(crtc);
1891         drm_flip_work_cleanup(&vop->fb_unref_work);
1892 }
1893
1894 static int vop_initial(struct vop *vop)
1895 {
1896         struct reset_control *ahb_rst;
1897         int i, ret;
1898
1899         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1900         if (IS_ERR(vop->hclk)) {
1901                 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1902                 return PTR_ERR(vop->hclk);
1903         }
1904         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1905         if (IS_ERR(vop->aclk)) {
1906                 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1907                 return PTR_ERR(vop->aclk);
1908         }
1909         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1910         if (IS_ERR(vop->dclk)) {
1911                 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1912                 return PTR_ERR(vop->dclk);
1913         }
1914
1915         ret = pm_runtime_get_sync(vop->dev);
1916         if (ret < 0) {
1917                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1918                 return ret;
1919         }
1920
1921         ret = clk_prepare(vop->dclk);
1922         if (ret < 0) {
1923                 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1924                 goto err_put_pm_runtime;
1925         }
1926
1927         /* Enable both the hclk and aclk to setup the vop */
1928         ret = clk_prepare_enable(vop->hclk);
1929         if (ret < 0) {
1930                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1931                 goto err_unprepare_dclk;
1932         }
1933
1934         ret = clk_prepare_enable(vop->aclk);
1935         if (ret < 0) {
1936                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1937                 goto err_disable_hclk;
1938         }
1939
1940         /*
1941          * do hclk_reset, reset all vop registers.
1942          */
1943         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1944         if (IS_ERR(ahb_rst)) {
1945                 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1946                 ret = PTR_ERR(ahb_rst);
1947                 goto err_disable_aclk;
1948         }
1949         reset_control_assert(ahb_rst);
1950         usleep_range(10, 20);
1951         reset_control_deassert(ahb_rst);
1952
1953         VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1954         VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1955
1956         for (i = 0; i < vop->len; i += sizeof(u32))
1957                 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1958
1959         VOP_REG_SET(vop, misc, global_regdone_en, 1);
1960         VOP_REG_SET(vop, common, dsp_blank, 0);
1961
1962         for (i = 0; i < vop->data->win_size; i++) {
1963                 struct vop_win *vop_win = &vop->win[i];
1964                 const struct vop_win_data *win = vop_win->data;
1965                 int channel = i * 2 + 1;
1966
1967                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1968                 vop_win_disable(vop, vop_win);
1969                 VOP_WIN_SET(vop, win, gate, 1);
1970         }
1971
1972         vop_cfg_done(vop);
1973
1974         /*
1975          * do dclk_reset, let all config take affect.
1976          */
1977         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1978         if (IS_ERR(vop->dclk_rst)) {
1979                 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1980                 ret = PTR_ERR(vop->dclk_rst);
1981                 goto err_disable_aclk;
1982         }
1983         reset_control_assert(vop->dclk_rst);
1984         usleep_range(10, 20);
1985         reset_control_deassert(vop->dclk_rst);
1986
1987         clk_disable(vop->hclk);
1988         clk_disable(vop->aclk);
1989
1990         vop->is_enabled = false;
1991
1992         pm_runtime_put_sync(vop->dev);
1993
1994         return 0;
1995
1996 err_disable_aclk:
1997         clk_disable_unprepare(vop->aclk);
1998 err_disable_hclk:
1999         clk_disable_unprepare(vop->hclk);
2000 err_unprepare_dclk:
2001         clk_unprepare(vop->dclk);
2002 err_put_pm_runtime:
2003         pm_runtime_put_sync(vop->dev);
2004         return ret;
2005 }
2006
2007 /*
2008  * Initialize the vop->win array elements.
2009  */
2010 static void vop_win_init(struct vop *vop)
2011 {
2012         const struct vop_data *vop_data = vop->data;
2013         unsigned int i;
2014
2015         for (i = 0; i < vop_data->win_size; i++) {
2016                 struct vop_win *vop_win = &vop->win[i];
2017                 const struct vop_win_data *win_data = &vop_data->win[i];
2018
2019                 vop_win->data = win_data;
2020                 vop_win->vop = vop;
2021
2022                 if (vop_data->win_yuv2yuv)
2023                         vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2024         }
2025 }
2026
2027 /**
2028  * rockchip_drm_wait_vact_end
2029  * @crtc: CRTC to enable line flag
2030  * @mstimeout: millisecond for timeout
2031  *
2032  * Wait for vact_end line flag irq or timeout.
2033  *
2034  * Returns:
2035  * Zero on success, negative errno on failure.
2036  */
2037 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2038 {
2039         struct vop *vop = to_vop(crtc);
2040         unsigned long jiffies_left;
2041         int ret = 0;
2042
2043         if (!crtc || !vop->is_enabled)
2044                 return -ENODEV;
2045
2046         mutex_lock(&vop->vop_lock);
2047         if (mstimeout <= 0) {
2048                 ret = -EINVAL;
2049                 goto out;
2050         }
2051
2052         if (vop_line_flag_irq_is_enabled(vop)) {
2053                 ret = -EBUSY;
2054                 goto out;
2055         }
2056
2057         reinit_completion(&vop->line_flag_completion);
2058         vop_line_flag_irq_enable(vop);
2059
2060         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2061                                                    msecs_to_jiffies(mstimeout));
2062         vop_line_flag_irq_disable(vop);
2063
2064         if (jiffies_left == 0) {
2065                 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2066                 ret = -ETIMEDOUT;
2067                 goto out;
2068         }
2069
2070 out:
2071         mutex_unlock(&vop->vop_lock);
2072         return ret;
2073 }
2074 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2075
2076 static int vop_bind(struct device *dev, struct device *master, void *data)
2077 {
2078         struct platform_device *pdev = to_platform_device(dev);
2079         const struct vop_data *vop_data;
2080         struct drm_device *drm_dev = data;
2081         struct vop *vop;
2082         struct resource *res;
2083         int ret, irq;
2084
2085         vop_data = of_device_get_match_data(dev);
2086         if (!vop_data)
2087                 return -ENODEV;
2088
2089         /* Allocate vop struct and its vop_win array */
2090         vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2091                            GFP_KERNEL);
2092         if (!vop)
2093                 return -ENOMEM;
2094
2095         vop->dev = dev;
2096         vop->data = vop_data;
2097         vop->drm_dev = drm_dev;
2098         dev_set_drvdata(dev, vop);
2099
2100         vop_win_init(vop);
2101
2102         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2103         vop->regs = devm_ioremap_resource(dev, res);
2104         if (IS_ERR(vop->regs))
2105                 return PTR_ERR(vop->regs);
2106         vop->len = resource_size(res);
2107
2108         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2109         if (res) {
2110                 if (!vop_data->lut_size) {
2111                         DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
2112                         return -EINVAL;
2113                 }
2114                 vop->lut_regs = devm_ioremap_resource(dev, res);
2115                 if (IS_ERR(vop->lut_regs))
2116                         return PTR_ERR(vop->lut_regs);
2117         }
2118
2119         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2120         if (!vop->regsbak)
2121                 return -ENOMEM;
2122
2123         irq = platform_get_irq(pdev, 0);
2124         if (irq < 0) {
2125                 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2126                 return irq;
2127         }
2128         vop->irq = (unsigned int)irq;
2129
2130         spin_lock_init(&vop->reg_lock);
2131         spin_lock_init(&vop->irq_lock);
2132         mutex_init(&vop->vop_lock);
2133
2134         ret = vop_create_crtc(vop);
2135         if (ret)
2136                 return ret;
2137
2138         pm_runtime_enable(&pdev->dev);
2139
2140         ret = vop_initial(vop);
2141         if (ret < 0) {
2142                 DRM_DEV_ERROR(&pdev->dev,
2143                               "cannot initial vop dev - err %d\n", ret);
2144                 goto err_disable_pm_runtime;
2145         }
2146
2147         ret = devm_request_irq(dev, vop->irq, vop_isr,
2148                                IRQF_SHARED, dev_name(dev), vop);
2149         if (ret)
2150                 goto err_disable_pm_runtime;
2151
2152         if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2153                 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
2154                 if (IS_ERR(vop->rgb)) {
2155                         ret = PTR_ERR(vop->rgb);
2156                         goto err_disable_pm_runtime;
2157                 }
2158         }
2159
2160         return 0;
2161
2162 err_disable_pm_runtime:
2163         pm_runtime_disable(&pdev->dev);
2164         vop_destroy_crtc(vop);
2165         return ret;
2166 }
2167
2168 static void vop_unbind(struct device *dev, struct device *master, void *data)
2169 {
2170         struct vop *vop = dev_get_drvdata(dev);
2171
2172         if (vop->rgb)
2173                 rockchip_rgb_fini(vop->rgb);
2174
2175         pm_runtime_disable(dev);
2176         vop_destroy_crtc(vop);
2177
2178         clk_unprepare(vop->aclk);
2179         clk_unprepare(vop->hclk);
2180         clk_unprepare(vop->dclk);
2181 }
2182
2183 const struct component_ops vop_component_ops = {
2184         .bind = vop_bind,
2185         .unbind = vop_unbind,
2186 };
2187 EXPORT_SYMBOL_GPL(vop_component_ops);