drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22 #ifdef CONFIG_DRM_ANALOGIX_DP
  23 #include <drm/bridge/analogix_dp.h>
  24 #endif
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <linux/iopoll.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/component.h>
  35
  36 #include <linux/reset.h>
  37 #include <linux/delay.h>
  38
  39 #include "rockchip_drm_drv.h"
  40 #include "rockchip_drm_gem.h"
  41 #include "rockchip_drm_fb.h"
  42 #include "rockchip_drm_psr.h"
  43 #include "rockchip_drm_vop.h"
  44
  45 #define VOP_WIN_SET(x, win, name, v) \
  46                 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
  47 #define VOP_SCL_SET(x, win, name, v) \
  48                 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
  49 #define VOP_SCL_SET_EXT(x, win, name, v) \
  50                 vop_reg_set(vop, &win->phy->scl->ext->name, \
  51                             win->base, ~0, v, #name)
  52
  53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  54                 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
  55
  56 #define VOP_REG_SET(vop, group, name, v) \
  57                     vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
  58
  59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  60         do { \
  61                 int i, reg = 0, mask = 0; \
  62                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  63                         if (vop->data->intr->intrs[i] & type) { \
  64                                 reg |= (v) << i; \
  65                                 mask |= 1 << i; \
  66                         } \
  67                 } \
  68                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
  69         } while (0)
  70 #define VOP_INTR_GET_TYPE(vop, name, type) \
  71                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  72
  73 #define VOP_WIN_GET(x, win, name) \
  74                 vop_read_reg(x, win->offset, win->phy->name)
  75
  76 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  77                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  78
  79 #define to_vop(x) container_of(x, struct vop, crtc)
  80 #define to_vop_win(x) container_of(x, struct vop_win, base)
  81
  82 enum vop_pending {
  83         VOP_PENDING_FB_UNREF,
  84 };
  85
  86 struct vop_win {
  87         struct drm_plane base;
  88         const struct vop_win_data *data;
  89         struct vop *vop;
  90 };
  91
  92 struct vop {
  93         struct drm_crtc crtc;
  94         struct device *dev;
  95         struct drm_device *drm_dev;
  96         bool is_enabled;
  97
  98         /* mutex vsync_ work */
  99         struct mutex vsync_mutex;
 100         bool vsync_work_pending;
 101         struct completion dsp_hold_completion;
 102
 103         /* protected by dev->event_lock */
 104         struct drm_pending_vblank_event *event;
 105
 106         struct drm_flip_work fb_unref_work;
 107         unsigned long pending;
 108
 109         struct completion line_flag_completion;
 110
 111         const struct vop_data *data;
 112
 113         uint32_t *regsbak;
 114         void __iomem *regs;
 115
 116         /* physical map length of vop register */
 117         uint32_t len;
 118
 119         /* one time only one process allowed to config the register */
 120         spinlock_t reg_lock;
 121         /* lock vop irq reg */
 122         spinlock_t irq_lock;
 123
 124         unsigned int irq;
 125
 126         /* vop AHP clk */
 127         struct clk *hclk;
 128         /* vop dclk */
 129         struct clk *dclk;
 130         /* vop share memory frequency */
 131         struct clk *aclk;
 132
 133         /* vop dclk reset */
 134         struct reset_control *dclk_rst;
 135
 136         struct vop_win win[];
 137 };
 138
 139 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 140 {
 141         writel(v, vop->regs + offset);
 142         vop->regsbak[offset >> 2] = v;
 143 }
 144
 145 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 146 {
 147         return readl(vop->regs + offset);
 148 }
 149
 150 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 151                                     const struct vop_reg *reg)
 152 {
 153         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 154 }
 155
 156 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
 157                         uint32_t _offset, uint32_t _mask, uint32_t v,
 158                         const char *reg_name)
 159 {
 160         int offset, mask, shift;
 161
 162         if (!reg || !reg->mask) {
 163                 dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
 164                 return;
 165         }
 166
 167         offset = reg->offset + _offset;
 168         mask = reg->mask & _mask;
 169         shift = reg->shift;
 170
 171         if (reg->write_mask) {
 172                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 173         } else {
 174                 uint32_t cached_val = vop->regsbak[offset >> 2];
 175
 176                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 177                 vop->regsbak[offset >> 2] = v;
 178         }
 179
 180         if (reg->relaxed)
 181                 writel_relaxed(v, vop->regs + offset);
 182         else
 183                 writel(v, vop->regs + offset);
 184 }
 185
 186 static inline uint32_t vop_get_intr_type(struct vop *vop,
 187                                          const struct vop_reg *reg, int type)
 188 {
 189         uint32_t i, ret = 0;
 190         uint32_t regs = vop_read_reg(vop, 0, reg);
 191
 192         for (i = 0; i < vop->data->intr->nintrs; i++) {
 193                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 194                         ret |= vop->data->intr->intrs[i];
 195         }
 196
 197         return ret;
 198 }
 199
 200 static inline void vop_cfg_done(struct vop *vop)
 201 {
 202         VOP_REG_SET(vop, common, cfg_done, 1);
 203 }
 204
 205 static bool has_rb_swapped(uint32_t version, uint32_t format)
 206 {
 207         switch (format) {
 208         case DRM_FORMAT_XBGR8888:
 209         case DRM_FORMAT_ABGR8888:
 210         case DRM_FORMAT_BGR565:
 211                 return true;
 212         /*
 213          * full framework (IP version 3.x) only need rb swapped for RGB888 and
 214          * little framework (IP version 2.x) only need rb swapped for BGR888,
 215          * check for 3.x to also only rb swap BGR888 for unknown vop version
 216          */
 217         case DRM_FORMAT_RGB888:
 218                 return VOP_MAJOR(version) == 3;
 219         case DRM_FORMAT_BGR888:
 220                 return VOP_MAJOR(version) != 3;
 221         default:
 222                 return false;
 223         }
 224 }
 225
 226 static enum vop_data_format vop_convert_format(uint32_t format)
 227 {
 228         switch (format) {
 229         case DRM_FORMAT_XRGB8888:
 230         case DRM_FORMAT_ARGB8888:
 231         case DRM_FORMAT_XBGR8888:
 232         case DRM_FORMAT_ABGR8888:
 233                 return VOP_FMT_ARGB8888;
 234         case DRM_FORMAT_RGB888:
 235         case DRM_FORMAT_BGR888:
 236                 return VOP_FMT_RGB888;
 237         case DRM_FORMAT_RGB565:
 238         case DRM_FORMAT_BGR565:
 239                 return VOP_FMT_RGB565;
 240         case DRM_FORMAT_NV12:
 241                 return VOP_FMT_YUV420SP;
 242         case DRM_FORMAT_NV16:
 243                 return VOP_FMT_YUV422SP;
 244         case DRM_FORMAT_NV24:
 245                 return VOP_FMT_YUV444SP;
 246         default:
 247                 DRM_ERROR("unsupported format[%08x]\n", format);
 248                 return -EINVAL;
 249         }
 250 }
 251
 252 static bool is_yuv_support(uint32_t format)
 253 {
 254         switch (format) {
 255         case DRM_FORMAT_NV12:
 256         case DRM_FORMAT_NV16:
 257         case DRM_FORMAT_NV24:
 258                 return true;
 259         default:
 260                 return false;
 261         }
 262 }
 263
 264 static bool is_alpha_support(uint32_t format)
 265 {
 266         switch (format) {
 267         case DRM_FORMAT_ARGB8888:
 268         case DRM_FORMAT_ABGR8888:
 269                 return true;
 270         default:
 271                 return false;
 272         }
 273 }
 274
 275 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 276                                   uint32_t dst, bool is_horizontal,
 277                                   int vsu_mode, int *vskiplines)
 278 {
 279         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 280
 281         if (is_horizontal) {
 282                 if (mode == SCALE_UP)
 283                         val = GET_SCL_FT_BIC(src, dst);
 284                 else if (mode == SCALE_DOWN)
 285                         val = GET_SCL_FT_BILI_DN(src, dst);
 286         } else {
 287                 if (mode == SCALE_UP) {
 288                         if (vsu_mode == SCALE_UP_BIL)
 289                                 val = GET_SCL_FT_BILI_UP(src, dst);
 290                         else
 291                                 val = GET_SCL_FT_BIC(src, dst);
 292                 } else if (mode == SCALE_DOWN) {
 293                         if (vskiplines) {
 294                                 *vskiplines = scl_get_vskiplines(src, dst);
 295                                 val = scl_get_bili_dn_vskip(src, dst,
 296                                                             *vskiplines);
 297                         } else {
 298                                 val = GET_SCL_FT_BILI_DN(src, dst);
 299                         }
 300                 }
 301         }
 302
 303         return val;
 304 }
 305
 306 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 307                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 308                              uint32_t dst_h, uint32_t pixel_format)
 309 {
 310         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 311         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 312         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 313         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 314         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 315         bool is_yuv = is_yuv_support(pixel_format);
 316         uint16_t cbcr_src_w = src_w / hsub;
 317         uint16_t cbcr_src_h = src_h / vsub;
 318         uint16_t vsu_mode;
 319         uint16_t lb_mode;
 320         uint32_t val;
 321         int vskiplines = 0;
 322
 323         if (dst_w > 3840) {
 324                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 325                 return;
 326         }
 327
 328         if (!win->phy->scl->ext) {
 329                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 330                             scl_cal_scale2(src_w, dst_w));
 331                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 332                             scl_cal_scale2(src_h, dst_h));
 333                 if (is_yuv) {
 334                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 335                                     scl_cal_scale2(cbcr_src_w, dst_w));
 336                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 337                                     scl_cal_scale2(cbcr_src_h, dst_h));
 338                 }
 339                 return;
 340         }
 341
 342         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 343         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 344
 345         if (is_yuv) {
 346                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 347                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 348                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 349                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 350                 else
 351                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 352         } else {
 353                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 354                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 355                 else
 356                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 357         }
 358
 359         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 360         if (lb_mode == LB_RGB_3840X2) {
 361                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 362                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 363                         return;
 364                 }
 365                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 366                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 367                         return;
 368                 }
 369                 vsu_mode = SCALE_UP_BIL;
 370         } else if (lb_mode == LB_RGB_2560X4) {
 371                 vsu_mode = SCALE_UP_BIL;
 372         } else {
 373                 vsu_mode = SCALE_UP_BIC;
 374         }
 375
 376         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 377                                 true, 0, NULL);
 378         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 379         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 380                                 false, vsu_mode, &vskiplines);
 381         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 382
 383         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 384         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 385
 386         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 387         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 388         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 389         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 390         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 391         if (is_yuv) {
 392                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 393                                         dst_w, true, 0, NULL);
 394                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 395                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 396                                         dst_h, false, vsu_mode, &vskiplines);
 397                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 398
 399                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 400                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 401                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 402                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 403                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 404                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 405                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 406         }
 407 }
 408
 409 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 410 {
 411         unsigned long flags;
 412
 413         if (WARN_ON(!vop->is_enabled))
 414                 return;
 415
 416         spin_lock_irqsave(&vop->irq_lock, flags);
 417
 418         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 419         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 420
 421         spin_unlock_irqrestore(&vop->irq_lock, flags);
 422 }
 423
 424 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 425 {
 426         unsigned long flags;
 427
 428         if (WARN_ON(!vop->is_enabled))
 429                 return;
 430
 431         spin_lock_irqsave(&vop->irq_lock, flags);
 432
 433         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 434
 435         spin_unlock_irqrestore(&vop->irq_lock, flags);
 436 }
 437
 438 /*
 439  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 440  *     the "FRAME_SYNC" interrupt.
 441  * (2) the active data region of each frame ends at dsp_vact_end
 442  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 443  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 444  *
 445  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 446  * Interrupts
 447  * LINE_FLAG -------------------------------+
 448  * FRAME_SYNC ----+                         |
 449  *                |                         |
 450  *                v                         v
 451  *                | Vsync | Vbp |  Vactive  | Vfp |
 452  *                        ^     ^           ^     ^
 453  *                        |     |           |     |
 454  *                        |     |           |     |
 455  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 456  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 457  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 458  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 459  */
 460 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 461 {
 462         uint32_t line_flag_irq;
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&vop->irq_lock, flags);
 466
 467         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 468
 469         spin_unlock_irqrestore(&vop->irq_lock, flags);
 470
 471         return !!line_flag_irq;
 472 }
 473
 474 static void vop_line_flag_irq_enable(struct vop *vop)
 475 {
 476         unsigned long flags;
 477
 478         if (WARN_ON(!vop->is_enabled))
 479                 return;
 480
 481         spin_lock_irqsave(&vop->irq_lock, flags);
 482
 483         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 484         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 485
 486         spin_unlock_irqrestore(&vop->irq_lock, flags);
 487 }
 488
 489 static void vop_line_flag_irq_disable(struct vop *vop)
 490 {
 491         unsigned long flags;
 492
 493         if (WARN_ON(!vop->is_enabled))
 494                 return;
 495
 496         spin_lock_irqsave(&vop->irq_lock, flags);
 497
 498         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 499
 500         spin_unlock_irqrestore(&vop->irq_lock, flags);
 501 }
 502
 503 static int vop_enable(struct drm_crtc *crtc)
 504 {
 505         struct vop *vop = to_vop(crtc);
 506         int ret, i;
 507
 508         ret = pm_runtime_get_sync(vop->dev);
 509         if (ret < 0) {
 510                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 511                 return ret;
 512         }
 513
 514         ret = clk_enable(vop->hclk);
 515         if (WARN_ON(ret < 0))
 516                 goto err_put_pm_runtime;
 517
 518         ret = clk_enable(vop->dclk);
 519         if (WARN_ON(ret < 0))
 520                 goto err_disable_hclk;
 521
 522         ret = clk_enable(vop->aclk);
 523         if (WARN_ON(ret < 0))
 524                 goto err_disable_dclk;
 525
 526         /*
 527          * Slave iommu shares power, irq and clock with vop.  It was associated
 528          * automatically with this master device via common driver code.
 529          * Now that we have enabled the clock we attach it to the shared drm
 530          * mapping.
 531          */
 532         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 533         if (ret) {
 534                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 535                 goto err_disable_aclk;
 536         }
 537
 538         memcpy(vop->regs, vop->regsbak, vop->len);
 539         /*
 540          * We need to make sure that all windows are disabled before we
 541          * enable the crtc. Otherwise we might try to scan from a destroyed
 542          * buffer later.
 543          */
 544         for (i = 0; i < vop->data->win_size; i++) {
 545                 struct vop_win *vop_win = &vop->win[i];
 546                 const struct vop_win_data *win = vop_win->data;
 547
 548                 spin_lock(&vop->reg_lock);
 549                 VOP_WIN_SET(vop, win, enable, 0);
 550                 spin_unlock(&vop->reg_lock);
 551         }
 552
 553         vop_cfg_done(vop);
 554
 555         /*
 556          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 557          */
 558         vop->is_enabled = true;
 559
 560         spin_lock(&vop->reg_lock);
 561
 562         VOP_REG_SET(vop, common, standby, 1);
 563
 564         spin_unlock(&vop->reg_lock);
 565
 566         enable_irq(vop->irq);
 567
 568         drm_crtc_vblank_on(crtc);
 569
 570         return 0;
 571
 572 err_disable_aclk:
 573         clk_disable(vop->aclk);
 574 err_disable_dclk:
 575         clk_disable(vop->dclk);
 576 err_disable_hclk:
 577         clk_disable(vop->hclk);
 578 err_put_pm_runtime:
 579         pm_runtime_put_sync(vop->dev);
 580         return ret;
 581 }
 582
 583 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 584                                     struct drm_crtc_state *old_state)
 585 {
 586         struct vop *vop = to_vop(crtc);
 587
 588         WARN_ON(vop->event);
 589
 590         rockchip_drm_psr_deactivate(&vop->crtc);
 591
 592         drm_crtc_vblank_off(crtc);
 593
 594         /*
 595          * Vop standby will take effect at end of current frame,
 596          * if dsp hold valid irq happen, it means standby complete.
 597          *
 598          * we must wait standby complete when we want to disable aclk,
 599          * if not, memory bus maybe dead.
 600          */
 601         reinit_completion(&vop->dsp_hold_completion);
 602         vop_dsp_hold_valid_irq_enable(vop);
 603
 604         spin_lock(&vop->reg_lock);
 605
 606         VOP_REG_SET(vop, common, standby, 1);
 607
 608         spin_unlock(&vop->reg_lock);
 609
 610         wait_for_completion(&vop->dsp_hold_completion);
 611
 612         vop_dsp_hold_valid_irq_disable(vop);
 613
 614         disable_irq(vop->irq);
 615
 616         vop->is_enabled = false;
 617
 618         /*
 619          * vop standby complete, so iommu detach is safe.
 620          */
 621         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 622
 623         clk_disable(vop->dclk);
 624         clk_disable(vop->aclk);
 625         clk_disable(vop->hclk);
 626         pm_runtime_put(vop->dev);
 627
 628         if (crtc->state->event && !crtc->state->active) {
 629                 spin_lock_irq(&crtc->dev->event_lock);
 630                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 631                 spin_unlock_irq(&crtc->dev->event_lock);
 632
 633                 crtc->state->event = NULL;
 634         }
 635 }
 636
 637 static void vop_plane_destroy(struct drm_plane *plane)
 638 {
 639         drm_plane_cleanup(plane);
 640 }
 641
 642 static int vop_plane_atomic_check(struct drm_plane *plane,
 643                            struct drm_plane_state *state)
 644 {
 645         struct drm_crtc *crtc = state->crtc;
 646         struct drm_crtc_state *crtc_state;
 647         struct drm_framebuffer *fb = state->fb;
 648         struct vop_win *vop_win = to_vop_win(plane);
 649         const struct vop_win_data *win = vop_win->data;
 650         int ret;
 651         struct drm_rect clip;
 652         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 653                                         DRM_PLANE_HELPER_NO_SCALING;
 654         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 655                                         DRM_PLANE_HELPER_NO_SCALING;
 656
 657         if (!crtc || !fb)
 658                 return 0;
 659
 660         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 661         if (WARN_ON(!crtc_state))
 662                 return -EINVAL;
 663
 664         clip.x1 = 0;
 665         clip.y1 = 0;
 666         clip.x2 = crtc_state->adjusted_mode.hdisplay;
 667         clip.y2 = crtc_state->adjusted_mode.vdisplay;
 668
 669         ret = drm_plane_helper_check_state(state, &clip,
 670                                            min_scale, max_scale,
 671                                            true, true);
 672         if (ret)
 673                 return ret;
 674
 675         if (!state->visible)
 676                 return 0;
 677
 678         ret = vop_convert_format(fb->format->format);
 679         if (ret < 0)
 680                 return ret;
 681
 682         /*
 683          * Src.x1 can be odd when do clip, but yuv plane start point
 684          * need align with 2 pixel.
 685          */
 686         if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) {
 687                 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
 688                 return -EINVAL;
 689         }
 690
 691         return 0;
 692 }
 693
 694 static void vop_plane_atomic_disable(struct drm_plane *plane,
 695                                      struct drm_plane_state *old_state)
 696 {
 697         struct vop_win *vop_win = to_vop_win(plane);
 698         const struct vop_win_data *win = vop_win->data;
 699         struct vop *vop = to_vop(old_state->crtc);
 700
 701         if (!old_state->crtc)
 702                 return;
 703
 704         spin_lock(&vop->reg_lock);
 705
 706         VOP_WIN_SET(vop, win, enable, 0);
 707
 708         spin_unlock(&vop->reg_lock);
 709 }
 710
 711 static void vop_plane_atomic_update(struct drm_plane *plane,
 712                 struct drm_plane_state *old_state)
 713 {
 714         struct drm_plane_state *state = plane->state;
 715         struct drm_crtc *crtc = state->crtc;
 716         struct vop_win *vop_win = to_vop_win(plane);
 717         const struct vop_win_data *win = vop_win->data;
 718         struct vop *vop = to_vop(state->crtc);
 719         struct drm_framebuffer *fb = state->fb;
 720         unsigned int actual_w, actual_h;
 721         unsigned int dsp_stx, dsp_sty;
 722         uint32_t act_info, dsp_info, dsp_st;
 723         struct drm_rect *src = &state->src;
 724         struct drm_rect *dest = &state->dst;
 725         struct drm_gem_object *obj, *uv_obj;
 726         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 727         unsigned long offset;
 728         dma_addr_t dma_addr;
 729         uint32_t val;
 730         bool rb_swap;
 731         int format;
 732
 733         /*
 734          * can't update plane when vop is disabled.
 735          */
 736         if (WARN_ON(!crtc))
 737                 return;
 738
 739         if (WARN_ON(!vop->is_enabled))
 740                 return;
 741
 742         if (!state->visible) {
 743                 vop_plane_atomic_disable(plane, old_state);
 744                 return;
 745         }
 746
 747         obj = rockchip_fb_get_gem_obj(fb, 0);
 748         rk_obj = to_rockchip_obj(obj);
 749
 750         actual_w = drm_rect_width(src) >> 16;
 751         actual_h = drm_rect_height(src) >> 16;
 752         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 753
 754         dsp_info = (drm_rect_height(dest) - 1) << 16;
 755         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 756
 757         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 758         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 759         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 760
 761         offset = (src->x1 >> 16) * fb->format->cpp[0];
 762         offset += (src->y1 >> 16) * fb->pitches[0];
 763         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 764
 765         format = vop_convert_format(fb->format->format);
 766
 767         spin_lock(&vop->reg_lock);
 768
 769         VOP_WIN_SET(vop, win, format, format);
 770         VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 771         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 772         if (is_yuv_support(fb->format->format)) {
 773                 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
 774                 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
 775                 int bpp = fb->format->cpp[1];
 776
 777                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 778                 rk_uv_obj = to_rockchip_obj(uv_obj);
 779
 780                 offset = (src->x1 >> 16) * bpp / hsub;
 781                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 782
 783                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 784                 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 785                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 786         }
 787
 788         if (win->phy->scl)
 789                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 790                                     drm_rect_width(dest), drm_rect_height(dest),
 791                                     fb->format->format);
 792
 793         VOP_WIN_SET(vop, win, act_info, act_info);
 794         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 795         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 796
 797         rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
 798         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 799
 800         if (is_alpha_support(fb->format->format)) {
 801                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 802                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 803                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 804                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 805                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 806                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 807                         SRC_FACTOR_M0(ALPHA_ONE);
 808                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 809         } else {
 810                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 811         }
 812
 813         VOP_WIN_SET(vop, win, enable, 1);
 814         spin_unlock(&vop->reg_lock);
 815 }
 816
 817 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 818         .atomic_check = vop_plane_atomic_check,
 819         .atomic_update = vop_plane_atomic_update,
 820         .atomic_disable = vop_plane_atomic_disable,
 821 };
 822
 823 static const struct drm_plane_funcs vop_plane_funcs = {
 824         .update_plane   = drm_atomic_helper_update_plane,
 825         .disable_plane  = drm_atomic_helper_disable_plane,
 826         .destroy = vop_plane_destroy,
 827         .reset = drm_atomic_helper_plane_reset,
 828         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 829         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 830 };
 831
 832 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 833 {
 834         struct vop *vop = to_vop(crtc);
 835         unsigned long flags;
 836
 837         if (WARN_ON(!vop->is_enabled))
 838                 return -EPERM;
 839
 840         spin_lock_irqsave(&vop->irq_lock, flags);
 841
 842         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
 843         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 844
 845         spin_unlock_irqrestore(&vop->irq_lock, flags);
 846
 847         return 0;
 848 }
 849
 850 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 851 {
 852         struct vop *vop = to_vop(crtc);
 853         unsigned long flags;
 854
 855         if (WARN_ON(!vop->is_enabled))
 856                 return;
 857
 858         spin_lock_irqsave(&vop->irq_lock, flags);
 859
 860         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 861
 862         spin_unlock_irqrestore(&vop->irq_lock, flags);
 863 }
 864
 865 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 866                                 const struct drm_display_mode *mode,
 867                                 struct drm_display_mode *adjusted_mode)
 868 {
 869         struct vop *vop = to_vop(crtc);
 870
 871         adjusted_mode->clock =
 872                 DIV_ROUND_UP(clk_round_rate(vop->dclk, mode->clock * 1000),
 873                              1000);
 874
 875         return true;
 876 }
 877
 878 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
 879                                    struct drm_crtc_state *old_state)
 880 {
 881         struct vop *vop = to_vop(crtc);
 882         const struct vop_data *vop_data = vop->data;
 883         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 884         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 885         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 886         u16 hdisplay = adjusted_mode->hdisplay;
 887         u16 htotal = adjusted_mode->htotal;
 888         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 889         u16 hact_end = hact_st + hdisplay;
 890         u16 vdisplay = adjusted_mode->vdisplay;
 891         u16 vtotal = adjusted_mode->vtotal;
 892         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 893         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 894         u16 vact_end = vact_st + vdisplay;
 895         uint32_t pin_pol, val;
 896         int ret;
 897
 898         WARN_ON(vop->event);
 899
 900         ret = vop_enable(crtc);
 901         if (ret) {
 902                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
 903                 return;
 904         }
 905
 906         pin_pol = BIT(DCLK_INVERT);
 907         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
 908                    BIT(HSYNC_POSITIVE) : 0;
 909         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
 910                    BIT(VSYNC_POSITIVE) : 0;
 911         VOP_REG_SET(vop, output, pin_pol, pin_pol);
 912
 913         switch (s->output_type) {
 914         case DRM_MODE_CONNECTOR_LVDS:
 915                 VOP_REG_SET(vop, output, rgb_en, 1);
 916                 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
 917                 break;
 918         case DRM_MODE_CONNECTOR_eDP:
 919                 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
 920                 VOP_REG_SET(vop, output, edp_en, 1);
 921                 break;
 922         case DRM_MODE_CONNECTOR_HDMIA:
 923                 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
 924                 VOP_REG_SET(vop, output, hdmi_en, 1);
 925                 break;
 926         case DRM_MODE_CONNECTOR_DSI:
 927                 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
 928                 VOP_REG_SET(vop, output, mipi_en, 1);
 929                 break;
 930         case DRM_MODE_CONNECTOR_DisplayPort:
 931                 pin_pol &= ~BIT(DCLK_INVERT);
 932                 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
 933                 VOP_REG_SET(vop, output, dp_en, 1);
 934                 break;
 935         default:
 936                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
 937                               s->output_type);
 938         }
 939
 940         /*
 941          * if vop is not support RGB10 output, need force RGB10 to RGB888.
 942          */
 943         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
 944             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
 945                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 946         VOP_REG_SET(vop, common, out_mode, s->output_mode);
 947
 948         VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
 949         val = hact_st << 16;
 950         val |= hact_end;
 951         VOP_REG_SET(vop, modeset, hact_st_end, val);
 952         VOP_REG_SET(vop, modeset, hpost_st_end, val);
 953
 954         VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
 955         val = vact_st << 16;
 956         val |= vact_end;
 957         VOP_REG_SET(vop, modeset, vact_st_end, val);
 958         VOP_REG_SET(vop, modeset, vpost_st_end, val);
 959
 960         VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
 961
 962         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 963
 964         VOP_REG_SET(vop, common, standby, 0);
 965
 966         rockchip_drm_psr_activate(&vop->crtc);
 967 }
 968
 969 static bool vop_fs_irq_is_pending(struct vop *vop)
 970 {
 971         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 972 }
 973
 974 static void vop_wait_for_irq_handler(struct vop *vop)
 975 {
 976         bool pending;
 977         int ret;
 978
 979         /*
 980          * Spin until frame start interrupt status bit goes low, which means
 981          * that interrupt handler was invoked and cleared it. The timeout of
 982          * 10 msecs is really too long, but it is just a safety measure if
 983          * something goes really wrong. The wait will only happen in the very
 984          * unlikely case of a vblank happening exactly at the same time and
 985          * shouldn't exceed microseconds range.
 986          */
 987         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
 988                                         !pending, 0, 10 * 1000);
 989         if (ret)
 990                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
 991
 992         synchronize_irq(vop->irq);
 993 }
 994
 995 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
 996                                   struct drm_crtc_state *old_crtc_state)
 997 {
 998         struct drm_atomic_state *old_state = old_crtc_state->state;
 999         struct drm_plane_state *old_plane_state, *new_plane_state;
1000         struct vop *vop = to_vop(crtc);
1001         struct drm_plane *plane;
1002         int i;
1003
1004         if (WARN_ON(!vop->is_enabled))
1005                 return;
1006
1007         spin_lock(&vop->reg_lock);
1008
1009         vop_cfg_done(vop);
1010
1011         spin_unlock(&vop->reg_lock);
1012
1013         /*
1014          * There is a (rather unlikely) possiblity that a vblank interrupt
1015          * fired before we set the cfg_done bit. To avoid spuriously
1016          * signalling flip completion we need to wait for it to finish.
1017          */
1018         vop_wait_for_irq_handler(vop);
1019
1020         spin_lock_irq(&crtc->dev->event_lock);
1021         if (crtc->state->event) {
1022                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1023                 WARN_ON(vop->event);
1024
1025                 vop->event = crtc->state->event;
1026                 crtc->state->event = NULL;
1027         }
1028         spin_unlock_irq(&crtc->dev->event_lock);
1029
1030         for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1031                                        new_plane_state, i) {
1032                 if (!old_plane_state->fb)
1033                         continue;
1034
1035                 if (old_plane_state->fb == new_plane_state->fb)
1036                         continue;
1037
1038                 drm_framebuffer_get(old_plane_state->fb);
1039                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1040                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1041                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1042         }
1043 }
1044
1045 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1046                                   struct drm_crtc_state *old_crtc_state)
1047 {
1048         rockchip_drm_psr_flush(crtc);
1049 }
1050
1051 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1052         .mode_fixup = vop_crtc_mode_fixup,
1053         .atomic_flush = vop_crtc_atomic_flush,
1054         .atomic_begin = vop_crtc_atomic_begin,
1055         .atomic_enable = vop_crtc_atomic_enable,
1056         .atomic_disable = vop_crtc_atomic_disable,
1057 };
1058
1059 static void vop_crtc_destroy(struct drm_crtc *crtc)
1060 {
1061         drm_crtc_cleanup(crtc);
1062 }
1063
1064 static void vop_crtc_reset(struct drm_crtc *crtc)
1065 {
1066         if (crtc->state)
1067                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1068         kfree(crtc->state);
1069
1070         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1071         if (crtc->state)
1072                 crtc->state->crtc = crtc;
1073 }
1074
1075 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1076 {
1077         struct rockchip_crtc_state *rockchip_state;
1078
1079         if (WARN_ON(!crtc->state))
1080                 return NULL;
1081
1082         rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state),
1083                                  sizeof(*rockchip_state), GFP_KERNEL);
1084         if (!rockchip_state)
1085                 return NULL;
1086
1087         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1088         return &rockchip_state->base;
1089 }
1090
1091 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1092                                    struct drm_crtc_state *state)
1093 {
1094         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1095
1096         __drm_atomic_helper_crtc_destroy_state(&s->base);
1097         kfree(s);
1098 }
1099
1100 #ifdef CONFIG_DRM_ANALOGIX_DP
1101 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1102 {
1103         struct drm_connector *connector;
1104         struct drm_connector_list_iter conn_iter;
1105
1106         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1107         drm_for_each_connector_iter(connector, &conn_iter) {
1108                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1109                         drm_connector_list_iter_end(&conn_iter);
1110                         return connector;
1111                 }
1112         }
1113         drm_connector_list_iter_end(&conn_iter);
1114
1115         return NULL;
1116 }
1117
1118 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1119                                    const char *source_name, size_t *values_cnt)
1120 {
1121         struct vop *vop = to_vop(crtc);
1122         struct drm_connector *connector;
1123         int ret;
1124
1125         connector = vop_get_edp_connector(vop);
1126         if (!connector)
1127                 return -EINVAL;
1128
1129         *values_cnt = 3;
1130
1131         if (source_name && strcmp(source_name, "auto") == 0)
1132                 ret = analogix_dp_start_crc(connector);
1133         else if (!source_name)
1134                 ret = analogix_dp_stop_crc(connector);
1135         else
1136                 ret = -EINVAL;
1137
1138         return ret;
1139 }
1140 #else
1141 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1142                                    const char *source_name, size_t *values_cnt)
1143 {
1144         return -ENODEV;
1145 }
1146 #endif
1147
1148 static const struct drm_crtc_funcs vop_crtc_funcs = {
1149         .set_config = drm_atomic_helper_set_config,
1150         .page_flip = drm_atomic_helper_page_flip,
1151         .destroy = vop_crtc_destroy,
1152         .reset = vop_crtc_reset,
1153         .atomic_duplicate_state = vop_crtc_duplicate_state,
1154         .atomic_destroy_state = vop_crtc_destroy_state,
1155         .enable_vblank = vop_crtc_enable_vblank,
1156         .disable_vblank = vop_crtc_disable_vblank,
1157         .set_crc_source = vop_crtc_set_crc_source,
1158 };
1159
1160 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1161 {
1162         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1163         struct drm_framebuffer *fb = val;
1164
1165         drm_crtc_vblank_put(&vop->crtc);
1166         drm_framebuffer_put(fb);
1167 }
1168
1169 static void vop_handle_vblank(struct vop *vop)
1170 {
1171         struct drm_device *drm = vop->drm_dev;
1172         struct drm_crtc *crtc = &vop->crtc;
1173         unsigned long flags;
1174
1175         spin_lock_irqsave(&drm->event_lock, flags);
1176         if (vop->event) {
1177                 drm_crtc_send_vblank_event(crtc, vop->event);
1178                 drm_crtc_vblank_put(crtc);
1179                 vop->event = NULL;
1180         }
1181         spin_unlock_irqrestore(&drm->event_lock, flags);
1182
1183         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1184                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1185 }
1186
1187 static irqreturn_t vop_isr(int irq, void *data)
1188 {
1189         struct vop *vop = data;
1190         struct drm_crtc *crtc = &vop->crtc;
1191         uint32_t active_irqs;
1192         unsigned long flags;
1193         int ret = IRQ_NONE;
1194
1195         /*
1196          * interrupt register has interrupt status, enable and clear bits, we
1197          * must hold irq_lock to avoid a race with enable/disable_vblank().
1198         */
1199         spin_lock_irqsave(&vop->irq_lock, flags);
1200
1201         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1202         /* Clear all active interrupt sources */
1203         if (active_irqs)
1204                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1205
1206         spin_unlock_irqrestore(&vop->irq_lock, flags);
1207
1208         /* This is expected for vop iommu irqs, since the irq is shared */
1209         if (!active_irqs)
1210                 return IRQ_NONE;
1211
1212         if (active_irqs & DSP_HOLD_VALID_INTR) {
1213                 complete(&vop->dsp_hold_completion);
1214                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1215                 ret = IRQ_HANDLED;
1216         }
1217
1218         if (active_irqs & LINE_FLAG_INTR) {
1219                 complete(&vop->line_flag_completion);
1220                 active_irqs &= ~LINE_FLAG_INTR;
1221                 ret = IRQ_HANDLED;
1222         }
1223
1224         if (active_irqs & FS_INTR) {
1225                 drm_crtc_handle_vblank(crtc);
1226                 vop_handle_vblank(vop);
1227                 active_irqs &= ~FS_INTR;
1228                 ret = IRQ_HANDLED;
1229         }
1230
1231         /* Unhandled irqs are spurious. */
1232         if (active_irqs)
1233                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1234                               active_irqs);
1235
1236         return ret;
1237 }
1238
1239 static int vop_create_crtc(struct vop *vop)
1240 {
1241         const struct vop_data *vop_data = vop->data;
1242         struct device *dev = vop->dev;
1243         struct drm_device *drm_dev = vop->drm_dev;
1244         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1245         struct drm_crtc *crtc = &vop->crtc;
1246         struct device_node *port;
1247         int ret;
1248         int i;
1249
1250         /*
1251          * Create drm_plane for primary and cursor planes first, since we need
1252          * to pass them to drm_crtc_init_with_planes, which sets the
1253          * "possible_crtcs" to the newly initialized crtc.
1254          */
1255         for (i = 0; i < vop_data->win_size; i++) {
1256                 struct vop_win *vop_win = &vop->win[i];
1257                 const struct vop_win_data *win_data = vop_win->data;
1258
1259                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1260                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1261                         continue;
1262
1263                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1264                                                0, &vop_plane_funcs,
1265                                                win_data->phy->data_formats,
1266                                                win_data->phy->nformats,
1267                                                NULL, win_data->type, NULL);
1268                 if (ret) {
1269                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1270                                       ret);
1271                         goto err_cleanup_planes;
1272                 }
1273
1274                 plane = &vop_win->base;
1275                 drm_plane_helper_add(plane, &plane_helper_funcs);
1276                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1277                         primary = plane;
1278                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1279                         cursor = plane;
1280         }
1281
1282         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1283                                         &vop_crtc_funcs, NULL);
1284         if (ret)
1285                 goto err_cleanup_planes;
1286
1287         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1288
1289         /*
1290          * Create drm_planes for overlay windows with possible_crtcs restricted
1291          * to the newly created crtc.
1292          */
1293         for (i = 0; i < vop_data->win_size; i++) {
1294                 struct vop_win *vop_win = &vop->win[i];
1295                 const struct vop_win_data *win_data = vop_win->data;
1296                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1297
1298                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1299                         continue;
1300
1301                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1302                                                possible_crtcs,
1303                                                &vop_plane_funcs,
1304                                                win_data->phy->data_formats,
1305                                                win_data->phy->nformats,
1306                                                NULL, win_data->type, NULL);
1307                 if (ret) {
1308                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1309                                       ret);
1310                         goto err_cleanup_crtc;
1311                 }
1312                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1313         }
1314
1315         port = of_get_child_by_name(dev->of_node, "port");
1316         if (!port) {
1317                 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1318                               dev->of_node);
1319                 ret = -ENOENT;
1320                 goto err_cleanup_crtc;
1321         }
1322
1323         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1324                            vop_fb_unref_worker);
1325
1326         init_completion(&vop->dsp_hold_completion);
1327         init_completion(&vop->line_flag_completion);
1328         crtc->port = port;
1329
1330         return 0;
1331
1332 err_cleanup_crtc:
1333         drm_crtc_cleanup(crtc);
1334 err_cleanup_planes:
1335         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1336                                  head)
1337                 drm_plane_cleanup(plane);
1338         return ret;
1339 }
1340
1341 static void vop_destroy_crtc(struct vop *vop)
1342 {
1343         struct drm_crtc *crtc = &vop->crtc;
1344         struct drm_device *drm_dev = vop->drm_dev;
1345         struct drm_plane *plane, *tmp;
1346
1347         of_node_put(crtc->port);
1348
1349         /*
1350          * We need to cleanup the planes now.  Why?
1351          *
1352          * The planes are "&vop->win[i].base".  That means the memory is
1353          * all part of the big "struct vop" chunk of memory.  That memory
1354          * was devm allocated and associated with this component.  We need to
1355          * free it ourselves before vop_unbind() finishes.
1356          */
1357         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1358                                  head)
1359                 vop_plane_destroy(plane);
1360
1361         /*
1362          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1363          * references the CRTC.
1364          */
1365         drm_crtc_cleanup(crtc);
1366         drm_flip_work_cleanup(&vop->fb_unref_work);
1367 }
1368
1369 static int vop_initial(struct vop *vop)
1370 {
1371         const struct vop_data *vop_data = vop->data;
1372         struct reset_control *ahb_rst;
1373         int i, ret;
1374
1375         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1376         if (IS_ERR(vop->hclk)) {
1377                 dev_err(vop->dev, "failed to get hclk source\n");
1378                 return PTR_ERR(vop->hclk);
1379         }
1380         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1381         if (IS_ERR(vop->aclk)) {
1382                 dev_err(vop->dev, "failed to get aclk source\n");
1383                 return PTR_ERR(vop->aclk);
1384         }
1385         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1386         if (IS_ERR(vop->dclk)) {
1387                 dev_err(vop->dev, "failed to get dclk source\n");
1388                 return PTR_ERR(vop->dclk);
1389         }
1390
1391         ret = pm_runtime_get_sync(vop->dev);
1392         if (ret < 0) {
1393                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1394                 return ret;
1395         }
1396
1397         ret = clk_prepare(vop->dclk);
1398         if (ret < 0) {
1399                 dev_err(vop->dev, "failed to prepare dclk\n");
1400                 goto err_put_pm_runtime;
1401         }
1402
1403         /* Enable both the hclk and aclk to setup the vop */
1404         ret = clk_prepare_enable(vop->hclk);
1405         if (ret < 0) {
1406                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1407                 goto err_unprepare_dclk;
1408         }
1409
1410         ret = clk_prepare_enable(vop->aclk);
1411         if (ret < 0) {
1412                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1413                 goto err_disable_hclk;
1414         }
1415
1416         /*
1417          * do hclk_reset, reset all vop registers.
1418          */
1419         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1420         if (IS_ERR(ahb_rst)) {
1421                 dev_err(vop->dev, "failed to get ahb reset\n");
1422                 ret = PTR_ERR(ahb_rst);
1423                 goto err_disable_aclk;
1424         }
1425         reset_control_assert(ahb_rst);
1426         usleep_range(10, 20);
1427         reset_control_deassert(ahb_rst);
1428
1429         VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1430         VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1431
1432         memcpy(vop->regsbak, vop->regs, vop->len);
1433
1434         VOP_REG_SET(vop, misc, global_regdone_en, 1);
1435         VOP_REG_SET(vop, common, dsp_blank, 0);
1436
1437         for (i = 0; i < vop_data->win_size; i++) {
1438                 const struct vop_win_data *win = &vop_data->win[i];
1439                 int channel = i * 2 + 1;
1440
1441                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1442                 VOP_WIN_SET(vop, win, enable, 0);
1443                 VOP_WIN_SET(vop, win, gate, 1);
1444         }
1445
1446         vop_cfg_done(vop);
1447
1448         /*
1449          * do dclk_reset, let all config take affect.
1450          */
1451         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1452         if (IS_ERR(vop->dclk_rst)) {
1453                 dev_err(vop->dev, "failed to get dclk reset\n");
1454                 ret = PTR_ERR(vop->dclk_rst);
1455                 goto err_disable_aclk;
1456         }
1457         reset_control_assert(vop->dclk_rst);
1458         usleep_range(10, 20);
1459         reset_control_deassert(vop->dclk_rst);
1460
1461         clk_disable(vop->hclk);
1462         clk_disable(vop->aclk);
1463
1464         vop->is_enabled = false;
1465
1466         pm_runtime_put_sync(vop->dev);
1467
1468         return 0;
1469
1470 err_disable_aclk:
1471         clk_disable_unprepare(vop->aclk);
1472 err_disable_hclk:
1473         clk_disable_unprepare(vop->hclk);
1474 err_unprepare_dclk:
1475         clk_unprepare(vop->dclk);
1476 err_put_pm_runtime:
1477         pm_runtime_put_sync(vop->dev);
1478         return ret;
1479 }
1480
1481 /*
1482  * Initialize the vop->win array elements.
1483  */
1484 static void vop_win_init(struct vop *vop)
1485 {
1486         const struct vop_data *vop_data = vop->data;
1487         unsigned int i;
1488
1489         for (i = 0; i < vop_data->win_size; i++) {
1490                 struct vop_win *vop_win = &vop->win[i];
1491                 const struct vop_win_data *win_data = &vop_data->win[i];
1492
1493                 vop_win->data = win_data;
1494                 vop_win->vop = vop;
1495         }
1496 }
1497
1498 /**
1499  * rockchip_drm_wait_vact_end
1500  * @crtc: CRTC to enable line flag
1501  * @mstimeout: millisecond for timeout
1502  *
1503  * Wait for vact_end line flag irq or timeout.
1504  *
1505  * Returns:
1506  * Zero on success, negative errno on failure.
1507  */
1508 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1509 {
1510         struct vop *vop = to_vop(crtc);
1511         unsigned long jiffies_left;
1512
1513         if (!crtc || !vop->is_enabled)
1514                 return -ENODEV;
1515
1516         if (mstimeout <= 0)
1517                 return -EINVAL;
1518
1519         if (vop_line_flag_irq_is_enabled(vop))
1520                 return -EBUSY;
1521
1522         reinit_completion(&vop->line_flag_completion);
1523         vop_line_flag_irq_enable(vop);
1524
1525         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1526                                                    msecs_to_jiffies(mstimeout));
1527         vop_line_flag_irq_disable(vop);
1528
1529         if (jiffies_left == 0) {
1530                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1531                 return -ETIMEDOUT;
1532         }
1533
1534         return 0;
1535 }
1536 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1537
1538 static int vop_bind(struct device *dev, struct device *master, void *data)
1539 {
1540         struct platform_device *pdev = to_platform_device(dev);
1541         const struct vop_data *vop_data;
1542         struct drm_device *drm_dev = data;
1543         struct vop *vop;
1544         struct resource *res;
1545         size_t alloc_size;
1546         int ret, irq;
1547
1548         vop_data = of_device_get_match_data(dev);
1549         if (!vop_data)
1550                 return -ENODEV;
1551
1552         /* Allocate vop struct and its vop_win array */
1553         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1554         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1555         if (!vop)
1556                 return -ENOMEM;
1557
1558         vop->dev = dev;
1559         vop->data = vop_data;
1560         vop->drm_dev = drm_dev;
1561         dev_set_drvdata(dev, vop);
1562
1563         vop_win_init(vop);
1564
1565         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1566         vop->regs = devm_ioremap_resource(dev, res);
1567         if (IS_ERR(vop->regs))
1568                 return PTR_ERR(vop->regs);
1569         vop->len = resource_size(res);
1570
1571         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1572         if (!vop->regsbak)
1573                 return -ENOMEM;
1574
1575         irq = platform_get_irq(pdev, 0);
1576         if (irq < 0) {
1577                 dev_err(dev, "cannot find irq for vop\n");
1578                 return irq;
1579         }
1580         vop->irq = (unsigned int)irq;
1581
1582         spin_lock_init(&vop->reg_lock);
1583         spin_lock_init(&vop->irq_lock);
1584
1585         mutex_init(&vop->vsync_mutex);
1586
1587         ret = vop_create_crtc(vop);
1588         if (ret)
1589                 return ret;
1590
1591         pm_runtime_enable(&pdev->dev);
1592
1593         ret = vop_initial(vop);
1594         if (ret < 0) {
1595                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1596                 goto err_disable_pm_runtime;
1597         }
1598
1599         ret = devm_request_irq(dev, vop->irq, vop_isr,
1600                                IRQF_SHARED, dev_name(dev), vop);
1601         if (ret)
1602                 goto err_disable_pm_runtime;
1603
1604         /* IRQ is initially disabled; it gets enabled in power_on */
1605         disable_irq(vop->irq);
1606
1607         return 0;
1608
1609 err_disable_pm_runtime:
1610         pm_runtime_disable(&pdev->dev);
1611         vop_destroy_crtc(vop);
1612         return ret;
1613 }
1614
1615 static void vop_unbind(struct device *dev, struct device *master, void *data)
1616 {
1617         struct vop *vop = dev_get_drvdata(dev);
1618
1619         pm_runtime_disable(dev);
1620         vop_destroy_crtc(vop);
1621
1622         clk_unprepare(vop->aclk);
1623         clk_unprepare(vop->hclk);
1624         clk_unprepare(vop->dclk);
1625 }
1626
1627 const struct component_ops vop_component_ops = {
1628         .bind = vop_bind,
1629         .unbind = vop_unbind,
1630 };
1631 EXPORT_SYMBOL_GPL(vop_component_ops);