2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
16 #include <drm/drm_of.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/bridge/dw_hdmi.h>
22 #include "rockchip_drm_drv.h"
23 #include "rockchip_drm_vop.h"
25 #define RK3288_GRF_SOC_CON6 0x025C
26 #define RK3288_HDMI_LCDC_SEL BIT(4)
27 #define RK3399_GRF_SOC_CON20 0x6250
28 #define RK3399_HDMI_LCDC_SEL BIT(6)
30 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
33 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
34 * @lcdsel_grf_reg: grf register offset of lcdc select
35 * @lcdsel_big: reg value of selecting vop big for HDMI
36 * @lcdsel_lit: reg value of selecting vop little for HDMI
38 struct rockchip_hdmi_chip_data {
44 struct rockchip_hdmi {
46 struct regmap *regmap;
47 struct drm_encoder encoder;
48 const struct rockchip_hdmi_chip_data *chip_data;
53 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
55 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
135 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
136 /* pixelclk bpp8 bpp10 bpp12 */
138 40000000, { 0x0018, 0x0018, 0x0018 },
140 65000000, { 0x0028, 0x0028, 0x0028 },
142 66000000, { 0x0038, 0x0038, 0x0038 },
144 74250000, { 0x0028, 0x0038, 0x0038 },
146 83500000, { 0x0028, 0x0038, 0x0038 },
148 146250000, { 0x0038, 0x0038, 0x0038 },
150 148500000, { 0x0000, 0x0038, 0x0038 },
152 ~0UL, { 0x0000, 0x0000, 0x0000},
156 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
157 /*pixelclk symbol term vlev*/
158 { 74250000, 0x8009, 0x0004, 0x0272},
159 { 148500000, 0x802b, 0x0004, 0x028d},
160 { 297000000, 0x8039, 0x0005, 0x028d},
161 { ~0UL, 0x0000, 0x0000, 0x0000}
164 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
166 struct device_node *np = hdmi->dev->of_node;
169 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
170 if (IS_ERR(hdmi->regmap)) {
171 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
172 return PTR_ERR(hdmi->regmap);
175 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
176 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
177 hdmi->vpll_clk = NULL;
178 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
179 return -EPROBE_DEFER;
180 } else if (IS_ERR(hdmi->vpll_clk)) {
181 dev_err(hdmi->dev, "failed to get grf clock\n");
182 return PTR_ERR(hdmi->vpll_clk);
185 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
186 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
187 hdmi->grf_clk = NULL;
188 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
189 return -EPROBE_DEFER;
190 } else if (IS_ERR(hdmi->grf_clk)) {
191 dev_err(hdmi->dev, "failed to get grf clock\n");
192 return PTR_ERR(hdmi->grf_clk);
195 ret = clk_prepare_enable(hdmi->vpll_clk);
197 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
204 static enum drm_mode_status
205 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
206 const struct drm_display_mode *mode)
208 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
209 int pclk = mode->clock * 1000;
213 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
214 if (pclk == mpll_cfg[i].mpixelclock) {
220 return (valid) ? MODE_OK : MODE_BAD;
223 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
224 .destroy = drm_encoder_cleanup,
227 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
232 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
233 const struct drm_display_mode *mode,
234 struct drm_display_mode *adj_mode)
239 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
240 struct drm_display_mode *mode,
241 struct drm_display_mode *adj_mode)
243 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
245 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
248 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
250 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
254 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
256 val = hdmi->chip_data->lcdsel_lit;
258 val = hdmi->chip_data->lcdsel_big;
260 ret = clk_prepare_enable(hdmi->grf_clk);
262 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
266 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
268 dev_err(hdmi->dev, "Could not write to GRF: %d\n", ret);
270 clk_disable_unprepare(hdmi->grf_clk);
271 dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
272 ret ? "LIT" : "BIG");
276 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
277 struct drm_crtc_state *crtc_state,
278 struct drm_connector_state *conn_state)
280 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
282 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
283 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
288 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
289 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
290 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
291 .enable = dw_hdmi_rockchip_encoder_enable,
292 .disable = dw_hdmi_rockchip_encoder_disable,
293 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
296 static struct rockchip_hdmi_chip_data rk3288_chip_data = {
297 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
298 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
299 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
302 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
303 .mode_valid = dw_hdmi_rockchip_mode_valid,
304 .mpll_cfg = rockchip_mpll_cfg,
305 .cur_ctr = rockchip_cur_ctr,
306 .phy_config = rockchip_phy_config,
307 .phy_data = &rk3288_chip_data,
310 static struct rockchip_hdmi_chip_data rk3399_chip_data = {
311 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
312 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
313 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
316 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
317 .mode_valid = dw_hdmi_rockchip_mode_valid,
318 .mpll_cfg = rockchip_mpll_cfg,
319 .cur_ctr = rockchip_cur_ctr,
320 .phy_config = rockchip_phy_config,
321 .phy_data = &rk3399_chip_data,
324 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
325 { .compatible = "rockchip,rk3288-dw-hdmi",
326 .data = &rk3288_hdmi_drv_data
328 { .compatible = "rockchip,rk3399-dw-hdmi",
329 .data = &rk3399_hdmi_drv_data
333 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
335 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
338 struct platform_device *pdev = to_platform_device(dev);
339 const struct dw_hdmi_plat_data *plat_data;
340 const struct of_device_id *match;
341 struct drm_device *drm = data;
342 struct drm_encoder *encoder;
343 struct rockchip_hdmi *hdmi;
346 if (!pdev->dev.of_node)
349 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
353 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
354 plat_data = match->data;
355 hdmi->dev = &pdev->dev;
356 hdmi->chip_data = plat_data->phy_data;
357 encoder = &hdmi->encoder;
359 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
361 * If we failed to find the CRTC(s) which this encoder is
362 * supposed to be connected to, it's because the CRTC has
363 * not been registered yet. Defer probing, and hope that
364 * the required CRTC is added later.
366 if (encoder->possible_crtcs == 0)
367 return -EPROBE_DEFER;
369 ret = rockchip_hdmi_parse_dt(hdmi);
371 dev_err(hdmi->dev, "Unable to parse OF data\n");
375 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
376 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
377 DRM_MODE_ENCODER_TMDS, NULL);
379 ret = dw_hdmi_bind(pdev, encoder, plat_data);
382 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
383 * which would have called the encoder cleanup. Do it manually.
386 drm_encoder_cleanup(encoder);
391 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
394 return dw_hdmi_unbind(dev);
397 static const struct component_ops dw_hdmi_rockchip_ops = {
398 .bind = dw_hdmi_rockchip_bind,
399 .unbind = dw_hdmi_rockchip_unbind,
402 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
404 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
407 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
409 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
414 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
415 .probe = dw_hdmi_rockchip_probe,
416 .remove = dw_hdmi_rockchip_remove,
418 .name = "dwhdmi-rockchip",
419 .of_match_table = dw_hdmi_rockchip_dt_ids,