1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/wait.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_fb_cma_helper.h>
22 #include <drm/drm_fb_helper.h>
23 #include <drm/drm_drv.h>
24 #include <drm/drm_gem_cma_helper.h>
25 #include <drm/drm_probe_helper.h>
27 #include "rcar_du_drv.h"
28 #include "rcar_du_kms.h"
29 #include "rcar_du_of.h"
30 #include "rcar_du_regs.h"
32 /* -----------------------------------------------------------------------------
36 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
38 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
39 | RCAR_DU_FEATURE_INTERLACED
40 | RCAR_DU_FEATURE_TVM_SYNC,
41 .channels_mask = BIT(1) | BIT(0),
44 * R8A774[34] has one RGB output and one LVDS output
46 [RCAR_DU_OUTPUT_DPAD0] = {
47 .possible_crtcs = BIT(1) | BIT(0),
50 [RCAR_DU_OUTPUT_LVDS0] = {
51 .possible_crtcs = BIT(0),
58 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
60 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
61 | RCAR_DU_FEATURE_INTERLACED
62 | RCAR_DU_FEATURE_TVM_SYNC,
63 .channels_mask = BIT(1) | BIT(0),
66 * R8A7745 has two RGB outputs
68 [RCAR_DU_OUTPUT_DPAD0] = {
69 .possible_crtcs = BIT(0),
72 [RCAR_DU_OUTPUT_DPAD1] = {
73 .possible_crtcs = BIT(1),
79 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
81 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
82 | RCAR_DU_FEATURE_INTERLACED
83 | RCAR_DU_FEATURE_TVM_SYNC,
84 .channels_mask = BIT(1) | BIT(0),
87 * R8A77470 has two RGB outputs, one LVDS output, and
88 * one (currently unsupported) analog video output
90 [RCAR_DU_OUTPUT_DPAD0] = {
91 .possible_crtcs = BIT(0),
94 [RCAR_DU_OUTPUT_DPAD1] = {
95 .possible_crtcs = BIT(1),
98 [RCAR_DU_OUTPUT_LVDS0] = {
99 .possible_crtcs = BIT(0) | BIT(1),
105 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
107 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
108 | RCAR_DU_FEATURE_VSP1_SOURCE
109 | RCAR_DU_FEATURE_INTERLACED
110 | RCAR_DU_FEATURE_TVM_SYNC,
111 .channels_mask = BIT(2) | BIT(1) | BIT(0),
114 * R8A774A1 has one RGB output, one LVDS output and one HDMI
117 [RCAR_DU_OUTPUT_DPAD0] = {
118 .possible_crtcs = BIT(2),
121 [RCAR_DU_OUTPUT_HDMI0] = {
122 .possible_crtcs = BIT(1),
125 [RCAR_DU_OUTPUT_LVDS0] = {
126 .possible_crtcs = BIT(0),
134 static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
136 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
137 | RCAR_DU_FEATURE_VSP1_SOURCE
138 | RCAR_DU_FEATURE_INTERLACED
139 | RCAR_DU_FEATURE_TVM_SYNC,
140 .channels_mask = BIT(3) | BIT(1) | BIT(0),
143 * R8A774B1 has one RGB output, one LVDS output and one HDMI
146 [RCAR_DU_OUTPUT_DPAD0] = {
147 .possible_crtcs = BIT(2),
150 [RCAR_DU_OUTPUT_HDMI0] = {
151 .possible_crtcs = BIT(1),
154 [RCAR_DU_OUTPUT_LVDS0] = {
155 .possible_crtcs = BIT(0),
163 static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
165 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
166 | RCAR_DU_FEATURE_VSP1_SOURCE,
167 .channels_mask = BIT(1) | BIT(0),
170 * R8A774C0 has one RGB output and two LVDS outputs
172 [RCAR_DU_OUTPUT_DPAD0] = {
173 .possible_crtcs = BIT(0) | BIT(1),
176 [RCAR_DU_OUTPUT_LVDS0] = {
177 .possible_crtcs = BIT(0),
180 [RCAR_DU_OUTPUT_LVDS1] = {
181 .possible_crtcs = BIT(1),
186 .lvds_clk_mask = BIT(1) | BIT(0),
189 static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
191 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
192 | RCAR_DU_FEATURE_VSP1_SOURCE
193 | RCAR_DU_FEATURE_INTERLACED
194 | RCAR_DU_FEATURE_TVM_SYNC,
195 .channels_mask = BIT(3) | BIT(1) | BIT(0),
198 * R8A774E1 has one RGB output, one LVDS output and one HDMI
201 [RCAR_DU_OUTPUT_DPAD0] = {
202 .possible_crtcs = BIT(2),
205 [RCAR_DU_OUTPUT_HDMI0] = {
206 .possible_crtcs = BIT(1),
209 [RCAR_DU_OUTPUT_LVDS0] = {
210 .possible_crtcs = BIT(0),
218 static const struct rcar_du_device_info rcar_du_r8a7779_info = {
220 .features = RCAR_DU_FEATURE_INTERLACED
221 | RCAR_DU_FEATURE_TVM_SYNC,
222 .channels_mask = BIT(1) | BIT(0),
225 * R8A7779 has two RGB outputs and one (currently unsupported)
228 [RCAR_DU_OUTPUT_DPAD0] = {
229 .possible_crtcs = BIT(0),
232 [RCAR_DU_OUTPUT_DPAD1] = {
233 .possible_crtcs = BIT(1) | BIT(0),
239 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
241 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
242 | RCAR_DU_FEATURE_INTERLACED
243 | RCAR_DU_FEATURE_TVM_SYNC,
244 .quirks = RCAR_DU_QUIRK_ALIGN_128B,
245 .channels_mask = BIT(2) | BIT(1) | BIT(0),
248 * R8A7742 and R8A7790 each have one RGB output and two LVDS
249 * outputs. Additionally R8A7790 supports one TCON output
250 * (currently unsupported by the driver).
252 [RCAR_DU_OUTPUT_DPAD0] = {
253 .possible_crtcs = BIT(2) | BIT(1) | BIT(0),
256 [RCAR_DU_OUTPUT_LVDS0] = {
257 .possible_crtcs = BIT(0),
260 [RCAR_DU_OUTPUT_LVDS1] = {
261 .possible_crtcs = BIT(2) | BIT(1),
268 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
269 static const struct rcar_du_device_info rcar_du_r8a7791_info = {
271 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
272 | RCAR_DU_FEATURE_INTERLACED
273 | RCAR_DU_FEATURE_TVM_SYNC,
274 .channels_mask = BIT(1) | BIT(0),
277 * R8A779[13] has one RGB output, one LVDS output and one
278 * (currently unsupported) TCON output.
280 [RCAR_DU_OUTPUT_DPAD0] = {
281 .possible_crtcs = BIT(1) | BIT(0),
284 [RCAR_DU_OUTPUT_LVDS0] = {
285 .possible_crtcs = BIT(0),
292 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
294 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
295 | RCAR_DU_FEATURE_INTERLACED
296 | RCAR_DU_FEATURE_TVM_SYNC,
297 .channels_mask = BIT(1) | BIT(0),
299 /* R8A7792 has two RGB outputs. */
300 [RCAR_DU_OUTPUT_DPAD0] = {
301 .possible_crtcs = BIT(0),
304 [RCAR_DU_OUTPUT_DPAD1] = {
305 .possible_crtcs = BIT(1),
311 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
313 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
314 | RCAR_DU_FEATURE_INTERLACED
315 | RCAR_DU_FEATURE_TVM_SYNC,
316 .channels_mask = BIT(1) | BIT(0),
319 * R8A7794 has two RGB outputs and one (currently unsupported)
322 [RCAR_DU_OUTPUT_DPAD0] = {
323 .possible_crtcs = BIT(0),
326 [RCAR_DU_OUTPUT_DPAD1] = {
327 .possible_crtcs = BIT(1),
333 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
335 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
336 | RCAR_DU_FEATURE_VSP1_SOURCE
337 | RCAR_DU_FEATURE_INTERLACED
338 | RCAR_DU_FEATURE_TVM_SYNC,
339 .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
342 * R8A7795 has one RGB output, two HDMI outputs and one
345 [RCAR_DU_OUTPUT_DPAD0] = {
346 .possible_crtcs = BIT(3),
349 [RCAR_DU_OUTPUT_HDMI0] = {
350 .possible_crtcs = BIT(1),
353 [RCAR_DU_OUTPUT_HDMI1] = {
354 .possible_crtcs = BIT(2),
357 [RCAR_DU_OUTPUT_LVDS0] = {
358 .possible_crtcs = BIT(0),
363 .dpll_mask = BIT(2) | BIT(1),
366 static const struct rcar_du_device_info rcar_du_r8a7796_info = {
368 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
369 | RCAR_DU_FEATURE_VSP1_SOURCE
370 | RCAR_DU_FEATURE_INTERLACED
371 | RCAR_DU_FEATURE_TVM_SYNC,
372 .channels_mask = BIT(2) | BIT(1) | BIT(0),
375 * R8A7796 has one RGB output, one LVDS output and one HDMI
378 [RCAR_DU_OUTPUT_DPAD0] = {
379 .possible_crtcs = BIT(2),
382 [RCAR_DU_OUTPUT_HDMI0] = {
383 .possible_crtcs = BIT(1),
386 [RCAR_DU_OUTPUT_LVDS0] = {
387 .possible_crtcs = BIT(0),
395 static const struct rcar_du_device_info rcar_du_r8a77965_info = {
397 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
398 | RCAR_DU_FEATURE_VSP1_SOURCE
399 | RCAR_DU_FEATURE_INTERLACED
400 | RCAR_DU_FEATURE_TVM_SYNC,
401 .channels_mask = BIT(3) | BIT(1) | BIT(0),
404 * R8A77965 has one RGB output, one LVDS output and one HDMI
407 [RCAR_DU_OUTPUT_DPAD0] = {
408 .possible_crtcs = BIT(2),
411 [RCAR_DU_OUTPUT_HDMI0] = {
412 .possible_crtcs = BIT(1),
415 [RCAR_DU_OUTPUT_LVDS0] = {
416 .possible_crtcs = BIT(0),
424 static const struct rcar_du_device_info rcar_du_r8a77970_info = {
426 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
427 | RCAR_DU_FEATURE_VSP1_SOURCE
428 | RCAR_DU_FEATURE_INTERLACED
429 | RCAR_DU_FEATURE_TVM_SYNC,
430 .channels_mask = BIT(0),
433 * R8A77970 and R8A77980 have one RGB output and one LVDS
436 [RCAR_DU_OUTPUT_DPAD0] = {
437 .possible_crtcs = BIT(0),
440 [RCAR_DU_OUTPUT_LVDS0] = {
441 .possible_crtcs = BIT(0),
448 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
450 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
451 | RCAR_DU_FEATURE_VSP1_SOURCE,
452 .channels_mask = BIT(1) | BIT(0),
455 * R8A77990 and R8A77995 have one RGB output and two LVDS
458 [RCAR_DU_OUTPUT_DPAD0] = {
459 .possible_crtcs = BIT(0) | BIT(1),
462 [RCAR_DU_OUTPUT_LVDS0] = {
463 .possible_crtcs = BIT(0),
466 [RCAR_DU_OUTPUT_LVDS1] = {
467 .possible_crtcs = BIT(1),
472 .lvds_clk_mask = BIT(1) | BIT(0),
475 static const struct of_device_id rcar_du_of_table[] = {
476 { .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
477 { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
478 { .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
479 { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
480 { .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },
481 { .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info },
482 { .compatible = "renesas,du-r8a774b1", .data = &rcar_du_r8a774b1_info },
483 { .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
484 { .compatible = "renesas,du-r8a774e1", .data = &rcar_du_r8a774e1_info },
485 { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
486 { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
487 { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
488 { .compatible = "renesas,du-r8a7792", .data = &rcar_du_r8a7792_info },
489 { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
490 { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
491 { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
492 { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
493 { .compatible = "renesas,du-r8a77961", .data = &rcar_du_r8a7796_info },
494 { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
495 { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
496 { .compatible = "renesas,du-r8a77980", .data = &rcar_du_r8a77970_info },
497 { .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
498 { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
502 MODULE_DEVICE_TABLE(of, rcar_du_of_table);
504 /* -----------------------------------------------------------------------------
508 DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops);
510 static struct drm_driver rcar_du_driver = {
511 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
512 DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(rcar_du_dumb_create),
513 .fops = &rcar_du_fops,
515 .desc = "Renesas R-Car Display Unit",
521 /* -----------------------------------------------------------------------------
525 #ifdef CONFIG_PM_SLEEP
526 static int rcar_du_pm_suspend(struct device *dev)
528 struct rcar_du_device *rcdu = dev_get_drvdata(dev);
530 return drm_mode_config_helper_suspend(rcdu->ddev);
533 static int rcar_du_pm_resume(struct device *dev)
535 struct rcar_du_device *rcdu = dev_get_drvdata(dev);
537 return drm_mode_config_helper_resume(rcdu->ddev);
541 static const struct dev_pm_ops rcar_du_pm_ops = {
542 SET_SYSTEM_SLEEP_PM_OPS(rcar_du_pm_suspend, rcar_du_pm_resume)
545 /* -----------------------------------------------------------------------------
549 static int rcar_du_remove(struct platform_device *pdev)
551 struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
552 struct drm_device *ddev = rcdu->ddev;
554 drm_dev_unregister(ddev);
556 drm_kms_helper_poll_fini(ddev);
563 static int rcar_du_probe(struct platform_device *pdev)
565 struct rcar_du_device *rcdu;
566 struct drm_device *ddev;
567 struct resource *mem;
570 /* Allocate and initialize the R-Car device structure. */
571 rcdu = devm_kzalloc(&pdev->dev, sizeof(*rcdu), GFP_KERNEL);
575 rcdu->dev = &pdev->dev;
576 rcdu->info = of_device_get_match_data(rcdu->dev);
578 platform_set_drvdata(pdev, rcdu);
581 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
582 rcdu->mmio = devm_ioremap_resource(&pdev->dev, mem);
583 if (IS_ERR(rcdu->mmio))
584 return PTR_ERR(rcdu->mmio);
586 /* DRM/KMS objects */
587 ddev = drm_dev_alloc(&rcar_du_driver, &pdev->dev);
589 return PTR_ERR(ddev);
592 ddev->dev_private = rcdu;
594 ret = rcar_du_modeset_init(rcdu);
596 if (ret != -EPROBE_DEFER)
598 "failed to initialize DRM/KMS (%d)\n", ret);
602 ddev->irq_enabled = 1;
605 * Register the DRM device with the core and the connectors with
608 ret = drm_dev_register(ddev, 0);
612 DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
614 drm_fbdev_generic_setup(ddev, 32);
619 rcar_du_remove(pdev);
624 static struct platform_driver rcar_du_platform_driver = {
625 .probe = rcar_du_probe,
626 .remove = rcar_du_remove,
629 .pm = &rcar_du_pm_ops,
630 .of_match_table = rcar_du_of_table,
634 static int __init rcar_du_init(void)
636 rcar_du_of_init(rcar_du_of_table);
638 return platform_driver_register(&rcar_du_platform_driver);
640 module_init(rcar_du_init);
642 static void __exit rcar_du_exit(void)
644 platform_driver_unregister(&rcar_du_platform_driver);
646 module_exit(rcar_du_exit);
648 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
649 MODULE_DESCRIPTION("Renesas R-Car Display Unit DRM Driver");
650 MODULE_LICENSE("GPL");