drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mutex.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/sys_soc.h>
  14
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_bridge.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_device.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <drm/drm_vblank.h>
  24
  25 #include "rcar_cmm.h"
  26 #include "rcar_du_crtc.h"
  27 #include "rcar_du_drv.h"
  28 #include "rcar_du_encoder.h"
  29 #include "rcar_du_kms.h"
  30 #include "rcar_du_plane.h"
  31 #include "rcar_du_regs.h"
  32 #include "rcar_du_vsp.h"
  33 #include "rcar_lvds.h"
  34
  35 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  36 {
  37         struct rcar_du_device *rcdu = rcrtc->dev;
  38
  39         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  40 }
  41
  42 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  43 {
  44         struct rcar_du_device *rcdu = rcrtc->dev;
  45
  46         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  47 }
  48
  49 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  50 {
  51         struct rcar_du_device *rcdu = rcrtc->dev;
  52
  53         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  54                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  55 }
  56
  57 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  58 {
  59         struct rcar_du_device *rcdu = rcrtc->dev;
  60
  61         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  62                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  63 }
  64
  65 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
  66 {
  67         struct rcar_du_device *rcdu = rcrtc->dev;
  68
  69         rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
  70         rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
  71 }
  72
  73 /* -----------------------------------------------------------------------------
  74  * Hardware Setup
  75  */
  76
  77 struct dpll_info {
  78         unsigned int output;
  79         unsigned int fdpll;
  80         unsigned int n;
  81         unsigned int m;
  82 };
  83
  84 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
  85                                  struct dpll_info *dpll,
  86                                  unsigned long input,
  87                                  unsigned long target)
  88 {
  89         unsigned long best_diff = (unsigned long)-1;
  90         unsigned long diff;
  91         unsigned int fdpll;
  92         unsigned int m;
  93         unsigned int n;
  94
  95         /*
  96          *   fin                                 fvco        fout       fclkout
  97          * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
  98          *              +-> |  |                             |
  99          *              |                                    |
 100          *              +---------------- [1/N] <------------+
 101          *
 102          *      fclkout = fvco / P / FDPLL -- (1)
 103          *
 104          * fin/M = fvco/P/N
 105          *
 106          *      fvco = fin * P *  N / M -- (2)
 107          *
 108          * (1) + (2) indicates
 109          *
 110          *      fclkout = fin * N / M / FDPLL
 111          *
 112          * NOTES
 113          *      N       : (n + 1)
 114          *      M       : (m + 1)
 115          *      FDPLL   : (fdpll + 1)
 116          *      P       : 2
 117          *      2kHz < fvco < 4096MHz
 118          *
 119          * To minimize the jitter,
 120          * N : as large as possible
 121          * M : as small as possible
 122          */
 123         for (m = 0; m < 4; m++) {
 124                 for (n = 119; n > 38; n--) {
 125                         /*
 126                          * This code only runs on 64-bit architectures, the
 127                          * unsigned long type can thus be used for 64-bit
 128                          * computation. It will still compile without any
 129                          * warning on 32-bit architectures.
 130                          *
 131                          * To optimize calculations, use fout instead of fvco
 132                          * to verify the VCO frequency constraint.
 133                          */
 134                         unsigned long fout = input * (n + 1) / (m + 1);
 135
 136                         if (fout < 1000 || fout > 2048 * 1000 * 1000U)
 137                                 continue;
 138
 139                         for (fdpll = 1; fdpll < 32; fdpll++) {
 140                                 unsigned long output;
 141
 142                                 output = fout / (fdpll + 1);
 143                                 if (output >= 400 * 1000 * 1000)
 144                                         continue;
 145
 146                                 diff = abs((long)output - (long)target);
 147                                 if (best_diff > diff) {
 148                                         best_diff = diff;
 149                                         dpll->n = n;
 150                                         dpll->m = m;
 151                                         dpll->fdpll = fdpll;
 152                                         dpll->output = output;
 153                                 }
 154
 155                                 if (diff == 0)
 156                                         goto done;
 157                         }
 158                 }
 159         }
 160
 161 done:
 162         dev_dbg(rcrtc->dev->dev,
 163                 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
 164                  dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff);
 165 }
 166
 167 struct du_clk_params {
 168         struct clk *clk;
 169         unsigned long rate;
 170         unsigned long diff;
 171         u32 escr;
 172 };
 173
 174 static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
 175                                  u32 escr, struct du_clk_params *params)
 176 {
 177         unsigned long rate;
 178         unsigned long diff;
 179         u32 div;
 180
 181         /*
 182          * If the target rate has already been achieved perfectly we can't do
 183          * better.
 184          */
 185         if (params->diff == 0)
 186                 return;
 187
 188         /*
 189          * Compute the input clock rate and internal divisor values to obtain
 190          * the clock rate closest to the target frequency.
 191          */
 192         rate = clk_round_rate(clk, target);
 193         div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
 194         diff = abs(rate / (div + 1) - target);
 195
 196         /*
 197          * Store the parameters if the resulting frequency is better than any
 198          * previously calculated value.
 199          */
 200         if (diff < params->diff) {
 201                 params->clk = clk;
 202                 params->rate = rate;
 203                 params->diff = diff;
 204                 params->escr = escr | div;
 205         }
 206 }
 207
 208 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
 209         { .soc_id = "r8a7795", .revision = "ES1.*" },
 210         { /* sentinel */ }
 211 };
 212
 213 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 214 {
 215         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 216         struct rcar_du_device *rcdu = rcrtc->dev;
 217         unsigned long mode_clock = mode->clock * 1000;
 218         unsigned int hdse_offset;
 219         u32 dsmr;
 220         u32 escr;
 221
 222         if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
 223                 unsigned long target = mode_clock;
 224                 struct dpll_info dpll = { 0 };
 225                 unsigned long extclk;
 226                 u32 dpllcr;
 227                 u32 div = 0;
 228
 229                 /*
 230                  * DU channels that have a display PLL can't use the internal
 231                  * system clock, and have no internal clock divider.
 232                  */
 233
 234                 /*
 235                  * The H3 ES1.x exhibits dot clock duty cycle stability issues.
 236                  * We can work around them by configuring the DPLL to twice the
 237                  * desired frequency, coupled with a /2 post-divider. Restrict
 238                  * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
 239                  * no post-divider when a display PLL is present (as shown by
 240                  * the workaround breaking HDMI output on M3-W during testing).
 241                  */
 242                 if (soc_device_match(rcar_du_r8a7795_es1)) {
 243                         target *= 2;
 244                         div = 1;
 245                 }
 246
 247                 extclk = clk_get_rate(rcrtc->extclock);
 248                 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
 249
 250                 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
 251                        | DPLLCR_FDPLL(dpll.fdpll)
 252                        | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
 253                        | DPLLCR_STBY;
 254
 255                 if (rcrtc->index == 1)
 256                         dpllcr |= DPLLCR_PLCS1
 257                                |  DPLLCR_INCS_DOTCLKIN1;
 258                 else
 259                         dpllcr |= DPLLCR_PLCS0
 260                                |  DPLLCR_INCS_DOTCLKIN0;
 261
 262                 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
 263
 264                 escr = ESCR_DCLKSEL_DCLKIN | div;
 265         } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
 266                 /*
 267                  * Use the LVDS PLL output as the dot clock when outputting to
 268                  * the LVDS encoder on an SoC that supports this clock routing
 269                  * option. We use the clock directly in that case, without any
 270                  * additional divider.
 271                  */
 272                 escr = ESCR_DCLKSEL_DCLKIN;
 273         } else {
 274                 struct du_clk_params params = { .diff = (unsigned long)-1 };
 275
 276                 rcar_du_escr_divider(rcrtc->clock, mode_clock,
 277                                      ESCR_DCLKSEL_CLKS, &params);
 278                 if (rcrtc->extclock)
 279                         rcar_du_escr_divider(rcrtc->extclock, mode_clock,
 280                                              ESCR_DCLKSEL_DCLKIN, &params);
 281
 282                 dev_dbg(rcrtc->dev->dev, "mode clock %lu %s rate %lu\n",
 283                         mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
 284                         params.rate);
 285
 286                 clk_set_rate(params.clk, params.rate);
 287                 escr = params.escr;
 288         }
 289
 290         dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 291
 292         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
 293         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
 294
 295         /* Signal polarities */
 296         dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
 297              | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
 298              | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
 299              | DSMR_DIPM_DISP | DSMR_CSPM;
 300         rcar_du_crtc_write(rcrtc, DSMR, dsmr);
 301
 302         hdse_offset = 19;
 303         if (rcrtc->group->cmms_mask & BIT(rcrtc->index % 2))
 304                 hdse_offset += 25;
 305
 306         /* Display timings */
 307         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start -
 308                                         hdse_offset);
 309         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 310                                         mode->hdisplay - hdse_offset);
 311         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 312                                         mode->hsync_start - 1);
 313         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 314
 315         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 316                                         mode->crtc_vsync_end - 2);
 317         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 318                                         mode->crtc_vsync_end +
 319                                         mode->crtc_vdisplay - 2);
 320         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 321                                         mode->crtc_vsync_end +
 322                                         mode->crtc_vsync_start - 1);
 323         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 324
 325         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
 326         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 327 }
 328
 329 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 330 {
 331         return plane->plane.state->normalized_zpos;
 332 }
 333
 334 static const struct rcar_du_format_info *
 335 plane_format(struct rcar_du_plane *plane)
 336 {
 337         return to_rcar_plane_state(plane->plane.state)->format;
 338 }
 339
 340 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 341 {
 342         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 343         struct rcar_du_device *rcdu = rcrtc->dev;
 344         unsigned int num_planes = 0;
 345         unsigned int dptsr_planes;
 346         unsigned int hwplanes = 0;
 347         unsigned int prio = 0;
 348         unsigned int i;
 349         u32 dspr = 0;
 350
 351         for (i = 0; i < rcrtc->group->num_planes; ++i) {
 352                 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
 353                 unsigned int j;
 354
 355                 if (plane->plane.state->crtc != &rcrtc->crtc ||
 356                     !plane->plane.state->visible)
 357                         continue;
 358
 359                 /* Insert the plane in the sorted planes array. */
 360                 for (j = num_planes++; j > 0; --j) {
 361                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 362                                 break;
 363                         planes[j] = planes[j-1];
 364                 }
 365
 366                 planes[j] = plane;
 367                 prio += plane_format(plane)->planes * 4;
 368         }
 369
 370         for (i = 0; i < num_planes; ++i) {
 371                 struct rcar_du_plane *plane = planes[i];
 372                 struct drm_plane_state *state = plane->plane.state;
 373                 unsigned int index = to_rcar_plane_state(state)->hwindex;
 374
 375                 prio -= 4;
 376                 dspr |= (index + 1) << prio;
 377                 hwplanes |= 1 << index;
 378
 379                 if (plane_format(plane)->planes == 2) {
 380                         index = (index + 1) % 8;
 381
 382                         prio -= 4;
 383                         dspr |= (index + 1) << prio;
 384                         hwplanes |= 1 << index;
 385                 }
 386         }
 387
 388         /* If VSP+DU integration is enabled the plane assignment is fixed. */
 389         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 390                 if (rcdu->info->gen < 3) {
 391                         dspr = (rcrtc->index % 2) + 1;
 392                         hwplanes = 1 << (rcrtc->index % 2);
 393                 } else {
 394                         dspr = (rcrtc->index % 2) ? 3 : 1;
 395                         hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
 396                 }
 397         }
 398
 399         /*
 400          * Update the planes to display timing and dot clock generator
 401          * associations.
 402          *
 403          * Updating the DPTSR register requires restarting the CRTC group,
 404          * resulting in visible flicker. To mitigate the issue only update the
 405          * association if needed by enabled planes. Planes being disabled will
 406          * keep their current association.
 407          */
 408         mutex_lock(&rcrtc->group->lock);
 409
 410         dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
 411                      : rcrtc->group->dptsr_planes & ~hwplanes;
 412
 413         if (dptsr_planes != rcrtc->group->dptsr_planes) {
 414                 rcar_du_group_write(rcrtc->group, DPTSR,
 415                                     (dptsr_planes << 16) | dptsr_planes);
 416                 rcrtc->group->dptsr_planes = dptsr_planes;
 417
 418                 if (rcrtc->group->used_crtcs)
 419                         rcar_du_group_restart(rcrtc->group);
 420         }
 421
 422         /* Restart the group if plane sources have changed. */
 423         if (rcrtc->group->need_restart)
 424                 rcar_du_group_restart(rcrtc->group);
 425
 426         mutex_unlock(&rcrtc->group->lock);
 427
 428         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 429                             dspr);
 430 }
 431
 432 /* -----------------------------------------------------------------------------
 433  * Page Flip
 434  */
 435
 436 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 437 {
 438         struct drm_pending_vblank_event *event;
 439         struct drm_device *dev = rcrtc->crtc.dev;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&dev->event_lock, flags);
 443         event = rcrtc->event;
 444         rcrtc->event = NULL;
 445         spin_unlock_irqrestore(&dev->event_lock, flags);
 446
 447         if (event == NULL)
 448                 return;
 449
 450         spin_lock_irqsave(&dev->event_lock, flags);
 451         drm_crtc_send_vblank_event(&rcrtc->crtc, event);
 452         wake_up(&rcrtc->flip_wait);
 453         spin_unlock_irqrestore(&dev->event_lock, flags);
 454
 455         drm_crtc_vblank_put(&rcrtc->crtc);
 456 }
 457
 458 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 459 {
 460         struct drm_device *dev = rcrtc->crtc.dev;
 461         unsigned long flags;
 462         bool pending;
 463
 464         spin_lock_irqsave(&dev->event_lock, flags);
 465         pending = rcrtc->event != NULL;
 466         spin_unlock_irqrestore(&dev->event_lock, flags);
 467
 468         return pending;
 469 }
 470
 471 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 472 {
 473         struct rcar_du_device *rcdu = rcrtc->dev;
 474
 475         if (wait_event_timeout(rcrtc->flip_wait,
 476                                !rcar_du_crtc_page_flip_pending(rcrtc),
 477                                msecs_to_jiffies(50)))
 478                 return;
 479
 480         dev_warn(rcdu->dev, "page flip timeout\n");
 481
 482         rcar_du_crtc_finish_page_flip(rcrtc);
 483 }
 484
 485 /* -----------------------------------------------------------------------------
 486  * Color Management Module (CMM)
 487  */
 488
 489 static int rcar_du_cmm_check(struct drm_crtc *crtc,
 490                              struct drm_crtc_state *state)
 491 {
 492         struct drm_property_blob *drm_lut = state->gamma_lut;
 493         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 494         struct device *dev = rcrtc->dev->dev;
 495
 496         if (!drm_lut)
 497                 return 0;
 498
 499         /* We only accept fully populated LUT tables. */
 500         if (drm_color_lut_size(drm_lut) != CM2_LUT_SIZE) {
 501                 dev_err(dev, "invalid gamma lut size: %zu bytes\n",
 502                         drm_lut->length);
 503                 return -EINVAL;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static void rcar_du_cmm_setup(struct drm_crtc *crtc)
 510 {
 511         struct drm_property_blob *drm_lut = crtc->state->gamma_lut;
 512         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 513         struct rcar_cmm_config cmm_config = {};
 514
 515         if (!rcrtc->cmm)
 516                 return;
 517
 518         if (drm_lut)
 519                 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data;
 520
 521         rcar_cmm_setup(rcrtc->cmm, &cmm_config);
 522 }
 523
 524 /* -----------------------------------------------------------------------------
 525  * Start/Stop and Suspend/Resume
 526  */
 527
 528 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
 529 {
 530         /* Set display off and background to black */
 531         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 532         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 533
 534         /* Configure display timings and output routing */
 535         rcar_du_crtc_set_display_timing(rcrtc);
 536         rcar_du_group_set_routing(rcrtc->group);
 537
 538         /* Start with all planes disabled. */
 539         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 540
 541         /* Enable the VSP compositor. */
 542         if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 543                 rcar_du_vsp_enable(rcrtc);
 544
 545         /* Turn vertical blanking interrupt reporting on. */
 546         drm_crtc_vblank_on(&rcrtc->crtc);
 547 }
 548
 549 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
 550 {
 551         int ret;
 552
 553         /*
 554          * Guard against double-get, as the function is called from both the
 555          * .atomic_enable() and .atomic_begin() handlers.
 556          */
 557         if (rcrtc->initialized)
 558                 return 0;
 559
 560         ret = clk_prepare_enable(rcrtc->clock);
 561         if (ret < 0)
 562                 return ret;
 563
 564         ret = clk_prepare_enable(rcrtc->extclock);
 565         if (ret < 0)
 566                 goto error_clock;
 567
 568         ret = rcar_du_group_get(rcrtc->group);
 569         if (ret < 0)
 570                 goto error_group;
 571
 572         rcar_du_crtc_setup(rcrtc);
 573         rcrtc->initialized = true;
 574
 575         return 0;
 576
 577 error_group:
 578         clk_disable_unprepare(rcrtc->extclock);
 579 error_clock:
 580         clk_disable_unprepare(rcrtc->clock);
 581         return ret;
 582 }
 583
 584 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
 585 {
 586         rcar_du_group_put(rcrtc->group);
 587
 588         clk_disable_unprepare(rcrtc->extclock);
 589         clk_disable_unprepare(rcrtc->clock);
 590
 591         rcrtc->initialized = false;
 592 }
 593
 594 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 595 {
 596         bool interlaced;
 597
 598         /*
 599          * Select master sync mode. This enables display operation in master
 600          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 601          * actively driven).
 602          */
 603         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 604         rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 605                                    (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 606                                    DSYSR_TVM_MASTER);
 607
 608         rcar_du_group_start_stop(rcrtc->group, true);
 609 }
 610
 611 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
 612 {
 613         struct rcar_du_device *rcdu = rcrtc->dev;
 614         struct drm_crtc *crtc = &rcrtc->crtc;
 615         u32 status;
 616
 617         /* Make sure vblank interrupts are enabled. */
 618         drm_crtc_vblank_get(crtc);
 619
 620         /*
 621          * Disable planes and calculate how many vertical blanking interrupts we
 622          * have to wait for. If a vertical blanking interrupt has been triggered
 623          * but not processed yet, we don't know whether it occurred before or
 624          * after the planes got disabled. We thus have to wait for two vblank
 625          * interrupts in that case.
 626          */
 627         spin_lock_irq(&rcrtc->vblank_lock);
 628         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 629         status = rcar_du_crtc_read(rcrtc, DSSR);
 630         rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
 631         spin_unlock_irq(&rcrtc->vblank_lock);
 632
 633         if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
 634                                 msecs_to_jiffies(100)))
 635                 dev_warn(rcdu->dev, "vertical blanking timeout\n");
 636
 637         drm_crtc_vblank_put(crtc);
 638 }
 639
 640 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 641 {
 642         struct drm_crtc *crtc = &rcrtc->crtc;
 643
 644         /*
 645          * Disable all planes and wait for the change to take effect. This is
 646          * required as the plane enable registers are updated on vblank, and no
 647          * vblank will occur once the CRTC is stopped. Disabling planes when
 648          * starting the CRTC thus wouldn't be enough as it would start scanning
 649          * out immediately from old frame buffers until the next vblank.
 650          *
 651          * This increases the CRTC stop delay, especially when multiple CRTCs
 652          * are stopped in one operation as we now wait for one vblank per CRTC.
 653          * Whether this can be improved needs to be researched.
 654          */
 655         rcar_du_crtc_disable_planes(rcrtc);
 656
 657         /*
 658          * Disable vertical blanking interrupt reporting. We first need to wait
 659          * for page flip completion before stopping the CRTC as userspace
 660          * expects page flips to eventually complete.
 661          */
 662         rcar_du_crtc_wait_page_flip(rcrtc);
 663         drm_crtc_vblank_off(crtc);
 664
 665         /* Disable the VSP compositor. */
 666         if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 667                 rcar_du_vsp_disable(rcrtc);
 668
 669         if (rcrtc->cmm)
 670                 rcar_cmm_disable(rcrtc->cmm);
 671
 672         /*
 673          * Select switch sync mode. This stops display operation and configures
 674          * the HSYNC and VSYNC signals as inputs.
 675          *
 676          * TODO: Find another way to stop the display for DUs that don't support
 677          * TVM sync.
 678          */
 679         if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_TVM_SYNC))
 680                 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
 681                                            DSYSR_TVM_SWITCH);
 682
 683         rcar_du_group_start_stop(rcrtc->group, false);
 684 }
 685
 686 /* -----------------------------------------------------------------------------
 687  * CRTC Functions
 688  */
 689
 690 static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
 691                                      struct drm_crtc_state *state)
 692 {
 693         struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(state);
 694         struct drm_encoder *encoder;
 695         int ret;
 696
 697         ret = rcar_du_cmm_check(crtc, state);
 698         if (ret)
 699                 return ret;
 700
 701         /* Store the routes from the CRTC output to the DU outputs. */
 702         rstate->outputs = 0;
 703
 704         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
 705                 struct rcar_du_encoder *renc;
 706
 707                 /* Skip the writeback encoder. */
 708                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 709                         continue;
 710
 711                 renc = to_rcar_encoder(encoder);
 712                 rstate->outputs |= BIT(renc->output);
 713         }
 714
 715         return 0;
 716 }
 717
 718 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
 719                                        struct drm_crtc_state *old_state)
 720 {
 721         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 722         struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);
 723         struct rcar_du_device *rcdu = rcrtc->dev;
 724
 725         if (rcrtc->cmm)
 726                 rcar_cmm_enable(rcrtc->cmm);
 727         rcar_du_crtc_get(rcrtc);
 728
 729         /*
 730          * On D3/E3 the dot clock is provided by the LVDS encoder attached to
 731          * the DU channel. We need to enable its clock output explicitly if
 732          * the LVDS output is disabled.
 733          */
 734         if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
 735             rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
 736                 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
 737                 const struct drm_display_mode *mode =
 738                         &crtc->state->adjusted_mode;
 739
 740                 rcar_lvds_clk_enable(bridge, mode->clock * 1000);
 741         }
 742
 743         rcar_du_crtc_start(rcrtc);
 744
 745         /*
 746          * TODO: The chip manual indicates that CMM tables should be written
 747          * after the DU channel has been activated. Investigate the impact
 748          * of this restriction on the first displayed frame.
 749          */
 750         rcar_du_cmm_setup(crtc);
 751 }
 752
 753 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
 754                                         struct drm_crtc_state *old_state)
 755 {
 756         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 757         struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);
 758         struct rcar_du_device *rcdu = rcrtc->dev;
 759
 760         rcar_du_crtc_stop(rcrtc);
 761         rcar_du_crtc_put(rcrtc);
 762
 763         if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
 764             rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
 765                 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
 766
 767                 /*
 768                  * Disable the LVDS clock output, see
 769                  * rcar_du_crtc_atomic_enable().
 770                  */
 771                 rcar_lvds_clk_disable(bridge);
 772         }
 773
 774         spin_lock_irq(&crtc->dev->event_lock);
 775         if (crtc->state->event) {
 776                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 777                 crtc->state->event = NULL;
 778         }
 779         spin_unlock_irq(&crtc->dev->event_lock);
 780 }
 781
 782 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
 783                                       struct drm_crtc_state *old_crtc_state)
 784 {
 785         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 786
 787         WARN_ON(!crtc->state->enable);
 788
 789         /*
 790          * If a mode set is in progress we can be called with the CRTC disabled.
 791          * We thus need to first get and setup the CRTC in order to configure
 792          * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
 793          * kept awake until the .atomic_enable() call that will follow. The get
 794          * operation in .atomic_enable() will in that case be a no-op, and the
 795          * CRTC will be put later in .atomic_disable().
 796          *
 797          * If a mode set is not in progress the CRTC is enabled, and the
 798          * following get call will be a no-op. There is thus no need to balance
 799          * it in .atomic_flush() either.
 800          */
 801         rcar_du_crtc_get(rcrtc);
 802
 803         /* If the active state changed, we let .atomic_enable handle CMM. */
 804         if (crtc->state->color_mgmt_changed && !crtc->state->active_changed)
 805                 rcar_du_cmm_setup(crtc);
 806
 807         if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 808                 rcar_du_vsp_atomic_begin(rcrtc);
 809 }
 810
 811 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
 812                                       struct drm_crtc_state *old_crtc_state)
 813 {
 814         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 815         struct drm_device *dev = rcrtc->crtc.dev;
 816         unsigned long flags;
 817
 818         rcar_du_crtc_update_planes(rcrtc);
 819
 820         if (crtc->state->event) {
 821                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 822
 823                 spin_lock_irqsave(&dev->event_lock, flags);
 824                 rcrtc->event = crtc->state->event;
 825                 crtc->state->event = NULL;
 826                 spin_unlock_irqrestore(&dev->event_lock, flags);
 827         }
 828
 829         if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 830                 rcar_du_vsp_atomic_flush(rcrtc);
 831 }
 832
 833 static enum drm_mode_status
 834 rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
 835                         const struct drm_display_mode *mode)
 836 {
 837         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 838         struct rcar_du_device *rcdu = rcrtc->dev;
 839         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 840         unsigned int min_sync_porch;
 841         unsigned int vbp;
 842
 843         if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
 844                 return MODE_NO_INTERLACE;
 845
 846         /*
 847          * The hardware requires a minimum combined horizontal sync and back
 848          * porch of 20 pixels (when CMM isn't used) or 45 pixels (when CMM is
 849          * used), and a minimum vertical back porch of 3 lines.
 850          */
 851         min_sync_porch = 20;
 852         if (rcrtc->group->cmms_mask & BIT(rcrtc->index % 2))
 853                 min_sync_porch += 25;
 854
 855         if (mode->htotal - mode->hsync_start < min_sync_porch)
 856                 return MODE_HBLANK_NARROW;
 857
 858         vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
 859         if (vbp < 3)
 860                 return MODE_VBLANK_NARROW;
 861
 862         return MODE_OK;
 863 }
 864
 865 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 866         .atomic_check = rcar_du_crtc_atomic_check,
 867         .atomic_begin = rcar_du_crtc_atomic_begin,
 868         .atomic_flush = rcar_du_crtc_atomic_flush,
 869         .atomic_enable = rcar_du_crtc_atomic_enable,
 870         .atomic_disable = rcar_du_crtc_atomic_disable,
 871         .mode_valid = rcar_du_crtc_mode_valid,
 872 };
 873
 874 static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
 875 {
 876         struct rcar_du_device *rcdu = rcrtc->dev;
 877         const char **sources;
 878         unsigned int count;
 879         int i = -1;
 880
 881         /* CRC available only on Gen3 HW. */
 882         if (rcdu->info->gen < 3)
 883                 return;
 884
 885         /* Reserve 1 for "auto" source. */
 886         count = rcrtc->vsp->num_planes + 1;
 887
 888         sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
 889         if (!sources)
 890                 return;
 891
 892         sources[0] = kstrdup("auto", GFP_KERNEL);
 893         if (!sources[0])
 894                 goto error;
 895
 896         for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 897                 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
 898                 char name[16];
 899
 900                 sprintf(name, "plane%u", plane->base.id);
 901                 sources[i + 1] = kstrdup(name, GFP_KERNEL);
 902                 if (!sources[i + 1])
 903                         goto error;
 904         }
 905
 906         rcrtc->sources = sources;
 907         rcrtc->sources_count = count;
 908         return;
 909
 910 error:
 911         while (i >= 0) {
 912                 kfree(sources[i]);
 913                 i--;
 914         }
 915         kfree(sources);
 916 }
 917
 918 static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
 919 {
 920         unsigned int i;
 921
 922         if (!rcrtc->sources)
 923                 return;
 924
 925         for (i = 0; i < rcrtc->sources_count; i++)
 926                 kfree(rcrtc->sources[i]);
 927         kfree(rcrtc->sources);
 928
 929         rcrtc->sources = NULL;
 930         rcrtc->sources_count = 0;
 931 }
 932
 933 static struct drm_crtc_state *
 934 rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
 935 {
 936         struct rcar_du_crtc_state *state;
 937         struct rcar_du_crtc_state *copy;
 938
 939         if (WARN_ON(!crtc->state))
 940                 return NULL;
 941
 942         state = to_rcar_crtc_state(crtc->state);
 943         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
 944         if (copy == NULL)
 945                 return NULL;
 946
 947         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
 948
 949         return &copy->state;
 950 }
 951
 952 static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
 953                                               struct drm_crtc_state *state)
 954 {
 955         __drm_atomic_helper_crtc_destroy_state(state);
 956         kfree(to_rcar_crtc_state(state));
 957 }
 958
 959 static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
 960 {
 961         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 962
 963         rcar_du_crtc_crc_cleanup(rcrtc);
 964
 965         return drm_crtc_cleanup(crtc);
 966 }
 967
 968 static void rcar_du_crtc_reset(struct drm_crtc *crtc)
 969 {
 970         struct rcar_du_crtc_state *state;
 971
 972         if (crtc->state) {
 973                 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
 974                 crtc->state = NULL;
 975         }
 976
 977         state = kzalloc(sizeof(*state), GFP_KERNEL);
 978         if (state == NULL)
 979                 return;
 980
 981         state->crc.source = VSP1_DU_CRC_NONE;
 982         state->crc.index = 0;
 983
 984         __drm_atomic_helper_crtc_reset(crtc, &state->state);
 985 }
 986
 987 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
 988 {
 989         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 990
 991         rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 992         rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 993         rcrtc->vblank_enable = true;
 994
 995         return 0;
 996 }
 997
 998 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
 999 {
1000         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1001
1002         rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
1003         rcrtc->vblank_enable = false;
1004 }
1005
1006 static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
1007                                          const char *source_name,
1008                                          enum vsp1_du_crc_source *source)
1009 {
1010         unsigned int index;
1011         int ret;
1012
1013         /*
1014          * Parse the source name. Supported values are "plane%u" to compute the
1015          * CRC on an input plane (%u is the plane ID), and "auto" to compute the
1016          * CRC on the composer (VSP) output.
1017          */
1018
1019         if (!source_name) {
1020                 *source = VSP1_DU_CRC_NONE;
1021                 return 0;
1022         } else if (!strcmp(source_name, "auto")) {
1023                 *source = VSP1_DU_CRC_OUTPUT;
1024                 return 0;
1025         } else if (strstarts(source_name, "plane")) {
1026                 unsigned int i;
1027
1028                 *source = VSP1_DU_CRC_PLANE;
1029
1030                 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
1031                 if (ret < 0)
1032                         return ret;
1033
1034                 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
1035                         if (index == rcrtc->vsp->planes[i].plane.base.id)
1036                                 return i;
1037                 }
1038         }
1039
1040         return -EINVAL;
1041 }
1042
1043 static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
1044                                           const char *source_name,
1045                                           size_t *values_cnt)
1046 {
1047         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1048         enum vsp1_du_crc_source source;
1049
1050         if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
1051                 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
1052                 return -EINVAL;
1053         }
1054
1055         *values_cnt = 1;
1056         return 0;
1057 }
1058
1059 static const char *const *
1060 rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
1061 {
1062         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1063
1064         *count = rcrtc->sources_count;
1065         return rcrtc->sources;
1066 }
1067
1068 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
1069                                        const char *source_name)
1070 {
1071         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1072         struct drm_modeset_acquire_ctx ctx;
1073         struct drm_crtc_state *crtc_state;
1074         struct drm_atomic_state *state;
1075         enum vsp1_du_crc_source source;
1076         unsigned int index;
1077         int ret;
1078
1079         ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
1080         if (ret < 0)
1081                 return ret;
1082
1083         index = ret;
1084
1085         /* Perform an atomic commit to set the CRC source. */
1086         drm_modeset_acquire_init(&ctx, 0);
1087
1088         state = drm_atomic_state_alloc(crtc->dev);
1089         if (!state) {
1090                 ret = -ENOMEM;
1091                 goto unlock;
1092         }
1093
1094         state->acquire_ctx = &ctx;
1095
1096 retry:
1097         crtc_state = drm_atomic_get_crtc_state(state, crtc);
1098         if (!IS_ERR(crtc_state)) {
1099                 struct rcar_du_crtc_state *rcrtc_state;
1100
1101                 rcrtc_state = to_rcar_crtc_state(crtc_state);
1102                 rcrtc_state->crc.source = source;
1103                 rcrtc_state->crc.index = index;
1104
1105                 ret = drm_atomic_commit(state);
1106         } else {
1107                 ret = PTR_ERR(crtc_state);
1108         }
1109
1110         if (ret == -EDEADLK) {
1111                 drm_atomic_state_clear(state);
1112                 drm_modeset_backoff(&ctx);
1113                 goto retry;
1114         }
1115
1116         drm_atomic_state_put(state);
1117
1118 unlock:
1119         drm_modeset_drop_locks(&ctx);
1120         drm_modeset_acquire_fini(&ctx);
1121
1122         return ret;
1123 }
1124
1125 static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1126         .reset = rcar_du_crtc_reset,
1127         .destroy = drm_crtc_cleanup,
1128         .set_config = drm_atomic_helper_set_config,
1129         .page_flip = drm_atomic_helper_page_flip,
1130         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1131         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1132         .enable_vblank = rcar_du_crtc_enable_vblank,
1133         .disable_vblank = rcar_du_crtc_disable_vblank,
1134 };
1135
1136 static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1137         .reset = rcar_du_crtc_reset,
1138         .destroy = rcar_du_crtc_cleanup,
1139         .set_config = drm_atomic_helper_set_config,
1140         .page_flip = drm_atomic_helper_page_flip,
1141         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1142         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1143         .enable_vblank = rcar_du_crtc_enable_vblank,
1144         .disable_vblank = rcar_du_crtc_disable_vblank,
1145         .set_crc_source = rcar_du_crtc_set_crc_source,
1146         .verify_crc_source = rcar_du_crtc_verify_crc_source,
1147         .get_crc_sources = rcar_du_crtc_get_crc_sources,
1148         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1149 };
1150
1151 /* -----------------------------------------------------------------------------
1152  * Interrupt Handling
1153  */
1154
1155 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1156 {
1157         struct rcar_du_crtc *rcrtc = arg;
1158         struct rcar_du_device *rcdu = rcrtc->dev;
1159         irqreturn_t ret = IRQ_NONE;
1160         u32 status;
1161
1162         spin_lock(&rcrtc->vblank_lock);
1163
1164         status = rcar_du_crtc_read(rcrtc, DSSR);
1165         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1166
1167         if (status & DSSR_VBK) {
1168                 /*
1169                  * Wake up the vblank wait if the counter reaches 0. This must
1170                  * be protected by the vblank_lock to avoid races in
1171                  * rcar_du_crtc_disable_planes().
1172                  */
1173                 if (rcrtc->vblank_count) {
1174                         if (--rcrtc->vblank_count == 0)
1175                                 wake_up(&rcrtc->vblank_wait);
1176                 }
1177         }
1178
1179         spin_unlock(&rcrtc->vblank_lock);
1180
1181         if (status & DSSR_VBK) {
1182                 if (rcdu->info->gen < 3) {
1183                         drm_crtc_handle_vblank(&rcrtc->crtc);
1184                         rcar_du_crtc_finish_page_flip(rcrtc);
1185                 }
1186
1187                 ret = IRQ_HANDLED;
1188         }
1189
1190         return ret;
1191 }
1192
1193 /* -----------------------------------------------------------------------------
1194  * Initialization
1195  */
1196
1197 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1198                         unsigned int hwindex)
1199 {
1200         static const unsigned int mmio_offsets[] = {
1201                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1202         };
1203
1204         struct rcar_du_device *rcdu = rgrp->dev;
1205         struct platform_device *pdev = to_platform_device(rcdu->dev);
1206         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1207         struct drm_crtc *crtc = &rcrtc->crtc;
1208         struct drm_plane *primary;
1209         unsigned int irqflags;
1210         struct clk *clk;
1211         char clk_name[9];
1212         char *name;
1213         int irq;
1214         int ret;
1215
1216         /* Get the CRTC clock and the optional external clock. */
1217         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1218                 sprintf(clk_name, "du.%u", hwindex);
1219                 name = clk_name;
1220         } else {
1221                 name = NULL;
1222         }
1223
1224         rcrtc->clock = devm_clk_get(rcdu->dev, name);
1225         if (IS_ERR(rcrtc->clock)) {
1226                 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1227                 return PTR_ERR(rcrtc->clock);
1228         }
1229
1230         sprintf(clk_name, "dclkin.%u", hwindex);
1231         clk = devm_clk_get(rcdu->dev, clk_name);
1232         if (!IS_ERR(clk)) {
1233                 rcrtc->extclock = clk;
1234         } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1235                 return -EPROBE_DEFER;
1236         } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1237                 /*
1238                  * DU channels that have a display PLL can't use the internal
1239                  * system clock and thus require an external clock.
1240                  */
1241                 ret = PTR_ERR(clk);
1242                 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1243                 return ret;
1244         }
1245
1246         init_waitqueue_head(&rcrtc->flip_wait);
1247         init_waitqueue_head(&rcrtc->vblank_wait);
1248         spin_lock_init(&rcrtc->vblank_lock);
1249
1250         rcrtc->dev = rcdu;
1251         rcrtc->group = rgrp;
1252         rcrtc->mmio_offset = mmio_offsets[hwindex];
1253         rcrtc->index = hwindex;
1254         rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1255
1256         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1257                 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1258         else
1259                 primary = &rgrp->planes[swindex % 2].plane;
1260
1261         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
1262                                         rcdu->info->gen <= 2 ?
1263                                         &crtc_funcs_gen2 : &crtc_funcs_gen3,
1264                                         NULL);
1265         if (ret < 0)
1266                 return ret;
1267
1268         /* CMM might be disabled for this CRTC. */
1269         if (rcdu->cmms[swindex]) {
1270                 rcrtc->cmm = rcdu->cmms[swindex];
1271                 rgrp->cmms_mask |= BIT(hwindex % 2);
1272
1273                 drm_mode_crtc_set_gamma_size(crtc, CM2_LUT_SIZE);
1274                 drm_crtc_enable_color_mgmt(crtc, 0, false, CM2_LUT_SIZE);
1275         }
1276
1277         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1278
1279         /* Register the interrupt handler. */
1280         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1281                 /* The IRQ's are associated with the CRTC (sw)index. */
1282                 irq = platform_get_irq(pdev, swindex);
1283                 irqflags = 0;
1284         } else {
1285                 irq = platform_get_irq(pdev, 0);
1286                 irqflags = IRQF_SHARED;
1287         }
1288
1289         if (irq < 0) {
1290                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1291                 return irq;
1292         }
1293
1294         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1295                                dev_name(rcdu->dev), rcrtc);
1296         if (ret < 0) {
1297                 dev_err(rcdu->dev,
1298                         "failed to register IRQ for CRTC %u\n", swindex);
1299                 return ret;
1300         }
1301
1302         rcar_du_crtc_crc_init(rcrtc);
1303
1304         return 0;
1305 }