drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 static const struct si_dte_data dte_data_tahiti_le =
 255 {
 256         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 257         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 258         0x5,
 259         0xAFC8,
 260         0x64,
 261         0x32,
 262         1,
 263         0,
 264         0x10,
 265         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 266         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 267         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 268         85,
 269         true
 270 };
 271
 272 static const struct si_dte_data dte_data_tahiti_pro =
 273 {
 274         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 275         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 276         5,
 277         45000,
 278         100,
 279         0xA,
 280         1,
 281         0,
 282         0x10,
 283         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 284         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 285         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 286         90,
 287         true
 288 };
 289
 290 static const struct si_dte_data dte_data_new_zealand =
 291 {
 292         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 293         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 294         0x5,
 295         0xAFC8,
 296         0x69,
 297         0x32,
 298         1,
 299         0,
 300         0x10,
 301         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 302         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 303         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 304         85,
 305         true
 306 };
 307
 308 static const struct si_dte_data dte_data_aruba_pro =
 309 {
 310         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 311         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 312         5,
 313         45000,
 314         100,
 315         0xA,
 316         1,
 317         0,
 318         0x10,
 319         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 320         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 321         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 322         90,
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_malta =
 327 {
 328         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 329         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 330         5,
 331         45000,
 332         100,
 333         0xA,
 334         1,
 335         0,
 336         0x10,
 337         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 338         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 339         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 340         90,
 341         true
 342 };
 343
 344 struct si_cac_config_reg cac_weights_pitcairn[] =
 345 {
 346         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 347         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 350         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 359         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 364         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 365         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 368         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 381         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 384         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 406         { 0xFFFFFFFF }
 407 };
 408
 409 static const struct si_cac_config_reg lcac_pitcairn[] =
 410 {
 411         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 412         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg cac_override_pitcairn[] =
 501 {
 502         { 0xFFFFFFFF }
 503 };
 504
 505 static const struct si_powertune_data powertune_data_pitcairn =
 506 {
 507         ((1 << 16) | 27027),
 508         5,
 509         0,
 510         6,
 511         100,
 512         {
 513                 51600000UL,
 514                 1800000UL,
 515                 7194395UL,
 516                 309631529UL,
 517                 -1270850L,
 518                 4513710L,
 519                 100
 520         },
 521         117830498UL,
 522         12,
 523         {
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0
 532         },
 533         true
 534 };
 535
 536 static const struct si_dte_data dte_data_pitcairn =
 537 {
 538         { 0, 0, 0, 0, 0 },
 539         { 0, 0, 0, 0, 0 },
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         0,
 551         false
 552 };
 553
 554 static const struct si_dte_data dte_data_curacao_xt =
 555 {
 556         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 557         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 558         5,
 559         45000,
 560         100,
 561         0xA,
 562         1,
 563         0,
 564         0x10,
 565         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 566         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 567         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 568         90,
 569         true
 570 };
 571
 572 static const struct si_dte_data dte_data_curacao_pro =
 573 {
 574         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 575         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 576         5,
 577         45000,
 578         100,
 579         0xA,
 580         1,
 581         0,
 582         0x10,
 583         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 584         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 585         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 586         90,
 587         true
 588 };
 589
 590 static const struct si_dte_data dte_data_neptune_xt =
 591 {
 592         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 593         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 594         5,
 595         45000,
 596         100,
 597         0xA,
 598         1,
 599         0,
 600         0x10,
 601         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 602         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 603         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 604         90,
 605         true
 606 };
 607
 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 609 {
 610         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 611         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 614         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 623         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 628         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 629         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 632         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 642         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 648         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 651         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 670         { 0xFFFFFFFF }
 671 };
 672
 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 674 {
 675         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 676         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 679         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 688         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 693         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 694         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 697         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 707         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 713         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 716         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 735         { 0xFFFFFFFF }
 736 };
 737
 738 static const struct si_cac_config_reg cac_weights_heathrow[] =
 739 {
 740         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 741         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 744         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 753         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 758         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 759         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 762         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 772         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 778         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 781         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 800         { 0xFFFFFFFF }
 801 };
 802
 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 804 {
 805         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 806         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 809         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 818         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 823         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 824         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 827         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 837         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 843         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 846         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 865         { 0xFFFFFFFF }
 866 };
 867
 868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 869 {
 870         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 871         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 874         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 883         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 888         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 889         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 892         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 902         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 908         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 911         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 930         { 0xFFFFFFFF }
 931 };
 932
 933 static const struct si_cac_config_reg lcac_cape_verde[] =
 934 {
 935         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 936         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0xFFFFFFFF }
 990 };
 991
 992 static const struct si_cac_config_reg cac_override_cape_verde[] =
 993 {
 994         { 0xFFFFFFFF }
 995 };
 996
 997 static const struct si_powertune_data powertune_data_cape_verde =
 998 {
 999         ((1 << 16) | 0x6993),
1000         5,
1001         0,
1002         7,
1003         105,
1004         {
1005                 0UL,
1006                 0UL,
1007                 7194395UL,
1008                 309631529UL,
1009                 -1270850L,
1010                 4513710L,
1011                 100
1012         },
1013         117830498UL,
1014         12,
1015         {
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0
1024         },
1025         true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030         { 0, 0, 0, 0, 0 },
1031         { 0, 0, 0, 0, 0 },
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         0,
1043         false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050         5,
1051         55000,
1052         0x69,
1053         0xA,
1054         1,
1055         0,
1056         0x3,
1057         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         90,
1061         true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068         5,
1069         55000,
1070         0x69,
1071         0xA,
1072         1,
1073         0,
1074         0x3,
1075         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         90,
1079         true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086         5,
1087         55000,
1088         0x69,
1089         0xA,
1090         1,
1091         0,
1092         0x3,
1093         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         90,
1097         true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162         { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227         { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292         { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357         { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422         { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521         { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526         ((1 << 16) | 0x6993),
1527         5,
1528         0,
1529         7,
1530         105,
1531         {
1532                 0UL,
1533                 0UL,
1534                 7194395UL,
1535                 309631529UL,
1536                 -1270850L,
1537                 4513710L,
1538                 100
1539         },
1540         117830498UL,
1541         12,
1542         {
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0
1551         },
1552         true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557         ((1 << 16) | 0x6993),
1558         5,
1559         0,
1560         7,
1561         105,
1562         {
1563                 0UL,
1564                 0UL,
1565                 7194395UL,
1566                 309631529UL,
1567                 -1270850L,
1568                 4513710L,
1569                 100
1570         },
1571         117830498UL,
1572         12,
1573         {
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0
1582         },
1583         true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588         { 0, 0, 0, 0, 0 },
1589         { 0, 0, 0, 0, 0 },
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         0,
1601         false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608         5,
1609         55000,
1610         105,
1611         0xA,
1612         1,
1613         0,
1614         0x10,
1615         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618         90,
1619         true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626         5,
1627         55000,
1628         105,
1629         0xA,
1630         1,
1631         0,
1632         0x10,
1633         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636         90,
1637         true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703         { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708         ((1 << 16) | 0x6993),
1709         5,
1710         0,
1711         9,
1712         105,
1713         {
1714                 0UL,
1715                 0UL,
1716                 7194395UL,
1717                 309631529UL,
1718                 -1270850L,
1719                 4513710L,
1720                 100
1721         },
1722         117830498UL,
1723         12,
1724         {
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0
1733         },
1734         true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746                                      const struct atom_voltage_table *table,
1747                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750                                     u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752                                       u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754                                          struct rv7xx_pl *pl,
1755                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757                                     u32 engine_clock,
1758                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765         struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767         return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773         s64 kt, kv, leakage_w, i_leakage, vddc;
1774         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775         s64 tmp;
1776
1777         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778         vddc = div64_s64(drm_int2fixp(v), 1000);
1779         temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785         t_ref = drm_int2fixp(coeff->t_ref);
1786
1787         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794         *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798                                              const struct ni_leakage_coeffients *coeff,
1799                                              u16 v,
1800                                              s32 t,
1801                                              u32 i_leakage,
1802                                              u32 *leakage)
1803 {
1804         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808                                                const u32 fixed_kt, u16 v,
1809                                                u32 ileakage, u32 *leakage)
1810 {
1811         s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814         vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822         *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826                                        const struct ni_leakage_coeffients *coeff,
1827                                        const u32 fixed_kt,
1828                                        u16 v,
1829                                        u32 i_leakage,
1830                                        u32 *leakage)
1831 {
1832         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837                                    struct si_dte_data *dte_data)
1838 {
1839         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841         u32 k = dte_data->k;
1842         u32 t_max = dte_data->max_t;
1843         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844         u32 t_0 = dte_data->t0;
1845         u32 i;
1846
1847         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848                 dte_data->tdep_count = 3;
1849
1850                 for (i = 0; i < k; i++) {
1851                         dte_data->r[i] =
1852                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853                                 (p_limit2  * (u32)100);
1854                 }
1855
1856                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859                         dte_data->tdep_r[i] = dte_data->r[4];
1860                 }
1861         } else {
1862                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863         }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869         struct si_power_info *si_pi = si_get_pi(rdev);
1870         bool update_dte_from_pl2 = false;
1871
1872         if (rdev->family == CHIP_TAHITI) {
1873                 si_pi->cac_weights = cac_weights_tahiti;
1874                 si_pi->lcac_config = lcac_tahiti;
1875                 si_pi->cac_override = cac_override_tahiti;
1876                 si_pi->powertune_data = &powertune_data_tahiti;
1877                 si_pi->dte_data = dte_data_tahiti;
1878
1879                 switch (rdev->pdev->device) {
1880                 case 0x6798:
1881                         si_pi->dte_data.enable_dte_by_default = true;
1882                         break;
1883                 case 0x6799:
1884                         si_pi->dte_data = dte_data_new_zealand;
1885                         break;
1886                 case 0x6790:
1887                 case 0x6791:
1888                 case 0x6792:
1889                 case 0x679E:
1890                         si_pi->dte_data = dte_data_aruba_pro;
1891                         update_dte_from_pl2 = true;
1892                         break;
1893                 case 0x679B:
1894                         si_pi->dte_data = dte_data_malta;
1895                         update_dte_from_pl2 = true;
1896                         break;
1897                 case 0x679A:
1898                         si_pi->dte_data = dte_data_tahiti_pro;
1899                         update_dte_from_pl2 = true;
1900                         break;
1901                 default:
1902                         if (si_pi->dte_data.enable_dte_by_default == true)
1903                                 DRM_ERROR("DTE is not enabled!\n");
1904                         break;
1905                 }
1906         } else if (rdev->family == CHIP_PITCAIRN) {
1907                 switch (rdev->pdev->device) {
1908                 case 0x6810:
1909                 case 0x6818:
1910                         si_pi->cac_weights = cac_weights_pitcairn;
1911                         si_pi->lcac_config = lcac_pitcairn;
1912                         si_pi->cac_override = cac_override_pitcairn;
1913                         si_pi->powertune_data = &powertune_data_pitcairn;
1914                         si_pi->dte_data = dte_data_curacao_xt;
1915                         update_dte_from_pl2 = true;
1916                         break;
1917                 case 0x6819:
1918                 case 0x6811:
1919                         si_pi->cac_weights = cac_weights_pitcairn;
1920                         si_pi->lcac_config = lcac_pitcairn;
1921                         si_pi->cac_override = cac_override_pitcairn;
1922                         si_pi->powertune_data = &powertune_data_pitcairn;
1923                         si_pi->dte_data = dte_data_curacao_pro;
1924                         update_dte_from_pl2 = true;
1925                         break;
1926                 case 0x6800:
1927                 case 0x6806:
1928                         si_pi->cac_weights = cac_weights_pitcairn;
1929                         si_pi->lcac_config = lcac_pitcairn;
1930                         si_pi->cac_override = cac_override_pitcairn;
1931                         si_pi->powertune_data = &powertune_data_pitcairn;
1932                         si_pi->dte_data = dte_data_neptune_xt;
1933                         update_dte_from_pl2 = true;
1934                         break;
1935                 default:
1936                         si_pi->cac_weights = cac_weights_pitcairn;
1937                         si_pi->lcac_config = lcac_pitcairn;
1938                         si_pi->cac_override = cac_override_pitcairn;
1939                         si_pi->powertune_data = &powertune_data_pitcairn;
1940                         si_pi->dte_data = dte_data_pitcairn;
1941                         break;
1942                 }
1943         } else if (rdev->family == CHIP_VERDE) {
1944                 si_pi->lcac_config = lcac_cape_verde;
1945                 si_pi->cac_override = cac_override_cape_verde;
1946                 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948                 switch (rdev->pdev->device) {
1949                 case 0x683B:
1950                 case 0x683F:
1951                 case 0x6829:
1952                 case 0x6835:
1953                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1954                         si_pi->dte_data = dte_data_cape_verde;
1955                         break;
1956                 case 0x682C:
1957                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1958                         si_pi->dte_data = dte_data_sun_xt;
1959                         update_dte_from_pl2 = true;
1960                         break;
1961                 case 0x6825:
1962                 case 0x6827:
1963                         si_pi->cac_weights = cac_weights_heathrow;
1964                         si_pi->dte_data = dte_data_cape_verde;
1965                         break;
1966                 case 0x6824:
1967                 case 0x682D:
1968                         si_pi->cac_weights = cac_weights_chelsea_xt;
1969                         si_pi->dte_data = dte_data_cape_verde;
1970                         break;
1971                 case 0x682F:
1972                         si_pi->cac_weights = cac_weights_chelsea_pro;
1973                         si_pi->dte_data = dte_data_cape_verde;
1974                         break;
1975                 case 0x6820:
1976                         si_pi->cac_weights = cac_weights_heathrow;
1977                         si_pi->dte_data = dte_data_venus_xtx;
1978                         break;
1979                 case 0x6821:
1980                         si_pi->cac_weights = cac_weights_heathrow;
1981                         si_pi->dte_data = dte_data_venus_xt;
1982                         break;
1983                 case 0x6823:
1984                 case 0x682B:
1985                 case 0x6822:
1986                 case 0x682A:
1987                         si_pi->cac_weights = cac_weights_chelsea_pro;
1988                         si_pi->dte_data = dte_data_venus_pro;
1989                         break;
1990                 default:
1991                         si_pi->cac_weights = cac_weights_cape_verde;
1992                         si_pi->dte_data = dte_data_cape_verde;
1993                         break;
1994                 }
1995         } else if (rdev->family == CHIP_OLAND) {
1996                 switch (rdev->pdev->device) {
1997                 case 0x6601:
1998                 case 0x6621:
1999                 case 0x6603:
2000                 case 0x6605:
2001                         si_pi->cac_weights = cac_weights_mars_pro;
2002                         si_pi->lcac_config = lcac_mars_pro;
2003                         si_pi->cac_override = cac_override_oland;
2004                         si_pi->powertune_data = &powertune_data_mars_pro;
2005                         si_pi->dte_data = dte_data_mars_pro;
2006                         update_dte_from_pl2 = true;
2007                         break;
2008                 case 0x6600:
2009                 case 0x6606:
2010                 case 0x6620:
2011                 case 0x6604:
2012                         si_pi->cac_weights = cac_weights_mars_xt;
2013                         si_pi->lcac_config = lcac_mars_pro;
2014                         si_pi->cac_override = cac_override_oland;
2015                         si_pi->powertune_data = &powertune_data_mars_pro;
2016                         si_pi->dte_data = dte_data_mars_pro;
2017                         update_dte_from_pl2 = true;
2018                         break;
2019                 case 0x6611:
2020                 case 0x6613:
2021                 case 0x6608:
2022                         si_pi->cac_weights = cac_weights_oland_pro;
2023                         si_pi->lcac_config = lcac_mars_pro;
2024                         si_pi->cac_override = cac_override_oland;
2025                         si_pi->powertune_data = &powertune_data_mars_pro;
2026                         si_pi->dte_data = dte_data_mars_pro;
2027                         update_dte_from_pl2 = true;
2028                         break;
2029                 case 0x6610:
2030                         si_pi->cac_weights = cac_weights_oland_xt;
2031                         si_pi->lcac_config = lcac_mars_pro;
2032                         si_pi->cac_override = cac_override_oland;
2033                         si_pi->powertune_data = &powertune_data_mars_pro;
2034                         si_pi->dte_data = dte_data_mars_pro;
2035                         update_dte_from_pl2 = true;
2036                         break;
2037                 default:
2038                         si_pi->cac_weights = cac_weights_oland;
2039                         si_pi->lcac_config = lcac_oland;
2040                         si_pi->cac_override = cac_override_oland;
2041                         si_pi->powertune_data = &powertune_data_oland;
2042                         si_pi->dte_data = dte_data_oland;
2043                         break;
2044                 }
2045         } else if (rdev->family == CHIP_HAINAN) {
2046                 si_pi->cac_weights = cac_weights_hainan;
2047                 si_pi->lcac_config = lcac_oland;
2048                 si_pi->cac_override = cac_override_oland;
2049                 si_pi->powertune_data = &powertune_data_hainan;
2050                 si_pi->dte_data = dte_data_sun_xt;
2051                 update_dte_from_pl2 = true;
2052         } else {
2053                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2054                 return;
2055         }
2056
2057         ni_pi->enable_power_containment = false;
2058         ni_pi->enable_cac = false;
2059         ni_pi->enable_sq_ramping = false;
2060         si_pi->enable_dte = false;
2061
2062         if (si_pi->powertune_data->enable_powertune_by_default) {
2063                 ni_pi->enable_power_containment= true;
2064                 ni_pi->enable_cac = true;
2065                 if (si_pi->dte_data.enable_dte_by_default) {
2066                         si_pi->enable_dte = true;
2067                         if (update_dte_from_pl2)
2068                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2069
2070                 }
2071                 ni_pi->enable_sq_ramping = true;
2072         }
2073
2074         ni_pi->driver_calculate_cac_leakage = true;
2075         ni_pi->cac_configuration_required = true;
2076
2077         if (ni_pi->cac_configuration_required) {
2078                 ni_pi->support_cac_long_term_average = true;
2079                 si_pi->dyn_powertune_data.l2_lta_window_size =
2080                         si_pi->powertune_data->l2_lta_window_size_default;
2081                 si_pi->dyn_powertune_data.lts_truncate =
2082                         si_pi->powertune_data->lts_truncate_default;
2083         } else {
2084                 ni_pi->support_cac_long_term_average = false;
2085                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2086                 si_pi->dyn_powertune_data.lts_truncate = 0;
2087         }
2088
2089         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2090 }
2091
2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2093 {
2094         return 1;
2095 }
2096
2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2098 {
2099         u32 xclk;
2100         u32 wintime;
2101         u32 cac_window;
2102         u32 cac_window_size;
2103
2104         xclk = radeon_get_xclk(rdev);
2105
2106         if (xclk == 0)
2107                 return 0;
2108
2109         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2110         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2111
2112         wintime = (cac_window_size * 100) / xclk;
2113
2114         return wintime;
2115 }
2116
2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2118 {
2119         return power_in_watts;
2120 }
2121
2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2123                                             bool adjust_polarity,
2124                                             u32 tdp_adjustment,
2125                                             u32 *tdp_limit,
2126                                             u32 *near_tdp_limit)
2127 {
2128         u32 adjustment_delta, max_tdp_limit;
2129
2130         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2131                 return -EINVAL;
2132
2133         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2134
2135         if (adjust_polarity) {
2136                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2137                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2138         } else {
2139                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2140                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2141                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2142                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2143                 else
2144                         *near_tdp_limit = 0;
2145         }
2146
2147         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2148                 return -EINVAL;
2149         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2150                 return -EINVAL;
2151
2152         return 0;
2153 }
2154
2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2156                                       struct radeon_ps *radeon_state)
2157 {
2158         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2159         struct si_power_info *si_pi = si_get_pi(rdev);
2160
2161         if (ni_pi->enable_power_containment) {
2162                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2163                 PP_SIslands_PAPMParameters *papm_parm;
2164                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2165                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2166                 u32 tdp_limit;
2167                 u32 near_tdp_limit;
2168                 int ret;
2169
2170                 if (scaling_factor == 0)
2171                         return -EINVAL;
2172
2173                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2174
2175                 ret = si_calculate_adjusted_tdp_limits(rdev,
2176                                                        false, /* ??? */
2177                                                        rdev->pm.dpm.tdp_adjustment,
2178                                                        &tdp_limit,
2179                                                        &near_tdp_limit);
2180                 if (ret)
2181                         return ret;
2182
2183                 smc_table->dpm2Params.TDPLimit =
2184                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2185                 smc_table->dpm2Params.NearTDPLimit =
2186                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2187                 smc_table->dpm2Params.SafePowerLimit =
2188                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2189
2190                 ret = si_copy_bytes_to_smc(rdev,
2191                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2192                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2193                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2194                                            sizeof(u32) * 3,
2195                                            si_pi->sram_end);
2196                 if (ret)
2197                         return ret;
2198
2199                 if (si_pi->enable_ppm) {
2200                         papm_parm = &si_pi->papm_parm;
2201                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2202                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2203                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2204                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2205                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2206                         papm_parm->PlatformPowerLimit = 0xffffffff;
2207                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2208
2209                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2210                                                    (u8 *)papm_parm,
2211                                                    sizeof(PP_SIslands_PAPMParameters),
2212                                                    si_pi->sram_end);
2213                         if (ret)
2214                                 return ret;
2215                 }
2216         }
2217         return 0;
2218 }
2219
2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2221                                         struct radeon_ps *radeon_state)
2222 {
2223         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2224         struct si_power_info *si_pi = si_get_pi(rdev);
2225
2226         if (ni_pi->enable_power_containment) {
2227                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2228                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2229                 int ret;
2230
2231                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2232
2233                 smc_table->dpm2Params.NearTDPLimit =
2234                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2235                 smc_table->dpm2Params.SafePowerLimit =
2236                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2237
2238                 ret = si_copy_bytes_to_smc(rdev,
2239                                            (si_pi->state_table_start +
2240                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2241                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2242                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2243                                            sizeof(u32) * 2,
2244                                            si_pi->sram_end);
2245                 if (ret)
2246                         return ret;
2247         }
2248
2249         return 0;
2250 }
2251
2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2253                                                const u16 prev_std_vddc,
2254                                                const u16 curr_std_vddc)
2255 {
2256         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2257         u64 prev_vddc = (u64)prev_std_vddc;
2258         u64 curr_vddc = (u64)curr_std_vddc;
2259         u64 pwr_efficiency_ratio, n, d;
2260
2261         if ((prev_vddc == 0) || (curr_vddc == 0))
2262                 return 0;
2263
2264         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2265         d = prev_vddc * prev_vddc;
2266         pwr_efficiency_ratio = div64_u64(n, d);
2267
2268         if (pwr_efficiency_ratio > (u64)0xFFFF)
2269                 return 0;
2270
2271         return (u16)pwr_efficiency_ratio;
2272 }
2273
2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2275                                             struct radeon_ps *radeon_state)
2276 {
2277         struct si_power_info *si_pi = si_get_pi(rdev);
2278
2279         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2280             radeon_state->vclk && radeon_state->dclk)
2281                 return true;
2282
2283         return false;
2284 }
2285
2286 static int si_populate_power_containment_values(struct radeon_device *rdev,
2287                                                 struct radeon_ps *radeon_state,
2288                                                 SISLANDS_SMC_SWSTATE *smc_state)
2289 {
2290         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2291         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2292         struct ni_ps *state = ni_get_ps(radeon_state);
2293         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2294         u32 prev_sclk;
2295         u32 max_sclk;
2296         u32 min_sclk;
2297         u16 prev_std_vddc;
2298         u16 curr_std_vddc;
2299         int i;
2300         u16 pwr_efficiency_ratio;
2301         u8 max_ps_percent;
2302         bool disable_uvd_power_tune;
2303         int ret;
2304
2305         if (ni_pi->enable_power_containment == false)
2306                 return 0;
2307
2308         if (state->performance_level_count == 0)
2309                 return -EINVAL;
2310
2311         if (smc_state->levelCount != state->performance_level_count)
2312                 return -EINVAL;
2313
2314         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2315
2316         smc_state->levels[0].dpm2.MaxPS = 0;
2317         smc_state->levels[0].dpm2.NearTDPDec = 0;
2318         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2319         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2320         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2321
2322         for (i = 1; i < state->performance_level_count; i++) {
2323                 prev_sclk = state->performance_levels[i-1].sclk;
2324                 max_sclk  = state->performance_levels[i].sclk;
2325                 if (i == 1)
2326                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2327                 else
2328                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2329
2330                 if (prev_sclk > max_sclk)
2331                         return -EINVAL;
2332
2333                 if ((max_ps_percent == 0) ||
2334                     (prev_sclk == max_sclk) ||
2335                     disable_uvd_power_tune) {
2336                         min_sclk = max_sclk;
2337                 } else if (i == 1) {
2338                         min_sclk = prev_sclk;
2339                 } else {
2340                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2341                 }
2342
2343                 if (min_sclk < state->performance_levels[0].sclk)
2344                         min_sclk = state->performance_levels[0].sclk;
2345
2346                 if (min_sclk == 0)
2347                         return -EINVAL;
2348
2349                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2350                                                 state->performance_levels[i-1].vddc, &vddc);
2351                 if (ret)
2352                         return ret;
2353
2354                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2355                 if (ret)
2356                         return ret;
2357
2358                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2359                                                 state->performance_levels[i].vddc, &vddc);
2360                 if (ret)
2361                         return ret;
2362
2363                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2364                 if (ret)
2365                         return ret;
2366
2367                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2368                                                                            prev_std_vddc, curr_std_vddc);
2369
2370                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2371                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2372                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2373                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2374                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2375         }
2376
2377         return 0;
2378 }
2379
2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2381                                          struct radeon_ps *radeon_state,
2382                                          SISLANDS_SMC_SWSTATE *smc_state)
2383 {
2384         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2385         struct ni_ps *state = ni_get_ps(radeon_state);
2386         u32 sq_power_throttle, sq_power_throttle2;
2387         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2388         int i;
2389
2390         if (state->performance_level_count == 0)
2391                 return -EINVAL;
2392
2393         if (smc_state->levelCount != state->performance_level_count)
2394                 return -EINVAL;
2395
2396         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2397                 return -EINVAL;
2398
2399         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2400                 enable_sq_ramping = false;
2401
2402         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2403                 enable_sq_ramping = false;
2404
2405         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2406                 enable_sq_ramping = false;
2407
2408         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2409                 enable_sq_ramping = false;
2410
2411         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2412                 enable_sq_ramping = false;
2413
2414         for (i = 0; i < state->performance_level_count; i++) {
2415                 sq_power_throttle = 0;
2416                 sq_power_throttle2 = 0;
2417
2418                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2419                     enable_sq_ramping) {
2420                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2421                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2422                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2423                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2424                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2425                 } else {
2426                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2427                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2428                 }
2429
2430                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2431                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int si_enable_power_containment(struct radeon_device *rdev,
2438                                        struct radeon_ps *radeon_new_state,
2439                                        bool enable)
2440 {
2441         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2442         PPSMC_Result smc_result;
2443         int ret = 0;
2444
2445         if (ni_pi->enable_power_containment) {
2446                 if (enable) {
2447                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2448                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2449                                 if (smc_result != PPSMC_Result_OK) {
2450                                         ret = -EINVAL;
2451                                         ni_pi->pc_enabled = false;
2452                                 } else {
2453                                         ni_pi->pc_enabled = true;
2454                                 }
2455                         }
2456                 } else {
2457                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2458                         if (smc_result != PPSMC_Result_OK)
2459                                 ret = -EINVAL;
2460                         ni_pi->pc_enabled = false;
2461                 }
2462         }
2463
2464         return ret;
2465 }
2466
2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2468 {
2469         struct si_power_info *si_pi = si_get_pi(rdev);
2470         int ret = 0;
2471         struct si_dte_data *dte_data = &si_pi->dte_data;
2472         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2473         u32 table_size;
2474         u8 tdep_count;
2475         u32 i;
2476
2477         if (dte_data == NULL)
2478                 si_pi->enable_dte = false;
2479
2480         if (si_pi->enable_dte == false)
2481                 return 0;
2482
2483         if (dte_data->k <= 0)
2484                 return -EINVAL;
2485
2486         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2487         if (dte_tables == NULL) {
2488                 si_pi->enable_dte = false;
2489                 return -ENOMEM;
2490         }
2491
2492         table_size = dte_data->k;
2493
2494         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2495                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2496
2497         tdep_count = dte_data->tdep_count;
2498         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2499                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2500
2501         dte_tables->K = cpu_to_be32(table_size);
2502         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2503         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2504         dte_tables->WindowSize = dte_data->window_size;
2505         dte_tables->temp_select = dte_data->temp_select;
2506         dte_tables->DTE_mode = dte_data->dte_mode;
2507         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2508
2509         if (tdep_count > 0)
2510                 table_size--;
2511
2512         for (i = 0; i < table_size; i++) {
2513                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2514                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2515         }
2516
2517         dte_tables->Tdep_count = tdep_count;
2518
2519         for (i = 0; i < (u32)tdep_count; i++) {
2520                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2521                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2522                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2523         }
2524
2525         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2526                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2527         kfree(dte_tables);
2528
2529         return ret;
2530 }
2531
2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2533                                           u16 *max, u16 *min)
2534 {
2535         struct si_power_info *si_pi = si_get_pi(rdev);
2536         struct radeon_cac_leakage_table *table =
2537                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2538         u32 i;
2539         u32 v0_loadline;
2540
2541
2542         if (table == NULL)
2543                 return -EINVAL;
2544
2545         *max = 0;
2546         *min = 0xFFFF;
2547
2548         for (i = 0; i < table->count; i++) {
2549                 if (table->entries[i].vddc > *max)
2550                         *max = table->entries[i].vddc;
2551                 if (table->entries[i].vddc < *min)
2552                         *min = table->entries[i].vddc;
2553         }
2554
2555         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2556                 return -EINVAL;
2557
2558         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2559
2560         if (v0_loadline > 0xFFFFUL)
2561                 return -EINVAL;
2562
2563         *min = (u16)v0_loadline;
2564
2565         if ((*min > *max) || (*max == 0) || (*min == 0))
2566                 return -EINVAL;
2567
2568         return 0;
2569 }
2570
2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2572 {
2573         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2574                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2575 }
2576
2577 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2578                                      PP_SIslands_CacConfig *cac_tables,
2579                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2580                                      u16 t0, u16 t_step)
2581 {
2582         struct si_power_info *si_pi = si_get_pi(rdev);
2583         u32 leakage;
2584         unsigned int i, j;
2585         s32 t;
2586         u32 smc_leakage;
2587         u32 scaling_factor;
2588         u16 voltage;
2589
2590         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2591
2592         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2593                 t = (1000 * (i * t_step + t0));
2594
2595                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2596                         voltage = vddc_max - (vddc_step * j);
2597
2598                         si_calculate_leakage_for_v_and_t(rdev,
2599                                                          &si_pi->powertune_data->leakage_coefficients,
2600                                                          voltage,
2601                                                          t,
2602                                                          si_pi->dyn_powertune_data.cac_leakage,
2603                                                          &leakage);
2604
2605                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2606
2607                         if (smc_leakage > 0xFFFF)
2608                                 smc_leakage = 0xFFFF;
2609
2610                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2611                                 cpu_to_be16((u16)smc_leakage);
2612                 }
2613         }
2614         return 0;
2615 }
2616
2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2618                                             PP_SIslands_CacConfig *cac_tables,
2619                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2620 {
2621         struct si_power_info *si_pi = si_get_pi(rdev);
2622         u32 leakage;
2623         unsigned int i, j;
2624         u32 smc_leakage;
2625         u32 scaling_factor;
2626         u16 voltage;
2627
2628         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2629
2630         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2631                 voltage = vddc_max - (vddc_step * j);
2632
2633                 si_calculate_leakage_for_v(rdev,
2634                                            &si_pi->powertune_data->leakage_coefficients,
2635                                            si_pi->powertune_data->fixed_kt,
2636                                            voltage,
2637                                            si_pi->dyn_powertune_data.cac_leakage,
2638                                            &leakage);
2639
2640                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2641
2642                 if (smc_leakage > 0xFFFF)
2643                         smc_leakage = 0xFFFF;
2644
2645                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2646                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2647                                 cpu_to_be16((u16)smc_leakage);
2648         }
2649         return 0;
2650 }
2651
2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2653 {
2654         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2655         struct si_power_info *si_pi = si_get_pi(rdev);
2656         PP_SIslands_CacConfig *cac_tables = NULL;
2657         u16 vddc_max, vddc_min, vddc_step;
2658         u16 t0, t_step;
2659         u32 load_line_slope, reg;
2660         int ret = 0;
2661         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2662
2663         if (ni_pi->enable_cac == false)
2664                 return 0;
2665
2666         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2667         if (!cac_tables)
2668                 return -ENOMEM;
2669
2670         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2671         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2672         WREG32(CG_CAC_CTRL, reg);
2673
2674         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2675         si_pi->dyn_powertune_data.dc_pwr_value =
2676                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2677         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2678         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2679
2680         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2681
2682         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2683         if (ret)
2684                 goto done_free;
2685
2686         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2687         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2688         t_step = 4;
2689         t0 = 60;
2690
2691         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2692                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2693                                                 vddc_max, vddc_min, vddc_step,
2694                                                 t0, t_step);
2695         else
2696                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2697                                                        vddc_max, vddc_min, vddc_step);
2698         if (ret)
2699                 goto done_free;
2700
2701         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2702
2703         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2704         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2705         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2706         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2707         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2708         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2709         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2710         cac_tables->calculation_repeats = cpu_to_be32(2);
2711         cac_tables->dc_cac = cpu_to_be32(0);
2712         cac_tables->log2_PG_LKG_SCALE = 12;
2713         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2714         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2715         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2716
2717         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2718                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2719
2720         if (ret)
2721                 goto done_free;
2722
2723         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2724
2725 done_free:
2726         if (ret) {
2727                 ni_pi->enable_cac = false;
2728                 ni_pi->enable_power_containment = false;
2729         }
2730
2731         kfree(cac_tables);
2732
2733         return 0;
2734 }
2735
2736 static int si_program_cac_config_registers(struct radeon_device *rdev,
2737                                            const struct si_cac_config_reg *cac_config_regs)
2738 {
2739         const struct si_cac_config_reg *config_regs = cac_config_regs;
2740         u32 data = 0, offset;
2741
2742         if (!config_regs)
2743                 return -EINVAL;
2744
2745         while (config_regs->offset != 0xFFFFFFFF) {
2746                 switch (config_regs->type) {
2747                 case SISLANDS_CACCONFIG_CGIND:
2748                         offset = SMC_CG_IND_START + config_regs->offset;
2749                         if (offset < SMC_CG_IND_END)
2750                                 data = RREG32_SMC(offset);
2751                         break;
2752                 default:
2753                         data = RREG32(config_regs->offset << 2);
2754                         break;
2755                 }
2756
2757                 data &= ~config_regs->mask;
2758                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2759
2760                 switch (config_regs->type) {
2761                 case SISLANDS_CACCONFIG_CGIND:
2762                         offset = SMC_CG_IND_START + config_regs->offset;
2763                         if (offset < SMC_CG_IND_END)
2764                                 WREG32_SMC(offset, data);
2765                         break;
2766                 default:
2767                         WREG32(config_regs->offset << 2, data);
2768                         break;
2769                 }
2770                 config_regs++;
2771         }
2772         return 0;
2773 }
2774
2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2776 {
2777         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2778         struct si_power_info *si_pi = si_get_pi(rdev);
2779         int ret;
2780
2781         if ((ni_pi->enable_cac == false) ||
2782             (ni_pi->cac_configuration_required == false))
2783                 return 0;
2784
2785         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2786         if (ret)
2787                 return ret;
2788         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2789         if (ret)
2790                 return ret;
2791         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2792         if (ret)
2793                 return ret;
2794
2795         return 0;
2796 }
2797
2798 static int si_enable_smc_cac(struct radeon_device *rdev,
2799                              struct radeon_ps *radeon_new_state,
2800                              bool enable)
2801 {
2802         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2803         struct si_power_info *si_pi = si_get_pi(rdev);
2804         PPSMC_Result smc_result;
2805         int ret = 0;
2806
2807         if (ni_pi->enable_cac) {
2808                 if (enable) {
2809                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2810                                 if (ni_pi->support_cac_long_term_average) {
2811                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2812                                         if (smc_result != PPSMC_Result_OK)
2813                                                 ni_pi->support_cac_long_term_average = false;
2814                                 }
2815
2816                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2817                                 if (smc_result != PPSMC_Result_OK) {
2818                                         ret = -EINVAL;
2819                                         ni_pi->cac_enabled = false;
2820                                 } else {
2821                                         ni_pi->cac_enabled = true;
2822                                 }
2823
2824                                 if (si_pi->enable_dte) {
2825                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2826                                         if (smc_result != PPSMC_Result_OK)
2827                                                 ret = -EINVAL;
2828                                 }
2829                         }
2830                 } else if (ni_pi->cac_enabled) {
2831                         if (si_pi->enable_dte)
2832                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2833
2834                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2835
2836                         ni_pi->cac_enabled = false;
2837
2838                         if (ni_pi->support_cac_long_term_average)
2839                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2840                 }
2841         }
2842         return ret;
2843 }
2844
2845 static int si_init_smc_spll_table(struct radeon_device *rdev)
2846 {
2847         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2848         struct si_power_info *si_pi = si_get_pi(rdev);
2849         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2850         SISLANDS_SMC_SCLK_VALUE sclk_params;
2851         u32 fb_div, p_div;
2852         u32 clk_s, clk_v;
2853         u32 sclk = 0;
2854         int ret = 0;
2855         u32 tmp;
2856         int i;
2857
2858         if (si_pi->spll_table_start == 0)
2859                 return -EINVAL;
2860
2861         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2862         if (spll_table == NULL)
2863                 return -ENOMEM;
2864
2865         for (i = 0; i < 256; i++) {
2866                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2867                 if (ret)
2868                         break;
2869
2870                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2871                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2872                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2873                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2874
2875                 fb_div &= ~0x00001FFF;
2876                 fb_div >>= 1;
2877                 clk_v >>= 6;
2878
2879                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2880                         ret = -EINVAL;
2881                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2882                         ret = -EINVAL;
2883                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2884                         ret = -EINVAL;
2885                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2886                         ret = -EINVAL;
2887
2888                 if (ret)
2889                         break;
2890
2891                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2892                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2893                 spll_table->freq[i] = cpu_to_be32(tmp);
2894
2895                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2896                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2897                 spll_table->ss[i] = cpu_to_be32(tmp);
2898
2899                 sclk += 512;
2900         }
2901
2902
2903         if (!ret)
2904                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2905                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2906                                            si_pi->sram_end);
2907
2908         if (ret)
2909                 ni_pi->enable_power_containment = false;
2910
2911         kfree(spll_table);
2912
2913         return ret;
2914 }
2915
2916 struct si_dpm_quirk {
2917         u32 chip_vendor;
2918         u32 chip_device;
2919         u32 subsys_vendor;
2920         u32 subsys_device;
2921         u32 max_sclk;
2922         u32 max_mclk;
2923 };
2924
2925 /* cards with dpm stability problems */
2926 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2927         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2928         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2929         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2930         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2931         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2932         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2933         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2934         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2935         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2936         { 0, 0, 0, 0 },
2937 };
2938
2939 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2940                                                    u16 vce_voltage)
2941 {
2942         u16 highest_leakage = 0;
2943         struct si_power_info *si_pi = si_get_pi(rdev);
2944         int i;
2945
2946         for (i = 0; i < si_pi->leakage_voltage.count; i++){
2947                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2948                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2949         }
2950
2951         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2952                 return highest_leakage;
2953
2954         return vce_voltage;
2955 }
2956
2957 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2958                                     u32 evclk, u32 ecclk, u16 *voltage)
2959 {
2960         u32 i;
2961         int ret = -EINVAL;
2962         struct radeon_vce_clock_voltage_dependency_table *table =
2963                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2964
2965         if (((evclk == 0) && (ecclk == 0)) ||
2966             (table && (table->count == 0))) {
2967                 *voltage = 0;
2968                 return 0;
2969         }
2970
2971         for (i = 0; i < table->count; i++) {
2972                 if ((evclk <= table->entries[i].evclk) &&
2973                     (ecclk <= table->entries[i].ecclk)) {
2974                         *voltage = table->entries[i].v;
2975                         ret = 0;
2976                         break;
2977                 }
2978         }
2979
2980         /* if no match return the highest voltage */
2981         if (ret)
2982                 *voltage = table->entries[table->count - 1].v;
2983
2984         *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2985
2986         return ret;
2987 }
2988
2989 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2990                                         struct radeon_ps *rps)
2991 {
2992         struct ni_ps *ps = ni_get_ps(rps);
2993         struct radeon_clock_and_voltage_limits *max_limits;
2994         bool disable_mclk_switching = false;
2995         bool disable_sclk_switching = false;
2996         u32 mclk, sclk;
2997         u16 vddc, vddci, min_vce_voltage = 0;
2998         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2999         u32 max_sclk = 0, max_mclk = 0;
3000         int i;
3001         struct si_dpm_quirk *p = si_dpm_quirk_list;
3002
3003         /* limit all SI kickers */
3004         if (rdev->family == CHIP_PITCAIRN) {
3005                 if ((rdev->pdev->revision == 0x81) ||
3006                     (rdev->pdev->device == 0x6810) ||
3007                     (rdev->pdev->device == 0x6811) ||
3008                     (rdev->pdev->device == 0x6816) ||
3009                     (rdev->pdev->device == 0x6817) ||
3010                     (rdev->pdev->device == 0x6806))
3011                         max_mclk = 120000;
3012         } else if (rdev->family == CHIP_OLAND) {
3013                 if ((rdev->pdev->revision == 0xC7) ||
3014                     (rdev->pdev->revision == 0x80) ||
3015                     (rdev->pdev->revision == 0x81) ||
3016                     (rdev->pdev->revision == 0x83) ||
3017                     (rdev->pdev->revision == 0x87) ||
3018                     (rdev->pdev->device == 0x6604) ||
3019                     (rdev->pdev->device == 0x6605)) {
3020                         max_sclk = 75000;
3021                         max_mclk = 80000;
3022                 }
3023         } else if (rdev->family == CHIP_HAINAN) {
3024                 if ((rdev->pdev->revision == 0x81) ||
3025                     (rdev->pdev->revision == 0x83) ||
3026                     (rdev->pdev->revision == 0xC3) ||
3027                     (rdev->pdev->device == 0x6664) ||
3028                     (rdev->pdev->device == 0x6665) ||
3029                     (rdev->pdev->device == 0x6667)) {
3030                         max_sclk = 75000;
3031                         max_mclk = 80000;
3032                 }
3033                 if ((rdev->pdev->revision == 0xC3) ||
3034                     (rdev->pdev->device == 0x6665)) {
3035                         max_sclk = 60000;
3036                         max_mclk = 80000;
3037                 }
3038         } else if (rdev->family == CHIP_OLAND) {
3039                 if ((rdev->pdev->revision == 0xC7) ||
3040                     (rdev->pdev->revision == 0x80) ||
3041                     (rdev->pdev->revision == 0x81) ||
3042                     (rdev->pdev->revision == 0x83) ||
3043                     (rdev->pdev->revision == 0x87) ||
3044                     (rdev->pdev->device == 0x6604) ||
3045                     (rdev->pdev->device == 0x6605)) {
3046                         max_sclk = 75000;
3047                 }
3048         }
3049         /* Apply dpm quirks */
3050         while (p && p->chip_device != 0) {
3051                 if (rdev->pdev->vendor == p->chip_vendor &&
3052                     rdev->pdev->device == p->chip_device &&
3053                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3054                     rdev->pdev->subsystem_device == p->subsys_device) {
3055                         max_sclk = p->max_sclk;
3056                         max_mclk = p->max_mclk;
3057                         break;
3058                 }
3059                 ++p;
3060         }
3061
3062         if (rps->vce_active) {
3063                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3064                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3065                 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3066                                          &min_vce_voltage);
3067         } else {
3068                 rps->evclk = 0;
3069                 rps->ecclk = 0;
3070         }
3071
3072         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3073             ni_dpm_vblank_too_short(rdev))
3074                 disable_mclk_switching = true;
3075
3076         if (rps->vclk || rps->dclk) {
3077                 disable_mclk_switching = true;
3078                 disable_sclk_switching = true;
3079         }
3080
3081         if (rdev->pm.dpm.ac_power)
3082                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3083         else
3084                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3085
3086         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3087                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3088                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3089         }
3090         if (rdev->pm.dpm.ac_power == false) {
3091                 for (i = 0; i < ps->performance_level_count; i++) {
3092                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3093                                 ps->performance_levels[i].mclk = max_limits->mclk;
3094                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3095                                 ps->performance_levels[i].sclk = max_limits->sclk;
3096                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3097                                 ps->performance_levels[i].vddc = max_limits->vddc;
3098                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3099                                 ps->performance_levels[i].vddci = max_limits->vddci;
3100                 }
3101         }
3102
3103         /* limit clocks to max supported clocks based on voltage dependency tables */
3104         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3105                                                         &max_sclk_vddc);
3106         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3107                                                         &max_mclk_vddci);
3108         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3109                                                         &max_mclk_vddc);
3110
3111         for (i = 0; i < ps->performance_level_count; i++) {
3112                 if (max_sclk_vddc) {
3113                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3114                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3115                 }
3116                 if (max_mclk_vddci) {
3117                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3118                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3119                 }
3120                 if (max_mclk_vddc) {
3121                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3122                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3123                 }
3124                 if (max_mclk) {
3125                         if (ps->performance_levels[i].mclk > max_mclk)
3126                                 ps->performance_levels[i].mclk = max_mclk;
3127                 }
3128                 if (max_sclk) {
3129                         if (ps->performance_levels[i].sclk > max_sclk)
3130                                 ps->performance_levels[i].sclk = max_sclk;
3131                 }
3132         }
3133
3134         /* XXX validate the min clocks required for display */
3135
3136         if (disable_mclk_switching) {
3137                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3138                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3139         } else {
3140                 mclk = ps->performance_levels[0].mclk;
3141                 vddci = ps->performance_levels[0].vddci;
3142         }
3143
3144         if (disable_sclk_switching) {
3145                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3146                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3147         } else {
3148                 sclk = ps->performance_levels[0].sclk;
3149                 vddc = ps->performance_levels[0].vddc;
3150         }
3151
3152         if (rps->vce_active) {
3153                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3154                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3155                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3156                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3157         }
3158
3159         /* adjusted low state */
3160         ps->performance_levels[0].sclk = sclk;
3161         ps->performance_levels[0].mclk = mclk;
3162         ps->performance_levels[0].vddc = vddc;
3163         ps->performance_levels[0].vddci = vddci;
3164
3165         if (disable_sclk_switching) {
3166                 sclk = ps->performance_levels[0].sclk;
3167                 for (i = 1; i < ps->performance_level_count; i++) {
3168                         if (sclk < ps->performance_levels[i].sclk)
3169                                 sclk = ps->performance_levels[i].sclk;
3170                 }
3171                 for (i = 0; i < ps->performance_level_count; i++) {
3172                         ps->performance_levels[i].sclk = sclk;
3173                         ps->performance_levels[i].vddc = vddc;
3174                 }
3175         } else {
3176                 for (i = 1; i < ps->performance_level_count; i++) {
3177                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3178                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3179                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3180                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3181                 }
3182         }
3183
3184         if (disable_mclk_switching) {
3185                 mclk = ps->performance_levels[0].mclk;
3186                 for (i = 1; i < ps->performance_level_count; i++) {
3187                         if (mclk < ps->performance_levels[i].mclk)
3188                                 mclk = ps->performance_levels[i].mclk;
3189                 }
3190                 for (i = 0; i < ps->performance_level_count; i++) {
3191                         ps->performance_levels[i].mclk = mclk;
3192                         ps->performance_levels[i].vddci = vddci;
3193                 }
3194         } else {
3195                 for (i = 1; i < ps->performance_level_count; i++) {
3196                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3197                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3198                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3199                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3200                 }
3201         }
3202
3203         for (i = 0; i < ps->performance_level_count; i++)
3204                 btc_adjust_clock_combinations(rdev, max_limits,
3205                                               &ps->performance_levels[i]);
3206
3207         for (i = 0; i < ps->performance_level_count; i++) {
3208                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3209                         ps->performance_levels[i].vddc = min_vce_voltage;
3210                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3211                                                    ps->performance_levels[i].sclk,
3212                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3213                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3214                                                    ps->performance_levels[i].mclk,
3215                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3216                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3217                                                    ps->performance_levels[i].mclk,
3218                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3219                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3220                                                    rdev->clock.current_dispclk,
3221                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3222         }
3223
3224         for (i = 0; i < ps->performance_level_count; i++) {
3225                 btc_apply_voltage_delta_rules(rdev,
3226                                               max_limits->vddc, max_limits->vddci,
3227                                               &ps->performance_levels[i].vddc,
3228                                               &ps->performance_levels[i].vddci);
3229         }
3230
3231         ps->dc_compatible = true;
3232         for (i = 0; i < ps->performance_level_count; i++) {
3233                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3234                         ps->dc_compatible = false;
3235         }
3236 }
3237
3238 #if 0
3239 static int si_read_smc_soft_register(struct radeon_device *rdev,
3240                                      u16 reg_offset, u32 *value)
3241 {
3242         struct si_power_info *si_pi = si_get_pi(rdev);
3243
3244         return si_read_smc_sram_dword(rdev,
3245                                       si_pi->soft_regs_start + reg_offset, value,
3246                                       si_pi->sram_end);
3247 }
3248 #endif
3249
3250 static int si_write_smc_soft_register(struct radeon_device *rdev,
3251                                       u16 reg_offset, u32 value)
3252 {
3253         struct si_power_info *si_pi = si_get_pi(rdev);
3254
3255         return si_write_smc_sram_dword(rdev,
3256                                        si_pi->soft_regs_start + reg_offset,
3257                                        value, si_pi->sram_end);
3258 }
3259
3260 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3261 {
3262         bool ret = false;
3263         u32 tmp, width, row, column, bank, density;
3264         bool is_memory_gddr5, is_special;
3265
3266         tmp = RREG32(MC_SEQ_MISC0);
3267         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3268         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3269                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3270
3271         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3272         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3273
3274         tmp = RREG32(MC_ARB_RAMCFG);
3275         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3276         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3277         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3278
3279         density = (1 << (row + column - 20 + bank)) * width;
3280
3281         if ((rdev->pdev->device == 0x6819) &&
3282             is_memory_gddr5 && is_special && (density == 0x400))
3283                 ret = true;
3284
3285         return ret;
3286 }
3287
3288 static void si_get_leakage_vddc(struct radeon_device *rdev)
3289 {
3290         struct si_power_info *si_pi = si_get_pi(rdev);
3291         u16 vddc, count = 0;
3292         int i, ret;
3293
3294         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3295                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3296
3297                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3298                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3299                         si_pi->leakage_voltage.entries[count].leakage_index =
3300                                 SISLANDS_LEAKAGE_INDEX0 + i;
3301                         count++;
3302                 }
3303         }
3304         si_pi->leakage_voltage.count = count;
3305 }
3306
3307 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3308                                                      u32 index, u16 *leakage_voltage)
3309 {
3310         struct si_power_info *si_pi = si_get_pi(rdev);
3311         int i;
3312
3313         if (leakage_voltage == NULL)
3314                 return -EINVAL;
3315
3316         if ((index & 0xff00) != 0xff00)
3317                 return -EINVAL;
3318
3319         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3320                 return -EINVAL;
3321
3322         if (index < SISLANDS_LEAKAGE_INDEX0)
3323                 return -EINVAL;
3324
3325         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3326                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3327                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3328                         return 0;
3329                 }
3330         }
3331         return -EAGAIN;
3332 }
3333
3334 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3335 {
3336         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3337         bool want_thermal_protection;
3338         enum radeon_dpm_event_src dpm_event_src;
3339
3340         switch (sources) {
3341         case 0:
3342         default:
3343                 want_thermal_protection = false;
3344                 break;
3345         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3346                 want_thermal_protection = true;
3347                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3348                 break;
3349         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3350                 want_thermal_protection = true;
3351                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3352                 break;
3353         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3354               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3355                 want_thermal_protection = true;
3356                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3357                 break;
3358         }
3359
3360         if (want_thermal_protection) {
3361                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3362                 if (pi->thermal_protection)
3363                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3364         } else {
3365                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3366         }
3367 }
3368
3369 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3370                                            enum radeon_dpm_auto_throttle_src source,
3371                                            bool enable)
3372 {
3373         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3374
3375         if (enable) {
3376                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3377                         pi->active_auto_throttle_sources |= 1 << source;
3378                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3379                 }
3380         } else {
3381                 if (pi->active_auto_throttle_sources & (1 << source)) {
3382                         pi->active_auto_throttle_sources &= ~(1 << source);
3383                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3384                 }
3385         }
3386 }
3387
3388 static void si_start_dpm(struct radeon_device *rdev)
3389 {
3390         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3391 }
3392
3393 static void si_stop_dpm(struct radeon_device *rdev)
3394 {
3395         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3396 }
3397
3398 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3399 {
3400         if (enable)
3401                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3402         else
3403                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3404
3405 }
3406
3407 #if 0
3408 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3409                                                u32 thermal_level)
3410 {
3411         PPSMC_Result ret;
3412
3413         if (thermal_level == 0) {
3414                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3415                 if (ret == PPSMC_Result_OK)
3416                         return 0;
3417                 else
3418                         return -EINVAL;
3419         }
3420         return 0;
3421 }
3422
3423 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3424 {
3425         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3426 }
3427 #endif
3428
3429 #if 0
3430 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3431 {
3432         if (ac_power)
3433                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3434                         0 : -EINVAL;
3435
3436         return 0;
3437 }
3438 #endif
3439
3440 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3441                                                       PPSMC_Msg msg, u32 parameter)
3442 {
3443         WREG32(SMC_SCRATCH0, parameter);
3444         return si_send_msg_to_smc(rdev, msg);
3445 }
3446
3447 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3448 {
3449         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3450                 return -EINVAL;
3451
3452         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3453                 0 : -EINVAL;
3454 }
3455
3456 int si_dpm_force_performance_level(struct radeon_device *rdev,
3457                                    enum radeon_dpm_forced_level level)
3458 {
3459         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3460         struct ni_ps *ps = ni_get_ps(rps);
3461         u32 levels = ps->performance_level_count;
3462
3463         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3464                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3465                         return -EINVAL;
3466
3467                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3468                         return -EINVAL;
3469         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3470                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3471                         return -EINVAL;
3472
3473                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3474                         return -EINVAL;
3475         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3476                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3477                         return -EINVAL;
3478
3479                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3480                         return -EINVAL;
3481         }
3482
3483         rdev->pm.dpm.forced_level = level;
3484
3485         return 0;
3486 }
3487
3488 #if 0
3489 static int si_set_boot_state(struct radeon_device *rdev)
3490 {
3491         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3492                 0 : -EINVAL;
3493 }
3494 #endif
3495
3496 static int si_set_sw_state(struct radeon_device *rdev)
3497 {
3498         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3499                 0 : -EINVAL;
3500 }
3501
3502 static int si_halt_smc(struct radeon_device *rdev)
3503 {
3504         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3505                 return -EINVAL;
3506
3507         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3508                 0 : -EINVAL;
3509 }
3510
3511 static int si_resume_smc(struct radeon_device *rdev)
3512 {
3513         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3514                 return -EINVAL;
3515
3516         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3517                 0 : -EINVAL;
3518 }
3519
3520 static void si_dpm_start_smc(struct radeon_device *rdev)
3521 {
3522         si_program_jump_on_start(rdev);
3523         si_start_smc(rdev);
3524         si_start_smc_clock(rdev);
3525 }
3526
3527 static void si_dpm_stop_smc(struct radeon_device *rdev)
3528 {
3529         si_reset_smc(rdev);
3530         si_stop_smc_clock(rdev);
3531 }
3532
3533 static int si_process_firmware_header(struct radeon_device *rdev)
3534 {
3535         struct si_power_info *si_pi = si_get_pi(rdev);
3536         u32 tmp;
3537         int ret;
3538
3539         ret = si_read_smc_sram_dword(rdev,
3540                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3541                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3542                                      &tmp, si_pi->sram_end);
3543         if (ret)
3544                 return ret;
3545
3546         si_pi->state_table_start = tmp;
3547
3548         ret = si_read_smc_sram_dword(rdev,
3549                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3550                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3551                                      &tmp, si_pi->sram_end);
3552         if (ret)
3553                 return ret;
3554
3555         si_pi->soft_regs_start = tmp;
3556
3557         ret = si_read_smc_sram_dword(rdev,
3558                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3559                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3560                                      &tmp, si_pi->sram_end);
3561         if (ret)
3562                 return ret;
3563
3564         si_pi->mc_reg_table_start = tmp;
3565
3566         ret = si_read_smc_sram_dword(rdev,
3567                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3568                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3569                                      &tmp, si_pi->sram_end);
3570         if (ret)
3571                 return ret;
3572
3573         si_pi->fan_table_start = tmp;
3574
3575         ret = si_read_smc_sram_dword(rdev,
3576                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3577                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3578                                      &tmp, si_pi->sram_end);
3579         if (ret)
3580                 return ret;
3581
3582         si_pi->arb_table_start = tmp;
3583
3584         ret = si_read_smc_sram_dword(rdev,
3585                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3586                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3587                                      &tmp, si_pi->sram_end);
3588         if (ret)
3589                 return ret;
3590
3591         si_pi->cac_table_start = tmp;
3592
3593         ret = si_read_smc_sram_dword(rdev,
3594                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3595                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3596                                      &tmp, si_pi->sram_end);
3597         if (ret)
3598                 return ret;
3599
3600         si_pi->dte_table_start = tmp;
3601
3602         ret = si_read_smc_sram_dword(rdev,
3603                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3604                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3605                                      &tmp, si_pi->sram_end);
3606         if (ret)
3607                 return ret;
3608
3609         si_pi->spll_table_start = tmp;
3610
3611         ret = si_read_smc_sram_dword(rdev,
3612                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3613                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3614                                      &tmp, si_pi->sram_end);
3615         if (ret)
3616                 return ret;
3617
3618         si_pi->papm_cfg_table_start = tmp;
3619
3620         return ret;
3621 }
3622
3623 static void si_read_clock_registers(struct radeon_device *rdev)
3624 {
3625         struct si_power_info *si_pi = si_get_pi(rdev);
3626
3627         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3628         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3629         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3630         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3631         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3632         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3633         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3634         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3635         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3636         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3637         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3638         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3639         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3640         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3641         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3642 }
3643
3644 static void si_enable_thermal_protection(struct radeon_device *rdev,
3645                                           bool enable)
3646 {
3647         if (enable)
3648                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3649         else
3650                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3651 }
3652
3653 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3654 {
3655         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3656 }
3657
3658 #if 0
3659 static int si_enter_ulp_state(struct radeon_device *rdev)
3660 {
3661         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3662
3663         udelay(25000);
3664
3665         return 0;
3666 }
3667
3668 static int si_exit_ulp_state(struct radeon_device *rdev)
3669 {
3670         int i;
3671
3672         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3673
3674         udelay(7000);
3675
3676         for (i = 0; i < rdev->usec_timeout; i++) {
3677                 if (RREG32(SMC_RESP_0) == 1)
3678                         break;
3679                 udelay(1000);
3680         }
3681
3682         return 0;
3683 }
3684 #endif
3685
3686 static int si_notify_smc_display_change(struct radeon_device *rdev,
3687                                      bool has_display)
3688 {
3689         PPSMC_Msg msg = has_display ?
3690                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3691
3692         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3693                 0 : -EINVAL;
3694 }
3695
3696 static void si_program_response_times(struct radeon_device *rdev)
3697 {
3698         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3699         u32 vddc_dly, acpi_dly, vbi_dly;
3700         u32 reference_clock;
3701
3702         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3703
3704         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3705         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3706
3707         if (voltage_response_time == 0)
3708                 voltage_response_time = 1000;
3709
3710         acpi_delay_time = 15000;
3711         vbi_time_out = 100000;
3712
3713         reference_clock = radeon_get_xclk(rdev);
3714
3715         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3716         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3717         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3718
3719         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3720         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3721         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3722         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3723 }
3724
3725 static void si_program_ds_registers(struct radeon_device *rdev)
3726 {
3727         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3728         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3729
3730         if (eg_pi->sclk_deep_sleep) {
3731                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3732                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3733                          ~AUTOSCALE_ON_SS_CLEAR);
3734         }
3735 }
3736
3737 static void si_program_display_gap(struct radeon_device *rdev)
3738 {
3739         u32 tmp, pipe;
3740         int i;
3741
3742         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3743         if (rdev->pm.dpm.new_active_crtc_count > 0)
3744                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3745         else
3746                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3747
3748         if (rdev->pm.dpm.new_active_crtc_count > 1)
3749                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3750         else
3751                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3752
3753         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3754
3755         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3756         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3757
3758         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3759             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3760                 /* find the first active crtc */
3761                 for (i = 0; i < rdev->num_crtc; i++) {
3762                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3763                                 break;
3764                 }
3765                 if (i == rdev->num_crtc)
3766                         pipe = 0;
3767                 else
3768                         pipe = i;
3769
3770                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3771                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3772                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3773         }
3774
3775         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3776          * This can be a problem on PowerXpress systems or if you want to use the card
3777          * for offscreen rendering or compute if there are no crtcs enabled.
3778          */
3779         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3780 }
3781
3782 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3783 {
3784         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3785
3786         if (enable) {
3787                 if (pi->sclk_ss)
3788                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3789         } else {
3790                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3791                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3792         }
3793 }
3794
3795 static void si_setup_bsp(struct radeon_device *rdev)
3796 {
3797         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3798         u32 xclk = radeon_get_xclk(rdev);
3799
3800         r600_calculate_u_and_p(pi->asi,
3801                                xclk,
3802                                16,
3803                                &pi->bsp,
3804                                &pi->bsu);
3805
3806         r600_calculate_u_and_p(pi->pasi,
3807                                xclk,
3808                                16,
3809                                &pi->pbsp,
3810                                &pi->pbsu);
3811
3812
3813         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3814         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3815
3816         WREG32(CG_BSP, pi->dsp);
3817 }
3818
3819 static void si_program_git(struct radeon_device *rdev)
3820 {
3821         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3822 }
3823
3824 static void si_program_tp(struct radeon_device *rdev)
3825 {
3826         int i;
3827         enum r600_td td = R600_TD_DFLT;
3828
3829         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3830                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3831
3832         if (td == R600_TD_AUTO)
3833                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3834         else
3835                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3836
3837         if (td == R600_TD_UP)
3838                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3839
3840         if (td == R600_TD_DOWN)
3841                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3842 }
3843
3844 static void si_program_tpp(struct radeon_device *rdev)
3845 {
3846         WREG32(CG_TPC, R600_TPC_DFLT);
3847 }
3848
3849 static void si_program_sstp(struct radeon_device *rdev)
3850 {
3851         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3852 }
3853
3854 static void si_enable_display_gap(struct radeon_device *rdev)
3855 {
3856         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3857
3858         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3859         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3860                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3861
3862         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3863         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3864                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3865         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3866 }
3867
3868 static void si_program_vc(struct radeon_device *rdev)
3869 {
3870         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3871
3872         WREG32(CG_FTV, pi->vrc);
3873 }
3874
3875 static void si_clear_vc(struct radeon_device *rdev)
3876 {
3877         WREG32(CG_FTV, 0);
3878 }
3879
3880 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3881 {
3882         u8 mc_para_index;
3883
3884         if (memory_clock < 10000)
3885                 mc_para_index = 0;
3886         else if (memory_clock >= 80000)
3887                 mc_para_index = 0x0f;
3888         else
3889                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3890         return mc_para_index;
3891 }
3892
3893 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3894 {
3895         u8 mc_para_index;
3896
3897         if (strobe_mode) {
3898                 if (memory_clock < 12500)
3899                         mc_para_index = 0x00;
3900                 else if (memory_clock > 47500)
3901                         mc_para_index = 0x0f;
3902                 else
3903                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3904         } else {
3905                 if (memory_clock < 65000)
3906                         mc_para_index = 0x00;
3907                 else if (memory_clock > 135000)
3908                         mc_para_index = 0x0f;
3909                 else
3910                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3911         }
3912         return mc_para_index;
3913 }
3914
3915 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3916 {
3917         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3918         bool strobe_mode = false;
3919         u8 result = 0;
3920
3921         if (mclk <= pi->mclk_strobe_mode_threshold)
3922                 strobe_mode = true;
3923
3924         if (pi->mem_gddr5)
3925                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3926         else
3927                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3928
3929         if (strobe_mode)
3930                 result |= SISLANDS_SMC_STROBE_ENABLE;
3931
3932         return result;
3933 }
3934
3935 static int si_upload_firmware(struct radeon_device *rdev)
3936 {
3937         struct si_power_info *si_pi = si_get_pi(rdev);
3938         int ret;
3939
3940         si_reset_smc(rdev);
3941         si_stop_smc_clock(rdev);
3942
3943         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3944
3945         return ret;
3946 }
3947
3948 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3949                                               const struct atom_voltage_table *table,
3950                                               const struct radeon_phase_shedding_limits_table *limits)
3951 {
3952         u32 data, num_bits, num_levels;
3953
3954         if ((table == NULL) || (limits == NULL))
3955                 return false;
3956
3957         data = table->mask_low;
3958
3959         num_bits = hweight32(data);
3960
3961         if (num_bits == 0)
3962                 return false;
3963
3964         num_levels = (1 << num_bits);
3965
3966         if (table->count != num_levels)
3967                 return false;
3968
3969         if (limits->count != (num_levels - 1))
3970                 return false;
3971
3972         return true;
3973 }
3974
3975 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3976                                               u32 max_voltage_steps,
3977                                               struct atom_voltage_table *voltage_table)
3978 {
3979         unsigned int i, diff;
3980
3981         if (voltage_table->count <= max_voltage_steps)
3982                 return;
3983
3984         diff = voltage_table->count - max_voltage_steps;
3985
3986         for (i= 0; i < max_voltage_steps; i++)
3987                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3988
3989         voltage_table->count = max_voltage_steps;
3990 }
3991
3992 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3993                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3994                                      struct atom_voltage_table *voltage_table)
3995 {
3996         u32 i;
3997
3998         if (voltage_dependency_table == NULL)
3999                 return -EINVAL;
4000
4001         voltage_table->mask_low = 0;
4002         voltage_table->phase_delay = 0;
4003
4004         voltage_table->count = voltage_dependency_table->count;
4005         for (i = 0; i < voltage_table->count; i++) {
4006                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4007                 voltage_table->entries[i].smio_low = 0;
4008         }
4009
4010         return 0;
4011 }
4012
4013 static int si_construct_voltage_tables(struct radeon_device *rdev)
4014 {
4015         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4016         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4017         struct si_power_info *si_pi = si_get_pi(rdev);
4018         int ret;
4019
4020         if (pi->voltage_control) {
4021                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4022                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4023                 if (ret)
4024                         return ret;
4025
4026                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4027                         si_trim_voltage_table_to_fit_state_table(rdev,
4028                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4029                                                                  &eg_pi->vddc_voltage_table);
4030         } else if (si_pi->voltage_control_svi2) {
4031                 ret = si_get_svi2_voltage_table(rdev,
4032                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4033                                                 &eg_pi->vddc_voltage_table);
4034                 if (ret)
4035                         return ret;
4036         } else {
4037                 return -EINVAL;
4038         }
4039
4040         if (eg_pi->vddci_control) {
4041                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
4042                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4043                 if (ret)
4044                         return ret;
4045
4046                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4047                         si_trim_voltage_table_to_fit_state_table(rdev,
4048                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4049                                                                  &eg_pi->vddci_voltage_table);
4050         }
4051         if (si_pi->vddci_control_svi2) {
4052                 ret = si_get_svi2_voltage_table(rdev,
4053                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4054                                                 &eg_pi->vddci_voltage_table);
4055                 if (ret)
4056                         return ret;
4057         }
4058
4059         if (pi->mvdd_control) {
4060                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4061                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4062
4063                 if (ret) {
4064                         pi->mvdd_control = false;
4065                         return ret;
4066                 }
4067
4068                 if (si_pi->mvdd_voltage_table.count == 0) {
4069                         pi->mvdd_control = false;
4070                         return -EINVAL;
4071                 }
4072
4073                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4074                         si_trim_voltage_table_to_fit_state_table(rdev,
4075                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4076                                                                  &si_pi->mvdd_voltage_table);
4077         }
4078
4079         if (si_pi->vddc_phase_shed_control) {
4080                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4081                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4082                 if (ret)
4083                         si_pi->vddc_phase_shed_control = false;
4084
4085                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4086                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4087                         si_pi->vddc_phase_shed_control = false;
4088         }
4089
4090         return 0;
4091 }
4092
4093 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4094                                           const struct atom_voltage_table *voltage_table,
4095                                           SISLANDS_SMC_STATETABLE *table)
4096 {
4097         unsigned int i;
4098
4099         for (i = 0; i < voltage_table->count; i++)
4100                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4101 }
4102
4103 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4104                                           SISLANDS_SMC_STATETABLE *table)
4105 {
4106         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4107         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4108         struct si_power_info *si_pi = si_get_pi(rdev);
4109         u8 i;
4110
4111         if (si_pi->voltage_control_svi2) {
4112                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4113                         si_pi->svc_gpio_id);
4114                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4115                         si_pi->svd_gpio_id);
4116                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4117                                            2);
4118         } else {
4119                 if (eg_pi->vddc_voltage_table.count) {
4120                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4121                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4122                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4123
4124                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4125                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4126                                         table->maxVDDCIndexInPPTable = i;
4127                                         break;
4128                                 }
4129                         }
4130                 }
4131
4132                 if (eg_pi->vddci_voltage_table.count) {
4133                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4134
4135                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4136                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4137                 }
4138
4139
4140                 if (si_pi->mvdd_voltage_table.count) {
4141                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4142
4143                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4144                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4145                 }
4146
4147                 if (si_pi->vddc_phase_shed_control) {
4148                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4149                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4150                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4151
4152                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4153                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4154
4155                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4156                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4157                         } else {
4158                                 si_pi->vddc_phase_shed_control = false;
4159                         }
4160                 }
4161         }
4162
4163         return 0;
4164 }
4165
4166 static int si_populate_voltage_value(struct radeon_device *rdev,
4167                                      const struct atom_voltage_table *table,
4168                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4169 {
4170         unsigned int i;
4171
4172         for (i = 0; i < table->count; i++) {
4173                 if (value <= table->entries[i].value) {
4174                         voltage->index = (u8)i;
4175                         voltage->value = cpu_to_be16(table->entries[i].value);
4176                         break;
4177                 }
4178         }
4179
4180         if (i >= table->count)
4181                 return -EINVAL;
4182
4183         return 0;
4184 }
4185
4186 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4187                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4188 {
4189         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4190         struct si_power_info *si_pi = si_get_pi(rdev);
4191
4192         if (pi->mvdd_control) {
4193                 if (mclk <= pi->mvdd_split_frequency)
4194                         voltage->index = 0;
4195                 else
4196                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4197
4198                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4199         }
4200         return 0;
4201 }
4202
4203 static int si_get_std_voltage_value(struct radeon_device *rdev,
4204                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4205                                     u16 *std_voltage)
4206 {
4207         u16 v_index;
4208         bool voltage_found = false;
4209         *std_voltage = be16_to_cpu(voltage->value);
4210
4211         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4212                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4213                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4214                                 return -EINVAL;
4215
4216                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4217                                 if (be16_to_cpu(voltage->value) ==
4218                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4219                                         voltage_found = true;
4220                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4221                                                 *std_voltage =
4222                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4223                                         else
4224                                                 *std_voltage =
4225                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4226                                         break;
4227                                 }
4228                         }
4229
4230                         if (!voltage_found) {
4231                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4232                                         if (be16_to_cpu(voltage->value) <=
4233                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4234                                                 voltage_found = true;
4235                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4236                                                         *std_voltage =
4237                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4238                                                 else
4239                                                         *std_voltage =
4240                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4241                                                 break;
4242                                         }
4243                                 }
4244                         }
4245                 } else {
4246                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4247                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4248                 }
4249         }
4250
4251         return 0;
4252 }
4253
4254 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4255                                          u16 value, u8 index,
4256                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4257 {
4258         voltage->index = index;
4259         voltage->value = cpu_to_be16(value);
4260
4261         return 0;
4262 }
4263
4264 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4265                                             const struct radeon_phase_shedding_limits_table *limits,
4266                                             u16 voltage, u32 sclk, u32 mclk,
4267                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4268 {
4269         unsigned int i;
4270
4271         for (i = 0; i < limits->count; i++) {
4272                 if ((voltage <= limits->entries[i].voltage) &&
4273                     (sclk <= limits->entries[i].sclk) &&
4274                     (mclk <= limits->entries[i].mclk))
4275                         break;
4276         }
4277
4278         smc_voltage->phase_settings = (u8)i;
4279
4280         return 0;
4281 }
4282
4283 static int si_init_arb_table_index(struct radeon_device *rdev)
4284 {
4285         struct si_power_info *si_pi = si_get_pi(rdev);
4286         u32 tmp;
4287         int ret;
4288
4289         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4290         if (ret)
4291                 return ret;
4292
4293         tmp &= 0x00FFFFFF;
4294         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4295
4296         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4297 }
4298
4299 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4300 {
4301         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4302 }
4303
4304 static int si_reset_to_default(struct radeon_device *rdev)
4305 {
4306         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4307                 0 : -EINVAL;
4308 }
4309
4310 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4311 {
4312         struct si_power_info *si_pi = si_get_pi(rdev);
4313         u32 tmp;
4314         int ret;
4315
4316         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4317                                      &tmp, si_pi->sram_end);
4318         if (ret)
4319                 return ret;
4320
4321         tmp = (tmp >> 24) & 0xff;
4322
4323         if (tmp == MC_CG_ARB_FREQ_F0)
4324                 return 0;
4325
4326         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4327 }
4328
4329 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4330                                             u32 engine_clock)
4331 {
4332         u32 dram_rows;
4333         u32 dram_refresh_rate;
4334         u32 mc_arb_rfsh_rate;
4335         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4336
4337         if (tmp >= 4)
4338                 dram_rows = 16384;
4339         else
4340                 dram_rows = 1 << (tmp + 10);
4341
4342         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4343         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4344
4345         return mc_arb_rfsh_rate;
4346 }
4347
4348 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4349                                                 struct rv7xx_pl *pl,
4350                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4351 {
4352         u32 dram_timing;
4353         u32 dram_timing2;
4354         u32 burst_time;
4355
4356         arb_regs->mc_arb_rfsh_rate =
4357                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4358
4359         radeon_atom_set_engine_dram_timings(rdev,
4360                                             pl->sclk,
4361                                             pl->mclk);
4362
4363         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4364         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4365         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4366
4367         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4368         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4369         arb_regs->mc_arb_burst_time = (u8)burst_time;
4370
4371         return 0;
4372 }
4373
4374 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4375                                                   struct radeon_ps *radeon_state,
4376                                                   unsigned int first_arb_set)
4377 {
4378         struct si_power_info *si_pi = si_get_pi(rdev);
4379         struct ni_ps *state = ni_get_ps(radeon_state);
4380         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4381         int i, ret = 0;
4382
4383         for (i = 0; i < state->performance_level_count; i++) {
4384                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4385                 if (ret)
4386                         break;
4387                 ret = si_copy_bytes_to_smc(rdev,
4388                                            si_pi->arb_table_start +
4389                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4390                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4391                                            (u8 *)&arb_regs,
4392                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4393                                            si_pi->sram_end);
4394                 if (ret)
4395                         break;
4396         }
4397
4398         return ret;
4399 }
4400
4401 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4402                                                struct radeon_ps *radeon_new_state)
4403 {
4404         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4405                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4406 }
4407
4408 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4409                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4410 {
4411         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4412         struct si_power_info *si_pi = si_get_pi(rdev);
4413
4414         if (pi->mvdd_control)
4415                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4416                                                  si_pi->mvdd_bootup_value, voltage);
4417
4418         return 0;
4419 }
4420
4421 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4422                                          struct radeon_ps *radeon_initial_state,
4423                                          SISLANDS_SMC_STATETABLE *table)
4424 {
4425         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4426         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4427         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4428         struct si_power_info *si_pi = si_get_pi(rdev);
4429         u32 reg;
4430         int ret;
4431
4432         table->initialState.levels[0].mclk.vDLL_CNTL =
4433                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4434         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4435                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4436         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4437                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4438         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4439                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4440         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4441                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4442         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4443                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4444         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4445                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4446         table->initialState.levels[0].mclk.vMPLL_SS =
4447                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4448         table->initialState.levels[0].mclk.vMPLL_SS2 =
4449                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4450
4451         table->initialState.levels[0].mclk.mclk_value =
4452                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4453
4454         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4455                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4456         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4457                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4458         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4459                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4460         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4461                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4462         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4463                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4464         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4465                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4466
4467         table->initialState.levels[0].sclk.sclk_value =
4468                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4469
4470         table->initialState.levels[0].arbRefreshState =
4471                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4472
4473         table->initialState.levels[0].ACIndex = 0;
4474
4475         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4476                                         initial_state->performance_levels[0].vddc,
4477                                         &table->initialState.levels[0].vddc);
4478
4479         if (!ret) {
4480                 u16 std_vddc;
4481
4482                 ret = si_get_std_voltage_value(rdev,
4483                                                &table->initialState.levels[0].vddc,
4484                                                &std_vddc);
4485                 if (!ret)
4486                         si_populate_std_voltage_value(rdev, std_vddc,
4487                                                       table->initialState.levels[0].vddc.index,
4488                                                       &table->initialState.levels[0].std_vddc);
4489         }
4490
4491         if (eg_pi->vddci_control)
4492                 si_populate_voltage_value(rdev,
4493                                           &eg_pi->vddci_voltage_table,
4494                                           initial_state->performance_levels[0].vddci,
4495                                           &table->initialState.levels[0].vddci);
4496
4497         if (si_pi->vddc_phase_shed_control)
4498                 si_populate_phase_shedding_value(rdev,
4499                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4500                                                  initial_state->performance_levels[0].vddc,
4501                                                  initial_state->performance_levels[0].sclk,
4502                                                  initial_state->performance_levels[0].mclk,
4503                                                  &table->initialState.levels[0].vddc);
4504
4505         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4506
4507         reg = CG_R(0xffff) | CG_L(0);
4508         table->initialState.levels[0].aT = cpu_to_be32(reg);
4509
4510         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4511
4512         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4513
4514         if (pi->mem_gddr5) {
4515                 table->initialState.levels[0].strobeMode =
4516                         si_get_strobe_mode_settings(rdev,
4517                                                     initial_state->performance_levels[0].mclk);
4518
4519                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4520                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4521                 else
4522                         table->initialState.levels[0].mcFlags =  0;
4523         }
4524
4525         table->initialState.levelCount = 1;
4526
4527         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4528
4529         table->initialState.levels[0].dpm2.MaxPS = 0;
4530         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4531         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4532         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4533         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4534
4535         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4536         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4537
4538         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4539         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4540
4541         return 0;
4542 }
4543
4544 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4545                                       SISLANDS_SMC_STATETABLE *table)
4546 {
4547         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4548         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4549         struct si_power_info *si_pi = si_get_pi(rdev);
4550         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4551         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4552         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4553         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4554         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4555         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4556         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4557         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4558         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4559         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4560         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4561         u32 reg;
4562         int ret;
4563
4564         table->ACPIState = table->initialState;
4565
4566         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4567
4568         if (pi->acpi_vddc) {
4569                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4570                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4571                 if (!ret) {
4572                         u16 std_vddc;
4573
4574                         ret = si_get_std_voltage_value(rdev,
4575                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4576                         if (!ret)
4577                                 si_populate_std_voltage_value(rdev, std_vddc,
4578                                                               table->ACPIState.levels[0].vddc.index,
4579                                                               &table->ACPIState.levels[0].std_vddc);
4580                 }
4581                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4582
4583                 if (si_pi->vddc_phase_shed_control) {
4584                         si_populate_phase_shedding_value(rdev,
4585                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4586                                                          pi->acpi_vddc,
4587                                                          0,
4588                                                          0,
4589                                                          &table->ACPIState.levels[0].vddc);
4590                 }
4591         } else {
4592                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4593                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4594                 if (!ret) {
4595                         u16 std_vddc;
4596
4597                         ret = si_get_std_voltage_value(rdev,
4598                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4599
4600                         if (!ret)
4601                                 si_populate_std_voltage_value(rdev, std_vddc,
4602                                                               table->ACPIState.levels[0].vddc.index,
4603                                                               &table->ACPIState.levels[0].std_vddc);
4604                 }
4605                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4606                                                                                     si_pi->sys_pcie_mask,
4607                                                                                     si_pi->boot_pcie_gen,
4608                                                                                     RADEON_PCIE_GEN1);
4609
4610                 if (si_pi->vddc_phase_shed_control)
4611                         si_populate_phase_shedding_value(rdev,
4612                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4613                                                          pi->min_vddc_in_table,
4614                                                          0,
4615                                                          0,
4616                                                          &table->ACPIState.levels[0].vddc);
4617         }
4618
4619         if (pi->acpi_vddc) {
4620                 if (eg_pi->acpi_vddci)
4621                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4622                                                   eg_pi->acpi_vddci,
4623                                                   &table->ACPIState.levels[0].vddci);
4624         }
4625
4626         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4627         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4628
4629         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4630
4631         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4632         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4633
4634         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4635                 cpu_to_be32(dll_cntl);
4636         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4637                 cpu_to_be32(mclk_pwrmgt_cntl);
4638         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4639                 cpu_to_be32(mpll_ad_func_cntl);
4640         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4641                 cpu_to_be32(mpll_dq_func_cntl);
4642         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4643                 cpu_to_be32(mpll_func_cntl);
4644         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4645                 cpu_to_be32(mpll_func_cntl_1);
4646         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4647                 cpu_to_be32(mpll_func_cntl_2);
4648         table->ACPIState.levels[0].mclk.vMPLL_SS =
4649                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4650         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4651                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4652
4653         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4654                 cpu_to_be32(spll_func_cntl);
4655         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4656                 cpu_to_be32(spll_func_cntl_2);
4657         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4658                 cpu_to_be32(spll_func_cntl_3);
4659         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4660                 cpu_to_be32(spll_func_cntl_4);
4661
4662         table->ACPIState.levels[0].mclk.mclk_value = 0;
4663         table->ACPIState.levels[0].sclk.sclk_value = 0;
4664
4665         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4666
4667         if (eg_pi->dynamic_ac_timing)
4668                 table->ACPIState.levels[0].ACIndex = 0;
4669
4670         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4671         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4672         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4673         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4674         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4675
4676         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4677         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4678
4679         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4680         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4681
4682         return 0;
4683 }
4684
4685 static int si_populate_ulv_state(struct radeon_device *rdev,
4686                                  SISLANDS_SMC_SWSTATE *state)
4687 {
4688         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4689         struct si_power_info *si_pi = si_get_pi(rdev);
4690         struct si_ulv_param *ulv = &si_pi->ulv;
4691         u32 sclk_in_sr = 1350; /* ??? */
4692         int ret;
4693
4694         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4695                                             &state->levels[0]);
4696         if (!ret) {
4697                 if (eg_pi->sclk_deep_sleep) {
4698                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4699                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4700                         else
4701                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4702                 }
4703                 if (ulv->one_pcie_lane_in_ulv)
4704                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4705                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4706                 state->levels[0].ACIndex = 1;
4707                 state->levels[0].std_vddc = state->levels[0].vddc;
4708                 state->levelCount = 1;
4709
4710                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4711         }
4712
4713         return ret;
4714 }
4715
4716 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4717 {
4718         struct si_power_info *si_pi = si_get_pi(rdev);
4719         struct si_ulv_param *ulv = &si_pi->ulv;
4720         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4721         int ret;
4722
4723         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4724                                                    &arb_regs);
4725         if (ret)
4726                 return ret;
4727
4728         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4729                                    ulv->volt_change_delay);
4730
4731         ret = si_copy_bytes_to_smc(rdev,
4732                                    si_pi->arb_table_start +
4733                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4734                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4735                                    (u8 *)&arb_regs,
4736                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4737                                    si_pi->sram_end);
4738
4739         return ret;
4740 }
4741
4742 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4743 {
4744         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4745
4746         pi->mvdd_split_frequency = 30000;
4747 }
4748
4749 static int si_init_smc_table(struct radeon_device *rdev)
4750 {
4751         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4752         struct si_power_info *si_pi = si_get_pi(rdev);
4753         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4754         const struct si_ulv_param *ulv = &si_pi->ulv;
4755         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4756         int ret;
4757         u32 lane_width;
4758         u32 vr_hot_gpio;
4759
4760         si_populate_smc_voltage_tables(rdev, table);
4761
4762         switch (rdev->pm.int_thermal_type) {
4763         case THERMAL_TYPE_SI:
4764         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4765                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4766                 break;
4767         case THERMAL_TYPE_NONE:
4768                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4769                 break;
4770         default:
4771                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4772                 break;
4773         }
4774
4775         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4776                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4777
4778         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4779                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4780                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4781         }
4782
4783         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4784                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4785
4786         if (pi->mem_gddr5)
4787                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4788
4789         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4790                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4791
4792         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4793                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4794                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4795                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4796                                            vr_hot_gpio);
4797         }
4798
4799         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4800         if (ret)
4801                 return ret;
4802
4803         ret = si_populate_smc_acpi_state(rdev, table);
4804         if (ret)
4805                 return ret;
4806
4807         table->driverState = table->initialState;
4808
4809         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4810                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4811         if (ret)
4812                 return ret;
4813
4814         if (ulv->supported && ulv->pl.vddc) {
4815                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4816                 if (ret)
4817                         return ret;
4818
4819                 ret = si_program_ulv_memory_timing_parameters(rdev);
4820                 if (ret)
4821                         return ret;
4822
4823                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4824                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4825
4826                 lane_width = radeon_get_pcie_lanes(rdev);
4827                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4828         } else {
4829                 table->ULVState = table->initialState;
4830         }
4831
4832         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4833                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4834                                     si_pi->sram_end);
4835 }
4836
4837 static int si_calculate_sclk_params(struct radeon_device *rdev,
4838                                     u32 engine_clock,
4839                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4840 {
4841         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4842         struct si_power_info *si_pi = si_get_pi(rdev);
4843         struct atom_clock_dividers dividers;
4844         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4845         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4846         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4847         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4848         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4849         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4850         u64 tmp;
4851         u32 reference_clock = rdev->clock.spll.reference_freq;
4852         u32 reference_divider;
4853         u32 fbdiv;
4854         int ret;
4855
4856         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4857                                              engine_clock, false, &dividers);
4858         if (ret)
4859                 return ret;
4860
4861         reference_divider = 1 + dividers.ref_div;
4862
4863         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4864         do_div(tmp, reference_clock);
4865         fbdiv = (u32) tmp;
4866
4867         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4868         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4869         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4870
4871         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4872         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4873
4874         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4875         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4876         spll_func_cntl_3 |= SPLL_DITHEN;
4877
4878         if (pi->sclk_ss) {
4879                 struct radeon_atom_ss ss;
4880                 u32 vco_freq = engine_clock * dividers.post_div;
4881
4882                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4883                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4884                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4885                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4886
4887                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4888                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4889                         cg_spll_spread_spectrum |= SSEN;
4890
4891                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4892                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4893                 }
4894         }
4895
4896         sclk->sclk_value = engine_clock;
4897         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4898         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4899         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4900         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4901         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4902         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4903
4904         return 0;
4905 }
4906
4907 static int si_populate_sclk_value(struct radeon_device *rdev,
4908                                   u32 engine_clock,
4909                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4910 {
4911         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4912         int ret;
4913
4914         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4915         if (!ret) {
4916                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4917                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4918                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4919                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4920                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4921                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4922                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4923         }
4924
4925         return ret;
4926 }
4927
4928 static int si_populate_mclk_value(struct radeon_device *rdev,
4929                                   u32 engine_clock,
4930                                   u32 memory_clock,
4931                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4932                                   bool strobe_mode,
4933                                   bool dll_state_on)
4934 {
4935         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4936         struct si_power_info *si_pi = si_get_pi(rdev);
4937         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4938         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4939         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4940         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4941         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4942         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4943         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4944         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4945         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4946         struct atom_mpll_param mpll_param;
4947         int ret;
4948
4949         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4950         if (ret)
4951                 return ret;
4952
4953         mpll_func_cntl &= ~BWCTRL_MASK;
4954         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4955
4956         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4957         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4958                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4959
4960         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4961         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4962
4963         if (pi->mem_gddr5) {
4964                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4965                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4966                         YCLK_POST_DIV(mpll_param.post_div);
4967         }
4968
4969         if (pi->mclk_ss) {
4970                 struct radeon_atom_ss ss;
4971                 u32 freq_nom;
4972                 u32 tmp;
4973                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4974
4975                 if (pi->mem_gddr5)
4976                         freq_nom = memory_clock * 4;
4977                 else
4978                         freq_nom = memory_clock * 2;
4979
4980                 tmp = freq_nom / reference_clock;
4981                 tmp = tmp * tmp;
4982                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4983                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4984                         u32 clks = reference_clock * 5 / ss.rate;
4985                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4986
4987                         mpll_ss1 &= ~CLKV_MASK;
4988                         mpll_ss1 |= CLKV(clkv);
4989
4990                         mpll_ss2 &= ~CLKS_MASK;
4991                         mpll_ss2 |= CLKS(clks);
4992                 }
4993         }
4994
4995         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4996         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4997
4998         if (dll_state_on)
4999                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5000         else
5001                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5002
5003         mclk->mclk_value = cpu_to_be32(memory_clock);
5004         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5005         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5006         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5007         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5008         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5009         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5010         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5011         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5012         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5013
5014         return 0;
5015 }
5016
5017 static void si_populate_smc_sp(struct radeon_device *rdev,
5018                                struct radeon_ps *radeon_state,
5019                                SISLANDS_SMC_SWSTATE *smc_state)
5020 {
5021         struct ni_ps *ps = ni_get_ps(radeon_state);
5022         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5023         int i;
5024
5025         for (i = 0; i < ps->performance_level_count - 1; i++)
5026                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5027
5028         smc_state->levels[ps->performance_level_count - 1].bSP =
5029                 cpu_to_be32(pi->psp);
5030 }
5031
5032 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
5033                                          struct rv7xx_pl *pl,
5034                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5035 {
5036         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5037         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5038         struct si_power_info *si_pi = si_get_pi(rdev);
5039         int ret;
5040         bool dll_state_on;
5041         u16 std_vddc;
5042         bool gmc_pg = false;
5043
5044         if (eg_pi->pcie_performance_request &&
5045             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5046                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5047         else
5048                 level->gen2PCIE = (u8)pl->pcie_gen;
5049
5050         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5051         if (ret)
5052                 return ret;
5053
5054         level->mcFlags =  0;
5055
5056         if (pi->mclk_stutter_mode_threshold &&
5057             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5058             !eg_pi->uvd_enabled &&
5059             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5060             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5061                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5062
5063                 if (gmc_pg)
5064                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5065         }
5066
5067         if (pi->mem_gddr5) {
5068                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5069                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5070
5071                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5072                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5073
5074                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5075
5076                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5077                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5078                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5079                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5080                         else
5081                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5082                 } else {
5083                         dll_state_on = false;
5084                 }
5085         } else {
5086                 level->strobeMode = si_get_strobe_mode_settings(rdev,
5087                                                                 pl->mclk);
5088
5089                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5090         }
5091
5092         ret = si_populate_mclk_value(rdev,
5093                                      pl->sclk,
5094                                      pl->mclk,
5095                                      &level->mclk,
5096                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5097         if (ret)
5098                 return ret;
5099
5100         ret = si_populate_voltage_value(rdev,
5101                                         &eg_pi->vddc_voltage_table,
5102                                         pl->vddc, &level->vddc);
5103         if (ret)
5104                 return ret;
5105
5106
5107         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5108         if (ret)
5109                 return ret;
5110
5111         ret = si_populate_std_voltage_value(rdev, std_vddc,
5112                                             level->vddc.index, &level->std_vddc);
5113         if (ret)
5114                 return ret;
5115
5116         if (eg_pi->vddci_control) {
5117                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5118                                                 pl->vddci, &level->vddci);
5119                 if (ret)
5120                         return ret;
5121         }
5122
5123         if (si_pi->vddc_phase_shed_control) {
5124                 ret = si_populate_phase_shedding_value(rdev,
5125                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5126                                                        pl->vddc,
5127                                                        pl->sclk,
5128                                                        pl->mclk,
5129                                                        &level->vddc);
5130                 if (ret)
5131                         return ret;
5132         }
5133
5134         level->MaxPoweredUpCU = si_pi->max_cu;
5135
5136         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5137
5138         return ret;
5139 }
5140
5141 static int si_populate_smc_t(struct radeon_device *rdev,
5142                              struct radeon_ps *radeon_state,
5143                              SISLANDS_SMC_SWSTATE *smc_state)
5144 {
5145         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5146         struct ni_ps *state = ni_get_ps(radeon_state);
5147         u32 a_t;
5148         u32 t_l, t_h;
5149         u32 high_bsp;
5150         int i, ret;
5151
5152         if (state->performance_level_count >= 9)
5153                 return -EINVAL;
5154
5155         if (state->performance_level_count < 2) {
5156                 a_t = CG_R(0xffff) | CG_L(0);
5157                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5158                 return 0;
5159         }
5160
5161         smc_state->levels[0].aT = cpu_to_be32(0);
5162
5163         for (i = 0; i <= state->performance_level_count - 2; i++) {
5164                 ret = r600_calculate_at(
5165                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5166                         100 * R600_AH_DFLT,
5167                         state->performance_levels[i + 1].sclk,
5168                         state->performance_levels[i].sclk,
5169                         &t_l,
5170                         &t_h);
5171
5172                 if (ret) {
5173                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5174                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5175                 }
5176
5177                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5178                 a_t |= CG_R(t_l * pi->bsp / 20000);
5179                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5180
5181                 high_bsp = (i == state->performance_level_count - 2) ?
5182                         pi->pbsp : pi->bsp;
5183                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5184                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5185         }
5186
5187         return 0;
5188 }
5189
5190 static int si_disable_ulv(struct radeon_device *rdev)
5191 {
5192         struct si_power_info *si_pi = si_get_pi(rdev);
5193         struct si_ulv_param *ulv = &si_pi->ulv;
5194
5195         if (ulv->supported)
5196                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5197                         0 : -EINVAL;
5198
5199         return 0;
5200 }
5201
5202 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5203                                        struct radeon_ps *radeon_state)
5204 {
5205         const struct si_power_info *si_pi = si_get_pi(rdev);
5206         const struct si_ulv_param *ulv = &si_pi->ulv;
5207         const struct ni_ps *state = ni_get_ps(radeon_state);
5208         int i;
5209
5210         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5211                 return false;
5212
5213         /* XXX validate against display requirements! */
5214
5215         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5216                 if (rdev->clock.current_dispclk <=
5217                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5218                         if (ulv->pl.vddc <
5219                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5220                                 return false;
5221                 }
5222         }
5223
5224         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5225                 return false;
5226
5227         return true;
5228 }
5229
5230 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5231                                                        struct radeon_ps *radeon_new_state)
5232 {
5233         const struct si_power_info *si_pi = si_get_pi(rdev);
5234         const struct si_ulv_param *ulv = &si_pi->ulv;
5235
5236         if (ulv->supported) {
5237                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5238                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5239                                 0 : -EINVAL;
5240         }
5241         return 0;
5242 }
5243
5244 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5245                                          struct radeon_ps *radeon_state,
5246                                          SISLANDS_SMC_SWSTATE *smc_state)
5247 {
5248         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5249         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5250         struct si_power_info *si_pi = si_get_pi(rdev);
5251         struct ni_ps *state = ni_get_ps(radeon_state);
5252         int i, ret;
5253         u32 threshold;
5254         u32 sclk_in_sr = 1350; /* ??? */
5255
5256         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5257                 return -EINVAL;
5258
5259         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5260
5261         if (radeon_state->vclk && radeon_state->dclk) {
5262                 eg_pi->uvd_enabled = true;
5263                 if (eg_pi->smu_uvd_hs)
5264                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5265         } else {
5266                 eg_pi->uvd_enabled = false;
5267         }
5268
5269         if (state->dc_compatible)
5270                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5271
5272         smc_state->levelCount = 0;
5273         for (i = 0; i < state->performance_level_count; i++) {
5274                 if (eg_pi->sclk_deep_sleep) {
5275                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5276                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5277                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5278                                 else
5279                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5280                         }
5281                 }
5282
5283                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5284                                                     &smc_state->levels[i]);
5285                 smc_state->levels[i].arbRefreshState =
5286                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5287
5288                 if (ret)
5289                         return ret;
5290
5291                 if (ni_pi->enable_power_containment)
5292                         smc_state->levels[i].displayWatermark =
5293                                 (state->performance_levels[i].sclk < threshold) ?
5294                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5295                 else
5296                         smc_state->levels[i].displayWatermark = (i < 2) ?
5297                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5298
5299                 if (eg_pi->dynamic_ac_timing)
5300                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5301                 else
5302                         smc_state->levels[i].ACIndex = 0;
5303
5304                 smc_state->levelCount++;
5305         }
5306
5307         si_write_smc_soft_register(rdev,
5308                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5309                                    threshold / 512);
5310
5311         si_populate_smc_sp(rdev, radeon_state, smc_state);
5312
5313         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5314         if (ret)
5315                 ni_pi->enable_power_containment = false;
5316
5317         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5318         if (ret)
5319                 ni_pi->enable_sq_ramping = false;
5320
5321         return si_populate_smc_t(rdev, radeon_state, smc_state);
5322 }
5323
5324 static int si_upload_sw_state(struct radeon_device *rdev,
5325                               struct radeon_ps *radeon_new_state)
5326 {
5327         struct si_power_info *si_pi = si_get_pi(rdev);
5328         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5329         int ret;
5330         u32 address = si_pi->state_table_start +
5331                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5332         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5333                 ((new_state->performance_level_count - 1) *
5334                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5335         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5336
5337         memset(smc_state, 0, state_size);
5338
5339         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5340         if (ret)
5341                 return ret;
5342
5343         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5344                                    state_size, si_pi->sram_end);
5345
5346         return ret;
5347 }
5348
5349 static int si_upload_ulv_state(struct radeon_device *rdev)
5350 {
5351         struct si_power_info *si_pi = si_get_pi(rdev);
5352         struct si_ulv_param *ulv = &si_pi->ulv;
5353         int ret = 0;
5354
5355         if (ulv->supported && ulv->pl.vddc) {
5356                 u32 address = si_pi->state_table_start +
5357                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5358                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5359                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5360
5361                 memset(smc_state, 0, state_size);
5362
5363                 ret = si_populate_ulv_state(rdev, smc_state);
5364                 if (!ret)
5365                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5366                                                    state_size, si_pi->sram_end);
5367         }
5368
5369         return ret;
5370 }
5371
5372 static int si_upload_smc_data(struct radeon_device *rdev)
5373 {
5374         struct radeon_crtc *radeon_crtc = NULL;
5375         int i;
5376
5377         if (rdev->pm.dpm.new_active_crtc_count == 0)
5378                 return 0;
5379
5380         for (i = 0; i < rdev->num_crtc; i++) {
5381                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5382                         radeon_crtc = rdev->mode_info.crtcs[i];
5383                         break;
5384                 }
5385         }
5386
5387         if (radeon_crtc == NULL)
5388                 return 0;
5389
5390         if (radeon_crtc->line_time <= 0)
5391                 return 0;
5392
5393         if (si_write_smc_soft_register(rdev,
5394                                        SI_SMC_SOFT_REGISTER_crtc_index,
5395                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5396                 return 0;
5397
5398         if (si_write_smc_soft_register(rdev,
5399                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5400                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5401                 return 0;
5402
5403         if (si_write_smc_soft_register(rdev,
5404                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5405                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5406                 return 0;
5407
5408         return 0;
5409 }
5410
5411 static int si_set_mc_special_registers(struct radeon_device *rdev,
5412                                        struct si_mc_reg_table *table)
5413 {
5414         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5415         u8 i, j, k;
5416         u32 temp_reg;
5417
5418         for (i = 0, j = table->last; i < table->last; i++) {
5419                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5420                         return -EINVAL;
5421                 switch (table->mc_reg_address[i].s1 << 2) {
5422                 case MC_SEQ_MISC1:
5423                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5424                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5425                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5426                         for (k = 0; k < table->num_entries; k++)
5427                                 table->mc_reg_table_entry[k].mc_data[j] =
5428                                         ((temp_reg & 0xffff0000)) |
5429                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5430                         j++;
5431                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5432                                 return -EINVAL;
5433
5434                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5435                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5436                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5437                         for (k = 0; k < table->num_entries; k++) {
5438                                 table->mc_reg_table_entry[k].mc_data[j] =
5439                                         (temp_reg & 0xffff0000) |
5440                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5441                                 if (!pi->mem_gddr5)
5442                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5443                         }
5444                         j++;
5445                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5446                                 return -EINVAL;
5447
5448                         if (!pi->mem_gddr5) {
5449                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5450                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5451                                 for (k = 0; k < table->num_entries; k++)
5452                                         table->mc_reg_table_entry[k].mc_data[j] =
5453                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5454                                 j++;
5455                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5456                                         return -EINVAL;
5457                         }
5458                         break;
5459                 case MC_SEQ_RESERVE_M:
5460                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5461                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5462                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5463                         for(k = 0; k < table->num_entries; k++)
5464                                 table->mc_reg_table_entry[k].mc_data[j] =
5465                                         (temp_reg & 0xffff0000) |
5466                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5467                         j++;
5468                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5469                                 return -EINVAL;
5470                         break;
5471                 default:
5472                         break;
5473                 }
5474         }
5475
5476         table->last = j;
5477
5478         return 0;
5479 }
5480
5481 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5482 {
5483         bool result = true;
5484
5485         switch (in_reg) {
5486         case  MC_SEQ_RAS_TIMING >> 2:
5487                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5488                 break;
5489         case MC_SEQ_CAS_TIMING >> 2:
5490                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5491                 break;
5492         case MC_SEQ_MISC_TIMING >> 2:
5493                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5494                 break;
5495         case MC_SEQ_MISC_TIMING2 >> 2:
5496                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5497                 break;
5498         case MC_SEQ_RD_CTL_D0 >> 2:
5499                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5500                 break;
5501         case MC_SEQ_RD_CTL_D1 >> 2:
5502                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5503                 break;
5504         case MC_SEQ_WR_CTL_D0 >> 2:
5505                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5506                 break;
5507         case MC_SEQ_WR_CTL_D1 >> 2:
5508                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5509                 break;
5510         case MC_PMG_CMD_EMRS >> 2:
5511                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5512                 break;
5513         case MC_PMG_CMD_MRS >> 2:
5514                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5515                 break;
5516         case MC_PMG_CMD_MRS1 >> 2:
5517                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5518                 break;
5519         case MC_SEQ_PMG_TIMING >> 2:
5520                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5521                 break;
5522         case MC_PMG_CMD_MRS2 >> 2:
5523                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5524                 break;
5525         case MC_SEQ_WR_CTL_2 >> 2:
5526                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5527                 break;
5528         default:
5529                 result = false;
5530                 break;
5531         }
5532
5533         return result;
5534 }
5535
5536 static void si_set_valid_flag(struct si_mc_reg_table *table)
5537 {
5538         u8 i, j;
5539
5540         for (i = 0; i < table->last; i++) {
5541                 for (j = 1; j < table->num_entries; j++) {
5542                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5543                                 table->valid_flag |= 1 << i;
5544                                 break;
5545                         }
5546                 }
5547         }
5548 }
5549
5550 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5551 {
5552         u32 i;
5553         u16 address;
5554
5555         for (i = 0; i < table->last; i++)
5556                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5557                         address : table->mc_reg_address[i].s1;
5558
5559 }
5560
5561 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5562                                       struct si_mc_reg_table *si_table)
5563 {
5564         u8 i, j;
5565
5566         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5567                 return -EINVAL;
5568         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5569                 return -EINVAL;
5570
5571         for (i = 0; i < table->last; i++)
5572                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5573         si_table->last = table->last;
5574
5575         for (i = 0; i < table->num_entries; i++) {
5576                 si_table->mc_reg_table_entry[i].mclk_max =
5577                         table->mc_reg_table_entry[i].mclk_max;
5578                 for (j = 0; j < table->last; j++) {
5579                         si_table->mc_reg_table_entry[i].mc_data[j] =
5580                                 table->mc_reg_table_entry[i].mc_data[j];
5581                 }
5582         }
5583         si_table->num_entries = table->num_entries;
5584
5585         return 0;
5586 }
5587
5588 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5589 {
5590         struct si_power_info *si_pi = si_get_pi(rdev);
5591         struct atom_mc_reg_table *table;
5592         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5593         u8 module_index = rv770_get_memory_module_index(rdev);
5594         int ret;
5595
5596         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5597         if (!table)
5598                 return -ENOMEM;
5599
5600         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5601         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5602         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5603         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5604         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5605         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5606         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5607         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5608         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5609         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5610         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5611         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5612         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5613         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5614
5615         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5616         if (ret)
5617                 goto init_mc_done;
5618
5619         ret = si_copy_vbios_mc_reg_table(table, si_table);
5620         if (ret)
5621                 goto init_mc_done;
5622
5623         si_set_s0_mc_reg_index(si_table);
5624
5625         ret = si_set_mc_special_registers(rdev, si_table);
5626         if (ret)
5627                 goto init_mc_done;
5628
5629         si_set_valid_flag(si_table);
5630
5631 init_mc_done:
5632         kfree(table);
5633
5634         return ret;
5635
5636 }
5637
5638 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5639                                          SMC_SIslands_MCRegisters *mc_reg_table)
5640 {
5641         struct si_power_info *si_pi = si_get_pi(rdev);
5642         u32 i, j;
5643
5644         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5645                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5646                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5647                                 break;
5648                         mc_reg_table->address[i].s0 =
5649                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5650                         mc_reg_table->address[i].s1 =
5651                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5652                         i++;
5653                 }
5654         }
5655         mc_reg_table->last = (u8)i;
5656 }
5657
5658 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5659                                     SMC_SIslands_MCRegisterSet *data,
5660                                     u32 num_entries, u32 valid_flag)
5661 {
5662         u32 i, j;
5663
5664         for(i = 0, j = 0; j < num_entries; j++) {
5665                 if (valid_flag & (1 << j)) {
5666                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5667                         i++;
5668                 }
5669         }
5670 }
5671
5672 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5673                                                  struct rv7xx_pl *pl,
5674                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5675 {
5676         struct si_power_info *si_pi = si_get_pi(rdev);
5677         u32 i = 0;
5678
5679         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5680                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5681                         break;
5682         }
5683
5684         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5685                 --i;
5686
5687         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5688                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5689                                 si_pi->mc_reg_table.valid_flag);
5690 }
5691
5692 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5693                                            struct radeon_ps *radeon_state,
5694                                            SMC_SIslands_MCRegisters *mc_reg_table)
5695 {
5696         struct ni_ps *state = ni_get_ps(radeon_state);
5697         int i;
5698
5699         for (i = 0; i < state->performance_level_count; i++) {
5700                 si_convert_mc_reg_table_entry_to_smc(rdev,
5701                                                      &state->performance_levels[i],
5702                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5703         }
5704 }
5705
5706 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5707                                     struct radeon_ps *radeon_boot_state)
5708 {
5709         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5710         struct si_power_info *si_pi = si_get_pi(rdev);
5711         struct si_ulv_param *ulv = &si_pi->ulv;
5712         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5713
5714         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5715
5716         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5717
5718         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5719
5720         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5721                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5722
5723         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5724                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5725                                 si_pi->mc_reg_table.last,
5726                                 si_pi->mc_reg_table.valid_flag);
5727
5728         if (ulv->supported && ulv->pl.vddc != 0)
5729                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5730                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5731         else
5732                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5733                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5734                                         si_pi->mc_reg_table.last,
5735                                         si_pi->mc_reg_table.valid_flag);
5736
5737         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5738
5739         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5740                                     (u8 *)smc_mc_reg_table,
5741                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5742 }
5743
5744 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5745                                   struct radeon_ps *radeon_new_state)
5746 {
5747         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5748         struct si_power_info *si_pi = si_get_pi(rdev);
5749         u32 address = si_pi->mc_reg_table_start +
5750                 offsetof(SMC_SIslands_MCRegisters,
5751                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5752         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5753
5754         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5755
5756         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5757
5758
5759         return si_copy_bytes_to_smc(rdev, address,
5760                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5761                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5762                                     si_pi->sram_end);
5763
5764 }
5765
5766 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5767 {
5768         if (enable)
5769                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5770         else
5771                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5772 }
5773
5774 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5775                                                       struct radeon_ps *radeon_state)
5776 {
5777         struct ni_ps *state = ni_get_ps(radeon_state);
5778         int i;
5779         u16 pcie_speed, max_speed = 0;
5780
5781         for (i = 0; i < state->performance_level_count; i++) {
5782                 pcie_speed = state->performance_levels[i].pcie_gen;
5783                 if (max_speed < pcie_speed)
5784                         max_speed = pcie_speed;
5785         }
5786         return max_speed;
5787 }
5788
5789 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5790 {
5791         u32 speed_cntl;
5792
5793         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5794         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5795
5796         return (u16)speed_cntl;
5797 }
5798
5799 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5800                                                              struct radeon_ps *radeon_new_state,
5801                                                              struct radeon_ps *radeon_current_state)
5802 {
5803         struct si_power_info *si_pi = si_get_pi(rdev);
5804         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5805         enum radeon_pcie_gen current_link_speed;
5806
5807         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5808                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5809         else
5810                 current_link_speed = si_pi->force_pcie_gen;
5811
5812         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5813         si_pi->pspp_notify_required = false;
5814         if (target_link_speed > current_link_speed) {
5815                 switch (target_link_speed) {
5816 #if defined(CONFIG_ACPI)
5817                 case RADEON_PCIE_GEN3:
5818                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5819                                 break;
5820                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5821                         if (current_link_speed == RADEON_PCIE_GEN2)
5822                                 break;
5823                 case RADEON_PCIE_GEN2:
5824                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5825                                 break;
5826 #endif
5827                 default:
5828                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5829                         break;
5830                 }
5831         } else {
5832                 if (target_link_speed < current_link_speed)
5833                         si_pi->pspp_notify_required = true;
5834         }
5835 }
5836
5837 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5838                                                            struct radeon_ps *radeon_new_state,
5839                                                            struct radeon_ps *radeon_current_state)
5840 {
5841         struct si_power_info *si_pi = si_get_pi(rdev);
5842         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5843         u8 request;
5844
5845         if (si_pi->pspp_notify_required) {
5846                 if (target_link_speed == RADEON_PCIE_GEN3)
5847                         request = PCIE_PERF_REQ_PECI_GEN3;
5848                 else if (target_link_speed == RADEON_PCIE_GEN2)
5849                         request = PCIE_PERF_REQ_PECI_GEN2;
5850                 else
5851                         request = PCIE_PERF_REQ_PECI_GEN1;
5852
5853                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5854                     (si_get_current_pcie_speed(rdev) > 0))
5855                         return;
5856
5857 #if defined(CONFIG_ACPI)
5858                 radeon_acpi_pcie_performance_request(rdev, request, false);
5859 #endif
5860         }
5861 }
5862
5863 #if 0
5864 static int si_ds_request(struct radeon_device *rdev,
5865                          bool ds_status_on, u32 count_write)
5866 {
5867         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5868
5869         if (eg_pi->sclk_deep_sleep) {
5870                 if (ds_status_on)
5871                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5872                                 PPSMC_Result_OK) ?
5873                                 0 : -EINVAL;
5874                 else
5875                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5876                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5877         }
5878         return 0;
5879 }
5880 #endif
5881
5882 static void si_set_max_cu_value(struct radeon_device *rdev)
5883 {
5884         struct si_power_info *si_pi = si_get_pi(rdev);
5885
5886         if (rdev->family == CHIP_VERDE) {
5887                 switch (rdev->pdev->device) {
5888                 case 0x6820:
5889                 case 0x6825:
5890                 case 0x6821:
5891                 case 0x6823:
5892                 case 0x6827:
5893                         si_pi->max_cu = 10;
5894                         break;
5895                 case 0x682D:
5896                 case 0x6824:
5897                 case 0x682F:
5898                 case 0x6826:
5899                         si_pi->max_cu = 8;
5900                         break;
5901                 case 0x6828:
5902                 case 0x6830:
5903                 case 0x6831:
5904                 case 0x6838:
5905                 case 0x6839:
5906                 case 0x683D:
5907                         si_pi->max_cu = 10;
5908                         break;
5909                 case 0x683B:
5910                 case 0x683F:
5911                 case 0x6829:
5912                         si_pi->max_cu = 8;
5913                         break;
5914                 default:
5915                         si_pi->max_cu = 0;
5916                         break;
5917                 }
5918         } else {
5919                 si_pi->max_cu = 0;
5920         }
5921 }
5922
5923 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5924                                                              struct radeon_clock_voltage_dependency_table *table)
5925 {
5926         u32 i;
5927         int j;
5928         u16 leakage_voltage;
5929
5930         if (table) {
5931                 for (i = 0; i < table->count; i++) {
5932                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5933                                                                           table->entries[i].v,
5934                                                                           &leakage_voltage)) {
5935                         case 0:
5936                                 table->entries[i].v = leakage_voltage;
5937                                 break;
5938                         case -EAGAIN:
5939                                 return -EINVAL;
5940                         case -EINVAL:
5941                         default:
5942                                 break;
5943                         }
5944                 }
5945
5946                 for (j = (table->count - 2); j >= 0; j--) {
5947                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5948                                 table->entries[j].v : table->entries[j + 1].v;
5949                 }
5950         }
5951         return 0;
5952 }
5953
5954 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5955 {
5956         int ret = 0;
5957
5958         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5959                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5960         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5961                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5962         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5963                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5964         return ret;
5965 }
5966
5967 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5968                                           struct radeon_ps *radeon_new_state,
5969                                           struct radeon_ps *radeon_current_state)
5970 {
5971         u32 lane_width;
5972         u32 new_lane_width =
5973                 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5974         u32 current_lane_width =
5975                 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5976
5977         if (new_lane_width != current_lane_width) {
5978                 radeon_set_pcie_lanes(rdev, new_lane_width);
5979                 lane_width = radeon_get_pcie_lanes(rdev);
5980                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5981         }
5982 }
5983
5984 static void si_set_vce_clock(struct radeon_device *rdev,
5985                              struct radeon_ps *new_rps,
5986                              struct radeon_ps *old_rps)
5987 {
5988         if ((old_rps->evclk != new_rps->evclk) ||
5989             (old_rps->ecclk != new_rps->ecclk)) {
5990                 /* turn the clocks on when encoding, off otherwise */
5991                 if (new_rps->evclk || new_rps->ecclk)
5992                         vce_v1_0_enable_mgcg(rdev, false);
5993                 else
5994                         vce_v1_0_enable_mgcg(rdev, true);
5995                 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5996         }
5997 }
5998
5999 void si_dpm_setup_asic(struct radeon_device *rdev)
6000 {
6001         int r;
6002
6003         r = si_mc_load_microcode(rdev);
6004         if (r)
6005                 DRM_ERROR("Failed to load MC firmware!\n");
6006         rv770_get_memory_type(rdev);
6007         si_read_clock_registers(rdev);
6008         si_enable_acpi_power_management(rdev);
6009 }
6010
6011 static int si_thermal_enable_alert(struct radeon_device *rdev,
6012                                    bool enable)
6013 {
6014         u32 thermal_int = RREG32(CG_THERMAL_INT);
6015
6016         if (enable) {
6017                 PPSMC_Result result;
6018
6019                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6020                 WREG32(CG_THERMAL_INT, thermal_int);
6021                 rdev->irq.dpm_thermal = false;
6022                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
6023                 if (result != PPSMC_Result_OK) {
6024                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6025                         return -EINVAL;
6026                 }
6027         } else {
6028                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6029                 WREG32(CG_THERMAL_INT, thermal_int);
6030                 rdev->irq.dpm_thermal = true;
6031         }
6032
6033         return 0;
6034 }
6035
6036 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6037                                             int min_temp, int max_temp)
6038 {
6039         int low_temp = 0 * 1000;
6040         int high_temp = 255 * 1000;
6041
6042         if (low_temp < min_temp)
6043                 low_temp = min_temp;
6044         if (high_temp > max_temp)
6045                 high_temp = max_temp;
6046         if (high_temp < low_temp) {
6047                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6048                 return -EINVAL;
6049         }
6050
6051         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6052         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6053         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6054
6055         rdev->pm.dpm.thermal.min_temp = low_temp;
6056         rdev->pm.dpm.thermal.max_temp = high_temp;
6057
6058         return 0;
6059 }
6060
6061 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6062 {
6063         struct si_power_info *si_pi = si_get_pi(rdev);
6064         u32 tmp;
6065
6066         if (si_pi->fan_ctrl_is_in_default_mode) {
6067                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6068                 si_pi->fan_ctrl_default_mode = tmp;
6069                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6070                 si_pi->t_min = tmp;
6071                 si_pi->fan_ctrl_is_in_default_mode = false;
6072         }
6073
6074         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6075         tmp |= TMIN(0);
6076         WREG32(CG_FDO_CTRL2, tmp);
6077
6078         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6079         tmp |= FDO_PWM_MODE(mode);
6080         WREG32(CG_FDO_CTRL2, tmp);
6081 }
6082
6083 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6084 {
6085         struct si_power_info *si_pi = si_get_pi(rdev);
6086         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6087         u32 duty100;
6088         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6089         u16 fdo_min, slope1, slope2;
6090         u32 reference_clock, tmp;
6091         int ret;
6092         u64 tmp64;
6093
6094         if (!si_pi->fan_table_start) {
6095                 rdev->pm.dpm.fan.ucode_fan_control = false;
6096                 return 0;
6097         }
6098
6099         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6100
6101         if (duty100 == 0) {
6102                 rdev->pm.dpm.fan.ucode_fan_control = false;
6103                 return 0;
6104         }
6105
6106         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6107         do_div(tmp64, 10000);
6108         fdo_min = (u16)tmp64;
6109
6110         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6111         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6112
6113         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6114         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6115
6116         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6117         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6118
6119         fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6120         fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6121         fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6122
6123         fan_table.slope1 = cpu_to_be16(slope1);
6124         fan_table.slope2 = cpu_to_be16(slope2);
6125
6126         fan_table.fdo_min = cpu_to_be16(fdo_min);
6127
6128         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6129
6130         fan_table.hys_up = cpu_to_be16(1);
6131
6132         fan_table.hys_slope = cpu_to_be16(1);
6133
6134         fan_table.temp_resp_lim = cpu_to_be16(5);
6135
6136         reference_clock = radeon_get_xclk(rdev);
6137
6138         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6139                                                 reference_clock) / 1600);
6140
6141         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6142
6143         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6144         fan_table.temp_src = (uint8_t)tmp;
6145
6146         ret = si_copy_bytes_to_smc(rdev,
6147                                    si_pi->fan_table_start,
6148                                    (u8 *)(&fan_table),
6149                                    sizeof(fan_table),
6150                                    si_pi->sram_end);
6151
6152         if (ret) {
6153                 DRM_ERROR("Failed to load fan table to the SMC.");
6154                 rdev->pm.dpm.fan.ucode_fan_control = false;
6155         }
6156
6157         return 0;
6158 }
6159
6160 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6161 {
6162         struct si_power_info *si_pi = si_get_pi(rdev);
6163         PPSMC_Result ret;
6164
6165         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6166         if (ret == PPSMC_Result_OK) {
6167                 si_pi->fan_is_controlled_by_smc = true;
6168                 return 0;
6169         } else {
6170                 return -EINVAL;
6171         }
6172 }
6173
6174 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6175 {
6176         struct si_power_info *si_pi = si_get_pi(rdev);
6177         PPSMC_Result ret;
6178
6179         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6180
6181         if (ret == PPSMC_Result_OK) {
6182                 si_pi->fan_is_controlled_by_smc = false;
6183                 return 0;
6184         } else {
6185                 return -EINVAL;
6186         }
6187 }
6188
6189 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6190                                       u32 *speed)
6191 {
6192         u32 duty, duty100;
6193         u64 tmp64;
6194
6195         if (rdev->pm.no_fan)
6196                 return -ENOENT;
6197
6198         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6199         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6200
6201         if (duty100 == 0)
6202                 return -EINVAL;
6203
6204         tmp64 = (u64)duty * 100;
6205         do_div(tmp64, duty100);
6206         *speed = (u32)tmp64;
6207
6208         if (*speed > 100)
6209                 *speed = 100;
6210
6211         return 0;
6212 }
6213
6214 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6215                                       u32 speed)
6216 {
6217         struct si_power_info *si_pi = si_get_pi(rdev);
6218         u32 tmp;
6219         u32 duty, duty100;
6220         u64 tmp64;
6221
6222         if (rdev->pm.no_fan)
6223                 return -ENOENT;
6224
6225         if (si_pi->fan_is_controlled_by_smc)
6226                 return -EINVAL;
6227
6228         if (speed > 100)
6229                 return -EINVAL;
6230
6231         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6232
6233         if (duty100 == 0)
6234                 return -EINVAL;
6235
6236         tmp64 = (u64)speed * duty100;
6237         do_div(tmp64, 100);
6238         duty = (u32)tmp64;
6239
6240         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6241         tmp |= FDO_STATIC_DUTY(duty);
6242         WREG32(CG_FDO_CTRL0, tmp);
6243
6244         return 0;
6245 }
6246
6247 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6248 {
6249         if (mode) {
6250                 /* stop auto-manage */
6251                 if (rdev->pm.dpm.fan.ucode_fan_control)
6252                         si_fan_ctrl_stop_smc_fan_control(rdev);
6253                 si_fan_ctrl_set_static_mode(rdev, mode);
6254         } else {
6255                 /* restart auto-manage */
6256                 if (rdev->pm.dpm.fan.ucode_fan_control)
6257                         si_thermal_start_smc_fan_control(rdev);
6258                 else
6259                         si_fan_ctrl_set_default_mode(rdev);
6260         }
6261 }
6262
6263 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6264 {
6265         struct si_power_info *si_pi = si_get_pi(rdev);
6266         u32 tmp;
6267
6268         if (si_pi->fan_is_controlled_by_smc)
6269                 return 0;
6270
6271         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6272         return (tmp >> FDO_PWM_MODE_SHIFT);
6273 }
6274
6275 #if 0
6276 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6277                                          u32 *speed)
6278 {
6279         u32 tach_period;
6280         u32 xclk = radeon_get_xclk(rdev);
6281
6282         if (rdev->pm.no_fan)
6283                 return -ENOENT;
6284
6285         if (rdev->pm.fan_pulses_per_revolution == 0)
6286                 return -ENOENT;
6287
6288         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6289         if (tach_period == 0)
6290                 return -ENOENT;
6291
6292         *speed = 60 * xclk * 10000 / tach_period;
6293
6294         return 0;
6295 }
6296
6297 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6298                                          u32 speed)
6299 {
6300         u32 tach_period, tmp;
6301         u32 xclk = radeon_get_xclk(rdev);
6302
6303         if (rdev->pm.no_fan)
6304                 return -ENOENT;
6305
6306         if (rdev->pm.fan_pulses_per_revolution == 0)
6307                 return -ENOENT;
6308
6309         if ((speed < rdev->pm.fan_min_rpm) ||
6310             (speed > rdev->pm.fan_max_rpm))
6311                 return -EINVAL;
6312
6313         if (rdev->pm.dpm.fan.ucode_fan_control)
6314                 si_fan_ctrl_stop_smc_fan_control(rdev);
6315
6316         tach_period = 60 * xclk * 10000 / (8 * speed);
6317         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6318         tmp |= TARGET_PERIOD(tach_period);
6319         WREG32(CG_TACH_CTRL, tmp);
6320
6321         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6322
6323         return 0;
6324 }
6325 #endif
6326
6327 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6328 {
6329         struct si_power_info *si_pi = si_get_pi(rdev);
6330         u32 tmp;
6331
6332         if (!si_pi->fan_ctrl_is_in_default_mode) {
6333                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6334                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6335                 WREG32(CG_FDO_CTRL2, tmp);
6336
6337                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6338                 tmp |= TMIN(si_pi->t_min);
6339                 WREG32(CG_FDO_CTRL2, tmp);
6340                 si_pi->fan_ctrl_is_in_default_mode = true;
6341         }
6342 }
6343
6344 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6345 {
6346         if (rdev->pm.dpm.fan.ucode_fan_control) {
6347                 si_fan_ctrl_start_smc_fan_control(rdev);
6348                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6349         }
6350 }
6351
6352 static void si_thermal_initialize(struct radeon_device *rdev)
6353 {
6354         u32 tmp;
6355
6356         if (rdev->pm.fan_pulses_per_revolution) {
6357                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6358                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6359                 WREG32(CG_TACH_CTRL, tmp);
6360         }
6361
6362         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6363         tmp |= TACH_PWM_RESP_RATE(0x28);
6364         WREG32(CG_FDO_CTRL2, tmp);
6365 }
6366
6367 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6368 {
6369         int ret;
6370
6371         si_thermal_initialize(rdev);
6372         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6373         if (ret)
6374                 return ret;
6375         ret = si_thermal_enable_alert(rdev, true);
6376         if (ret)
6377                 return ret;
6378         if (rdev->pm.dpm.fan.ucode_fan_control) {
6379                 ret = si_halt_smc(rdev);
6380                 if (ret)
6381                         return ret;
6382                 ret = si_thermal_setup_fan_table(rdev);
6383                 if (ret)
6384                         return ret;
6385                 ret = si_resume_smc(rdev);
6386                 if (ret)
6387                         return ret;
6388                 si_thermal_start_smc_fan_control(rdev);
6389         }
6390
6391         return 0;
6392 }
6393
6394 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6395 {
6396         if (!rdev->pm.no_fan) {
6397                 si_fan_ctrl_set_default_mode(rdev);
6398                 si_fan_ctrl_stop_smc_fan_control(rdev);
6399         }
6400 }
6401
6402 int si_dpm_enable(struct radeon_device *rdev)
6403 {
6404         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6405         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6406         struct si_power_info *si_pi = si_get_pi(rdev);
6407         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6408         int ret;
6409
6410         if (si_is_smc_running(rdev))
6411                 return -EINVAL;
6412         if (pi->voltage_control || si_pi->voltage_control_svi2)
6413                 si_enable_voltage_control(rdev, true);
6414         if (pi->mvdd_control)
6415                 si_get_mvdd_configuration(rdev);
6416         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6417                 ret = si_construct_voltage_tables(rdev);
6418                 if (ret) {
6419                         DRM_ERROR("si_construct_voltage_tables failed\n");
6420                         return ret;
6421                 }
6422         }
6423         if (eg_pi->dynamic_ac_timing) {
6424                 ret = si_initialize_mc_reg_table(rdev);
6425                 if (ret)
6426                         eg_pi->dynamic_ac_timing = false;
6427         }
6428         if (pi->dynamic_ss)
6429                 si_enable_spread_spectrum(rdev, true);
6430         if (pi->thermal_protection)
6431                 si_enable_thermal_protection(rdev, true);
6432         si_setup_bsp(rdev);
6433         si_program_git(rdev);
6434         si_program_tp(rdev);
6435         si_program_tpp(rdev);
6436         si_program_sstp(rdev);
6437         si_enable_display_gap(rdev);
6438         si_program_vc(rdev);
6439         ret = si_upload_firmware(rdev);
6440         if (ret) {
6441                 DRM_ERROR("si_upload_firmware failed\n");
6442                 return ret;
6443         }
6444         ret = si_process_firmware_header(rdev);
6445         if (ret) {
6446                 DRM_ERROR("si_process_firmware_header failed\n");
6447                 return ret;
6448         }
6449         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6450         if (ret) {
6451                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6452                 return ret;
6453         }
6454         ret = si_init_smc_table(rdev);
6455         if (ret) {
6456                 DRM_ERROR("si_init_smc_table failed\n");
6457                 return ret;
6458         }
6459         ret = si_init_smc_spll_table(rdev);
6460         if (ret) {
6461                 DRM_ERROR("si_init_smc_spll_table failed\n");
6462                 return ret;
6463         }
6464         ret = si_init_arb_table_index(rdev);
6465         if (ret) {
6466                 DRM_ERROR("si_init_arb_table_index failed\n");
6467                 return ret;
6468         }
6469         if (eg_pi->dynamic_ac_timing) {
6470                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6471                 if (ret) {
6472                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6473                         return ret;
6474                 }
6475         }
6476         ret = si_initialize_smc_cac_tables(rdev);
6477         if (ret) {
6478                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6479                 return ret;
6480         }
6481         ret = si_initialize_hardware_cac_manager(rdev);
6482         if (ret) {
6483                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6484                 return ret;
6485         }
6486         ret = si_initialize_smc_dte_tables(rdev);
6487         if (ret) {
6488                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6489                 return ret;
6490         }
6491         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6492         if (ret) {
6493                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6494                 return ret;
6495         }
6496         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6497         if (ret) {
6498                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6499                 return ret;
6500         }
6501         si_program_response_times(rdev);
6502         si_program_ds_registers(rdev);
6503         si_dpm_start_smc(rdev);
6504         ret = si_notify_smc_display_change(rdev, false);
6505         if (ret) {
6506                 DRM_ERROR("si_notify_smc_display_change failed\n");
6507                 return ret;
6508         }
6509         si_enable_sclk_control(rdev, true);
6510         si_start_dpm(rdev);
6511
6512         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6513
6514         si_thermal_start_thermal_controller(rdev);
6515
6516         ni_update_current_ps(rdev, boot_ps);
6517
6518         return 0;
6519 }
6520
6521 static int si_set_temperature_range(struct radeon_device *rdev)
6522 {
6523         int ret;
6524
6525         ret = si_thermal_enable_alert(rdev, false);
6526         if (ret)
6527                 return ret;
6528         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6529         if (ret)
6530                 return ret;
6531         ret = si_thermal_enable_alert(rdev, true);
6532         if (ret)
6533                 return ret;
6534
6535         return ret;
6536 }
6537
6538 int si_dpm_late_enable(struct radeon_device *rdev)
6539 {
6540         int ret;
6541
6542         ret = si_set_temperature_range(rdev);
6543         if (ret)
6544                 return ret;
6545
6546         return ret;
6547 }
6548
6549 void si_dpm_disable(struct radeon_device *rdev)
6550 {
6551         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6552         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6553
6554         if (!si_is_smc_running(rdev))
6555                 return;
6556         si_thermal_stop_thermal_controller(rdev);
6557         si_disable_ulv(rdev);
6558         si_clear_vc(rdev);
6559         if (pi->thermal_protection)
6560                 si_enable_thermal_protection(rdev, false);
6561         si_enable_power_containment(rdev, boot_ps, false);
6562         si_enable_smc_cac(rdev, boot_ps, false);
6563         si_enable_spread_spectrum(rdev, false);
6564         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6565         si_stop_dpm(rdev);
6566         si_reset_to_default(rdev);
6567         si_dpm_stop_smc(rdev);
6568         si_force_switch_to_arb_f0(rdev);
6569
6570         ni_update_current_ps(rdev, boot_ps);
6571 }
6572
6573 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6574 {
6575         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6576         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6577         struct radeon_ps *new_ps = &requested_ps;
6578
6579         ni_update_requested_ps(rdev, new_ps);
6580
6581         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6582
6583         return 0;
6584 }
6585
6586 static int si_power_control_set_level(struct radeon_device *rdev)
6587 {
6588         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6589         int ret;
6590
6591         ret = si_restrict_performance_levels_before_switch(rdev);
6592         if (ret)
6593                 return ret;
6594         ret = si_halt_smc(rdev);
6595         if (ret)
6596                 return ret;
6597         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6598         if (ret)
6599                 return ret;
6600         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6601         if (ret)
6602                 return ret;
6603         ret = si_resume_smc(rdev);
6604         if (ret)
6605                 return ret;
6606         ret = si_set_sw_state(rdev);
6607         if (ret)
6608                 return ret;
6609         return 0;
6610 }
6611
6612 int si_dpm_set_power_state(struct radeon_device *rdev)
6613 {
6614         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6615         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6616         struct radeon_ps *old_ps = &eg_pi->current_rps;
6617         int ret;
6618
6619         ret = si_disable_ulv(rdev);
6620         if (ret) {
6621                 DRM_ERROR("si_disable_ulv failed\n");
6622                 return ret;
6623         }
6624         ret = si_restrict_performance_levels_before_switch(rdev);
6625         if (ret) {
6626                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6627                 return ret;
6628         }
6629         if (eg_pi->pcie_performance_request)
6630                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6631         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6632         ret = si_enable_power_containment(rdev, new_ps, false);
6633         if (ret) {
6634                 DRM_ERROR("si_enable_power_containment failed\n");
6635                 return ret;
6636         }
6637         ret = si_enable_smc_cac(rdev, new_ps, false);
6638         if (ret) {
6639                 DRM_ERROR("si_enable_smc_cac failed\n");
6640                 return ret;
6641         }
6642         ret = si_halt_smc(rdev);
6643         if (ret) {
6644                 DRM_ERROR("si_halt_smc failed\n");
6645                 return ret;
6646         }
6647         ret = si_upload_sw_state(rdev, new_ps);
6648         if (ret) {
6649                 DRM_ERROR("si_upload_sw_state failed\n");
6650                 return ret;
6651         }
6652         ret = si_upload_smc_data(rdev);
6653         if (ret) {
6654                 DRM_ERROR("si_upload_smc_data failed\n");
6655                 return ret;
6656         }
6657         ret = si_upload_ulv_state(rdev);
6658         if (ret) {
6659                 DRM_ERROR("si_upload_ulv_state failed\n");
6660                 return ret;
6661         }
6662         if (eg_pi->dynamic_ac_timing) {
6663                 ret = si_upload_mc_reg_table(rdev, new_ps);
6664                 if (ret) {
6665                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6666                         return ret;
6667                 }
6668         }
6669         ret = si_program_memory_timing_parameters(rdev, new_ps);
6670         if (ret) {
6671                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6672                 return ret;
6673         }
6674         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6675
6676         ret = si_resume_smc(rdev);
6677         if (ret) {
6678                 DRM_ERROR("si_resume_smc failed\n");
6679                 return ret;
6680         }
6681         ret = si_set_sw_state(rdev);
6682         if (ret) {
6683                 DRM_ERROR("si_set_sw_state failed\n");
6684                 return ret;
6685         }
6686         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6687         si_set_vce_clock(rdev, new_ps, old_ps);
6688         if (eg_pi->pcie_performance_request)
6689                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6690         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6691         if (ret) {
6692                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6693                 return ret;
6694         }
6695         ret = si_enable_smc_cac(rdev, new_ps, true);
6696         if (ret) {
6697                 DRM_ERROR("si_enable_smc_cac failed\n");
6698                 return ret;
6699         }
6700         ret = si_enable_power_containment(rdev, new_ps, true);
6701         if (ret) {
6702                 DRM_ERROR("si_enable_power_containment failed\n");
6703                 return ret;
6704         }
6705
6706         ret = si_power_control_set_level(rdev);
6707         if (ret) {
6708                 DRM_ERROR("si_power_control_set_level failed\n");
6709                 return ret;
6710         }
6711
6712         return 0;
6713 }
6714
6715 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6716 {
6717         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6718         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6719
6720         ni_update_current_ps(rdev, new_ps);
6721 }
6722
6723 #if 0
6724 void si_dpm_reset_asic(struct radeon_device *rdev)
6725 {
6726         si_restrict_performance_levels_before_switch(rdev);
6727         si_disable_ulv(rdev);
6728         si_set_boot_state(rdev);
6729 }
6730 #endif
6731
6732 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6733 {
6734         si_program_display_gap(rdev);
6735 }
6736
6737 union power_info {
6738         struct _ATOM_POWERPLAY_INFO info;
6739         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6740         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6741         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6742         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6743         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6744 };
6745
6746 union pplib_clock_info {
6747         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6748         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6749         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6750         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6751         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6752 };
6753
6754 union pplib_power_state {
6755         struct _ATOM_PPLIB_STATE v1;
6756         struct _ATOM_PPLIB_STATE_V2 v2;
6757 };
6758
6759 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6760                                           struct radeon_ps *rps,
6761                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6762                                           u8 table_rev)
6763 {
6764         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6765         rps->class = le16_to_cpu(non_clock_info->usClassification);
6766         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6767
6768         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6769                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6770                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6771         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6772                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6773                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6774         } else {
6775                 rps->vclk = 0;
6776                 rps->dclk = 0;
6777         }
6778
6779         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6780                 rdev->pm.dpm.boot_ps = rps;
6781         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6782                 rdev->pm.dpm.uvd_ps = rps;
6783 }
6784
6785 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6786                                       struct radeon_ps *rps, int index,
6787                                       union pplib_clock_info *clock_info)
6788 {
6789         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6790         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6791         struct si_power_info *si_pi = si_get_pi(rdev);
6792         struct ni_ps *ps = ni_get_ps(rps);
6793         u16 leakage_voltage;
6794         struct rv7xx_pl *pl = &ps->performance_levels[index];
6795         int ret;
6796
6797         ps->performance_level_count = index + 1;
6798
6799         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6800         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6801         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6802         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6803
6804         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6805         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6806         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6807         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6808                                                  si_pi->sys_pcie_mask,
6809                                                  si_pi->boot_pcie_gen,
6810                                                  clock_info->si.ucPCIEGen);
6811
6812         /* patch up vddc if necessary */
6813         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6814                                                         &leakage_voltage);
6815         if (ret == 0)
6816                 pl->vddc = leakage_voltage;
6817
6818         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6819                 pi->acpi_vddc = pl->vddc;
6820                 eg_pi->acpi_vddci = pl->vddci;
6821                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6822         }
6823
6824         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6825             index == 0) {
6826                 /* XXX disable for A0 tahiti */
6827                 si_pi->ulv.supported = false;
6828                 si_pi->ulv.pl = *pl;
6829                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6830                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6831                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6832                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6833         }
6834
6835         if (pi->min_vddc_in_table > pl->vddc)
6836                 pi->min_vddc_in_table = pl->vddc;
6837
6838         if (pi->max_vddc_in_table < pl->vddc)
6839                 pi->max_vddc_in_table = pl->vddc;
6840
6841         /* patch up boot state */
6842         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6843                 u16 vddc, vddci, mvdd;
6844                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6845                 pl->mclk = rdev->clock.default_mclk;
6846                 pl->sclk = rdev->clock.default_sclk;
6847                 pl->vddc = vddc;
6848                 pl->vddci = vddci;
6849                 si_pi->mvdd_bootup_value = mvdd;
6850         }
6851
6852         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6853             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6854                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6855                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6856                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6857                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6858         }
6859 }
6860
6861 static int si_parse_power_table(struct radeon_device *rdev)
6862 {
6863         struct radeon_mode_info *mode_info = &rdev->mode_info;
6864         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6865         union pplib_power_state *power_state;
6866         int i, j, k, non_clock_array_index, clock_array_index;
6867         union pplib_clock_info *clock_info;
6868         struct _StateArray *state_array;
6869         struct _ClockInfoArray *clock_info_array;
6870         struct _NonClockInfoArray *non_clock_info_array;
6871         union power_info *power_info;
6872         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6873         u16 data_offset;
6874         u8 frev, crev;
6875         u8 *power_state_offset;
6876         struct ni_ps *ps;
6877
6878         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6879                                    &frev, &crev, &data_offset))
6880                 return -EINVAL;
6881         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6882
6883         state_array = (struct _StateArray *)
6884                 (mode_info->atom_context->bios + data_offset +
6885                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6886         clock_info_array = (struct _ClockInfoArray *)
6887                 (mode_info->atom_context->bios + data_offset +
6888                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6889         non_clock_info_array = (struct _NonClockInfoArray *)
6890                 (mode_info->atom_context->bios + data_offset +
6891                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6892
6893         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6894                                   state_array->ucNumEntries, GFP_KERNEL);
6895         if (!rdev->pm.dpm.ps)
6896                 return -ENOMEM;
6897         power_state_offset = (u8 *)state_array->states;
6898         for (i = 0; i < state_array->ucNumEntries; i++) {
6899                 u8 *idx;
6900                 power_state = (union pplib_power_state *)power_state_offset;
6901                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6902                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6903                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6904                 if (!rdev->pm.power_state[i].clock_info)
6905                         return -EINVAL;
6906                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6907                 if (ps == NULL) {
6908                         kfree(rdev->pm.dpm.ps);
6909                         return -ENOMEM;
6910                 }
6911                 rdev->pm.dpm.ps[i].ps_priv = ps;
6912                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6913                                               non_clock_info,
6914                                               non_clock_info_array->ucEntrySize);
6915                 k = 0;
6916                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6917                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6918                         clock_array_index = idx[j];
6919                         if (clock_array_index >= clock_info_array->ucNumEntries)
6920                                 continue;
6921                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6922                                 break;
6923                         clock_info = (union pplib_clock_info *)
6924                                 ((u8 *)&clock_info_array->clockInfo[0] +
6925                                  (clock_array_index * clock_info_array->ucEntrySize));
6926                         si_parse_pplib_clock_info(rdev,
6927                                                   &rdev->pm.dpm.ps[i], k,
6928                                                   clock_info);
6929                         k++;
6930                 }
6931                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6932         }
6933         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6934
6935         /* fill in the vce power states */
6936         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6937                 u32 sclk, mclk;
6938                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6939                 clock_info = (union pplib_clock_info *)
6940                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6941                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6942                 sclk |= clock_info->si.ucEngineClockHigh << 16;
6943                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6944                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6945                 rdev->pm.dpm.vce_states[i].sclk = sclk;
6946                 rdev->pm.dpm.vce_states[i].mclk = mclk;
6947         }
6948
6949         return 0;
6950 }
6951
6952 int si_dpm_init(struct radeon_device *rdev)
6953 {
6954         struct rv7xx_power_info *pi;
6955         struct evergreen_power_info *eg_pi;
6956         struct ni_power_info *ni_pi;
6957         struct si_power_info *si_pi;
6958         struct atom_clock_dividers dividers;
6959         int ret;
6960         u32 mask;
6961
6962         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6963         if (si_pi == NULL)
6964                 return -ENOMEM;
6965         rdev->pm.dpm.priv = si_pi;
6966         ni_pi = &si_pi->ni;
6967         eg_pi = &ni_pi->eg;
6968         pi = &eg_pi->rv7xx;
6969
6970         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6971         if (ret)
6972                 si_pi->sys_pcie_mask = 0;
6973         else
6974                 si_pi->sys_pcie_mask = mask;
6975         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6976         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6977
6978         si_set_max_cu_value(rdev);
6979
6980         rv770_get_max_vddc(rdev);
6981         si_get_leakage_vddc(rdev);
6982         si_patch_dependency_tables_based_on_leakage(rdev);
6983
6984         pi->acpi_vddc = 0;
6985         eg_pi->acpi_vddci = 0;
6986         pi->min_vddc_in_table = 0;
6987         pi->max_vddc_in_table = 0;
6988
6989         ret = r600_get_platform_caps(rdev);
6990         if (ret)
6991                 return ret;
6992
6993         ret = r600_parse_extended_power_table(rdev);
6994         if (ret)
6995                 return ret;
6996
6997         ret = si_parse_power_table(rdev);
6998         if (ret)
6999                 return ret;
7000
7001         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7002                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
7003         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7004                 r600_free_extended_power_table(rdev);
7005                 return -ENOMEM;
7006         }
7007         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7008         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7009         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7010         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7011         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7012         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7013         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7014         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7015         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7016
7017         if (rdev->pm.dpm.voltage_response_time == 0)
7018                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7019         if (rdev->pm.dpm.backbias_response_time == 0)
7020                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7021
7022         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
7023                                              0, false, &dividers);
7024         if (ret)
7025                 pi->ref_div = dividers.ref_div + 1;
7026         else
7027                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7028
7029         eg_pi->smu_uvd_hs = false;
7030
7031         pi->mclk_strobe_mode_threshold = 40000;
7032         if (si_is_special_1gb_platform(rdev))
7033                 pi->mclk_stutter_mode_threshold = 0;
7034         else
7035                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7036         pi->mclk_edc_enable_threshold = 40000;
7037         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7038
7039         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7040
7041         pi->voltage_control =
7042                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7043                                             VOLTAGE_OBJ_GPIO_LUT);
7044         if (!pi->voltage_control) {
7045                 si_pi->voltage_control_svi2 =
7046                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7047                                                     VOLTAGE_OBJ_SVID2);
7048                 if (si_pi->voltage_control_svi2)
7049                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7050                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7051         }
7052
7053         pi->mvdd_control =
7054                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7055                                             VOLTAGE_OBJ_GPIO_LUT);
7056
7057         eg_pi->vddci_control =
7058                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7059                                             VOLTAGE_OBJ_GPIO_LUT);
7060         if (!eg_pi->vddci_control)
7061                 si_pi->vddci_control_svi2 =
7062                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7063                                                     VOLTAGE_OBJ_SVID2);
7064
7065         si_pi->vddc_phase_shed_control =
7066                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7067                                             VOLTAGE_OBJ_PHASE_LUT);
7068
7069         rv770_get_engine_memory_ss(rdev);
7070
7071         pi->asi = RV770_ASI_DFLT;
7072         pi->pasi = CYPRESS_HASI_DFLT;
7073         pi->vrc = SISLANDS_VRC_DFLT;
7074
7075         pi->gfx_clock_gating = true;
7076
7077         eg_pi->sclk_deep_sleep = true;
7078         si_pi->sclk_deep_sleep_above_low = false;
7079
7080         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7081                 pi->thermal_protection = true;
7082         else
7083                 pi->thermal_protection = false;
7084
7085         eg_pi->dynamic_ac_timing = true;
7086
7087         eg_pi->light_sleep = true;
7088 #if defined(CONFIG_ACPI)
7089         eg_pi->pcie_performance_request =
7090                 radeon_acpi_is_pcie_performance_request_supported(rdev);
7091 #else
7092         eg_pi->pcie_performance_request = false;
7093 #endif
7094
7095         si_pi->sram_end = SMC_RAM_END;
7096
7097         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7098         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7099         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7100         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7101         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7102         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7103         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7104
7105         si_initialize_powertune_defaults(rdev);
7106
7107         /* make sure dc limits are valid */
7108         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7109             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7110                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7111                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7112
7113         si_pi->fan_ctrl_is_in_default_mode = true;
7114
7115         return 0;
7116 }
7117
7118 void si_dpm_fini(struct radeon_device *rdev)
7119 {
7120         int i;
7121
7122         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7123                 kfree(rdev->pm.dpm.ps[i].ps_priv);
7124         }
7125         kfree(rdev->pm.dpm.ps);
7126         kfree(rdev->pm.dpm.priv);
7127         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7128         r600_free_extended_power_table(rdev);
7129 }
7130
7131 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7132                                                     struct seq_file *m)
7133 {
7134         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7135         struct radeon_ps *rps = &eg_pi->current_rps;
7136         struct ni_ps *ps = ni_get_ps(rps);
7137         struct rv7xx_pl *pl;
7138         u32 current_index =
7139                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7140                 CURRENT_STATE_INDEX_SHIFT;
7141
7142         if (current_index >= ps->performance_level_count) {
7143                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7144         } else {
7145                 pl = &ps->performance_levels[current_index];
7146                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7147                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7148                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7149         }
7150 }
7151
7152 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7153 {
7154         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7155         struct radeon_ps *rps = &eg_pi->current_rps;
7156         struct ni_ps *ps = ni_get_ps(rps);
7157         struct rv7xx_pl *pl;
7158         u32 current_index =
7159                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7160                 CURRENT_STATE_INDEX_SHIFT;
7161
7162         if (current_index >= ps->performance_level_count) {
7163                 return 0;
7164         } else {
7165                 pl = &ps->performance_levels[current_index];
7166                 return pl->sclk;
7167         }
7168 }
7169
7170 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7171 {
7172         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7173         struct radeon_ps *rps = &eg_pi->current_rps;
7174         struct ni_ps *ps = ni_get_ps(rps);
7175         struct rv7xx_pl *pl;
7176         u32 current_index =
7177                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7178                 CURRENT_STATE_INDEX_SHIFT;
7179
7180         if (current_index >= ps->performance_level_count) {
7181                 return 0;
7182         } else {
7183                 pl = &ps->performance_levels[current_index];
7184                 return pl->mclk;
7185         }
7186 }