2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon_asic.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
39 #define SMC_RAM_END 0x20000
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
43 static const struct si_cac_config_reg cac_weights_tahiti[] =
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
108 static const struct si_cac_config_reg lcac_tahiti[] =
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
200 static const struct si_cac_config_reg cac_override_tahiti[] =
205 static const struct si_powertune_data powertune_data_tahiti =
236 static const struct si_dte_data dte_data_tahiti =
238 { 1159409, 0, 0, 0, 0 },
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
254 static const struct si_dte_data dte_data_tahiti_le =
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
272 static const struct si_dte_data dte_data_tahiti_pro =
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
290 static const struct si_dte_data dte_data_new_zealand =
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
308 static const struct si_dte_data dte_data_aruba_pro =
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
326 static const struct si_dte_data dte_data_malta =
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
344 struct si_cac_config_reg cac_weights_pitcairn[] =
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
409 static const struct si_cac_config_reg lcac_pitcairn[] =
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
500 static const struct si_cac_config_reg cac_override_pitcairn[] =
505 static const struct si_powertune_data powertune_data_pitcairn =
536 static const struct si_dte_data dte_data_pitcairn =
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
554 static const struct si_dte_data dte_data_curacao_xt =
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
572 static const struct si_dte_data dte_data_curacao_pro =
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
590 static const struct si_dte_data dte_data_neptune_xt =
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
738 static const struct si_cac_config_reg cac_weights_heathrow[] =
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
933 static const struct si_cac_config_reg lcac_cape_verde[] =
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
992 static const struct si_cac_config_reg cac_override_cape_verde[] =
997 static const struct si_powertune_data powertune_data_cape_verde =
999 ((1 << 16) | 0x6993),
1028 static const struct si_dte_data dte_data_cape_verde =
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1046 static const struct si_dte_data dte_data_venus_xtx =
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1064 static const struct si_dte_data dte_data_venus_xt =
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1082 static const struct si_dte_data dte_data_venus_pro =
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1100 struct si_cac_config_reg cac_weights_oland[] =
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1425 static const struct si_cac_config_reg lcac_oland[] =
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519 static const struct si_cac_config_reg cac_override_oland[] =
1524 static const struct si_powertune_data powertune_data_oland =
1526 ((1 << 16) | 0x6993),
1555 static const struct si_powertune_data powertune_data_mars_pro =
1557 ((1 << 16) | 0x6993),
1586 static const struct si_dte_data dte_data_oland =
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1604 static const struct si_dte_data dte_data_mars_pro =
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1622 static const struct si_dte_data dte_data_sun_xt =
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1706 static const struct si_powertune_data powertune_data_hainan =
1708 ((1 << 16) | 0x6993),
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1850 for (i = 0; i < k; i++) {
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1879 switch (rdev->pdev->device) {
1881 si_pi->dte_data.enable_dte_by_default = true;
1884 si_pi->dte_data = dte_data_new_zealand;
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1948 switch (rdev->pdev->device) {
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1959 update_dte_from_pl2 = true;
1963 si_pi->cac_weights = cac_weights_heathrow;
1964 si_pi->dte_data = dte_data_cape_verde;
1968 si_pi->cac_weights = cac_weights_chelsea_xt;
1969 si_pi->dte_data = dte_data_cape_verde;
1972 si_pi->cac_weights = cac_weights_chelsea_pro;
1973 si_pi->dte_data = dte_data_cape_verde;
1976 si_pi->cac_weights = cac_weights_heathrow;
1977 si_pi->dte_data = dte_data_venus_xtx;
1980 si_pi->cac_weights = cac_weights_heathrow;
1981 si_pi->dte_data = dte_data_venus_xt;
1987 si_pi->cac_weights = cac_weights_chelsea_pro;
1988 si_pi->dte_data = dte_data_venus_pro;
1991 si_pi->cac_weights = cac_weights_cape_verde;
1992 si_pi->dte_data = dte_data_cape_verde;
1995 } else if (rdev->family == CHIP_OLAND) {
1996 switch (rdev->pdev->device) {
2001 si_pi->cac_weights = cac_weights_mars_pro;
2002 si_pi->lcac_config = lcac_mars_pro;
2003 si_pi->cac_override = cac_override_oland;
2004 si_pi->powertune_data = &powertune_data_mars_pro;
2005 si_pi->dte_data = dte_data_mars_pro;
2006 update_dte_from_pl2 = true;
2012 si_pi->cac_weights = cac_weights_mars_xt;
2013 si_pi->lcac_config = lcac_mars_pro;
2014 si_pi->cac_override = cac_override_oland;
2015 si_pi->powertune_data = &powertune_data_mars_pro;
2016 si_pi->dte_data = dte_data_mars_pro;
2017 update_dte_from_pl2 = true;
2022 si_pi->cac_weights = cac_weights_oland_pro;
2023 si_pi->lcac_config = lcac_mars_pro;
2024 si_pi->cac_override = cac_override_oland;
2025 si_pi->powertune_data = &powertune_data_mars_pro;
2026 si_pi->dte_data = dte_data_mars_pro;
2027 update_dte_from_pl2 = true;
2030 si_pi->cac_weights = cac_weights_oland_xt;
2031 si_pi->lcac_config = lcac_mars_pro;
2032 si_pi->cac_override = cac_override_oland;
2033 si_pi->powertune_data = &powertune_data_mars_pro;
2034 si_pi->dte_data = dte_data_mars_pro;
2035 update_dte_from_pl2 = true;
2038 si_pi->cac_weights = cac_weights_oland;
2039 si_pi->lcac_config = lcac_oland;
2040 si_pi->cac_override = cac_override_oland;
2041 si_pi->powertune_data = &powertune_data_oland;
2042 si_pi->dte_data = dte_data_oland;
2045 } else if (rdev->family == CHIP_HAINAN) {
2046 si_pi->cac_weights = cac_weights_hainan;
2047 si_pi->lcac_config = lcac_oland;
2048 si_pi->cac_override = cac_override_oland;
2049 si_pi->powertune_data = &powertune_data_hainan;
2050 si_pi->dte_data = dte_data_sun_xt;
2051 update_dte_from_pl2 = true;
2053 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2057 ni_pi->enable_power_containment = false;
2058 ni_pi->enable_cac = false;
2059 ni_pi->enable_sq_ramping = false;
2060 si_pi->enable_dte = false;
2062 if (si_pi->powertune_data->enable_powertune_by_default) {
2063 ni_pi->enable_power_containment= true;
2064 ni_pi->enable_cac = true;
2065 if (si_pi->dte_data.enable_dte_by_default) {
2066 si_pi->enable_dte = true;
2067 if (update_dte_from_pl2)
2068 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2071 ni_pi->enable_sq_ramping = true;
2074 ni_pi->driver_calculate_cac_leakage = true;
2075 ni_pi->cac_configuration_required = true;
2077 if (ni_pi->cac_configuration_required) {
2078 ni_pi->support_cac_long_term_average = true;
2079 si_pi->dyn_powertune_data.l2_lta_window_size =
2080 si_pi->powertune_data->l2_lta_window_size_default;
2081 si_pi->dyn_powertune_data.lts_truncate =
2082 si_pi->powertune_data->lts_truncate_default;
2084 ni_pi->support_cac_long_term_average = false;
2085 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2086 si_pi->dyn_powertune_data.lts_truncate = 0;
2089 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2092 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2097 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2102 u32 cac_window_size;
2104 xclk = radeon_get_xclk(rdev);
2109 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2110 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2112 wintime = (cac_window_size * 100) / xclk;
2117 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2119 return power_in_watts;
2122 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2123 bool adjust_polarity,
2126 u32 *near_tdp_limit)
2128 u32 adjustment_delta, max_tdp_limit;
2130 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2133 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2135 if (adjust_polarity) {
2136 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2139 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2140 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2141 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2142 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2144 *near_tdp_limit = 0;
2147 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2149 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2155 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2156 struct radeon_ps *radeon_state)
2158 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2159 struct si_power_info *si_pi = si_get_pi(rdev);
2161 if (ni_pi->enable_power_containment) {
2162 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2163 PP_SIslands_PAPMParameters *papm_parm;
2164 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2165 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2170 if (scaling_factor == 0)
2173 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2175 ret = si_calculate_adjusted_tdp_limits(rdev,
2177 rdev->pm.dpm.tdp_adjustment,
2183 smc_table->dpm2Params.TDPLimit =
2184 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2185 smc_table->dpm2Params.NearTDPLimit =
2186 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2187 smc_table->dpm2Params.SafePowerLimit =
2188 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2190 ret = si_copy_bytes_to_smc(rdev,
2191 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2192 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2193 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2199 if (si_pi->enable_ppm) {
2200 papm_parm = &si_pi->papm_parm;
2201 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2202 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2203 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2204 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2205 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2206 papm_parm->PlatformPowerLimit = 0xffffffff;
2207 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2209 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2211 sizeof(PP_SIslands_PAPMParameters),
2220 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2221 struct radeon_ps *radeon_state)
2223 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2224 struct si_power_info *si_pi = si_get_pi(rdev);
2226 if (ni_pi->enable_power_containment) {
2227 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2228 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2231 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2233 smc_table->dpm2Params.NearTDPLimit =
2234 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2235 smc_table->dpm2Params.SafePowerLimit =
2236 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2238 ret = si_copy_bytes_to_smc(rdev,
2239 (si_pi->state_table_start +
2240 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2241 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2242 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2252 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2253 const u16 prev_std_vddc,
2254 const u16 curr_std_vddc)
2256 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2257 u64 prev_vddc = (u64)prev_std_vddc;
2258 u64 curr_vddc = (u64)curr_std_vddc;
2259 u64 pwr_efficiency_ratio, n, d;
2261 if ((prev_vddc == 0) || (curr_vddc == 0))
2264 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2265 d = prev_vddc * prev_vddc;
2266 pwr_efficiency_ratio = div64_u64(n, d);
2268 if (pwr_efficiency_ratio > (u64)0xFFFF)
2271 return (u16)pwr_efficiency_ratio;
2274 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2275 struct radeon_ps *radeon_state)
2277 struct si_power_info *si_pi = si_get_pi(rdev);
2279 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2280 radeon_state->vclk && radeon_state->dclk)
2286 static int si_populate_power_containment_values(struct radeon_device *rdev,
2287 struct radeon_ps *radeon_state,
2288 SISLANDS_SMC_SWSTATE *smc_state)
2290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2291 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2292 struct ni_ps *state = ni_get_ps(radeon_state);
2293 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2300 u16 pwr_efficiency_ratio;
2302 bool disable_uvd_power_tune;
2305 if (ni_pi->enable_power_containment == false)
2308 if (state->performance_level_count == 0)
2311 if (smc_state->levelCount != state->performance_level_count)
2314 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2316 smc_state->levels[0].dpm2.MaxPS = 0;
2317 smc_state->levels[0].dpm2.NearTDPDec = 0;
2318 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2319 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2320 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2322 for (i = 1; i < state->performance_level_count; i++) {
2323 prev_sclk = state->performance_levels[i-1].sclk;
2324 max_sclk = state->performance_levels[i].sclk;
2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2328 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2330 if (prev_sclk > max_sclk)
2333 if ((max_ps_percent == 0) ||
2334 (prev_sclk == max_sclk) ||
2335 disable_uvd_power_tune) {
2336 min_sclk = max_sclk;
2337 } else if (i == 1) {
2338 min_sclk = prev_sclk;
2340 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2343 if (min_sclk < state->performance_levels[0].sclk)
2344 min_sclk = state->performance_levels[0].sclk;
2349 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2350 state->performance_levels[i-1].vddc, &vddc);
2354 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2359 state->performance_levels[i].vddc, &vddc);
2363 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2367 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2368 prev_std_vddc, curr_std_vddc);
2370 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2371 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2372 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2373 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2374 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2380 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2381 struct radeon_ps *radeon_state,
2382 SISLANDS_SMC_SWSTATE *smc_state)
2384 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2385 struct ni_ps *state = ni_get_ps(radeon_state);
2386 u32 sq_power_throttle, sq_power_throttle2;
2387 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2390 if (state->performance_level_count == 0)
2393 if (smc_state->levelCount != state->performance_level_count)
2396 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2399 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2400 enable_sq_ramping = false;
2402 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2403 enable_sq_ramping = false;
2405 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2406 enable_sq_ramping = false;
2408 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2409 enable_sq_ramping = false;
2411 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2412 enable_sq_ramping = false;
2414 for (i = 0; i < state->performance_level_count; i++) {
2415 sq_power_throttle = 0;
2416 sq_power_throttle2 = 0;
2418 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2419 enable_sq_ramping) {
2420 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2421 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2422 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2423 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2424 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2426 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2427 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2430 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2431 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2437 static int si_enable_power_containment(struct radeon_device *rdev,
2438 struct radeon_ps *radeon_new_state,
2441 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2442 PPSMC_Result smc_result;
2445 if (ni_pi->enable_power_containment) {
2447 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2448 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2449 if (smc_result != PPSMC_Result_OK) {
2451 ni_pi->pc_enabled = false;
2453 ni_pi->pc_enabled = true;
2457 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2458 if (smc_result != PPSMC_Result_OK)
2460 ni_pi->pc_enabled = false;
2467 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2469 struct si_power_info *si_pi = si_get_pi(rdev);
2471 struct si_dte_data *dte_data = &si_pi->dte_data;
2472 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2477 if (dte_data == NULL)
2478 si_pi->enable_dte = false;
2480 if (si_pi->enable_dte == false)
2483 if (dte_data->k <= 0)
2486 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2487 if (dte_tables == NULL) {
2488 si_pi->enable_dte = false;
2492 table_size = dte_data->k;
2494 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2495 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2497 tdep_count = dte_data->tdep_count;
2498 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2499 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2501 dte_tables->K = cpu_to_be32(table_size);
2502 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2503 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2504 dte_tables->WindowSize = dte_data->window_size;
2505 dte_tables->temp_select = dte_data->temp_select;
2506 dte_tables->DTE_mode = dte_data->dte_mode;
2507 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2512 for (i = 0; i < table_size; i++) {
2513 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2514 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2517 dte_tables->Tdep_count = tdep_count;
2519 for (i = 0; i < (u32)tdep_count; i++) {
2520 dte_tables->T_limits[i] = dte_data->t_limits[i];
2521 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2522 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2525 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2526 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2532 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2535 struct si_power_info *si_pi = si_get_pi(rdev);
2536 struct radeon_cac_leakage_table *table =
2537 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2548 for (i = 0; i < table->count; i++) {
2549 if (table->entries[i].vddc > *max)
2550 *max = table->entries[i].vddc;
2551 if (table->entries[i].vddc < *min)
2552 *min = table->entries[i].vddc;
2555 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2558 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2560 if (v0_loadline > 0xFFFFUL)
2563 *min = (u16)v0_loadline;
2565 if ((*min > *max) || (*max == 0) || (*min == 0))
2571 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2573 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2574 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2577 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2578 PP_SIslands_CacConfig *cac_tables,
2579 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2582 struct si_power_info *si_pi = si_get_pi(rdev);
2590 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2592 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2593 t = (1000 * (i * t_step + t0));
2595 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2596 voltage = vddc_max - (vddc_step * j);
2598 si_calculate_leakage_for_v_and_t(rdev,
2599 &si_pi->powertune_data->leakage_coefficients,
2602 si_pi->dyn_powertune_data.cac_leakage,
2605 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2607 if (smc_leakage > 0xFFFF)
2608 smc_leakage = 0xFFFF;
2610 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2611 cpu_to_be16((u16)smc_leakage);
2617 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2618 PP_SIslands_CacConfig *cac_tables,
2619 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2621 struct si_power_info *si_pi = si_get_pi(rdev);
2628 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2630 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2631 voltage = vddc_max - (vddc_step * j);
2633 si_calculate_leakage_for_v(rdev,
2634 &si_pi->powertune_data->leakage_coefficients,
2635 si_pi->powertune_data->fixed_kt,
2637 si_pi->dyn_powertune_data.cac_leakage,
2640 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2642 if (smc_leakage > 0xFFFF)
2643 smc_leakage = 0xFFFF;
2645 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2646 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2647 cpu_to_be16((u16)smc_leakage);
2652 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2654 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2655 struct si_power_info *si_pi = si_get_pi(rdev);
2656 PP_SIslands_CacConfig *cac_tables = NULL;
2657 u16 vddc_max, vddc_min, vddc_step;
2659 u32 load_line_slope, reg;
2661 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2663 if (ni_pi->enable_cac == false)
2666 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2670 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2671 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2672 WREG32(CG_CAC_CTRL, reg);
2674 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2675 si_pi->dyn_powertune_data.dc_pwr_value =
2676 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2677 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2678 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2680 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2682 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2686 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2687 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2691 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2692 ret = si_init_dte_leakage_table(rdev, cac_tables,
2693 vddc_max, vddc_min, vddc_step,
2696 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2697 vddc_max, vddc_min, vddc_step);
2701 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2703 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2704 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2705 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2706 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2707 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2708 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2709 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2710 cac_tables->calculation_repeats = cpu_to_be32(2);
2711 cac_tables->dc_cac = cpu_to_be32(0);
2712 cac_tables->log2_PG_LKG_SCALE = 12;
2713 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2714 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2715 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2717 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2718 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2723 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2727 ni_pi->enable_cac = false;
2728 ni_pi->enable_power_containment = false;
2736 static int si_program_cac_config_registers(struct radeon_device *rdev,
2737 const struct si_cac_config_reg *cac_config_regs)
2739 const struct si_cac_config_reg *config_regs = cac_config_regs;
2740 u32 data = 0, offset;
2745 while (config_regs->offset != 0xFFFFFFFF) {
2746 switch (config_regs->type) {
2747 case SISLANDS_CACCONFIG_CGIND:
2748 offset = SMC_CG_IND_START + config_regs->offset;
2749 if (offset < SMC_CG_IND_END)
2750 data = RREG32_SMC(offset);
2753 data = RREG32(config_regs->offset << 2);
2757 data &= ~config_regs->mask;
2758 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2760 switch (config_regs->type) {
2761 case SISLANDS_CACCONFIG_CGIND:
2762 offset = SMC_CG_IND_START + config_regs->offset;
2763 if (offset < SMC_CG_IND_END)
2764 WREG32_SMC(offset, data);
2767 WREG32(config_regs->offset << 2, data);
2775 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2777 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2778 struct si_power_info *si_pi = si_get_pi(rdev);
2781 if ((ni_pi->enable_cac == false) ||
2782 (ni_pi->cac_configuration_required == false))
2785 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2788 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2791 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2798 static int si_enable_smc_cac(struct radeon_device *rdev,
2799 struct radeon_ps *radeon_new_state,
2802 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2803 struct si_power_info *si_pi = si_get_pi(rdev);
2804 PPSMC_Result smc_result;
2807 if (ni_pi->enable_cac) {
2809 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2810 if (ni_pi->support_cac_long_term_average) {
2811 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2812 if (smc_result != PPSMC_Result_OK)
2813 ni_pi->support_cac_long_term_average = false;
2816 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2817 if (smc_result != PPSMC_Result_OK) {
2819 ni_pi->cac_enabled = false;
2821 ni_pi->cac_enabled = true;
2824 if (si_pi->enable_dte) {
2825 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2826 if (smc_result != PPSMC_Result_OK)
2830 } else if (ni_pi->cac_enabled) {
2831 if (si_pi->enable_dte)
2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2834 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2836 ni_pi->cac_enabled = false;
2838 if (ni_pi->support_cac_long_term_average)
2839 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2845 static int si_init_smc_spll_table(struct radeon_device *rdev)
2847 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2848 struct si_power_info *si_pi = si_get_pi(rdev);
2849 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2850 SISLANDS_SMC_SCLK_VALUE sclk_params;
2858 if (si_pi->spll_table_start == 0)
2861 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2862 if (spll_table == NULL)
2865 for (i = 0; i < 256; i++) {
2866 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2870 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2871 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2872 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2873 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2875 fb_div &= ~0x00001FFF;
2879 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2881 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2883 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2885 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2891 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2892 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2893 spll_table->freq[i] = cpu_to_be32(tmp);
2895 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2896 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2897 spll_table->ss[i] = cpu_to_be32(tmp);
2904 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2905 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2909 ni_pi->enable_power_containment = false;
2916 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2919 u16 highest_leakage = 0;
2920 struct si_power_info *si_pi = si_get_pi(rdev);
2923 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2924 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2925 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2928 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2929 return highest_leakage;
2934 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2935 u32 evclk, u32 ecclk, u16 *voltage)
2939 struct radeon_vce_clock_voltage_dependency_table *table =
2940 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2942 if (((evclk == 0) && (ecclk == 0)) ||
2943 (table && (table->count == 0))) {
2948 for (i = 0; i < table->count; i++) {
2949 if ((evclk <= table->entries[i].evclk) &&
2950 (ecclk <= table->entries[i].ecclk)) {
2951 *voltage = table->entries[i].v;
2957 /* if no match return the highest voltage */
2959 *voltage = table->entries[table->count - 1].v;
2961 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2966 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2967 struct radeon_ps *rps)
2969 struct ni_ps *ps = ni_get_ps(rps);
2970 struct radeon_clock_and_voltage_limits *max_limits;
2971 bool disable_mclk_switching = false;
2972 bool disable_sclk_switching = false;
2974 u16 vddc, vddci, min_vce_voltage = 0;
2975 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2976 u32 max_sclk = 0, max_mclk = 0;
2979 if (rdev->family == CHIP_HAINAN) {
2980 if ((rdev->pdev->revision == 0x81) ||
2981 (rdev->pdev->revision == 0x83) ||
2982 (rdev->pdev->revision == 0xC3) ||
2983 (rdev->pdev->device == 0x6664) ||
2984 (rdev->pdev->device == 0x6665) ||
2985 (rdev->pdev->device == 0x6667)) {
2988 if ((rdev->pdev->revision == 0xC3) ||
2989 (rdev->pdev->device == 0x6665)) {
2993 } else if (rdev->family == CHIP_OLAND) {
2994 if ((rdev->pdev->revision == 0xC7) ||
2995 (rdev->pdev->revision == 0x80) ||
2996 (rdev->pdev->revision == 0x81) ||
2997 (rdev->pdev->revision == 0x83) ||
2998 (rdev->pdev->revision == 0x87) ||
2999 (rdev->pdev->device == 0x6604) ||
3000 (rdev->pdev->device == 0x6605)) {
3004 if (rdev->pm.dpm.high_pixelclock_count > 1)
3005 disable_sclk_switching = true;
3008 if (rps->vce_active) {
3009 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3010 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3011 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3018 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3019 ni_dpm_vblank_too_short(rdev))
3020 disable_mclk_switching = true;
3022 if (rps->vclk || rps->dclk) {
3023 disable_mclk_switching = true;
3024 disable_sclk_switching = true;
3027 if (rdev->pm.dpm.ac_power)
3028 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3030 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3032 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3033 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3034 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3036 if (rdev->pm.dpm.ac_power == false) {
3037 for (i = 0; i < ps->performance_level_count; i++) {
3038 if (ps->performance_levels[i].mclk > max_limits->mclk)
3039 ps->performance_levels[i].mclk = max_limits->mclk;
3040 if (ps->performance_levels[i].sclk > max_limits->sclk)
3041 ps->performance_levels[i].sclk = max_limits->sclk;
3042 if (ps->performance_levels[i].vddc > max_limits->vddc)
3043 ps->performance_levels[i].vddc = max_limits->vddc;
3044 if (ps->performance_levels[i].vddci > max_limits->vddci)
3045 ps->performance_levels[i].vddci = max_limits->vddci;
3049 /* limit clocks to max supported clocks based on voltage dependency tables */
3050 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3052 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3054 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3057 for (i = 0; i < ps->performance_level_count; i++) {
3058 if (max_sclk_vddc) {
3059 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3060 ps->performance_levels[i].sclk = max_sclk_vddc;
3062 if (max_mclk_vddci) {
3063 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3064 ps->performance_levels[i].mclk = max_mclk_vddci;
3066 if (max_mclk_vddc) {
3067 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3068 ps->performance_levels[i].mclk = max_mclk_vddc;
3071 if (ps->performance_levels[i].mclk > max_mclk)
3072 ps->performance_levels[i].mclk = max_mclk;
3075 if (ps->performance_levels[i].sclk > max_sclk)
3076 ps->performance_levels[i].sclk = max_sclk;
3080 /* XXX validate the min clocks required for display */
3082 if (disable_mclk_switching) {
3083 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3084 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3086 mclk = ps->performance_levels[0].mclk;
3087 vddci = ps->performance_levels[0].vddci;
3090 if (disable_sclk_switching) {
3091 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3092 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3094 sclk = ps->performance_levels[0].sclk;
3095 vddc = ps->performance_levels[0].vddc;
3098 if (rps->vce_active) {
3099 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3100 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3101 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3102 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3105 /* adjusted low state */
3106 ps->performance_levels[0].sclk = sclk;
3107 ps->performance_levels[0].mclk = mclk;
3108 ps->performance_levels[0].vddc = vddc;
3109 ps->performance_levels[0].vddci = vddci;
3111 if (disable_sclk_switching) {
3112 sclk = ps->performance_levels[0].sclk;
3113 for (i = 1; i < ps->performance_level_count; i++) {
3114 if (sclk < ps->performance_levels[i].sclk)
3115 sclk = ps->performance_levels[i].sclk;
3117 for (i = 0; i < ps->performance_level_count; i++) {
3118 ps->performance_levels[i].sclk = sclk;
3119 ps->performance_levels[i].vddc = vddc;
3122 for (i = 1; i < ps->performance_level_count; i++) {
3123 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3124 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3125 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3126 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3130 if (disable_mclk_switching) {
3131 mclk = ps->performance_levels[0].mclk;
3132 for (i = 1; i < ps->performance_level_count; i++) {
3133 if (mclk < ps->performance_levels[i].mclk)
3134 mclk = ps->performance_levels[i].mclk;
3136 for (i = 0; i < ps->performance_level_count; i++) {
3137 ps->performance_levels[i].mclk = mclk;
3138 ps->performance_levels[i].vddci = vddci;
3141 for (i = 1; i < ps->performance_level_count; i++) {
3142 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3143 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3144 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3145 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3149 for (i = 0; i < ps->performance_level_count; i++)
3150 btc_adjust_clock_combinations(rdev, max_limits,
3151 &ps->performance_levels[i]);
3153 for (i = 0; i < ps->performance_level_count; i++) {
3154 if (ps->performance_levels[i].vddc < min_vce_voltage)
3155 ps->performance_levels[i].vddc = min_vce_voltage;
3156 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3157 ps->performance_levels[i].sclk,
3158 max_limits->vddc, &ps->performance_levels[i].vddc);
3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3160 ps->performance_levels[i].mclk,
3161 max_limits->vddci, &ps->performance_levels[i].vddci);
3162 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3163 ps->performance_levels[i].mclk,
3164 max_limits->vddc, &ps->performance_levels[i].vddc);
3165 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3166 rdev->clock.current_dispclk,
3167 max_limits->vddc, &ps->performance_levels[i].vddc);
3170 for (i = 0; i < ps->performance_level_count; i++) {
3171 btc_apply_voltage_delta_rules(rdev,
3172 max_limits->vddc, max_limits->vddci,
3173 &ps->performance_levels[i].vddc,
3174 &ps->performance_levels[i].vddci);
3177 ps->dc_compatible = true;
3178 for (i = 0; i < ps->performance_level_count; i++) {
3179 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3180 ps->dc_compatible = false;
3185 static int si_read_smc_soft_register(struct radeon_device *rdev,
3186 u16 reg_offset, u32 *value)
3188 struct si_power_info *si_pi = si_get_pi(rdev);
3190 return si_read_smc_sram_dword(rdev,
3191 si_pi->soft_regs_start + reg_offset, value,
3196 static int si_write_smc_soft_register(struct radeon_device *rdev,
3197 u16 reg_offset, u32 value)
3199 struct si_power_info *si_pi = si_get_pi(rdev);
3201 return si_write_smc_sram_dword(rdev,
3202 si_pi->soft_regs_start + reg_offset,
3203 value, si_pi->sram_end);
3206 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3209 u32 tmp, width, row, column, bank, density;
3210 bool is_memory_gddr5, is_special;
3212 tmp = RREG32(MC_SEQ_MISC0);
3213 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3214 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3215 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3217 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3218 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3220 tmp = RREG32(MC_ARB_RAMCFG);
3221 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3222 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3223 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3225 density = (1 << (row + column - 20 + bank)) * width;
3227 if ((rdev->pdev->device == 0x6819) &&
3228 is_memory_gddr5 && is_special && (density == 0x400))
3234 static void si_get_leakage_vddc(struct radeon_device *rdev)
3236 struct si_power_info *si_pi = si_get_pi(rdev);
3237 u16 vddc, count = 0;
3240 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3241 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3243 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3244 si_pi->leakage_voltage.entries[count].voltage = vddc;
3245 si_pi->leakage_voltage.entries[count].leakage_index =
3246 SISLANDS_LEAKAGE_INDEX0 + i;
3250 si_pi->leakage_voltage.count = count;
3253 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3254 u32 index, u16 *leakage_voltage)
3256 struct si_power_info *si_pi = si_get_pi(rdev);
3259 if (leakage_voltage == NULL)
3262 if ((index & 0xff00) != 0xff00)
3265 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3268 if (index < SISLANDS_LEAKAGE_INDEX0)
3271 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3272 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3273 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3280 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3282 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3283 bool want_thermal_protection;
3284 enum radeon_dpm_event_src dpm_event_src;
3289 want_thermal_protection = false;
3291 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3292 want_thermal_protection = true;
3293 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3295 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3296 want_thermal_protection = true;
3297 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3299 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3300 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3301 want_thermal_protection = true;
3302 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3306 if (want_thermal_protection) {
3307 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3308 if (pi->thermal_protection)
3309 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3311 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3315 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3316 enum radeon_dpm_auto_throttle_src source,
3319 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3322 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3323 pi->active_auto_throttle_sources |= 1 << source;
3324 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3327 if (pi->active_auto_throttle_sources & (1 << source)) {
3328 pi->active_auto_throttle_sources &= ~(1 << source);
3329 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3334 static void si_start_dpm(struct radeon_device *rdev)
3336 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3339 static void si_stop_dpm(struct radeon_device *rdev)
3341 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3344 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3347 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3349 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3354 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3359 if (thermal_level == 0) {
3360 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3361 if (ret == PPSMC_Result_OK)
3369 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3371 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3376 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3379 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3386 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3387 PPSMC_Msg msg, u32 parameter)
3389 WREG32(SMC_SCRATCH0, parameter);
3390 return si_send_msg_to_smc(rdev, msg);
3393 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3395 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3398 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3402 int si_dpm_force_performance_level(struct radeon_device *rdev,
3403 enum radeon_dpm_forced_level level)
3405 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3406 struct ni_ps *ps = ni_get_ps(rps);
3407 u32 levels = ps->performance_level_count;
3409 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3410 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3413 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3415 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3416 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3419 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3421 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3422 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3425 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3429 rdev->pm.dpm.forced_level = level;
3435 static int si_set_boot_state(struct radeon_device *rdev)
3437 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3442 static int si_set_sw_state(struct radeon_device *rdev)
3444 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3448 static int si_halt_smc(struct radeon_device *rdev)
3450 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3453 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3457 static int si_resume_smc(struct radeon_device *rdev)
3459 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3462 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3466 static void si_dpm_start_smc(struct radeon_device *rdev)
3468 si_program_jump_on_start(rdev);
3470 si_start_smc_clock(rdev);
3473 static void si_dpm_stop_smc(struct radeon_device *rdev)
3476 si_stop_smc_clock(rdev);
3479 static int si_process_firmware_header(struct radeon_device *rdev)
3481 struct si_power_info *si_pi = si_get_pi(rdev);
3485 ret = si_read_smc_sram_dword(rdev,
3486 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3487 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3488 &tmp, si_pi->sram_end);
3492 si_pi->state_table_start = tmp;
3494 ret = si_read_smc_sram_dword(rdev,
3495 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3496 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3497 &tmp, si_pi->sram_end);
3501 si_pi->soft_regs_start = tmp;
3503 ret = si_read_smc_sram_dword(rdev,
3504 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3505 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3506 &tmp, si_pi->sram_end);
3510 si_pi->mc_reg_table_start = tmp;
3512 ret = si_read_smc_sram_dword(rdev,
3513 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3514 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3515 &tmp, si_pi->sram_end);
3519 si_pi->fan_table_start = tmp;
3521 ret = si_read_smc_sram_dword(rdev,
3522 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3523 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3524 &tmp, si_pi->sram_end);
3528 si_pi->arb_table_start = tmp;
3530 ret = si_read_smc_sram_dword(rdev,
3531 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3532 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3533 &tmp, si_pi->sram_end);
3537 si_pi->cac_table_start = tmp;
3539 ret = si_read_smc_sram_dword(rdev,
3540 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3541 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3542 &tmp, si_pi->sram_end);
3546 si_pi->dte_table_start = tmp;
3548 ret = si_read_smc_sram_dword(rdev,
3549 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3550 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3551 &tmp, si_pi->sram_end);
3555 si_pi->spll_table_start = tmp;
3557 ret = si_read_smc_sram_dword(rdev,
3558 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3559 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3560 &tmp, si_pi->sram_end);
3564 si_pi->papm_cfg_table_start = tmp;
3569 static void si_read_clock_registers(struct radeon_device *rdev)
3571 struct si_power_info *si_pi = si_get_pi(rdev);
3573 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3574 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3575 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3576 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3577 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3578 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3579 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3580 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3581 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3582 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3583 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3584 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3585 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3586 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3587 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3590 static void si_enable_thermal_protection(struct radeon_device *rdev,
3594 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3596 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3599 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3601 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3605 static int si_enter_ulp_state(struct radeon_device *rdev)
3607 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3614 static int si_exit_ulp_state(struct radeon_device *rdev)
3618 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3622 for (i = 0; i < rdev->usec_timeout; i++) {
3623 if (RREG32(SMC_RESP_0) == 1)
3632 static int si_notify_smc_display_change(struct radeon_device *rdev,
3635 PPSMC_Msg msg = has_display ?
3636 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3638 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3642 static void si_program_response_times(struct radeon_device *rdev)
3644 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3645 u32 vddc_dly, acpi_dly, vbi_dly;
3646 u32 reference_clock;
3648 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3650 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3651 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3653 if (voltage_response_time == 0)
3654 voltage_response_time = 1000;
3656 acpi_delay_time = 15000;
3657 vbi_time_out = 100000;
3659 reference_clock = radeon_get_xclk(rdev);
3661 vddc_dly = (voltage_response_time * reference_clock) / 100;
3662 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3663 vbi_dly = (vbi_time_out * reference_clock) / 100;
3665 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3666 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3667 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3668 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3671 static void si_program_ds_registers(struct radeon_device *rdev)
3673 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3674 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3676 if (eg_pi->sclk_deep_sleep) {
3677 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3678 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3679 ~AUTOSCALE_ON_SS_CLEAR);
3683 static void si_program_display_gap(struct radeon_device *rdev)
3688 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3689 if (rdev->pm.dpm.new_active_crtc_count > 0)
3690 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3692 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3694 if (rdev->pm.dpm.new_active_crtc_count > 1)
3695 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3697 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3699 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3701 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3702 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3704 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3705 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3706 /* find the first active crtc */
3707 for (i = 0; i < rdev->num_crtc; i++) {
3708 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3711 if (i == rdev->num_crtc)
3716 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3717 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3718 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3721 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3722 * This can be a problem on PowerXpress systems or if you want to use the card
3723 * for offscreen rendering or compute if there are no crtcs enabled.
3725 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3728 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3730 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3734 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3736 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3737 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3741 static void si_setup_bsp(struct radeon_device *rdev)
3743 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3744 u32 xclk = radeon_get_xclk(rdev);
3746 r600_calculate_u_and_p(pi->asi,
3752 r600_calculate_u_and_p(pi->pasi,
3759 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3760 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3762 WREG32(CG_BSP, pi->dsp);
3765 static void si_program_git(struct radeon_device *rdev)
3767 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3770 static void si_program_tp(struct radeon_device *rdev)
3773 enum r600_td td = R600_TD_DFLT;
3775 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3776 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3778 if (td == R600_TD_AUTO)
3779 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3781 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3783 if (td == R600_TD_UP)
3784 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3786 if (td == R600_TD_DOWN)
3787 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3790 static void si_program_tpp(struct radeon_device *rdev)
3792 WREG32(CG_TPC, R600_TPC_DFLT);
3795 static void si_program_sstp(struct radeon_device *rdev)
3797 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3800 static void si_enable_display_gap(struct radeon_device *rdev)
3802 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3804 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3805 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3806 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3808 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3809 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3810 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3811 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3814 static void si_program_vc(struct radeon_device *rdev)
3816 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3818 WREG32(CG_FTV, pi->vrc);
3821 static void si_clear_vc(struct radeon_device *rdev)
3826 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3830 if (memory_clock < 10000)
3832 else if (memory_clock >= 80000)
3833 mc_para_index = 0x0f;
3835 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3836 return mc_para_index;
3839 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3844 if (memory_clock < 12500)
3845 mc_para_index = 0x00;
3846 else if (memory_clock > 47500)
3847 mc_para_index = 0x0f;
3849 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3851 if (memory_clock < 65000)
3852 mc_para_index = 0x00;
3853 else if (memory_clock > 135000)
3854 mc_para_index = 0x0f;
3856 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3858 return mc_para_index;
3861 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3863 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3864 bool strobe_mode = false;
3867 if (mclk <= pi->mclk_strobe_mode_threshold)
3871 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3873 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3876 result |= SISLANDS_SMC_STROBE_ENABLE;
3881 static int si_upload_firmware(struct radeon_device *rdev)
3883 struct si_power_info *si_pi = si_get_pi(rdev);
3887 si_stop_smc_clock(rdev);
3889 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3894 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3895 const struct atom_voltage_table *table,
3896 const struct radeon_phase_shedding_limits_table *limits)
3898 u32 data, num_bits, num_levels;
3900 if ((table == NULL) || (limits == NULL))
3903 data = table->mask_low;
3905 num_bits = hweight32(data);
3910 num_levels = (1 << num_bits);
3912 if (table->count != num_levels)
3915 if (limits->count != (num_levels - 1))
3921 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3922 u32 max_voltage_steps,
3923 struct atom_voltage_table *voltage_table)
3925 unsigned int i, diff;
3927 if (voltage_table->count <= max_voltage_steps)
3930 diff = voltage_table->count - max_voltage_steps;
3932 for (i= 0; i < max_voltage_steps; i++)
3933 voltage_table->entries[i] = voltage_table->entries[i + diff];
3935 voltage_table->count = max_voltage_steps;
3938 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3939 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3940 struct atom_voltage_table *voltage_table)
3944 if (voltage_dependency_table == NULL)
3947 voltage_table->mask_low = 0;
3948 voltage_table->phase_delay = 0;
3950 voltage_table->count = voltage_dependency_table->count;
3951 for (i = 0; i < voltage_table->count; i++) {
3952 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3953 voltage_table->entries[i].smio_low = 0;
3959 static int si_construct_voltage_tables(struct radeon_device *rdev)
3961 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3962 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3963 struct si_power_info *si_pi = si_get_pi(rdev);
3966 if (pi->voltage_control) {
3967 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3968 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3972 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3973 si_trim_voltage_table_to_fit_state_table(rdev,
3974 SISLANDS_MAX_NO_VREG_STEPS,
3975 &eg_pi->vddc_voltage_table);
3976 } else if (si_pi->voltage_control_svi2) {
3977 ret = si_get_svi2_voltage_table(rdev,
3978 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3979 &eg_pi->vddc_voltage_table);
3986 if (eg_pi->vddci_control) {
3987 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3988 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3992 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3993 si_trim_voltage_table_to_fit_state_table(rdev,
3994 SISLANDS_MAX_NO_VREG_STEPS,
3995 &eg_pi->vddci_voltage_table);
3997 if (si_pi->vddci_control_svi2) {
3998 ret = si_get_svi2_voltage_table(rdev,
3999 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4000 &eg_pi->vddci_voltage_table);
4005 if (pi->mvdd_control) {
4006 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4007 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4010 pi->mvdd_control = false;
4014 if (si_pi->mvdd_voltage_table.count == 0) {
4015 pi->mvdd_control = false;
4019 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4020 si_trim_voltage_table_to_fit_state_table(rdev,
4021 SISLANDS_MAX_NO_VREG_STEPS,
4022 &si_pi->mvdd_voltage_table);
4025 if (si_pi->vddc_phase_shed_control) {
4026 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4027 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4029 si_pi->vddc_phase_shed_control = false;
4031 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4032 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4033 si_pi->vddc_phase_shed_control = false;
4039 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4040 const struct atom_voltage_table *voltage_table,
4041 SISLANDS_SMC_STATETABLE *table)
4045 for (i = 0; i < voltage_table->count; i++)
4046 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4049 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4050 SISLANDS_SMC_STATETABLE *table)
4052 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4053 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4054 struct si_power_info *si_pi = si_get_pi(rdev);
4057 if (si_pi->voltage_control_svi2) {
4058 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4059 si_pi->svc_gpio_id);
4060 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4061 si_pi->svd_gpio_id);
4062 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4065 if (eg_pi->vddc_voltage_table.count) {
4066 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4067 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4068 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4070 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4071 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4072 table->maxVDDCIndexInPPTable = i;
4078 if (eg_pi->vddci_voltage_table.count) {
4079 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4081 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4082 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4086 if (si_pi->mvdd_voltage_table.count) {
4087 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4089 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4090 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4093 if (si_pi->vddc_phase_shed_control) {
4094 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4095 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4096 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4098 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4099 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4101 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4102 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4104 si_pi->vddc_phase_shed_control = false;
4112 static int si_populate_voltage_value(struct radeon_device *rdev,
4113 const struct atom_voltage_table *table,
4114 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4118 for (i = 0; i < table->count; i++) {
4119 if (value <= table->entries[i].value) {
4120 voltage->index = (u8)i;
4121 voltage->value = cpu_to_be16(table->entries[i].value);
4126 if (i >= table->count)
4132 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4133 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4135 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4136 struct si_power_info *si_pi = si_get_pi(rdev);
4138 if (pi->mvdd_control) {
4139 if (mclk <= pi->mvdd_split_frequency)
4142 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4144 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4149 static int si_get_std_voltage_value(struct radeon_device *rdev,
4150 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4154 bool voltage_found = false;
4155 *std_voltage = be16_to_cpu(voltage->value);
4157 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4158 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4159 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4162 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4163 if (be16_to_cpu(voltage->value) ==
4164 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4165 voltage_found = true;
4166 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4168 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4171 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4176 if (!voltage_found) {
4177 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4178 if (be16_to_cpu(voltage->value) <=
4179 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4180 voltage_found = true;
4181 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4183 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4186 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4192 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4193 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4200 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4201 u16 value, u8 index,
4202 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4204 voltage->index = index;
4205 voltage->value = cpu_to_be16(value);
4210 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4211 const struct radeon_phase_shedding_limits_table *limits,
4212 u16 voltage, u32 sclk, u32 mclk,
4213 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4217 for (i = 0; i < limits->count; i++) {
4218 if ((voltage <= limits->entries[i].voltage) &&
4219 (sclk <= limits->entries[i].sclk) &&
4220 (mclk <= limits->entries[i].mclk))
4224 smc_voltage->phase_settings = (u8)i;
4229 static int si_init_arb_table_index(struct radeon_device *rdev)
4231 struct si_power_info *si_pi = si_get_pi(rdev);
4235 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4240 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4242 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4245 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4247 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4250 static int si_reset_to_default(struct radeon_device *rdev)
4252 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4256 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4258 struct si_power_info *si_pi = si_get_pi(rdev);
4262 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4263 &tmp, si_pi->sram_end);
4267 tmp = (tmp >> 24) & 0xff;
4269 if (tmp == MC_CG_ARB_FREQ_F0)
4272 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4275 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4279 u32 dram_refresh_rate;
4280 u32 mc_arb_rfsh_rate;
4281 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4286 dram_rows = 1 << (tmp + 10);
4288 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4289 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4291 return mc_arb_rfsh_rate;
4294 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4295 struct rv7xx_pl *pl,
4296 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4302 arb_regs->mc_arb_rfsh_rate =
4303 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4305 radeon_atom_set_engine_dram_timings(rdev,
4309 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4310 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4311 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4313 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4314 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4315 arb_regs->mc_arb_burst_time = (u8)burst_time;
4320 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4321 struct radeon_ps *radeon_state,
4322 unsigned int first_arb_set)
4324 struct si_power_info *si_pi = si_get_pi(rdev);
4325 struct ni_ps *state = ni_get_ps(radeon_state);
4326 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4329 for (i = 0; i < state->performance_level_count; i++) {
4330 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4333 ret = si_copy_bytes_to_smc(rdev,
4334 si_pi->arb_table_start +
4335 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4336 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4338 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4347 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4348 struct radeon_ps *radeon_new_state)
4350 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4351 SISLANDS_DRIVER_STATE_ARB_INDEX);
4354 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4355 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4357 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4358 struct si_power_info *si_pi = si_get_pi(rdev);
4360 if (pi->mvdd_control)
4361 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4362 si_pi->mvdd_bootup_value, voltage);
4367 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4368 struct radeon_ps *radeon_initial_state,
4369 SISLANDS_SMC_STATETABLE *table)
4371 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4372 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4373 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4374 struct si_power_info *si_pi = si_get_pi(rdev);
4378 table->initialState.levels[0].mclk.vDLL_CNTL =
4379 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4380 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4381 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4382 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4383 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4384 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4385 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4386 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4387 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4388 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4389 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4390 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4391 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4392 table->initialState.levels[0].mclk.vMPLL_SS =
4393 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4394 table->initialState.levels[0].mclk.vMPLL_SS2 =
4395 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4397 table->initialState.levels[0].mclk.mclk_value =
4398 cpu_to_be32(initial_state->performance_levels[0].mclk);
4400 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4401 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4402 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4403 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4404 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4405 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4406 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4407 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4408 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4409 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4410 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4411 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4413 table->initialState.levels[0].sclk.sclk_value =
4414 cpu_to_be32(initial_state->performance_levels[0].sclk);
4416 table->initialState.levels[0].arbRefreshState =
4417 SISLANDS_INITIAL_STATE_ARB_INDEX;
4419 table->initialState.levels[0].ACIndex = 0;
4421 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4422 initial_state->performance_levels[0].vddc,
4423 &table->initialState.levels[0].vddc);
4428 ret = si_get_std_voltage_value(rdev,
4429 &table->initialState.levels[0].vddc,
4432 si_populate_std_voltage_value(rdev, std_vddc,
4433 table->initialState.levels[0].vddc.index,
4434 &table->initialState.levels[0].std_vddc);
4437 if (eg_pi->vddci_control)
4438 si_populate_voltage_value(rdev,
4439 &eg_pi->vddci_voltage_table,
4440 initial_state->performance_levels[0].vddci,
4441 &table->initialState.levels[0].vddci);
4443 if (si_pi->vddc_phase_shed_control)
4444 si_populate_phase_shedding_value(rdev,
4445 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4446 initial_state->performance_levels[0].vddc,
4447 initial_state->performance_levels[0].sclk,
4448 initial_state->performance_levels[0].mclk,
4449 &table->initialState.levels[0].vddc);
4451 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4453 reg = CG_R(0xffff) | CG_L(0);
4454 table->initialState.levels[0].aT = cpu_to_be32(reg);
4456 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4458 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4460 if (pi->mem_gddr5) {
4461 table->initialState.levels[0].strobeMode =
4462 si_get_strobe_mode_settings(rdev,
4463 initial_state->performance_levels[0].mclk);
4465 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4466 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4468 table->initialState.levels[0].mcFlags = 0;
4471 table->initialState.levelCount = 1;
4473 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4475 table->initialState.levels[0].dpm2.MaxPS = 0;
4476 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4477 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4478 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4479 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4481 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4482 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4484 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4485 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4490 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4491 SISLANDS_SMC_STATETABLE *table)
4493 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4494 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4495 struct si_power_info *si_pi = si_get_pi(rdev);
4496 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4497 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4498 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4499 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4500 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4501 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4502 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4503 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4504 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4505 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4506 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4510 table->ACPIState = table->initialState;
4512 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4514 if (pi->acpi_vddc) {
4515 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4516 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4520 ret = si_get_std_voltage_value(rdev,
4521 &table->ACPIState.levels[0].vddc, &std_vddc);
4523 si_populate_std_voltage_value(rdev, std_vddc,
4524 table->ACPIState.levels[0].vddc.index,
4525 &table->ACPIState.levels[0].std_vddc);
4527 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4529 if (si_pi->vddc_phase_shed_control) {
4530 si_populate_phase_shedding_value(rdev,
4531 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4535 &table->ACPIState.levels[0].vddc);
4538 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4539 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4543 ret = si_get_std_voltage_value(rdev,
4544 &table->ACPIState.levels[0].vddc, &std_vddc);
4547 si_populate_std_voltage_value(rdev, std_vddc,
4548 table->ACPIState.levels[0].vddc.index,
4549 &table->ACPIState.levels[0].std_vddc);
4551 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4552 si_pi->sys_pcie_mask,
4553 si_pi->boot_pcie_gen,
4556 if (si_pi->vddc_phase_shed_control)
4557 si_populate_phase_shedding_value(rdev,
4558 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4559 pi->min_vddc_in_table,
4562 &table->ACPIState.levels[0].vddc);
4565 if (pi->acpi_vddc) {
4566 if (eg_pi->acpi_vddci)
4567 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4569 &table->ACPIState.levels[0].vddci);
4572 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4573 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4575 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4577 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4578 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4580 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4581 cpu_to_be32(dll_cntl);
4582 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4583 cpu_to_be32(mclk_pwrmgt_cntl);
4584 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4585 cpu_to_be32(mpll_ad_func_cntl);
4586 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4587 cpu_to_be32(mpll_dq_func_cntl);
4588 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4589 cpu_to_be32(mpll_func_cntl);
4590 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4591 cpu_to_be32(mpll_func_cntl_1);
4592 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4593 cpu_to_be32(mpll_func_cntl_2);
4594 table->ACPIState.levels[0].mclk.vMPLL_SS =
4595 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4596 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4597 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4599 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4600 cpu_to_be32(spll_func_cntl);
4601 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4602 cpu_to_be32(spll_func_cntl_2);
4603 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4604 cpu_to_be32(spll_func_cntl_3);
4605 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4606 cpu_to_be32(spll_func_cntl_4);
4608 table->ACPIState.levels[0].mclk.mclk_value = 0;
4609 table->ACPIState.levels[0].sclk.sclk_value = 0;
4611 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4613 if (eg_pi->dynamic_ac_timing)
4614 table->ACPIState.levels[0].ACIndex = 0;
4616 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4617 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4618 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4619 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4620 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4622 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4623 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4625 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4626 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4631 static int si_populate_ulv_state(struct radeon_device *rdev,
4632 SISLANDS_SMC_SWSTATE *state)
4634 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4635 struct si_power_info *si_pi = si_get_pi(rdev);
4636 struct si_ulv_param *ulv = &si_pi->ulv;
4637 u32 sclk_in_sr = 1350; /* ??? */
4640 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4643 if (eg_pi->sclk_deep_sleep) {
4644 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4645 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4647 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4649 if (ulv->one_pcie_lane_in_ulv)
4650 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4651 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4652 state->levels[0].ACIndex = 1;
4653 state->levels[0].std_vddc = state->levels[0].vddc;
4654 state->levelCount = 1;
4656 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4662 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4664 struct si_power_info *si_pi = si_get_pi(rdev);
4665 struct si_ulv_param *ulv = &si_pi->ulv;
4666 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4669 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4674 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4675 ulv->volt_change_delay);
4677 ret = si_copy_bytes_to_smc(rdev,
4678 si_pi->arb_table_start +
4679 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4680 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4682 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4688 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4690 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4692 pi->mvdd_split_frequency = 30000;
4695 static int si_init_smc_table(struct radeon_device *rdev)
4697 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4698 struct si_power_info *si_pi = si_get_pi(rdev);
4699 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4700 const struct si_ulv_param *ulv = &si_pi->ulv;
4701 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4706 si_populate_smc_voltage_tables(rdev, table);
4708 switch (rdev->pm.int_thermal_type) {
4709 case THERMAL_TYPE_SI:
4710 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4711 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4713 case THERMAL_TYPE_NONE:
4714 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4717 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4721 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4722 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4724 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4725 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4726 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4729 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4730 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4733 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4735 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4736 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4738 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4739 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4740 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4741 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4745 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4749 ret = si_populate_smc_acpi_state(rdev, table);
4753 table->driverState = table->initialState;
4755 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4756 SISLANDS_INITIAL_STATE_ARB_INDEX);
4760 if (ulv->supported && ulv->pl.vddc) {
4761 ret = si_populate_ulv_state(rdev, &table->ULVState);
4765 ret = si_program_ulv_memory_timing_parameters(rdev);
4769 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4770 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4772 lane_width = radeon_get_pcie_lanes(rdev);
4773 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4775 table->ULVState = table->initialState;
4778 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4779 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4783 static int si_calculate_sclk_params(struct radeon_device *rdev,
4785 SISLANDS_SMC_SCLK_VALUE *sclk)
4787 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4788 struct si_power_info *si_pi = si_get_pi(rdev);
4789 struct atom_clock_dividers dividers;
4790 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4791 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4792 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4793 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4794 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4795 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4797 u32 reference_clock = rdev->clock.spll.reference_freq;
4798 u32 reference_divider;
4802 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4803 engine_clock, false, ÷rs);
4807 reference_divider = 1 + dividers.ref_div;
4809 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4810 do_div(tmp, reference_clock);
4813 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4814 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4815 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4817 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4818 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4820 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4821 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4822 spll_func_cntl_3 |= SPLL_DITHEN;
4825 struct radeon_atom_ss ss;
4826 u32 vco_freq = engine_clock * dividers.post_div;
4828 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4829 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4830 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4831 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4833 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4834 cg_spll_spread_spectrum |= CLK_S(clk_s);
4835 cg_spll_spread_spectrum |= SSEN;
4837 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4838 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4842 sclk->sclk_value = engine_clock;
4843 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4844 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4845 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4846 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4847 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4848 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4853 static int si_populate_sclk_value(struct radeon_device *rdev,
4855 SISLANDS_SMC_SCLK_VALUE *sclk)
4857 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4860 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4862 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4863 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4864 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4865 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4866 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4867 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4868 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4874 static int si_populate_mclk_value(struct radeon_device *rdev,
4877 SISLANDS_SMC_MCLK_VALUE *mclk,
4881 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4882 struct si_power_info *si_pi = si_get_pi(rdev);
4883 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4884 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4885 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4886 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4887 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4888 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4889 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4890 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4891 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4892 struct atom_mpll_param mpll_param;
4895 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4899 mpll_func_cntl &= ~BWCTRL_MASK;
4900 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4902 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4903 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4904 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4906 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4907 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4909 if (pi->mem_gddr5) {
4910 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4911 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4912 YCLK_POST_DIV(mpll_param.post_div);
4916 struct radeon_atom_ss ss;
4919 u32 reference_clock = rdev->clock.mpll.reference_freq;
4922 freq_nom = memory_clock * 4;
4924 freq_nom = memory_clock * 2;
4926 tmp = freq_nom / reference_clock;
4928 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4929 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4930 u32 clks = reference_clock * 5 / ss.rate;
4931 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4933 mpll_ss1 &= ~CLKV_MASK;
4934 mpll_ss1 |= CLKV(clkv);
4936 mpll_ss2 &= ~CLKS_MASK;
4937 mpll_ss2 |= CLKS(clks);
4941 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4942 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4945 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4947 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4949 mclk->mclk_value = cpu_to_be32(memory_clock);
4950 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4951 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4952 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4953 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4954 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4955 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4956 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4957 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4958 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4963 static void si_populate_smc_sp(struct radeon_device *rdev,
4964 struct radeon_ps *radeon_state,
4965 SISLANDS_SMC_SWSTATE *smc_state)
4967 struct ni_ps *ps = ni_get_ps(radeon_state);
4968 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4971 for (i = 0; i < ps->performance_level_count - 1; i++)
4972 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4974 smc_state->levels[ps->performance_level_count - 1].bSP =
4975 cpu_to_be32(pi->psp);
4978 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4979 struct rv7xx_pl *pl,
4980 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4982 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4983 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4984 struct si_power_info *si_pi = si_get_pi(rdev);
4988 bool gmc_pg = false;
4990 if (eg_pi->pcie_performance_request &&
4991 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4992 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4994 level->gen2PCIE = (u8)pl->pcie_gen;
4996 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5002 if (pi->mclk_stutter_mode_threshold &&
5003 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5004 !eg_pi->uvd_enabled &&
5005 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5006 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5007 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5010 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5013 if (pi->mem_gddr5) {
5014 if (pl->mclk > pi->mclk_edc_enable_threshold)
5015 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5017 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5018 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5020 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5022 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5023 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5024 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5025 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5027 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5029 dll_state_on = false;
5032 level->strobeMode = si_get_strobe_mode_settings(rdev,
5035 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5038 ret = si_populate_mclk_value(rdev,
5042 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5046 ret = si_populate_voltage_value(rdev,
5047 &eg_pi->vddc_voltage_table,
5048 pl->vddc, &level->vddc);
5053 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5057 ret = si_populate_std_voltage_value(rdev, std_vddc,
5058 level->vddc.index, &level->std_vddc);
5062 if (eg_pi->vddci_control) {
5063 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5064 pl->vddci, &level->vddci);
5069 if (si_pi->vddc_phase_shed_control) {
5070 ret = si_populate_phase_shedding_value(rdev,
5071 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5080 level->MaxPoweredUpCU = si_pi->max_cu;
5082 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5087 static int si_populate_smc_t(struct radeon_device *rdev,
5088 struct radeon_ps *radeon_state,
5089 SISLANDS_SMC_SWSTATE *smc_state)
5091 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5092 struct ni_ps *state = ni_get_ps(radeon_state);
5098 if (state->performance_level_count >= 9)
5101 if (state->performance_level_count < 2) {
5102 a_t = CG_R(0xffff) | CG_L(0);
5103 smc_state->levels[0].aT = cpu_to_be32(a_t);
5107 smc_state->levels[0].aT = cpu_to_be32(0);
5109 for (i = 0; i <= state->performance_level_count - 2; i++) {
5110 ret = r600_calculate_at(
5111 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5113 state->performance_levels[i + 1].sclk,
5114 state->performance_levels[i].sclk,
5119 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5120 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5123 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5124 a_t |= CG_R(t_l * pi->bsp / 20000);
5125 smc_state->levels[i].aT = cpu_to_be32(a_t);
5127 high_bsp = (i == state->performance_level_count - 2) ?
5129 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5130 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5136 static int si_disable_ulv(struct radeon_device *rdev)
5138 struct si_power_info *si_pi = si_get_pi(rdev);
5139 struct si_ulv_param *ulv = &si_pi->ulv;
5142 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5148 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5149 struct radeon_ps *radeon_state)
5151 const struct si_power_info *si_pi = si_get_pi(rdev);
5152 const struct si_ulv_param *ulv = &si_pi->ulv;
5153 const struct ni_ps *state = ni_get_ps(radeon_state);
5156 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5159 /* XXX validate against display requirements! */
5161 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5162 if (rdev->clock.current_dispclk <=
5163 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5165 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5170 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5176 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5177 struct radeon_ps *radeon_new_state)
5179 const struct si_power_info *si_pi = si_get_pi(rdev);
5180 const struct si_ulv_param *ulv = &si_pi->ulv;
5182 if (ulv->supported) {
5183 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5184 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5190 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5191 struct radeon_ps *radeon_state,
5192 SISLANDS_SMC_SWSTATE *smc_state)
5194 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5195 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5196 struct si_power_info *si_pi = si_get_pi(rdev);
5197 struct ni_ps *state = ni_get_ps(radeon_state);
5200 u32 sclk_in_sr = 1350; /* ??? */
5202 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5205 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5207 if (radeon_state->vclk && radeon_state->dclk) {
5208 eg_pi->uvd_enabled = true;
5209 if (eg_pi->smu_uvd_hs)
5210 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5212 eg_pi->uvd_enabled = false;
5215 if (state->dc_compatible)
5216 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5218 smc_state->levelCount = 0;
5219 for (i = 0; i < state->performance_level_count; i++) {
5220 if (eg_pi->sclk_deep_sleep) {
5221 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5222 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5223 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5225 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5229 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5230 &smc_state->levels[i]);
5231 smc_state->levels[i].arbRefreshState =
5232 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5237 if (ni_pi->enable_power_containment)
5238 smc_state->levels[i].displayWatermark =
5239 (state->performance_levels[i].sclk < threshold) ?
5240 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5242 smc_state->levels[i].displayWatermark = (i < 2) ?
5243 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5245 if (eg_pi->dynamic_ac_timing)
5246 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5248 smc_state->levels[i].ACIndex = 0;
5250 smc_state->levelCount++;
5253 si_write_smc_soft_register(rdev,
5254 SI_SMC_SOFT_REGISTER_watermark_threshold,
5257 si_populate_smc_sp(rdev, radeon_state, smc_state);
5259 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5261 ni_pi->enable_power_containment = false;
5263 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5265 ni_pi->enable_sq_ramping = false;
5267 return si_populate_smc_t(rdev, radeon_state, smc_state);
5270 static int si_upload_sw_state(struct radeon_device *rdev,
5271 struct radeon_ps *radeon_new_state)
5273 struct si_power_info *si_pi = si_get_pi(rdev);
5274 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5276 u32 address = si_pi->state_table_start +
5277 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5278 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5279 ((new_state->performance_level_count - 1) *
5280 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5281 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5283 memset(smc_state, 0, state_size);
5285 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5289 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5290 state_size, si_pi->sram_end);
5295 static int si_upload_ulv_state(struct radeon_device *rdev)
5297 struct si_power_info *si_pi = si_get_pi(rdev);
5298 struct si_ulv_param *ulv = &si_pi->ulv;
5301 if (ulv->supported && ulv->pl.vddc) {
5302 u32 address = si_pi->state_table_start +
5303 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5304 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5305 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5307 memset(smc_state, 0, state_size);
5309 ret = si_populate_ulv_state(rdev, smc_state);
5311 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5312 state_size, si_pi->sram_end);
5318 static int si_upload_smc_data(struct radeon_device *rdev)
5320 struct radeon_crtc *radeon_crtc = NULL;
5323 if (rdev->pm.dpm.new_active_crtc_count == 0)
5326 for (i = 0; i < rdev->num_crtc; i++) {
5327 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5328 radeon_crtc = rdev->mode_info.crtcs[i];
5333 if (radeon_crtc == NULL)
5336 if (radeon_crtc->line_time <= 0)
5339 if (si_write_smc_soft_register(rdev,
5340 SI_SMC_SOFT_REGISTER_crtc_index,
5341 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5344 if (si_write_smc_soft_register(rdev,
5345 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5346 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5349 if (si_write_smc_soft_register(rdev,
5350 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5351 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5357 static int si_set_mc_special_registers(struct radeon_device *rdev,
5358 struct si_mc_reg_table *table)
5360 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5364 for (i = 0, j = table->last; i < table->last; i++) {
5365 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5367 switch (table->mc_reg_address[i].s1 << 2) {
5369 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5370 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5371 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5372 for (k = 0; k < table->num_entries; k++)
5373 table->mc_reg_table_entry[k].mc_data[j] =
5374 ((temp_reg & 0xffff0000)) |
5375 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5377 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5380 temp_reg = RREG32(MC_PMG_CMD_MRS);
5381 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5382 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5383 for (k = 0; k < table->num_entries; k++) {
5384 table->mc_reg_table_entry[k].mc_data[j] =
5385 (temp_reg & 0xffff0000) |
5386 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5388 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5391 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5394 if (!pi->mem_gddr5) {
5395 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5396 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5397 for (k = 0; k < table->num_entries; k++)
5398 table->mc_reg_table_entry[k].mc_data[j] =
5399 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5401 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5405 case MC_SEQ_RESERVE_M:
5406 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5407 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5408 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5409 for(k = 0; k < table->num_entries; k++)
5410 table->mc_reg_table_entry[k].mc_data[j] =
5411 (temp_reg & 0xffff0000) |
5412 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5414 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5427 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5432 case MC_SEQ_RAS_TIMING >> 2:
5433 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5435 case MC_SEQ_CAS_TIMING >> 2:
5436 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5438 case MC_SEQ_MISC_TIMING >> 2:
5439 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5441 case MC_SEQ_MISC_TIMING2 >> 2:
5442 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5444 case MC_SEQ_RD_CTL_D0 >> 2:
5445 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5447 case MC_SEQ_RD_CTL_D1 >> 2:
5448 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5450 case MC_SEQ_WR_CTL_D0 >> 2:
5451 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5453 case MC_SEQ_WR_CTL_D1 >> 2:
5454 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5456 case MC_PMG_CMD_EMRS >> 2:
5457 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5459 case MC_PMG_CMD_MRS >> 2:
5460 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5462 case MC_PMG_CMD_MRS1 >> 2:
5463 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5465 case MC_SEQ_PMG_TIMING >> 2:
5466 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5468 case MC_PMG_CMD_MRS2 >> 2:
5469 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5471 case MC_SEQ_WR_CTL_2 >> 2:
5472 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5482 static void si_set_valid_flag(struct si_mc_reg_table *table)
5486 for (i = 0; i < table->last; i++) {
5487 for (j = 1; j < table->num_entries; j++) {
5488 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5489 table->valid_flag |= 1 << i;
5496 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5501 for (i = 0; i < table->last; i++)
5502 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5503 address : table->mc_reg_address[i].s1;
5507 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5508 struct si_mc_reg_table *si_table)
5512 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5514 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5517 for (i = 0; i < table->last; i++)
5518 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5519 si_table->last = table->last;
5521 for (i = 0; i < table->num_entries; i++) {
5522 si_table->mc_reg_table_entry[i].mclk_max =
5523 table->mc_reg_table_entry[i].mclk_max;
5524 for (j = 0; j < table->last; j++) {
5525 si_table->mc_reg_table_entry[i].mc_data[j] =
5526 table->mc_reg_table_entry[i].mc_data[j];
5529 si_table->num_entries = table->num_entries;
5534 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5536 struct si_power_info *si_pi = si_get_pi(rdev);
5537 struct atom_mc_reg_table *table;
5538 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5539 u8 module_index = rv770_get_memory_module_index(rdev);
5542 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5546 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5547 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5548 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5549 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5550 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5551 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5552 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5553 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5554 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5555 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5556 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5557 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5558 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5559 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5561 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5565 ret = si_copy_vbios_mc_reg_table(table, si_table);
5569 si_set_s0_mc_reg_index(si_table);
5571 ret = si_set_mc_special_registers(rdev, si_table);
5575 si_set_valid_flag(si_table);
5584 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5585 SMC_SIslands_MCRegisters *mc_reg_table)
5587 struct si_power_info *si_pi = si_get_pi(rdev);
5590 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5591 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5592 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5594 mc_reg_table->address[i].s0 =
5595 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5596 mc_reg_table->address[i].s1 =
5597 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5601 mc_reg_table->last = (u8)i;
5604 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5605 SMC_SIslands_MCRegisterSet *data,
5606 u32 num_entries, u32 valid_flag)
5610 for(i = 0, j = 0; j < num_entries; j++) {
5611 if (valid_flag & (1 << j)) {
5612 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5618 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5619 struct rv7xx_pl *pl,
5620 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5622 struct si_power_info *si_pi = si_get_pi(rdev);
5625 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5626 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5630 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5633 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5634 mc_reg_table_data, si_pi->mc_reg_table.last,
5635 si_pi->mc_reg_table.valid_flag);
5638 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5639 struct radeon_ps *radeon_state,
5640 SMC_SIslands_MCRegisters *mc_reg_table)
5642 struct ni_ps *state = ni_get_ps(radeon_state);
5645 for (i = 0; i < state->performance_level_count; i++) {
5646 si_convert_mc_reg_table_entry_to_smc(rdev,
5647 &state->performance_levels[i],
5648 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5652 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5653 struct radeon_ps *radeon_boot_state)
5655 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5656 struct si_power_info *si_pi = si_get_pi(rdev);
5657 struct si_ulv_param *ulv = &si_pi->ulv;
5658 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5660 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5662 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5664 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5666 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5667 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5669 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5670 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5671 si_pi->mc_reg_table.last,
5672 si_pi->mc_reg_table.valid_flag);
5674 if (ulv->supported && ulv->pl.vddc != 0)
5675 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5676 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5678 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5679 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5680 si_pi->mc_reg_table.last,
5681 si_pi->mc_reg_table.valid_flag);
5683 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5685 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5686 (u8 *)smc_mc_reg_table,
5687 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5690 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5691 struct radeon_ps *radeon_new_state)
5693 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5694 struct si_power_info *si_pi = si_get_pi(rdev);
5695 u32 address = si_pi->mc_reg_table_start +
5696 offsetof(SMC_SIslands_MCRegisters,
5697 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5698 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5700 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5702 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5705 return si_copy_bytes_to_smc(rdev, address,
5706 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5707 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5712 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5715 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5717 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5720 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5721 struct radeon_ps *radeon_state)
5723 struct ni_ps *state = ni_get_ps(radeon_state);
5725 u16 pcie_speed, max_speed = 0;
5727 for (i = 0; i < state->performance_level_count; i++) {
5728 pcie_speed = state->performance_levels[i].pcie_gen;
5729 if (max_speed < pcie_speed)
5730 max_speed = pcie_speed;
5735 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5739 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5740 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5742 return (u16)speed_cntl;
5745 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5746 struct radeon_ps *radeon_new_state,
5747 struct radeon_ps *radeon_current_state)
5749 struct si_power_info *si_pi = si_get_pi(rdev);
5750 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5751 enum radeon_pcie_gen current_link_speed;
5753 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5754 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5756 current_link_speed = si_pi->force_pcie_gen;
5758 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5759 si_pi->pspp_notify_required = false;
5760 if (target_link_speed > current_link_speed) {
5761 switch (target_link_speed) {
5762 #if defined(CONFIG_ACPI)
5763 case RADEON_PCIE_GEN3:
5764 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5766 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5767 if (current_link_speed == RADEON_PCIE_GEN2)
5769 case RADEON_PCIE_GEN2:
5770 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5774 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5778 if (target_link_speed < current_link_speed)
5779 si_pi->pspp_notify_required = true;
5783 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5784 struct radeon_ps *radeon_new_state,
5785 struct radeon_ps *radeon_current_state)
5787 struct si_power_info *si_pi = si_get_pi(rdev);
5788 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5791 if (si_pi->pspp_notify_required) {
5792 if (target_link_speed == RADEON_PCIE_GEN3)
5793 request = PCIE_PERF_REQ_PECI_GEN3;
5794 else if (target_link_speed == RADEON_PCIE_GEN2)
5795 request = PCIE_PERF_REQ_PECI_GEN2;
5797 request = PCIE_PERF_REQ_PECI_GEN1;
5799 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5800 (si_get_current_pcie_speed(rdev) > 0))
5803 #if defined(CONFIG_ACPI)
5804 radeon_acpi_pcie_performance_request(rdev, request, false);
5810 static int si_ds_request(struct radeon_device *rdev,
5811 bool ds_status_on, u32 count_write)
5813 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5815 if (eg_pi->sclk_deep_sleep) {
5817 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5821 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5822 PPSMC_Result_OK) ? 0 : -EINVAL;
5828 static void si_set_max_cu_value(struct radeon_device *rdev)
5830 struct si_power_info *si_pi = si_get_pi(rdev);
5832 if (rdev->family == CHIP_VERDE) {
5833 switch (rdev->pdev->device) {
5869 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5870 struct radeon_clock_voltage_dependency_table *table)
5874 u16 leakage_voltage;
5877 for (i = 0; i < table->count; i++) {
5878 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5879 table->entries[i].v,
5880 &leakage_voltage)) {
5882 table->entries[i].v = leakage_voltage;
5892 for (j = (table->count - 2); j >= 0; j--) {
5893 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5894 table->entries[j].v : table->entries[j + 1].v;
5900 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5904 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5905 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5906 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5907 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5908 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5909 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5913 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5914 struct radeon_ps *radeon_new_state,
5915 struct radeon_ps *radeon_current_state)
5918 u32 new_lane_width =
5919 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5920 u32 current_lane_width =
5921 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5923 if (new_lane_width != current_lane_width) {
5924 radeon_set_pcie_lanes(rdev, new_lane_width);
5925 lane_width = radeon_get_pcie_lanes(rdev);
5926 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5930 static void si_set_vce_clock(struct radeon_device *rdev,
5931 struct radeon_ps *new_rps,
5932 struct radeon_ps *old_rps)
5934 if ((old_rps->evclk != new_rps->evclk) ||
5935 (old_rps->ecclk != new_rps->ecclk)) {
5936 /* turn the clocks on when encoding, off otherwise */
5937 if (new_rps->evclk || new_rps->ecclk)
5938 vce_v1_0_enable_mgcg(rdev, false);
5940 vce_v1_0_enable_mgcg(rdev, true);
5941 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5945 void si_dpm_setup_asic(struct radeon_device *rdev)
5949 r = si_mc_load_microcode(rdev);
5951 DRM_ERROR("Failed to load MC firmware!\n");
5952 rv770_get_memory_type(rdev);
5953 si_read_clock_registers(rdev);
5954 si_enable_acpi_power_management(rdev);
5957 static int si_thermal_enable_alert(struct radeon_device *rdev,
5960 u32 thermal_int = RREG32(CG_THERMAL_INT);
5963 PPSMC_Result result;
5965 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5966 WREG32(CG_THERMAL_INT, thermal_int);
5967 rdev->irq.dpm_thermal = false;
5968 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5969 if (result != PPSMC_Result_OK) {
5970 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5974 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5975 WREG32(CG_THERMAL_INT, thermal_int);
5976 rdev->irq.dpm_thermal = true;
5982 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5983 int min_temp, int max_temp)
5985 int low_temp = 0 * 1000;
5986 int high_temp = 255 * 1000;
5988 if (low_temp < min_temp)
5989 low_temp = min_temp;
5990 if (high_temp > max_temp)
5991 high_temp = max_temp;
5992 if (high_temp < low_temp) {
5993 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5997 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5998 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5999 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6001 rdev->pm.dpm.thermal.min_temp = low_temp;
6002 rdev->pm.dpm.thermal.max_temp = high_temp;
6007 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6009 struct si_power_info *si_pi = si_get_pi(rdev);
6012 if (si_pi->fan_ctrl_is_in_default_mode) {
6013 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6014 si_pi->fan_ctrl_default_mode = tmp;
6015 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6017 si_pi->fan_ctrl_is_in_default_mode = false;
6020 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6022 WREG32(CG_FDO_CTRL2, tmp);
6024 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6025 tmp |= FDO_PWM_MODE(mode);
6026 WREG32(CG_FDO_CTRL2, tmp);
6029 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6031 struct si_power_info *si_pi = si_get_pi(rdev);
6032 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6034 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6035 u16 fdo_min, slope1, slope2;
6036 u32 reference_clock, tmp;
6040 if (!si_pi->fan_table_start) {
6041 rdev->pm.dpm.fan.ucode_fan_control = false;
6045 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6048 rdev->pm.dpm.fan.ucode_fan_control = false;
6052 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6053 do_div(tmp64, 10000);
6054 fdo_min = (u16)tmp64;
6056 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6057 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6059 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6060 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6062 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6063 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6065 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6066 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6067 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6069 fan_table.slope1 = cpu_to_be16(slope1);
6070 fan_table.slope2 = cpu_to_be16(slope2);
6072 fan_table.fdo_min = cpu_to_be16(fdo_min);
6074 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6076 fan_table.hys_up = cpu_to_be16(1);
6078 fan_table.hys_slope = cpu_to_be16(1);
6080 fan_table.temp_resp_lim = cpu_to_be16(5);
6082 reference_clock = radeon_get_xclk(rdev);
6084 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6085 reference_clock) / 1600);
6087 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6089 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6090 fan_table.temp_src = (uint8_t)tmp;
6092 ret = si_copy_bytes_to_smc(rdev,
6093 si_pi->fan_table_start,
6099 DRM_ERROR("Failed to load fan table to the SMC.");
6100 rdev->pm.dpm.fan.ucode_fan_control = false;
6106 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6108 struct si_power_info *si_pi = si_get_pi(rdev);
6111 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6112 if (ret == PPSMC_Result_OK) {
6113 si_pi->fan_is_controlled_by_smc = true;
6120 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6122 struct si_power_info *si_pi = si_get_pi(rdev);
6125 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6127 if (ret == PPSMC_Result_OK) {
6128 si_pi->fan_is_controlled_by_smc = false;
6135 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6141 if (rdev->pm.no_fan)
6144 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6145 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6150 tmp64 = (u64)duty * 100;
6151 do_div(tmp64, duty100);
6152 *speed = (u32)tmp64;
6160 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6163 struct si_power_info *si_pi = si_get_pi(rdev);
6168 if (rdev->pm.no_fan)
6171 if (si_pi->fan_is_controlled_by_smc)
6177 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6182 tmp64 = (u64)speed * duty100;
6186 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6187 tmp |= FDO_STATIC_DUTY(duty);
6188 WREG32(CG_FDO_CTRL0, tmp);
6193 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6196 /* stop auto-manage */
6197 if (rdev->pm.dpm.fan.ucode_fan_control)
6198 si_fan_ctrl_stop_smc_fan_control(rdev);
6199 si_fan_ctrl_set_static_mode(rdev, mode);
6201 /* restart auto-manage */
6202 if (rdev->pm.dpm.fan.ucode_fan_control)
6203 si_thermal_start_smc_fan_control(rdev);
6205 si_fan_ctrl_set_default_mode(rdev);
6209 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6211 struct si_power_info *si_pi = si_get_pi(rdev);
6214 if (si_pi->fan_is_controlled_by_smc)
6217 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6218 return (tmp >> FDO_PWM_MODE_SHIFT);
6222 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6226 u32 xclk = radeon_get_xclk(rdev);
6228 if (rdev->pm.no_fan)
6231 if (rdev->pm.fan_pulses_per_revolution == 0)
6234 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6235 if (tach_period == 0)
6238 *speed = 60 * xclk * 10000 / tach_period;
6243 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6246 u32 tach_period, tmp;
6247 u32 xclk = radeon_get_xclk(rdev);
6249 if (rdev->pm.no_fan)
6252 if (rdev->pm.fan_pulses_per_revolution == 0)
6255 if ((speed < rdev->pm.fan_min_rpm) ||
6256 (speed > rdev->pm.fan_max_rpm))
6259 if (rdev->pm.dpm.fan.ucode_fan_control)
6260 si_fan_ctrl_stop_smc_fan_control(rdev);
6262 tach_period = 60 * xclk * 10000 / (8 * speed);
6263 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6264 tmp |= TARGET_PERIOD(tach_period);
6265 WREG32(CG_TACH_CTRL, tmp);
6267 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6273 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6275 struct si_power_info *si_pi = si_get_pi(rdev);
6278 if (!si_pi->fan_ctrl_is_in_default_mode) {
6279 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6280 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6281 WREG32(CG_FDO_CTRL2, tmp);
6283 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6284 tmp |= TMIN(si_pi->t_min);
6285 WREG32(CG_FDO_CTRL2, tmp);
6286 si_pi->fan_ctrl_is_in_default_mode = true;
6290 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6292 if (rdev->pm.dpm.fan.ucode_fan_control) {
6293 si_fan_ctrl_start_smc_fan_control(rdev);
6294 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6298 static void si_thermal_initialize(struct radeon_device *rdev)
6302 if (rdev->pm.fan_pulses_per_revolution) {
6303 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6304 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6305 WREG32(CG_TACH_CTRL, tmp);
6308 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6309 tmp |= TACH_PWM_RESP_RATE(0x28);
6310 WREG32(CG_FDO_CTRL2, tmp);
6313 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6317 si_thermal_initialize(rdev);
6318 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6321 ret = si_thermal_enable_alert(rdev, true);
6324 if (rdev->pm.dpm.fan.ucode_fan_control) {
6325 ret = si_halt_smc(rdev);
6328 ret = si_thermal_setup_fan_table(rdev);
6331 ret = si_resume_smc(rdev);
6334 si_thermal_start_smc_fan_control(rdev);
6340 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6342 if (!rdev->pm.no_fan) {
6343 si_fan_ctrl_set_default_mode(rdev);
6344 si_fan_ctrl_stop_smc_fan_control(rdev);
6348 int si_dpm_enable(struct radeon_device *rdev)
6350 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6351 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6352 struct si_power_info *si_pi = si_get_pi(rdev);
6353 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6356 if (si_is_smc_running(rdev))
6358 if (pi->voltage_control || si_pi->voltage_control_svi2)
6359 si_enable_voltage_control(rdev, true);
6360 if (pi->mvdd_control)
6361 si_get_mvdd_configuration(rdev);
6362 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6363 ret = si_construct_voltage_tables(rdev);
6365 DRM_ERROR("si_construct_voltage_tables failed\n");
6369 if (eg_pi->dynamic_ac_timing) {
6370 ret = si_initialize_mc_reg_table(rdev);
6372 eg_pi->dynamic_ac_timing = false;
6375 si_enable_spread_spectrum(rdev, true);
6376 if (pi->thermal_protection)
6377 si_enable_thermal_protection(rdev, true);
6379 si_program_git(rdev);
6380 si_program_tp(rdev);
6381 si_program_tpp(rdev);
6382 si_program_sstp(rdev);
6383 si_enable_display_gap(rdev);
6384 si_program_vc(rdev);
6385 ret = si_upload_firmware(rdev);
6387 DRM_ERROR("si_upload_firmware failed\n");
6390 ret = si_process_firmware_header(rdev);
6392 DRM_ERROR("si_process_firmware_header failed\n");
6395 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6397 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6400 ret = si_init_smc_table(rdev);
6402 DRM_ERROR("si_init_smc_table failed\n");
6405 ret = si_init_smc_spll_table(rdev);
6407 DRM_ERROR("si_init_smc_spll_table failed\n");
6410 ret = si_init_arb_table_index(rdev);
6412 DRM_ERROR("si_init_arb_table_index failed\n");
6415 if (eg_pi->dynamic_ac_timing) {
6416 ret = si_populate_mc_reg_table(rdev, boot_ps);
6418 DRM_ERROR("si_populate_mc_reg_table failed\n");
6422 ret = si_initialize_smc_cac_tables(rdev);
6424 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6427 ret = si_initialize_hardware_cac_manager(rdev);
6429 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6432 ret = si_initialize_smc_dte_tables(rdev);
6434 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6437 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6439 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6442 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6444 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6447 si_program_response_times(rdev);
6448 si_program_ds_registers(rdev);
6449 si_dpm_start_smc(rdev);
6450 ret = si_notify_smc_display_change(rdev, false);
6452 DRM_ERROR("si_notify_smc_display_change failed\n");
6455 si_enable_sclk_control(rdev, true);
6458 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6460 si_thermal_start_thermal_controller(rdev);
6462 ni_update_current_ps(rdev, boot_ps);
6467 static int si_set_temperature_range(struct radeon_device *rdev)
6471 ret = si_thermal_enable_alert(rdev, false);
6474 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6477 ret = si_thermal_enable_alert(rdev, true);
6484 int si_dpm_late_enable(struct radeon_device *rdev)
6488 ret = si_set_temperature_range(rdev);
6495 void si_dpm_disable(struct radeon_device *rdev)
6497 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6498 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6500 if (!si_is_smc_running(rdev))
6502 si_thermal_stop_thermal_controller(rdev);
6503 si_disable_ulv(rdev);
6505 if (pi->thermal_protection)
6506 si_enable_thermal_protection(rdev, false);
6507 si_enable_power_containment(rdev, boot_ps, false);
6508 si_enable_smc_cac(rdev, boot_ps, false);
6509 si_enable_spread_spectrum(rdev, false);
6510 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6512 si_reset_to_default(rdev);
6513 si_dpm_stop_smc(rdev);
6514 si_force_switch_to_arb_f0(rdev);
6516 ni_update_current_ps(rdev, boot_ps);
6519 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6521 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6522 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6523 struct radeon_ps *new_ps = &requested_ps;
6525 ni_update_requested_ps(rdev, new_ps);
6527 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6532 static int si_power_control_set_level(struct radeon_device *rdev)
6534 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6537 ret = si_restrict_performance_levels_before_switch(rdev);
6540 ret = si_halt_smc(rdev);
6543 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6546 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6549 ret = si_resume_smc(rdev);
6552 ret = si_set_sw_state(rdev);
6558 int si_dpm_set_power_state(struct radeon_device *rdev)
6560 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6561 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6562 struct radeon_ps *old_ps = &eg_pi->current_rps;
6565 ret = si_disable_ulv(rdev);
6567 DRM_ERROR("si_disable_ulv failed\n");
6570 ret = si_restrict_performance_levels_before_switch(rdev);
6572 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6575 if (eg_pi->pcie_performance_request)
6576 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6577 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6578 ret = si_enable_power_containment(rdev, new_ps, false);
6580 DRM_ERROR("si_enable_power_containment failed\n");
6583 ret = si_enable_smc_cac(rdev, new_ps, false);
6585 DRM_ERROR("si_enable_smc_cac failed\n");
6588 ret = si_halt_smc(rdev);
6590 DRM_ERROR("si_halt_smc failed\n");
6593 ret = si_upload_sw_state(rdev, new_ps);
6595 DRM_ERROR("si_upload_sw_state failed\n");
6598 ret = si_upload_smc_data(rdev);
6600 DRM_ERROR("si_upload_smc_data failed\n");
6603 ret = si_upload_ulv_state(rdev);
6605 DRM_ERROR("si_upload_ulv_state failed\n");
6608 if (eg_pi->dynamic_ac_timing) {
6609 ret = si_upload_mc_reg_table(rdev, new_ps);
6611 DRM_ERROR("si_upload_mc_reg_table failed\n");
6615 ret = si_program_memory_timing_parameters(rdev, new_ps);
6617 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6620 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6622 ret = si_resume_smc(rdev);
6624 DRM_ERROR("si_resume_smc failed\n");
6627 ret = si_set_sw_state(rdev);
6629 DRM_ERROR("si_set_sw_state failed\n");
6632 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6633 si_set_vce_clock(rdev, new_ps, old_ps);
6634 if (eg_pi->pcie_performance_request)
6635 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6636 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6638 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6641 ret = si_enable_smc_cac(rdev, new_ps, true);
6643 DRM_ERROR("si_enable_smc_cac failed\n");
6646 ret = si_enable_power_containment(rdev, new_ps, true);
6648 DRM_ERROR("si_enable_power_containment failed\n");
6652 ret = si_power_control_set_level(rdev);
6654 DRM_ERROR("si_power_control_set_level failed\n");
6661 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6663 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6664 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6666 ni_update_current_ps(rdev, new_ps);
6670 void si_dpm_reset_asic(struct radeon_device *rdev)
6672 si_restrict_performance_levels_before_switch(rdev);
6673 si_disable_ulv(rdev);
6674 si_set_boot_state(rdev);
6678 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6680 si_program_display_gap(rdev);
6684 struct _ATOM_POWERPLAY_INFO info;
6685 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6686 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6687 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6688 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6689 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6692 union pplib_clock_info {
6693 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6694 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6695 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6696 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6697 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6700 union pplib_power_state {
6701 struct _ATOM_PPLIB_STATE v1;
6702 struct _ATOM_PPLIB_STATE_V2 v2;
6705 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6706 struct radeon_ps *rps,
6707 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6710 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6711 rps->class = le16_to_cpu(non_clock_info->usClassification);
6712 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6714 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6715 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6716 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6717 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6718 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6719 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6725 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6726 rdev->pm.dpm.boot_ps = rps;
6727 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6728 rdev->pm.dpm.uvd_ps = rps;
6731 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6732 struct radeon_ps *rps, int index,
6733 union pplib_clock_info *clock_info)
6735 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6736 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6737 struct si_power_info *si_pi = si_get_pi(rdev);
6738 struct ni_ps *ps = ni_get_ps(rps);
6739 u16 leakage_voltage;
6740 struct rv7xx_pl *pl = &ps->performance_levels[index];
6743 ps->performance_level_count = index + 1;
6745 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6746 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6747 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6748 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6750 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6751 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6752 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6753 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6754 si_pi->sys_pcie_mask,
6755 si_pi->boot_pcie_gen,
6756 clock_info->si.ucPCIEGen);
6758 /* patch up vddc if necessary */
6759 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6762 pl->vddc = leakage_voltage;
6764 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6765 pi->acpi_vddc = pl->vddc;
6766 eg_pi->acpi_vddci = pl->vddci;
6767 si_pi->acpi_pcie_gen = pl->pcie_gen;
6770 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6772 /* XXX disable for A0 tahiti */
6773 si_pi->ulv.supported = false;
6774 si_pi->ulv.pl = *pl;
6775 si_pi->ulv.one_pcie_lane_in_ulv = false;
6776 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6777 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6778 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6781 if (pi->min_vddc_in_table > pl->vddc)
6782 pi->min_vddc_in_table = pl->vddc;
6784 if (pi->max_vddc_in_table < pl->vddc)
6785 pi->max_vddc_in_table = pl->vddc;
6787 /* patch up boot state */
6788 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6789 u16 vddc, vddci, mvdd;
6790 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6791 pl->mclk = rdev->clock.default_mclk;
6792 pl->sclk = rdev->clock.default_sclk;
6795 si_pi->mvdd_bootup_value = mvdd;
6798 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6799 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6800 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6801 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6802 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6807 static int si_parse_power_table(struct radeon_device *rdev)
6809 struct radeon_mode_info *mode_info = &rdev->mode_info;
6810 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6811 union pplib_power_state *power_state;
6812 int i, j, k, non_clock_array_index, clock_array_index;
6813 union pplib_clock_info *clock_info;
6814 struct _StateArray *state_array;
6815 struct _ClockInfoArray *clock_info_array;
6816 struct _NonClockInfoArray *non_clock_info_array;
6817 union power_info *power_info;
6818 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6821 u8 *power_state_offset;
6824 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6825 &frev, &crev, &data_offset))
6827 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6829 state_array = (struct _StateArray *)
6830 (mode_info->atom_context->bios + data_offset +
6831 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6832 clock_info_array = (struct _ClockInfoArray *)
6833 (mode_info->atom_context->bios + data_offset +
6834 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6835 non_clock_info_array = (struct _NonClockInfoArray *)
6836 (mode_info->atom_context->bios + data_offset +
6837 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6839 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
6840 sizeof(struct radeon_ps),
6842 if (!rdev->pm.dpm.ps)
6844 power_state_offset = (u8 *)state_array->states;
6845 for (i = 0; i < state_array->ucNumEntries; i++) {
6847 power_state = (union pplib_power_state *)power_state_offset;
6848 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6849 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6850 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6851 if (!rdev->pm.power_state[i].clock_info)
6853 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6855 kfree(rdev->pm.dpm.ps);
6858 rdev->pm.dpm.ps[i].ps_priv = ps;
6859 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6861 non_clock_info_array->ucEntrySize);
6863 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6864 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6865 clock_array_index = idx[j];
6866 if (clock_array_index >= clock_info_array->ucNumEntries)
6868 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6870 clock_info = (union pplib_clock_info *)
6871 ((u8 *)&clock_info_array->clockInfo[0] +
6872 (clock_array_index * clock_info_array->ucEntrySize));
6873 si_parse_pplib_clock_info(rdev,
6874 &rdev->pm.dpm.ps[i], k,
6878 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6880 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6882 /* fill in the vce power states */
6883 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6885 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6886 clock_info = (union pplib_clock_info *)
6887 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6888 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6889 sclk |= clock_info->si.ucEngineClockHigh << 16;
6890 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6891 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6892 rdev->pm.dpm.vce_states[i].sclk = sclk;
6893 rdev->pm.dpm.vce_states[i].mclk = mclk;
6899 int si_dpm_init(struct radeon_device *rdev)
6901 struct rv7xx_power_info *pi;
6902 struct evergreen_power_info *eg_pi;
6903 struct ni_power_info *ni_pi;
6904 struct si_power_info *si_pi;
6905 struct atom_clock_dividers dividers;
6906 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN;
6907 struct pci_dev *root = rdev->pdev->bus->self;
6910 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6913 rdev->pm.dpm.priv = si_pi;
6918 if (!pci_is_root_bus(rdev->pdev->bus))
6919 speed_cap = pcie_get_speed_cap(root);
6920 if (speed_cap == PCI_SPEED_UNKNOWN) {
6921 si_pi->sys_pcie_mask = 0;
6923 if (speed_cap == PCIE_SPEED_8_0GT)
6924 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
6925 RADEON_PCIE_SPEED_50 |
6926 RADEON_PCIE_SPEED_80;
6927 else if (speed_cap == PCIE_SPEED_5_0GT)
6928 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |
6929 RADEON_PCIE_SPEED_50;
6931 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;
6933 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6934 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6936 si_set_max_cu_value(rdev);
6938 rv770_get_max_vddc(rdev);
6939 si_get_leakage_vddc(rdev);
6940 si_patch_dependency_tables_based_on_leakage(rdev);
6943 eg_pi->acpi_vddci = 0;
6944 pi->min_vddc_in_table = 0;
6945 pi->max_vddc_in_table = 0;
6947 ret = r600_get_platform_caps(rdev);
6951 ret = r600_parse_extended_power_table(rdev);
6955 ret = si_parse_power_table(rdev);
6959 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6961 sizeof(struct radeon_clock_voltage_dependency_entry),
6963 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6964 r600_free_extended_power_table(rdev);
6967 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6975 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6977 if (rdev->pm.dpm.voltage_response_time == 0)
6978 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6979 if (rdev->pm.dpm.backbias_response_time == 0)
6980 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6982 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6983 0, false, ÷rs);
6985 pi->ref_div = dividers.ref_div + 1;
6987 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6989 eg_pi->smu_uvd_hs = false;
6991 pi->mclk_strobe_mode_threshold = 40000;
6992 if (si_is_special_1gb_platform(rdev))
6993 pi->mclk_stutter_mode_threshold = 0;
6995 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6996 pi->mclk_edc_enable_threshold = 40000;
6997 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6999 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7001 pi->voltage_control =
7002 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7003 VOLTAGE_OBJ_GPIO_LUT);
7004 if (!pi->voltage_control) {
7005 si_pi->voltage_control_svi2 =
7006 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7008 if (si_pi->voltage_control_svi2)
7009 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7010 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7014 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7015 VOLTAGE_OBJ_GPIO_LUT);
7017 eg_pi->vddci_control =
7018 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7019 VOLTAGE_OBJ_GPIO_LUT);
7020 if (!eg_pi->vddci_control)
7021 si_pi->vddci_control_svi2 =
7022 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7025 si_pi->vddc_phase_shed_control =
7026 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7027 VOLTAGE_OBJ_PHASE_LUT);
7029 rv770_get_engine_memory_ss(rdev);
7031 pi->asi = RV770_ASI_DFLT;
7032 pi->pasi = CYPRESS_HASI_DFLT;
7033 pi->vrc = SISLANDS_VRC_DFLT;
7035 pi->gfx_clock_gating = true;
7037 eg_pi->sclk_deep_sleep = true;
7038 si_pi->sclk_deep_sleep_above_low = false;
7040 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7041 pi->thermal_protection = true;
7043 pi->thermal_protection = false;
7045 eg_pi->dynamic_ac_timing = true;
7047 eg_pi->light_sleep = true;
7048 #if defined(CONFIG_ACPI)
7049 eg_pi->pcie_performance_request =
7050 radeon_acpi_is_pcie_performance_request_supported(rdev);
7052 eg_pi->pcie_performance_request = false;
7055 si_pi->sram_end = SMC_RAM_END;
7057 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7058 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7059 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7060 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7061 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7062 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7063 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7065 si_initialize_powertune_defaults(rdev);
7067 /* make sure dc limits are valid */
7068 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7069 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7070 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7071 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7073 si_pi->fan_ctrl_is_in_default_mode = true;
7078 void si_dpm_fini(struct radeon_device *rdev)
7082 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7083 kfree(rdev->pm.dpm.ps[i].ps_priv);
7085 kfree(rdev->pm.dpm.ps);
7086 kfree(rdev->pm.dpm.priv);
7087 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7088 r600_free_extended_power_table(rdev);
7091 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7094 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7095 struct radeon_ps *rps = &eg_pi->current_rps;
7096 struct ni_ps *ps = ni_get_ps(rps);
7097 struct rv7xx_pl *pl;
7099 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7100 CURRENT_STATE_INDEX_SHIFT;
7102 if (current_index >= ps->performance_level_count) {
7103 seq_printf(m, "invalid dpm profile %d\n", current_index);
7105 pl = &ps->performance_levels[current_index];
7106 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7107 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7108 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7112 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7114 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7115 struct radeon_ps *rps = &eg_pi->current_rps;
7116 struct ni_ps *ps = ni_get_ps(rps);
7117 struct rv7xx_pl *pl;
7119 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7120 CURRENT_STATE_INDEX_SHIFT;
7122 if (current_index >= ps->performance_level_count) {
7125 pl = &ps->performance_levels[current_index];
7130 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7132 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7133 struct radeon_ps *rps = &eg_pi->current_rps;
7134 struct ni_ps *ps = ni_get_ps(rps);
7135 struct rv7xx_pl *pl;
7137 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7138 CURRENT_STATE_INDEX_SHIFT;
7140 if (current_index >= ps->performance_level_count) {
7143 pl = &ps->performance_levels[current_index];