2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include <drm/radeon_drm.h>
34 #include "si_blit_shaders.h"
35 #include "clearstate_si.h"
36 #include "radeon_ucode.h"
41 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
42 static void si_pcie_gen3_enable(struct radeon_device *rdev);
43 static void si_program_aspm(struct radeon_device *rdev);
44 extern void sumo_rlc_fini(struct radeon_device *rdev);
45 extern int sumo_rlc_init(struct radeon_device *rdev);
46 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
47 extern void r600_ih_ring_fini(struct radeon_device *rdev);
48 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
49 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
50 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
51 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
52 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
53 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
54 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
56 static void si_init_pg(struct radeon_device *rdev);
57 static void si_init_cg(struct radeon_device *rdev);
58 static void si_fini_pg(struct radeon_device *rdev);
59 static void si_fini_cg(struct radeon_device *rdev);
60 static void si_rlc_stop(struct radeon_device *rdev);
62 static const u32 verde_rlc_save_restore_register_list[] =
64 (0x8000 << 16) | (0x98f4 >> 2),
66 (0x8040 << 16) | (0x98f4 >> 2),
68 (0x8000 << 16) | (0xe80 >> 2),
70 (0x8040 << 16) | (0xe80 >> 2),
72 (0x8000 << 16) | (0x89bc >> 2),
74 (0x8040 << 16) | (0x89bc >> 2),
76 (0x8000 << 16) | (0x8c1c >> 2),
78 (0x8040 << 16) | (0x8c1c >> 2),
80 (0x9c00 << 16) | (0x98f0 >> 2),
82 (0x9c00 << 16) | (0xe7c >> 2),
84 (0x8000 << 16) | (0x9148 >> 2),
86 (0x8040 << 16) | (0x9148 >> 2),
88 (0x9c00 << 16) | (0x9150 >> 2),
90 (0x9c00 << 16) | (0x897c >> 2),
92 (0x9c00 << 16) | (0x8d8c >> 2),
94 (0x9c00 << 16) | (0xac54 >> 2),
97 (0x9c00 << 16) | (0x98f8 >> 2),
99 (0x9c00 << 16) | (0x9910 >> 2),
101 (0x9c00 << 16) | (0x9914 >> 2),
103 (0x9c00 << 16) | (0x9918 >> 2),
105 (0x9c00 << 16) | (0x991c >> 2),
107 (0x9c00 << 16) | (0x9920 >> 2),
109 (0x9c00 << 16) | (0x9924 >> 2),
111 (0x9c00 << 16) | (0x9928 >> 2),
113 (0x9c00 << 16) | (0x992c >> 2),
115 (0x9c00 << 16) | (0x9930 >> 2),
117 (0x9c00 << 16) | (0x9934 >> 2),
119 (0x9c00 << 16) | (0x9938 >> 2),
121 (0x9c00 << 16) | (0x993c >> 2),
123 (0x9c00 << 16) | (0x9940 >> 2),
125 (0x9c00 << 16) | (0x9944 >> 2),
127 (0x9c00 << 16) | (0x9948 >> 2),
129 (0x9c00 << 16) | (0x994c >> 2),
131 (0x9c00 << 16) | (0x9950 >> 2),
133 (0x9c00 << 16) | (0x9954 >> 2),
135 (0x9c00 << 16) | (0x9958 >> 2),
137 (0x9c00 << 16) | (0x995c >> 2),
139 (0x9c00 << 16) | (0x9960 >> 2),
141 (0x9c00 << 16) | (0x9964 >> 2),
143 (0x9c00 << 16) | (0x9968 >> 2),
145 (0x9c00 << 16) | (0x996c >> 2),
147 (0x9c00 << 16) | (0x9970 >> 2),
149 (0x9c00 << 16) | (0x9974 >> 2),
151 (0x9c00 << 16) | (0x9978 >> 2),
153 (0x9c00 << 16) | (0x997c >> 2),
155 (0x9c00 << 16) | (0x9980 >> 2),
157 (0x9c00 << 16) | (0x9984 >> 2),
159 (0x9c00 << 16) | (0x9988 >> 2),
161 (0x9c00 << 16) | (0x998c >> 2),
163 (0x9c00 << 16) | (0x8c00 >> 2),
165 (0x9c00 << 16) | (0x8c14 >> 2),
167 (0x9c00 << 16) | (0x8c04 >> 2),
169 (0x9c00 << 16) | (0x8c08 >> 2),
171 (0x8000 << 16) | (0x9b7c >> 2),
173 (0x8040 << 16) | (0x9b7c >> 2),
175 (0x8000 << 16) | (0xe84 >> 2),
177 (0x8040 << 16) | (0xe84 >> 2),
179 (0x8000 << 16) | (0x89c0 >> 2),
181 (0x8040 << 16) | (0x89c0 >> 2),
183 (0x8000 << 16) | (0x914c >> 2),
185 (0x8040 << 16) | (0x914c >> 2),
187 (0x8000 << 16) | (0x8c20 >> 2),
189 (0x8040 << 16) | (0x8c20 >> 2),
191 (0x8000 << 16) | (0x9354 >> 2),
193 (0x8040 << 16) | (0x9354 >> 2),
195 (0x9c00 << 16) | (0x9060 >> 2),
197 (0x9c00 << 16) | (0x9364 >> 2),
199 (0x9c00 << 16) | (0x9100 >> 2),
201 (0x9c00 << 16) | (0x913c >> 2),
203 (0x8000 << 16) | (0x90e0 >> 2),
205 (0x8000 << 16) | (0x90e4 >> 2),
207 (0x8000 << 16) | (0x90e8 >> 2),
209 (0x8040 << 16) | (0x90e0 >> 2),
211 (0x8040 << 16) | (0x90e4 >> 2),
213 (0x8040 << 16) | (0x90e8 >> 2),
215 (0x9c00 << 16) | (0x8bcc >> 2),
217 (0x9c00 << 16) | (0x8b24 >> 2),
219 (0x9c00 << 16) | (0x88c4 >> 2),
221 (0x9c00 << 16) | (0x8e50 >> 2),
223 (0x9c00 << 16) | (0x8c0c >> 2),
225 (0x9c00 << 16) | (0x8e58 >> 2),
227 (0x9c00 << 16) | (0x8e5c >> 2),
229 (0x9c00 << 16) | (0x9508 >> 2),
231 (0x9c00 << 16) | (0x950c >> 2),
233 (0x9c00 << 16) | (0x9494 >> 2),
235 (0x9c00 << 16) | (0xac0c >> 2),
237 (0x9c00 << 16) | (0xac10 >> 2),
239 (0x9c00 << 16) | (0xac14 >> 2),
241 (0x9c00 << 16) | (0xae00 >> 2),
243 (0x9c00 << 16) | (0xac08 >> 2),
245 (0x9c00 << 16) | (0x88d4 >> 2),
247 (0x9c00 << 16) | (0x88c8 >> 2),
249 (0x9c00 << 16) | (0x88cc >> 2),
251 (0x9c00 << 16) | (0x89b0 >> 2),
253 (0x9c00 << 16) | (0x8b10 >> 2),
255 (0x9c00 << 16) | (0x8a14 >> 2),
257 (0x9c00 << 16) | (0x9830 >> 2),
259 (0x9c00 << 16) | (0x9834 >> 2),
261 (0x9c00 << 16) | (0x9838 >> 2),
263 (0x9c00 << 16) | (0x9a10 >> 2),
265 (0x8000 << 16) | (0x9870 >> 2),
267 (0x8000 << 16) | (0x9874 >> 2),
269 (0x8001 << 16) | (0x9870 >> 2),
271 (0x8001 << 16) | (0x9874 >> 2),
273 (0x8040 << 16) | (0x9870 >> 2),
275 (0x8040 << 16) | (0x9874 >> 2),
277 (0x8041 << 16) | (0x9870 >> 2),
279 (0x8041 << 16) | (0x9874 >> 2),
284 static const u32 tahiti_golden_rlc_registers[] =
286 0xc424, 0xffffffff, 0x00601005,
287 0xc47c, 0xffffffff, 0x10104040,
288 0xc488, 0xffffffff, 0x0100000a,
289 0xc314, 0xffffffff, 0x00000800,
290 0xc30c, 0xffffffff, 0x800000f4,
291 0xf4a8, 0xffffffff, 0x00000000
294 static const u32 tahiti_golden_registers[] =
296 0x9a10, 0x00010000, 0x00018208,
297 0x9830, 0xffffffff, 0x00000000,
298 0x9834, 0xf00fffff, 0x00000400,
299 0x9838, 0x0002021c, 0x00020200,
300 0xc78, 0x00000080, 0x00000000,
301 0xd030, 0x000300c0, 0x00800040,
302 0xd830, 0x000300c0, 0x00800040,
303 0x5bb0, 0x000000f0, 0x00000070,
304 0x5bc0, 0x00200000, 0x50100000,
305 0x7030, 0x31000311, 0x00000011,
306 0x277c, 0x00000003, 0x000007ff,
307 0x240c, 0x000007ff, 0x00000000,
308 0x8a14, 0xf000001f, 0x00000007,
309 0x8b24, 0xffffffff, 0x00ffffff,
310 0x8b10, 0x0000ff0f, 0x00000000,
311 0x28a4c, 0x07ffffff, 0x4e000000,
312 0x28350, 0x3f3f3fff, 0x2a00126a,
313 0x30, 0x000000ff, 0x0040,
314 0x34, 0x00000040, 0x00004040,
315 0x9100, 0x07ffffff, 0x03000000,
316 0x8e88, 0x01ff1f3f, 0x00000000,
317 0x8e84, 0x01ff1f3f, 0x00000000,
318 0x9060, 0x0000007f, 0x00000020,
319 0x9508, 0x00010000, 0x00010000,
320 0xac14, 0x00000200, 0x000002fb,
321 0xac10, 0xffffffff, 0x0000543b,
322 0xac0c, 0xffffffff, 0xa9210876,
323 0x88d0, 0xffffffff, 0x000fff40,
324 0x88d4, 0x0000001f, 0x00000010,
325 0x1410, 0x20000000, 0x20fffed8,
326 0x15c0, 0x000c0fc0, 0x000c0400
329 static const u32 tahiti_golden_registers2[] =
331 0xc64, 0x00000001, 0x00000001
334 static const u32 pitcairn_golden_rlc_registers[] =
336 0xc424, 0xffffffff, 0x00601004,
337 0xc47c, 0xffffffff, 0x10102020,
338 0xc488, 0xffffffff, 0x01000020,
339 0xc314, 0xffffffff, 0x00000800,
340 0xc30c, 0xffffffff, 0x800000a4
343 static const u32 pitcairn_golden_registers[] =
345 0x9a10, 0x00010000, 0x00018208,
346 0x9830, 0xffffffff, 0x00000000,
347 0x9834, 0xf00fffff, 0x00000400,
348 0x9838, 0x0002021c, 0x00020200,
349 0xc78, 0x00000080, 0x00000000,
350 0xd030, 0x000300c0, 0x00800040,
351 0xd830, 0x000300c0, 0x00800040,
352 0x5bb0, 0x000000f0, 0x00000070,
353 0x5bc0, 0x00200000, 0x50100000,
354 0x7030, 0x31000311, 0x00000011,
355 0x2ae4, 0x00073ffe, 0x000022a2,
356 0x240c, 0x000007ff, 0x00000000,
357 0x8a14, 0xf000001f, 0x00000007,
358 0x8b24, 0xffffffff, 0x00ffffff,
359 0x8b10, 0x0000ff0f, 0x00000000,
360 0x28a4c, 0x07ffffff, 0x4e000000,
361 0x28350, 0x3f3f3fff, 0x2a00126a,
362 0x30, 0x000000ff, 0x0040,
363 0x34, 0x00000040, 0x00004040,
364 0x9100, 0x07ffffff, 0x03000000,
365 0x9060, 0x0000007f, 0x00000020,
366 0x9508, 0x00010000, 0x00010000,
367 0xac14, 0x000003ff, 0x000000f7,
368 0xac10, 0xffffffff, 0x00000000,
369 0xac0c, 0xffffffff, 0x32761054,
370 0x88d4, 0x0000001f, 0x00000010,
371 0x15c0, 0x000c0fc0, 0x000c0400
374 static const u32 verde_golden_rlc_registers[] =
376 0xc424, 0xffffffff, 0x033f1005,
377 0xc47c, 0xffffffff, 0x10808020,
378 0xc488, 0xffffffff, 0x00800008,
379 0xc314, 0xffffffff, 0x00001000,
380 0xc30c, 0xffffffff, 0x80010014
383 static const u32 verde_golden_registers[] =
385 0x9a10, 0x00010000, 0x00018208,
386 0x9830, 0xffffffff, 0x00000000,
387 0x9834, 0xf00fffff, 0x00000400,
388 0x9838, 0x0002021c, 0x00020200,
389 0xc78, 0x00000080, 0x00000000,
390 0xd030, 0x000300c0, 0x00800040,
391 0xd030, 0x000300c0, 0x00800040,
392 0xd830, 0x000300c0, 0x00800040,
393 0xd830, 0x000300c0, 0x00800040,
394 0x5bb0, 0x000000f0, 0x00000070,
395 0x5bc0, 0x00200000, 0x50100000,
396 0x7030, 0x31000311, 0x00000011,
397 0x2ae4, 0x00073ffe, 0x000022a2,
398 0x2ae4, 0x00073ffe, 0x000022a2,
399 0x2ae4, 0x00073ffe, 0x000022a2,
400 0x240c, 0x000007ff, 0x00000000,
401 0x240c, 0x000007ff, 0x00000000,
402 0x240c, 0x000007ff, 0x00000000,
403 0x8a14, 0xf000001f, 0x00000007,
404 0x8a14, 0xf000001f, 0x00000007,
405 0x8a14, 0xf000001f, 0x00000007,
406 0x8b24, 0xffffffff, 0x00ffffff,
407 0x8b10, 0x0000ff0f, 0x00000000,
408 0x28a4c, 0x07ffffff, 0x4e000000,
409 0x28350, 0x3f3f3fff, 0x0000124a,
410 0x28350, 0x3f3f3fff, 0x0000124a,
411 0x28350, 0x3f3f3fff, 0x0000124a,
412 0x30, 0x000000ff, 0x0040,
413 0x34, 0x00000040, 0x00004040,
414 0x9100, 0x07ffffff, 0x03000000,
415 0x9100, 0x07ffffff, 0x03000000,
416 0x8e88, 0x01ff1f3f, 0x00000000,
417 0x8e88, 0x01ff1f3f, 0x00000000,
418 0x8e88, 0x01ff1f3f, 0x00000000,
419 0x8e84, 0x01ff1f3f, 0x00000000,
420 0x8e84, 0x01ff1f3f, 0x00000000,
421 0x8e84, 0x01ff1f3f, 0x00000000,
422 0x9060, 0x0000007f, 0x00000020,
423 0x9508, 0x00010000, 0x00010000,
424 0xac14, 0x000003ff, 0x00000003,
425 0xac14, 0x000003ff, 0x00000003,
426 0xac14, 0x000003ff, 0x00000003,
427 0xac10, 0xffffffff, 0x00000000,
428 0xac10, 0xffffffff, 0x00000000,
429 0xac10, 0xffffffff, 0x00000000,
430 0xac0c, 0xffffffff, 0x00001032,
431 0xac0c, 0xffffffff, 0x00001032,
432 0xac0c, 0xffffffff, 0x00001032,
433 0x88d4, 0x0000001f, 0x00000010,
434 0x88d4, 0x0000001f, 0x00000010,
435 0x88d4, 0x0000001f, 0x00000010,
436 0x15c0, 0x000c0fc0, 0x000c0400
439 static const u32 oland_golden_rlc_registers[] =
441 0xc424, 0xffffffff, 0x00601005,
442 0xc47c, 0xffffffff, 0x10104040,
443 0xc488, 0xffffffff, 0x0100000a,
444 0xc314, 0xffffffff, 0x00000800,
445 0xc30c, 0xffffffff, 0x800000f4
448 static const u32 oland_golden_registers[] =
450 0x9a10, 0x00010000, 0x00018208,
451 0x9830, 0xffffffff, 0x00000000,
452 0x9834, 0xf00fffff, 0x00000400,
453 0x9838, 0x0002021c, 0x00020200,
454 0xc78, 0x00000080, 0x00000000,
455 0xd030, 0x000300c0, 0x00800040,
456 0xd830, 0x000300c0, 0x00800040,
457 0x5bb0, 0x000000f0, 0x00000070,
458 0x5bc0, 0x00200000, 0x50100000,
459 0x7030, 0x31000311, 0x00000011,
460 0x2ae4, 0x00073ffe, 0x000022a2,
461 0x240c, 0x000007ff, 0x00000000,
462 0x8a14, 0xf000001f, 0x00000007,
463 0x8b24, 0xffffffff, 0x00ffffff,
464 0x8b10, 0x0000ff0f, 0x00000000,
465 0x28a4c, 0x07ffffff, 0x4e000000,
466 0x28350, 0x3f3f3fff, 0x00000082,
467 0x30, 0x000000ff, 0x0040,
468 0x34, 0x00000040, 0x00004040,
469 0x9100, 0x07ffffff, 0x03000000,
470 0x9060, 0x0000007f, 0x00000020,
471 0x9508, 0x00010000, 0x00010000,
472 0xac14, 0x000003ff, 0x000000f3,
473 0xac10, 0xffffffff, 0x00000000,
474 0xac0c, 0xffffffff, 0x00003210,
475 0x88d4, 0x0000001f, 0x00000010,
476 0x15c0, 0x000c0fc0, 0x000c0400
479 static const u32 hainan_golden_registers[] =
481 0x9a10, 0x00010000, 0x00018208,
482 0x9830, 0xffffffff, 0x00000000,
483 0x9834, 0xf00fffff, 0x00000400,
484 0x9838, 0x0002021c, 0x00020200,
485 0xd0c0, 0xff000fff, 0x00000100,
486 0xd030, 0x000300c0, 0x00800040,
487 0xd8c0, 0xff000fff, 0x00000100,
488 0xd830, 0x000300c0, 0x00800040,
489 0x2ae4, 0x00073ffe, 0x000022a2,
490 0x240c, 0x000007ff, 0x00000000,
491 0x8a14, 0xf000001f, 0x00000007,
492 0x8b24, 0xffffffff, 0x00ffffff,
493 0x8b10, 0x0000ff0f, 0x00000000,
494 0x28a4c, 0x07ffffff, 0x4e000000,
495 0x28350, 0x3f3f3fff, 0x00000000,
496 0x30, 0x000000ff, 0x0040,
497 0x34, 0x00000040, 0x00004040,
498 0x9100, 0x03e00000, 0x03600000,
499 0x9060, 0x0000007f, 0x00000020,
500 0x9508, 0x00010000, 0x00010000,
501 0xac14, 0x000003ff, 0x000000f1,
502 0xac10, 0xffffffff, 0x00000000,
503 0xac0c, 0xffffffff, 0x00003210,
504 0x88d4, 0x0000001f, 0x00000010,
505 0x15c0, 0x000c0fc0, 0x000c0400
508 static const u32 hainan_golden_registers2[] =
510 0x98f8, 0xffffffff, 0x02010001
513 static const u32 tahiti_mgcg_cgcg_init[] =
515 0xc400, 0xffffffff, 0xfffffffc,
516 0x802c, 0xffffffff, 0xe0000000,
517 0x9a60, 0xffffffff, 0x00000100,
518 0x92a4, 0xffffffff, 0x00000100,
519 0xc164, 0xffffffff, 0x00000100,
520 0x9774, 0xffffffff, 0x00000100,
521 0x8984, 0xffffffff, 0x06000100,
522 0x8a18, 0xffffffff, 0x00000100,
523 0x92a0, 0xffffffff, 0x00000100,
524 0xc380, 0xffffffff, 0x00000100,
525 0x8b28, 0xffffffff, 0x00000100,
526 0x9144, 0xffffffff, 0x00000100,
527 0x8d88, 0xffffffff, 0x00000100,
528 0x8d8c, 0xffffffff, 0x00000100,
529 0x9030, 0xffffffff, 0x00000100,
530 0x9034, 0xffffffff, 0x00000100,
531 0x9038, 0xffffffff, 0x00000100,
532 0x903c, 0xffffffff, 0x00000100,
533 0xad80, 0xffffffff, 0x00000100,
534 0xac54, 0xffffffff, 0x00000100,
535 0x897c, 0xffffffff, 0x06000100,
536 0x9868, 0xffffffff, 0x00000100,
537 0x9510, 0xffffffff, 0x00000100,
538 0xaf04, 0xffffffff, 0x00000100,
539 0xae04, 0xffffffff, 0x00000100,
540 0x949c, 0xffffffff, 0x00000100,
541 0x802c, 0xffffffff, 0xe0000000,
542 0x9160, 0xffffffff, 0x00010000,
543 0x9164, 0xffffffff, 0x00030002,
544 0x9168, 0xffffffff, 0x00040007,
545 0x916c, 0xffffffff, 0x00060005,
546 0x9170, 0xffffffff, 0x00090008,
547 0x9174, 0xffffffff, 0x00020001,
548 0x9178, 0xffffffff, 0x00040003,
549 0x917c, 0xffffffff, 0x00000007,
550 0x9180, 0xffffffff, 0x00060005,
551 0x9184, 0xffffffff, 0x00090008,
552 0x9188, 0xffffffff, 0x00030002,
553 0x918c, 0xffffffff, 0x00050004,
554 0x9190, 0xffffffff, 0x00000008,
555 0x9194, 0xffffffff, 0x00070006,
556 0x9198, 0xffffffff, 0x000a0009,
557 0x919c, 0xffffffff, 0x00040003,
558 0x91a0, 0xffffffff, 0x00060005,
559 0x91a4, 0xffffffff, 0x00000009,
560 0x91a8, 0xffffffff, 0x00080007,
561 0x91ac, 0xffffffff, 0x000b000a,
562 0x91b0, 0xffffffff, 0x00050004,
563 0x91b4, 0xffffffff, 0x00070006,
564 0x91b8, 0xffffffff, 0x0008000b,
565 0x91bc, 0xffffffff, 0x000a0009,
566 0x91c0, 0xffffffff, 0x000d000c,
567 0x91c4, 0xffffffff, 0x00060005,
568 0x91c8, 0xffffffff, 0x00080007,
569 0x91cc, 0xffffffff, 0x0000000b,
570 0x91d0, 0xffffffff, 0x000a0009,
571 0x91d4, 0xffffffff, 0x000d000c,
572 0x91d8, 0xffffffff, 0x00070006,
573 0x91dc, 0xffffffff, 0x00090008,
574 0x91e0, 0xffffffff, 0x0000000c,
575 0x91e4, 0xffffffff, 0x000b000a,
576 0x91e8, 0xffffffff, 0x000e000d,
577 0x91ec, 0xffffffff, 0x00080007,
578 0x91f0, 0xffffffff, 0x000a0009,
579 0x91f4, 0xffffffff, 0x0000000d,
580 0x91f8, 0xffffffff, 0x000c000b,
581 0x91fc, 0xffffffff, 0x000f000e,
582 0x9200, 0xffffffff, 0x00090008,
583 0x9204, 0xffffffff, 0x000b000a,
584 0x9208, 0xffffffff, 0x000c000f,
585 0x920c, 0xffffffff, 0x000e000d,
586 0x9210, 0xffffffff, 0x00110010,
587 0x9214, 0xffffffff, 0x000a0009,
588 0x9218, 0xffffffff, 0x000c000b,
589 0x921c, 0xffffffff, 0x0000000f,
590 0x9220, 0xffffffff, 0x000e000d,
591 0x9224, 0xffffffff, 0x00110010,
592 0x9228, 0xffffffff, 0x000b000a,
593 0x922c, 0xffffffff, 0x000d000c,
594 0x9230, 0xffffffff, 0x00000010,
595 0x9234, 0xffffffff, 0x000f000e,
596 0x9238, 0xffffffff, 0x00120011,
597 0x923c, 0xffffffff, 0x000c000b,
598 0x9240, 0xffffffff, 0x000e000d,
599 0x9244, 0xffffffff, 0x00000011,
600 0x9248, 0xffffffff, 0x0010000f,
601 0x924c, 0xffffffff, 0x00130012,
602 0x9250, 0xffffffff, 0x000d000c,
603 0x9254, 0xffffffff, 0x000f000e,
604 0x9258, 0xffffffff, 0x00100013,
605 0x925c, 0xffffffff, 0x00120011,
606 0x9260, 0xffffffff, 0x00150014,
607 0x9264, 0xffffffff, 0x000e000d,
608 0x9268, 0xffffffff, 0x0010000f,
609 0x926c, 0xffffffff, 0x00000013,
610 0x9270, 0xffffffff, 0x00120011,
611 0x9274, 0xffffffff, 0x00150014,
612 0x9278, 0xffffffff, 0x000f000e,
613 0x927c, 0xffffffff, 0x00110010,
614 0x9280, 0xffffffff, 0x00000014,
615 0x9284, 0xffffffff, 0x00130012,
616 0x9288, 0xffffffff, 0x00160015,
617 0x928c, 0xffffffff, 0x0010000f,
618 0x9290, 0xffffffff, 0x00120011,
619 0x9294, 0xffffffff, 0x00000015,
620 0x9298, 0xffffffff, 0x00140013,
621 0x929c, 0xffffffff, 0x00170016,
622 0x9150, 0xffffffff, 0x96940200,
623 0x8708, 0xffffffff, 0x00900100,
624 0xc478, 0xffffffff, 0x00000080,
625 0xc404, 0xffffffff, 0x0020003f,
626 0x30, 0xffffffff, 0x0000001c,
627 0x34, 0x000f0000, 0x000f0000,
628 0x160c, 0xffffffff, 0x00000100,
629 0x1024, 0xffffffff, 0x00000100,
630 0x102c, 0x00000101, 0x00000000,
631 0x20a8, 0xffffffff, 0x00000104,
632 0x264c, 0x000c0000, 0x000c0000,
633 0x2648, 0x000c0000, 0x000c0000,
634 0x55e4, 0xff000fff, 0x00000100,
635 0x55e8, 0x00000001, 0x00000001,
636 0x2f50, 0x00000001, 0x00000001,
637 0x30cc, 0xc0000fff, 0x00000104,
638 0xc1e4, 0x00000001, 0x00000001,
639 0xd0c0, 0xfffffff0, 0x00000100,
640 0xd8c0, 0xfffffff0, 0x00000100
643 static const u32 pitcairn_mgcg_cgcg_init[] =
645 0xc400, 0xffffffff, 0xfffffffc,
646 0x802c, 0xffffffff, 0xe0000000,
647 0x9a60, 0xffffffff, 0x00000100,
648 0x92a4, 0xffffffff, 0x00000100,
649 0xc164, 0xffffffff, 0x00000100,
650 0x9774, 0xffffffff, 0x00000100,
651 0x8984, 0xffffffff, 0x06000100,
652 0x8a18, 0xffffffff, 0x00000100,
653 0x92a0, 0xffffffff, 0x00000100,
654 0xc380, 0xffffffff, 0x00000100,
655 0x8b28, 0xffffffff, 0x00000100,
656 0x9144, 0xffffffff, 0x00000100,
657 0x8d88, 0xffffffff, 0x00000100,
658 0x8d8c, 0xffffffff, 0x00000100,
659 0x9030, 0xffffffff, 0x00000100,
660 0x9034, 0xffffffff, 0x00000100,
661 0x9038, 0xffffffff, 0x00000100,
662 0x903c, 0xffffffff, 0x00000100,
663 0xad80, 0xffffffff, 0x00000100,
664 0xac54, 0xffffffff, 0x00000100,
665 0x897c, 0xffffffff, 0x06000100,
666 0x9868, 0xffffffff, 0x00000100,
667 0x9510, 0xffffffff, 0x00000100,
668 0xaf04, 0xffffffff, 0x00000100,
669 0xae04, 0xffffffff, 0x00000100,
670 0x949c, 0xffffffff, 0x00000100,
671 0x802c, 0xffffffff, 0xe0000000,
672 0x9160, 0xffffffff, 0x00010000,
673 0x9164, 0xffffffff, 0x00030002,
674 0x9168, 0xffffffff, 0x00040007,
675 0x916c, 0xffffffff, 0x00060005,
676 0x9170, 0xffffffff, 0x00090008,
677 0x9174, 0xffffffff, 0x00020001,
678 0x9178, 0xffffffff, 0x00040003,
679 0x917c, 0xffffffff, 0x00000007,
680 0x9180, 0xffffffff, 0x00060005,
681 0x9184, 0xffffffff, 0x00090008,
682 0x9188, 0xffffffff, 0x00030002,
683 0x918c, 0xffffffff, 0x00050004,
684 0x9190, 0xffffffff, 0x00000008,
685 0x9194, 0xffffffff, 0x00070006,
686 0x9198, 0xffffffff, 0x000a0009,
687 0x919c, 0xffffffff, 0x00040003,
688 0x91a0, 0xffffffff, 0x00060005,
689 0x91a4, 0xffffffff, 0x00000009,
690 0x91a8, 0xffffffff, 0x00080007,
691 0x91ac, 0xffffffff, 0x000b000a,
692 0x91b0, 0xffffffff, 0x00050004,
693 0x91b4, 0xffffffff, 0x00070006,
694 0x91b8, 0xffffffff, 0x0008000b,
695 0x91bc, 0xffffffff, 0x000a0009,
696 0x91c0, 0xffffffff, 0x000d000c,
697 0x9200, 0xffffffff, 0x00090008,
698 0x9204, 0xffffffff, 0x000b000a,
699 0x9208, 0xffffffff, 0x000c000f,
700 0x920c, 0xffffffff, 0x000e000d,
701 0x9210, 0xffffffff, 0x00110010,
702 0x9214, 0xffffffff, 0x000a0009,
703 0x9218, 0xffffffff, 0x000c000b,
704 0x921c, 0xffffffff, 0x0000000f,
705 0x9220, 0xffffffff, 0x000e000d,
706 0x9224, 0xffffffff, 0x00110010,
707 0x9228, 0xffffffff, 0x000b000a,
708 0x922c, 0xffffffff, 0x000d000c,
709 0x9230, 0xffffffff, 0x00000010,
710 0x9234, 0xffffffff, 0x000f000e,
711 0x9238, 0xffffffff, 0x00120011,
712 0x923c, 0xffffffff, 0x000c000b,
713 0x9240, 0xffffffff, 0x000e000d,
714 0x9244, 0xffffffff, 0x00000011,
715 0x9248, 0xffffffff, 0x0010000f,
716 0x924c, 0xffffffff, 0x00130012,
717 0x9250, 0xffffffff, 0x000d000c,
718 0x9254, 0xffffffff, 0x000f000e,
719 0x9258, 0xffffffff, 0x00100013,
720 0x925c, 0xffffffff, 0x00120011,
721 0x9260, 0xffffffff, 0x00150014,
722 0x9150, 0xffffffff, 0x96940200,
723 0x8708, 0xffffffff, 0x00900100,
724 0xc478, 0xffffffff, 0x00000080,
725 0xc404, 0xffffffff, 0x0020003f,
726 0x30, 0xffffffff, 0x0000001c,
727 0x34, 0x000f0000, 0x000f0000,
728 0x160c, 0xffffffff, 0x00000100,
729 0x1024, 0xffffffff, 0x00000100,
730 0x102c, 0x00000101, 0x00000000,
731 0x20a8, 0xffffffff, 0x00000104,
732 0x55e4, 0xff000fff, 0x00000100,
733 0x55e8, 0x00000001, 0x00000001,
734 0x2f50, 0x00000001, 0x00000001,
735 0x30cc, 0xc0000fff, 0x00000104,
736 0xc1e4, 0x00000001, 0x00000001,
737 0xd0c0, 0xfffffff0, 0x00000100,
738 0xd8c0, 0xfffffff0, 0x00000100
741 static const u32 verde_mgcg_cgcg_init[] =
743 0xc400, 0xffffffff, 0xfffffffc,
744 0x802c, 0xffffffff, 0xe0000000,
745 0x9a60, 0xffffffff, 0x00000100,
746 0x92a4, 0xffffffff, 0x00000100,
747 0xc164, 0xffffffff, 0x00000100,
748 0x9774, 0xffffffff, 0x00000100,
749 0x8984, 0xffffffff, 0x06000100,
750 0x8a18, 0xffffffff, 0x00000100,
751 0x92a0, 0xffffffff, 0x00000100,
752 0xc380, 0xffffffff, 0x00000100,
753 0x8b28, 0xffffffff, 0x00000100,
754 0x9144, 0xffffffff, 0x00000100,
755 0x8d88, 0xffffffff, 0x00000100,
756 0x8d8c, 0xffffffff, 0x00000100,
757 0x9030, 0xffffffff, 0x00000100,
758 0x9034, 0xffffffff, 0x00000100,
759 0x9038, 0xffffffff, 0x00000100,
760 0x903c, 0xffffffff, 0x00000100,
761 0xad80, 0xffffffff, 0x00000100,
762 0xac54, 0xffffffff, 0x00000100,
763 0x897c, 0xffffffff, 0x06000100,
764 0x9868, 0xffffffff, 0x00000100,
765 0x9510, 0xffffffff, 0x00000100,
766 0xaf04, 0xffffffff, 0x00000100,
767 0xae04, 0xffffffff, 0x00000100,
768 0x949c, 0xffffffff, 0x00000100,
769 0x802c, 0xffffffff, 0xe0000000,
770 0x9160, 0xffffffff, 0x00010000,
771 0x9164, 0xffffffff, 0x00030002,
772 0x9168, 0xffffffff, 0x00040007,
773 0x916c, 0xffffffff, 0x00060005,
774 0x9170, 0xffffffff, 0x00090008,
775 0x9174, 0xffffffff, 0x00020001,
776 0x9178, 0xffffffff, 0x00040003,
777 0x917c, 0xffffffff, 0x00000007,
778 0x9180, 0xffffffff, 0x00060005,
779 0x9184, 0xffffffff, 0x00090008,
780 0x9188, 0xffffffff, 0x00030002,
781 0x918c, 0xffffffff, 0x00050004,
782 0x9190, 0xffffffff, 0x00000008,
783 0x9194, 0xffffffff, 0x00070006,
784 0x9198, 0xffffffff, 0x000a0009,
785 0x919c, 0xffffffff, 0x00040003,
786 0x91a0, 0xffffffff, 0x00060005,
787 0x91a4, 0xffffffff, 0x00000009,
788 0x91a8, 0xffffffff, 0x00080007,
789 0x91ac, 0xffffffff, 0x000b000a,
790 0x91b0, 0xffffffff, 0x00050004,
791 0x91b4, 0xffffffff, 0x00070006,
792 0x91b8, 0xffffffff, 0x0008000b,
793 0x91bc, 0xffffffff, 0x000a0009,
794 0x91c0, 0xffffffff, 0x000d000c,
795 0x9200, 0xffffffff, 0x00090008,
796 0x9204, 0xffffffff, 0x000b000a,
797 0x9208, 0xffffffff, 0x000c000f,
798 0x920c, 0xffffffff, 0x000e000d,
799 0x9210, 0xffffffff, 0x00110010,
800 0x9214, 0xffffffff, 0x000a0009,
801 0x9218, 0xffffffff, 0x000c000b,
802 0x921c, 0xffffffff, 0x0000000f,
803 0x9220, 0xffffffff, 0x000e000d,
804 0x9224, 0xffffffff, 0x00110010,
805 0x9228, 0xffffffff, 0x000b000a,
806 0x922c, 0xffffffff, 0x000d000c,
807 0x9230, 0xffffffff, 0x00000010,
808 0x9234, 0xffffffff, 0x000f000e,
809 0x9238, 0xffffffff, 0x00120011,
810 0x923c, 0xffffffff, 0x000c000b,
811 0x9240, 0xffffffff, 0x000e000d,
812 0x9244, 0xffffffff, 0x00000011,
813 0x9248, 0xffffffff, 0x0010000f,
814 0x924c, 0xffffffff, 0x00130012,
815 0x9250, 0xffffffff, 0x000d000c,
816 0x9254, 0xffffffff, 0x000f000e,
817 0x9258, 0xffffffff, 0x00100013,
818 0x925c, 0xffffffff, 0x00120011,
819 0x9260, 0xffffffff, 0x00150014,
820 0x9150, 0xffffffff, 0x96940200,
821 0x8708, 0xffffffff, 0x00900100,
822 0xc478, 0xffffffff, 0x00000080,
823 0xc404, 0xffffffff, 0x0020003f,
824 0x30, 0xffffffff, 0x0000001c,
825 0x34, 0x000f0000, 0x000f0000,
826 0x160c, 0xffffffff, 0x00000100,
827 0x1024, 0xffffffff, 0x00000100,
828 0x102c, 0x00000101, 0x00000000,
829 0x20a8, 0xffffffff, 0x00000104,
830 0x264c, 0x000c0000, 0x000c0000,
831 0x2648, 0x000c0000, 0x000c0000,
832 0x55e4, 0xff000fff, 0x00000100,
833 0x55e8, 0x00000001, 0x00000001,
834 0x2f50, 0x00000001, 0x00000001,
835 0x30cc, 0xc0000fff, 0x00000104,
836 0xc1e4, 0x00000001, 0x00000001,
837 0xd0c0, 0xfffffff0, 0x00000100,
838 0xd8c0, 0xfffffff0, 0x00000100
841 static const u32 oland_mgcg_cgcg_init[] =
843 0xc400, 0xffffffff, 0xfffffffc,
844 0x802c, 0xffffffff, 0xe0000000,
845 0x9a60, 0xffffffff, 0x00000100,
846 0x92a4, 0xffffffff, 0x00000100,
847 0xc164, 0xffffffff, 0x00000100,
848 0x9774, 0xffffffff, 0x00000100,
849 0x8984, 0xffffffff, 0x06000100,
850 0x8a18, 0xffffffff, 0x00000100,
851 0x92a0, 0xffffffff, 0x00000100,
852 0xc380, 0xffffffff, 0x00000100,
853 0x8b28, 0xffffffff, 0x00000100,
854 0x9144, 0xffffffff, 0x00000100,
855 0x8d88, 0xffffffff, 0x00000100,
856 0x8d8c, 0xffffffff, 0x00000100,
857 0x9030, 0xffffffff, 0x00000100,
858 0x9034, 0xffffffff, 0x00000100,
859 0x9038, 0xffffffff, 0x00000100,
860 0x903c, 0xffffffff, 0x00000100,
861 0xad80, 0xffffffff, 0x00000100,
862 0xac54, 0xffffffff, 0x00000100,
863 0x897c, 0xffffffff, 0x06000100,
864 0x9868, 0xffffffff, 0x00000100,
865 0x9510, 0xffffffff, 0x00000100,
866 0xaf04, 0xffffffff, 0x00000100,
867 0xae04, 0xffffffff, 0x00000100,
868 0x949c, 0xffffffff, 0x00000100,
869 0x802c, 0xffffffff, 0xe0000000,
870 0x9160, 0xffffffff, 0x00010000,
871 0x9164, 0xffffffff, 0x00030002,
872 0x9168, 0xffffffff, 0x00040007,
873 0x916c, 0xffffffff, 0x00060005,
874 0x9170, 0xffffffff, 0x00090008,
875 0x9174, 0xffffffff, 0x00020001,
876 0x9178, 0xffffffff, 0x00040003,
877 0x917c, 0xffffffff, 0x00000007,
878 0x9180, 0xffffffff, 0x00060005,
879 0x9184, 0xffffffff, 0x00090008,
880 0x9188, 0xffffffff, 0x00030002,
881 0x918c, 0xffffffff, 0x00050004,
882 0x9190, 0xffffffff, 0x00000008,
883 0x9194, 0xffffffff, 0x00070006,
884 0x9198, 0xffffffff, 0x000a0009,
885 0x919c, 0xffffffff, 0x00040003,
886 0x91a0, 0xffffffff, 0x00060005,
887 0x91a4, 0xffffffff, 0x00000009,
888 0x91a8, 0xffffffff, 0x00080007,
889 0x91ac, 0xffffffff, 0x000b000a,
890 0x91b0, 0xffffffff, 0x00050004,
891 0x91b4, 0xffffffff, 0x00070006,
892 0x91b8, 0xffffffff, 0x0008000b,
893 0x91bc, 0xffffffff, 0x000a0009,
894 0x91c0, 0xffffffff, 0x000d000c,
895 0x91c4, 0xffffffff, 0x00060005,
896 0x91c8, 0xffffffff, 0x00080007,
897 0x91cc, 0xffffffff, 0x0000000b,
898 0x91d0, 0xffffffff, 0x000a0009,
899 0x91d4, 0xffffffff, 0x000d000c,
900 0x9150, 0xffffffff, 0x96940200,
901 0x8708, 0xffffffff, 0x00900100,
902 0xc478, 0xffffffff, 0x00000080,
903 0xc404, 0xffffffff, 0x0020003f,
904 0x30, 0xffffffff, 0x0000001c,
905 0x34, 0x000f0000, 0x000f0000,
906 0x160c, 0xffffffff, 0x00000100,
907 0x1024, 0xffffffff, 0x00000100,
908 0x102c, 0x00000101, 0x00000000,
909 0x20a8, 0xffffffff, 0x00000104,
910 0x264c, 0x000c0000, 0x000c0000,
911 0x2648, 0x000c0000, 0x000c0000,
912 0x55e4, 0xff000fff, 0x00000100,
913 0x55e8, 0x00000001, 0x00000001,
914 0x2f50, 0x00000001, 0x00000001,
915 0x30cc, 0xc0000fff, 0x00000104,
916 0xc1e4, 0x00000001, 0x00000001,
917 0xd0c0, 0xfffffff0, 0x00000100,
918 0xd8c0, 0xfffffff0, 0x00000100
921 static const u32 hainan_mgcg_cgcg_init[] =
923 0xc400, 0xffffffff, 0xfffffffc,
924 0x802c, 0xffffffff, 0xe0000000,
925 0x9a60, 0xffffffff, 0x00000100,
926 0x92a4, 0xffffffff, 0x00000100,
927 0xc164, 0xffffffff, 0x00000100,
928 0x9774, 0xffffffff, 0x00000100,
929 0x8984, 0xffffffff, 0x06000100,
930 0x8a18, 0xffffffff, 0x00000100,
931 0x92a0, 0xffffffff, 0x00000100,
932 0xc380, 0xffffffff, 0x00000100,
933 0x8b28, 0xffffffff, 0x00000100,
934 0x9144, 0xffffffff, 0x00000100,
935 0x8d88, 0xffffffff, 0x00000100,
936 0x8d8c, 0xffffffff, 0x00000100,
937 0x9030, 0xffffffff, 0x00000100,
938 0x9034, 0xffffffff, 0x00000100,
939 0x9038, 0xffffffff, 0x00000100,
940 0x903c, 0xffffffff, 0x00000100,
941 0xad80, 0xffffffff, 0x00000100,
942 0xac54, 0xffffffff, 0x00000100,
943 0x897c, 0xffffffff, 0x06000100,
944 0x9868, 0xffffffff, 0x00000100,
945 0x9510, 0xffffffff, 0x00000100,
946 0xaf04, 0xffffffff, 0x00000100,
947 0xae04, 0xffffffff, 0x00000100,
948 0x949c, 0xffffffff, 0x00000100,
949 0x802c, 0xffffffff, 0xe0000000,
950 0x9160, 0xffffffff, 0x00010000,
951 0x9164, 0xffffffff, 0x00030002,
952 0x9168, 0xffffffff, 0x00040007,
953 0x916c, 0xffffffff, 0x00060005,
954 0x9170, 0xffffffff, 0x00090008,
955 0x9174, 0xffffffff, 0x00020001,
956 0x9178, 0xffffffff, 0x00040003,
957 0x917c, 0xffffffff, 0x00000007,
958 0x9180, 0xffffffff, 0x00060005,
959 0x9184, 0xffffffff, 0x00090008,
960 0x9188, 0xffffffff, 0x00030002,
961 0x918c, 0xffffffff, 0x00050004,
962 0x9190, 0xffffffff, 0x00000008,
963 0x9194, 0xffffffff, 0x00070006,
964 0x9198, 0xffffffff, 0x000a0009,
965 0x919c, 0xffffffff, 0x00040003,
966 0x91a0, 0xffffffff, 0x00060005,
967 0x91a4, 0xffffffff, 0x00000009,
968 0x91a8, 0xffffffff, 0x00080007,
969 0x91ac, 0xffffffff, 0x000b000a,
970 0x91b0, 0xffffffff, 0x00050004,
971 0x91b4, 0xffffffff, 0x00070006,
972 0x91b8, 0xffffffff, 0x0008000b,
973 0x91bc, 0xffffffff, 0x000a0009,
974 0x91c0, 0xffffffff, 0x000d000c,
975 0x91c4, 0xffffffff, 0x00060005,
976 0x91c8, 0xffffffff, 0x00080007,
977 0x91cc, 0xffffffff, 0x0000000b,
978 0x91d0, 0xffffffff, 0x000a0009,
979 0x91d4, 0xffffffff, 0x000d000c,
980 0x9150, 0xffffffff, 0x96940200,
981 0x8708, 0xffffffff, 0x00900100,
982 0xc478, 0xffffffff, 0x00000080,
983 0xc404, 0xffffffff, 0x0020003f,
984 0x30, 0xffffffff, 0x0000001c,
985 0x34, 0x000f0000, 0x000f0000,
986 0x160c, 0xffffffff, 0x00000100,
987 0x1024, 0xffffffff, 0x00000100,
988 0x20a8, 0xffffffff, 0x00000104,
989 0x264c, 0x000c0000, 0x000c0000,
990 0x2648, 0x000c0000, 0x000c0000,
991 0x2f50, 0x00000001, 0x00000001,
992 0x30cc, 0xc0000fff, 0x00000104,
993 0xc1e4, 0x00000001, 0x00000001,
994 0xd0c0, 0xfffffff0, 0x00000100,
995 0xd8c0, 0xfffffff0, 0x00000100
998 static u32 verde_pg_init[] =
1000 0x353c, 0xffffffff, 0x40000,
1001 0x3538, 0xffffffff, 0x200010ff,
1002 0x353c, 0xffffffff, 0x0,
1003 0x353c, 0xffffffff, 0x0,
1004 0x353c, 0xffffffff, 0x0,
1005 0x353c, 0xffffffff, 0x0,
1006 0x353c, 0xffffffff, 0x0,
1007 0x353c, 0xffffffff, 0x7007,
1008 0x3538, 0xffffffff, 0x300010ff,
1009 0x353c, 0xffffffff, 0x0,
1010 0x353c, 0xffffffff, 0x0,
1011 0x353c, 0xffffffff, 0x0,
1012 0x353c, 0xffffffff, 0x0,
1013 0x353c, 0xffffffff, 0x0,
1014 0x353c, 0xffffffff, 0x400000,
1015 0x3538, 0xffffffff, 0x100010ff,
1016 0x353c, 0xffffffff, 0x0,
1017 0x353c, 0xffffffff, 0x0,
1018 0x353c, 0xffffffff, 0x0,
1019 0x353c, 0xffffffff, 0x0,
1020 0x353c, 0xffffffff, 0x0,
1021 0x353c, 0xffffffff, 0x120200,
1022 0x3538, 0xffffffff, 0x500010ff,
1023 0x353c, 0xffffffff, 0x0,
1024 0x353c, 0xffffffff, 0x0,
1025 0x353c, 0xffffffff, 0x0,
1026 0x353c, 0xffffffff, 0x0,
1027 0x353c, 0xffffffff, 0x0,
1028 0x353c, 0xffffffff, 0x1e1e16,
1029 0x3538, 0xffffffff, 0x600010ff,
1030 0x353c, 0xffffffff, 0x0,
1031 0x353c, 0xffffffff, 0x0,
1032 0x353c, 0xffffffff, 0x0,
1033 0x353c, 0xffffffff, 0x0,
1034 0x353c, 0xffffffff, 0x0,
1035 0x353c, 0xffffffff, 0x171f1e,
1036 0x3538, 0xffffffff, 0x700010ff,
1037 0x353c, 0xffffffff, 0x0,
1038 0x353c, 0xffffffff, 0x0,
1039 0x353c, 0xffffffff, 0x0,
1040 0x353c, 0xffffffff, 0x0,
1041 0x353c, 0xffffffff, 0x0,
1042 0x353c, 0xffffffff, 0x0,
1043 0x3538, 0xffffffff, 0x9ff,
1044 0x3500, 0xffffffff, 0x0,
1045 0x3504, 0xffffffff, 0x10000800,
1046 0x3504, 0xffffffff, 0xf,
1047 0x3504, 0xffffffff, 0xf,
1048 0x3500, 0xffffffff, 0x4,
1049 0x3504, 0xffffffff, 0x1000051e,
1050 0x3504, 0xffffffff, 0xffff,
1051 0x3504, 0xffffffff, 0xffff,
1052 0x3500, 0xffffffff, 0x8,
1053 0x3504, 0xffffffff, 0x80500,
1054 0x3500, 0xffffffff, 0x12,
1055 0x3504, 0xffffffff, 0x9050c,
1056 0x3500, 0xffffffff, 0x1d,
1057 0x3504, 0xffffffff, 0xb052c,
1058 0x3500, 0xffffffff, 0x2a,
1059 0x3504, 0xffffffff, 0x1053e,
1060 0x3500, 0xffffffff, 0x2d,
1061 0x3504, 0xffffffff, 0x10546,
1062 0x3500, 0xffffffff, 0x30,
1063 0x3504, 0xffffffff, 0xa054e,
1064 0x3500, 0xffffffff, 0x3c,
1065 0x3504, 0xffffffff, 0x1055f,
1066 0x3500, 0xffffffff, 0x3f,
1067 0x3504, 0xffffffff, 0x10567,
1068 0x3500, 0xffffffff, 0x42,
1069 0x3504, 0xffffffff, 0x1056f,
1070 0x3500, 0xffffffff, 0x45,
1071 0x3504, 0xffffffff, 0x10572,
1072 0x3500, 0xffffffff, 0x48,
1073 0x3504, 0xffffffff, 0x20575,
1074 0x3500, 0xffffffff, 0x4c,
1075 0x3504, 0xffffffff, 0x190801,
1076 0x3500, 0xffffffff, 0x67,
1077 0x3504, 0xffffffff, 0x1082a,
1078 0x3500, 0xffffffff, 0x6a,
1079 0x3504, 0xffffffff, 0x1b082d,
1080 0x3500, 0xffffffff, 0x87,
1081 0x3504, 0xffffffff, 0x310851,
1082 0x3500, 0xffffffff, 0xba,
1083 0x3504, 0xffffffff, 0x891,
1084 0x3500, 0xffffffff, 0xbc,
1085 0x3504, 0xffffffff, 0x893,
1086 0x3500, 0xffffffff, 0xbe,
1087 0x3504, 0xffffffff, 0x20895,
1088 0x3500, 0xffffffff, 0xc2,
1089 0x3504, 0xffffffff, 0x20899,
1090 0x3500, 0xffffffff, 0xc6,
1091 0x3504, 0xffffffff, 0x2089d,
1092 0x3500, 0xffffffff, 0xca,
1093 0x3504, 0xffffffff, 0x8a1,
1094 0x3500, 0xffffffff, 0xcc,
1095 0x3504, 0xffffffff, 0x8a3,
1096 0x3500, 0xffffffff, 0xce,
1097 0x3504, 0xffffffff, 0x308a5,
1098 0x3500, 0xffffffff, 0xd3,
1099 0x3504, 0xffffffff, 0x6d08cd,
1100 0x3500, 0xffffffff, 0x142,
1101 0x3504, 0xffffffff, 0x2000095a,
1102 0x3504, 0xffffffff, 0x1,
1103 0x3500, 0xffffffff, 0x144,
1104 0x3504, 0xffffffff, 0x301f095b,
1105 0x3500, 0xffffffff, 0x165,
1106 0x3504, 0xffffffff, 0xc094d,
1107 0x3500, 0xffffffff, 0x173,
1108 0x3504, 0xffffffff, 0xf096d,
1109 0x3500, 0xffffffff, 0x184,
1110 0x3504, 0xffffffff, 0x15097f,
1111 0x3500, 0xffffffff, 0x19b,
1112 0x3504, 0xffffffff, 0xc0998,
1113 0x3500, 0xffffffff, 0x1a9,
1114 0x3504, 0xffffffff, 0x409a7,
1115 0x3500, 0xffffffff, 0x1af,
1116 0x3504, 0xffffffff, 0xcdc,
1117 0x3500, 0xffffffff, 0x1b1,
1118 0x3504, 0xffffffff, 0x800,
1119 0x3508, 0xffffffff, 0x6c9b2000,
1120 0x3510, 0xfc00, 0x2000,
1121 0x3544, 0xffffffff, 0xfc0,
1122 0x28d4, 0x00000100, 0x100
1125 static void si_init_golden_registers(struct radeon_device *rdev)
1127 switch (rdev->family) {
1129 radeon_program_register_sequence(rdev,
1130 tahiti_golden_registers,
1131 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1132 radeon_program_register_sequence(rdev,
1133 tahiti_golden_rlc_registers,
1134 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1135 radeon_program_register_sequence(rdev,
1136 tahiti_mgcg_cgcg_init,
1137 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1138 radeon_program_register_sequence(rdev,
1139 tahiti_golden_registers2,
1140 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1143 radeon_program_register_sequence(rdev,
1144 pitcairn_golden_registers,
1145 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1146 radeon_program_register_sequence(rdev,
1147 pitcairn_golden_rlc_registers,
1148 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1149 radeon_program_register_sequence(rdev,
1150 pitcairn_mgcg_cgcg_init,
1151 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1154 radeon_program_register_sequence(rdev,
1155 verde_golden_registers,
1156 (const u32)ARRAY_SIZE(verde_golden_registers));
1157 radeon_program_register_sequence(rdev,
1158 verde_golden_rlc_registers,
1159 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1160 radeon_program_register_sequence(rdev,
1161 verde_mgcg_cgcg_init,
1162 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1163 radeon_program_register_sequence(rdev,
1165 (const u32)ARRAY_SIZE(verde_pg_init));
1168 radeon_program_register_sequence(rdev,
1169 oland_golden_registers,
1170 (const u32)ARRAY_SIZE(oland_golden_registers));
1171 radeon_program_register_sequence(rdev,
1172 oland_golden_rlc_registers,
1173 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1174 radeon_program_register_sequence(rdev,
1175 oland_mgcg_cgcg_init,
1176 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1179 radeon_program_register_sequence(rdev,
1180 hainan_golden_registers,
1181 (const u32)ARRAY_SIZE(hainan_golden_registers));
1182 radeon_program_register_sequence(rdev,
1183 hainan_golden_registers2,
1184 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1185 radeon_program_register_sequence(rdev,
1186 hainan_mgcg_cgcg_init,
1187 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1195 * si_get_allowed_info_register - fetch the register for the info ioctl
1197 * @rdev: radeon_device pointer
1198 * @reg: register offset in bytes
1199 * @val: register value
1201 * Returns 0 for success or -EINVAL for an invalid register
1204 int si_get_allowed_info_register(struct radeon_device *rdev,
1210 case GRBM_STATUS_SE0:
1211 case GRBM_STATUS_SE1:
1214 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1215 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
1224 #define PCIE_BUS_CLK 10000
1225 #define TCLK (PCIE_BUS_CLK / 10)
1228 * si_get_xclk - get the xclk
1230 * @rdev: radeon_device pointer
1232 * Returns the reference clock used by the gfx engine
1235 u32 si_get_xclk(struct radeon_device *rdev)
1237 u32 reference_clock = rdev->clock.spll.reference_freq;
1240 tmp = RREG32(CG_CLKPIN_CNTL_2);
1241 if (tmp & MUX_TCLK_TO_XCLK)
1244 tmp = RREG32(CG_CLKPIN_CNTL);
1245 if (tmp & XTALIN_DIVIDE)
1246 return reference_clock / 4;
1248 return reference_clock;
1251 /* get temperature in millidegrees */
1252 int si_get_temp(struct radeon_device *rdev)
1255 int actual_temp = 0;
1257 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1263 actual_temp = temp & 0x1ff;
1265 actual_temp = (actual_temp * 1000);
1270 #define TAHITI_IO_MC_REGS_SIZE 36
1272 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1273 {0x0000006f, 0x03044000},
1274 {0x00000070, 0x0480c018},
1275 {0x00000071, 0x00000040},
1276 {0x00000072, 0x01000000},
1277 {0x00000074, 0x000000ff},
1278 {0x00000075, 0x00143400},
1279 {0x00000076, 0x08ec0800},
1280 {0x00000077, 0x040000cc},
1281 {0x00000079, 0x00000000},
1282 {0x0000007a, 0x21000409},
1283 {0x0000007c, 0x00000000},
1284 {0x0000007d, 0xe8000000},
1285 {0x0000007e, 0x044408a8},
1286 {0x0000007f, 0x00000003},
1287 {0x00000080, 0x00000000},
1288 {0x00000081, 0x01000000},
1289 {0x00000082, 0x02000000},
1290 {0x00000083, 0x00000000},
1291 {0x00000084, 0xe3f3e4f4},
1292 {0x00000085, 0x00052024},
1293 {0x00000087, 0x00000000},
1294 {0x00000088, 0x66036603},
1295 {0x00000089, 0x01000000},
1296 {0x0000008b, 0x1c0a0000},
1297 {0x0000008c, 0xff010000},
1298 {0x0000008e, 0xffffefff},
1299 {0x0000008f, 0xfff3efff},
1300 {0x00000090, 0xfff3efbf},
1301 {0x00000094, 0x00101101},
1302 {0x00000095, 0x00000fff},
1303 {0x00000096, 0x00116fff},
1304 {0x00000097, 0x60010000},
1305 {0x00000098, 0x10010000},
1306 {0x00000099, 0x00006000},
1307 {0x0000009a, 0x00001000},
1308 {0x0000009f, 0x00a77400}
1311 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1312 {0x0000006f, 0x03044000},
1313 {0x00000070, 0x0480c018},
1314 {0x00000071, 0x00000040},
1315 {0x00000072, 0x01000000},
1316 {0x00000074, 0x000000ff},
1317 {0x00000075, 0x00143400},
1318 {0x00000076, 0x08ec0800},
1319 {0x00000077, 0x040000cc},
1320 {0x00000079, 0x00000000},
1321 {0x0000007a, 0x21000409},
1322 {0x0000007c, 0x00000000},
1323 {0x0000007d, 0xe8000000},
1324 {0x0000007e, 0x044408a8},
1325 {0x0000007f, 0x00000003},
1326 {0x00000080, 0x00000000},
1327 {0x00000081, 0x01000000},
1328 {0x00000082, 0x02000000},
1329 {0x00000083, 0x00000000},
1330 {0x00000084, 0xe3f3e4f4},
1331 {0x00000085, 0x00052024},
1332 {0x00000087, 0x00000000},
1333 {0x00000088, 0x66036603},
1334 {0x00000089, 0x01000000},
1335 {0x0000008b, 0x1c0a0000},
1336 {0x0000008c, 0xff010000},
1337 {0x0000008e, 0xffffefff},
1338 {0x0000008f, 0xfff3efff},
1339 {0x00000090, 0xfff3efbf},
1340 {0x00000094, 0x00101101},
1341 {0x00000095, 0x00000fff},
1342 {0x00000096, 0x00116fff},
1343 {0x00000097, 0x60010000},
1344 {0x00000098, 0x10010000},
1345 {0x00000099, 0x00006000},
1346 {0x0000009a, 0x00001000},
1347 {0x0000009f, 0x00a47400}
1350 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1351 {0x0000006f, 0x03044000},
1352 {0x00000070, 0x0480c018},
1353 {0x00000071, 0x00000040},
1354 {0x00000072, 0x01000000},
1355 {0x00000074, 0x000000ff},
1356 {0x00000075, 0x00143400},
1357 {0x00000076, 0x08ec0800},
1358 {0x00000077, 0x040000cc},
1359 {0x00000079, 0x00000000},
1360 {0x0000007a, 0x21000409},
1361 {0x0000007c, 0x00000000},
1362 {0x0000007d, 0xe8000000},
1363 {0x0000007e, 0x044408a8},
1364 {0x0000007f, 0x00000003},
1365 {0x00000080, 0x00000000},
1366 {0x00000081, 0x01000000},
1367 {0x00000082, 0x02000000},
1368 {0x00000083, 0x00000000},
1369 {0x00000084, 0xe3f3e4f4},
1370 {0x00000085, 0x00052024},
1371 {0x00000087, 0x00000000},
1372 {0x00000088, 0x66036603},
1373 {0x00000089, 0x01000000},
1374 {0x0000008b, 0x1c0a0000},
1375 {0x0000008c, 0xff010000},
1376 {0x0000008e, 0xffffefff},
1377 {0x0000008f, 0xfff3efff},
1378 {0x00000090, 0xfff3efbf},
1379 {0x00000094, 0x00101101},
1380 {0x00000095, 0x00000fff},
1381 {0x00000096, 0x00116fff},
1382 {0x00000097, 0x60010000},
1383 {0x00000098, 0x10010000},
1384 {0x00000099, 0x00006000},
1385 {0x0000009a, 0x00001000},
1386 {0x0000009f, 0x00a37400}
1389 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1390 {0x0000006f, 0x03044000},
1391 {0x00000070, 0x0480c018},
1392 {0x00000071, 0x00000040},
1393 {0x00000072, 0x01000000},
1394 {0x00000074, 0x000000ff},
1395 {0x00000075, 0x00143400},
1396 {0x00000076, 0x08ec0800},
1397 {0x00000077, 0x040000cc},
1398 {0x00000079, 0x00000000},
1399 {0x0000007a, 0x21000409},
1400 {0x0000007c, 0x00000000},
1401 {0x0000007d, 0xe8000000},
1402 {0x0000007e, 0x044408a8},
1403 {0x0000007f, 0x00000003},
1404 {0x00000080, 0x00000000},
1405 {0x00000081, 0x01000000},
1406 {0x00000082, 0x02000000},
1407 {0x00000083, 0x00000000},
1408 {0x00000084, 0xe3f3e4f4},
1409 {0x00000085, 0x00052024},
1410 {0x00000087, 0x00000000},
1411 {0x00000088, 0x66036603},
1412 {0x00000089, 0x01000000},
1413 {0x0000008b, 0x1c0a0000},
1414 {0x0000008c, 0xff010000},
1415 {0x0000008e, 0xffffefff},
1416 {0x0000008f, 0xfff3efff},
1417 {0x00000090, 0xfff3efbf},
1418 {0x00000094, 0x00101101},
1419 {0x00000095, 0x00000fff},
1420 {0x00000096, 0x00116fff},
1421 {0x00000097, 0x60010000},
1422 {0x00000098, 0x10010000},
1423 {0x00000099, 0x00006000},
1424 {0x0000009a, 0x00001000},
1425 {0x0000009f, 0x00a17730}
1428 static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1429 {0x0000006f, 0x03044000},
1430 {0x00000070, 0x0480c018},
1431 {0x00000071, 0x00000040},
1432 {0x00000072, 0x01000000},
1433 {0x00000074, 0x000000ff},
1434 {0x00000075, 0x00143400},
1435 {0x00000076, 0x08ec0800},
1436 {0x00000077, 0x040000cc},
1437 {0x00000079, 0x00000000},
1438 {0x0000007a, 0x21000409},
1439 {0x0000007c, 0x00000000},
1440 {0x0000007d, 0xe8000000},
1441 {0x0000007e, 0x044408a8},
1442 {0x0000007f, 0x00000003},
1443 {0x00000080, 0x00000000},
1444 {0x00000081, 0x01000000},
1445 {0x00000082, 0x02000000},
1446 {0x00000083, 0x00000000},
1447 {0x00000084, 0xe3f3e4f4},
1448 {0x00000085, 0x00052024},
1449 {0x00000087, 0x00000000},
1450 {0x00000088, 0x66036603},
1451 {0x00000089, 0x01000000},
1452 {0x0000008b, 0x1c0a0000},
1453 {0x0000008c, 0xff010000},
1454 {0x0000008e, 0xffffefff},
1455 {0x0000008f, 0xfff3efff},
1456 {0x00000090, 0xfff3efbf},
1457 {0x00000094, 0x00101101},
1458 {0x00000095, 0x00000fff},
1459 {0x00000096, 0x00116fff},
1460 {0x00000097, 0x60010000},
1461 {0x00000098, 0x10010000},
1462 {0x00000099, 0x00006000},
1463 {0x0000009a, 0x00001000},
1464 {0x0000009f, 0x00a07730}
1468 int si_mc_load_microcode(struct radeon_device *rdev)
1470 const __be32 *fw_data = NULL;
1471 const __le32 *new_fw_data = NULL;
1472 u32 running, blackout = 0;
1473 u32 *io_mc_regs = NULL;
1474 const __le32 *new_io_mc_regs = NULL;
1475 int i, regs_size, ucode_size;
1481 const struct mc_firmware_header_v1_0 *hdr =
1482 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1484 radeon_ucode_print_mc_hdr(&hdr->header);
1485 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1486 new_io_mc_regs = (const __le32 *)
1487 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1488 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1489 new_fw_data = (const __le32 *)
1490 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1492 ucode_size = rdev->mc_fw->size / 4;
1494 switch (rdev->family) {
1496 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1497 regs_size = TAHITI_IO_MC_REGS_SIZE;
1500 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1501 regs_size = TAHITI_IO_MC_REGS_SIZE;
1505 io_mc_regs = (u32 *)&verde_io_mc_regs;
1506 regs_size = TAHITI_IO_MC_REGS_SIZE;
1509 io_mc_regs = (u32 *)&oland_io_mc_regs;
1510 regs_size = TAHITI_IO_MC_REGS_SIZE;
1513 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1514 regs_size = TAHITI_IO_MC_REGS_SIZE;
1517 fw_data = (const __be32 *)rdev->mc_fw->data;
1520 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1524 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1525 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1528 /* reset the engine and set to writable */
1529 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1530 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1532 /* load mc io regs */
1533 for (i = 0; i < regs_size; i++) {
1535 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1536 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1538 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1539 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1542 /* load the MC ucode */
1543 for (i = 0; i < ucode_size; i++) {
1545 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1547 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1550 /* put the engine back into the active state */
1551 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1552 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1553 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1555 /* wait for training to complete */
1556 for (i = 0; i < rdev->usec_timeout; i++) {
1557 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1561 for (i = 0; i < rdev->usec_timeout; i++) {
1562 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1568 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1574 static int si_init_microcode(struct radeon_device *rdev)
1576 const char *chip_name;
1577 const char *new_chip_name;
1578 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1579 size_t smc_req_size, mc2_req_size;
1586 switch (rdev->family) {
1588 chip_name = "TAHITI";
1589 new_chip_name = "tahiti";
1590 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1591 me_req_size = SI_PM4_UCODE_SIZE * 4;
1592 ce_req_size = SI_CE_UCODE_SIZE * 4;
1593 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1594 mc_req_size = SI_MC_UCODE_SIZE * 4;
1595 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1596 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1599 chip_name = "PITCAIRN";
1600 new_chip_name = "pitcairn";
1601 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1602 me_req_size = SI_PM4_UCODE_SIZE * 4;
1603 ce_req_size = SI_CE_UCODE_SIZE * 4;
1604 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1605 mc_req_size = SI_MC_UCODE_SIZE * 4;
1606 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1607 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1610 chip_name = "VERDE";
1611 new_chip_name = "verde";
1612 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1613 me_req_size = SI_PM4_UCODE_SIZE * 4;
1614 ce_req_size = SI_CE_UCODE_SIZE * 4;
1615 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1616 mc_req_size = SI_MC_UCODE_SIZE * 4;
1617 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1618 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1621 chip_name = "OLAND";
1622 new_chip_name = "oland";
1623 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1624 me_req_size = SI_PM4_UCODE_SIZE * 4;
1625 ce_req_size = SI_CE_UCODE_SIZE * 4;
1626 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1627 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1628 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1631 chip_name = "HAINAN";
1632 new_chip_name = "hainan";
1633 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1634 me_req_size = SI_PM4_UCODE_SIZE * 4;
1635 ce_req_size = SI_CE_UCODE_SIZE * 4;
1636 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1637 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1638 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1643 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1645 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", new_chip_name);
1646 err = reject_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1648 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1649 err = reject_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1652 if (rdev->pfp_fw->size != pfp_req_size) {
1654 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1655 rdev->pfp_fw->size, fw_name);
1660 err = radeon_ucode_validate(rdev->pfp_fw);
1663 "si_cp: validation failed for firmware \"%s\"\n",
1671 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", new_chip_name);
1672 err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
1674 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1675 err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
1678 if (rdev->me_fw->size != me_req_size) {
1680 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1681 rdev->me_fw->size, fw_name);
1685 err = radeon_ucode_validate(rdev->me_fw);
1688 "si_cp: validation failed for firmware \"%s\"\n",
1696 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", new_chip_name);
1697 err = reject_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1699 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1700 err = reject_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1703 if (rdev->ce_fw->size != ce_req_size) {
1705 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1706 rdev->ce_fw->size, fw_name);
1710 err = radeon_ucode_validate(rdev->ce_fw);
1713 "si_cp: validation failed for firmware \"%s\"\n",
1721 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", new_chip_name);
1722 err = reject_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1724 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1725 err = reject_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1728 if (rdev->rlc_fw->size != rlc_req_size) {
1730 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
1731 rdev->rlc_fw->size, fw_name);
1735 err = radeon_ucode_validate(rdev->rlc_fw);
1738 "si_cp: validation failed for firmware \"%s\"\n",
1746 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", new_chip_name);
1747 err = reject_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1749 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1750 err = reject_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1752 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1753 err = reject_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1757 if ((rdev->mc_fw->size != mc_req_size) &&
1758 (rdev->mc_fw->size != mc2_req_size)) {
1760 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1761 rdev->mc_fw->size, fw_name);
1764 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1766 err = radeon_ucode_validate(rdev->mc_fw);
1769 "si_cp: validation failed for firmware \"%s\"\n",
1777 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", new_chip_name);
1778 err = reject_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1780 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1781 err = reject_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1784 "smc: error loading firmware \"%s\"\n",
1786 release_firmware(rdev->smc_fw);
1787 rdev->smc_fw = NULL;
1789 } else if (rdev->smc_fw->size != smc_req_size) {
1791 "si_smc: Bogus length %zu in firmware \"%s\"\n",
1792 rdev->smc_fw->size, fw_name);
1796 err = radeon_ucode_validate(rdev->smc_fw);
1799 "si_cp: validation failed for firmware \"%s\"\n",
1808 rdev->new_fw = false;
1809 } else if (new_fw < 6) {
1810 printk(KERN_ERR "si_fw: mixing new and old firmware!\n");
1813 rdev->new_fw = true;
1819 "si_cp: Failed to load firmware \"%s\"\n",
1821 release_firmware(rdev->pfp_fw);
1822 rdev->pfp_fw = NULL;
1823 release_firmware(rdev->me_fw);
1825 release_firmware(rdev->ce_fw);
1827 release_firmware(rdev->rlc_fw);
1828 rdev->rlc_fw = NULL;
1829 release_firmware(rdev->mc_fw);
1831 release_firmware(rdev->smc_fw);
1832 rdev->smc_fw = NULL;
1837 /* watermark setup */
1838 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1839 struct radeon_crtc *radeon_crtc,
1840 struct drm_display_mode *mode,
1841 struct drm_display_mode *other_mode)
1843 u32 tmp, buffer_alloc, i;
1844 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
1847 * There are 3 line buffers, each one shared by 2 display controllers.
1848 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1849 * the display controllers. The paritioning is done via one of four
1850 * preset allocations specified in bits 21:20:
1852 * 2 - whole lb, other crtc must be disabled
1854 /* this can get tricky if we have two large displays on a paired group
1855 * of crtcs. Ideally for multiple large displays we'd assign them to
1856 * non-linked crtcs for maximum line buffer allocation.
1858 if (radeon_crtc->base.enabled && mode) {
1863 tmp = 2; /* whole */
1871 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
1872 DC_LB_MEMORY_CONFIG(tmp));
1874 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1875 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1876 for (i = 0; i < rdev->usec_timeout; i++) {
1877 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1878 DMIF_BUFFERS_ALLOCATED_COMPLETED)
1883 if (radeon_crtc->base.enabled && mode) {
1893 /* controller not enabled, so no lb used */
1897 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
1899 u32 tmp = RREG32(MC_SHARED_CHMAP);
1901 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1924 struct dce6_wm_params {
1925 u32 dram_channels; /* number of dram channels */
1926 u32 yclk; /* bandwidth per dram data pin in kHz */
1927 u32 sclk; /* engine clock in kHz */
1928 u32 disp_clk; /* display clock in kHz */
1929 u32 src_width; /* viewport width */
1930 u32 active_time; /* active display time in ns */
1931 u32 blank_time; /* blank time in ns */
1932 bool interlaced; /* mode is interlaced */
1933 fixed20_12 vsc; /* vertical scale ratio */
1934 u32 num_heads; /* number of active crtcs */
1935 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
1936 u32 lb_size; /* line buffer allocated to pipe */
1937 u32 vtaps; /* vertical scaler taps */
1940 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
1942 /* Calculate raw DRAM Bandwidth */
1943 fixed20_12 dram_efficiency; /* 0.7 */
1944 fixed20_12 yclk, dram_channels, bandwidth;
1947 a.full = dfixed_const(1000);
1948 yclk.full = dfixed_const(wm->yclk);
1949 yclk.full = dfixed_div(yclk, a);
1950 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1951 a.full = dfixed_const(10);
1952 dram_efficiency.full = dfixed_const(7);
1953 dram_efficiency.full = dfixed_div(dram_efficiency, a);
1954 bandwidth.full = dfixed_mul(dram_channels, yclk);
1955 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
1957 return dfixed_trunc(bandwidth);
1960 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
1962 /* Calculate DRAM Bandwidth and the part allocated to display. */
1963 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1964 fixed20_12 yclk, dram_channels, bandwidth;
1967 a.full = dfixed_const(1000);
1968 yclk.full = dfixed_const(wm->yclk);
1969 yclk.full = dfixed_div(yclk, a);
1970 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1971 a.full = dfixed_const(10);
1972 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1973 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1974 bandwidth.full = dfixed_mul(dram_channels, yclk);
1975 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1977 return dfixed_trunc(bandwidth);
1980 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
1982 /* Calculate the display Data return Bandwidth */
1983 fixed20_12 return_efficiency; /* 0.8 */
1984 fixed20_12 sclk, bandwidth;
1987 a.full = dfixed_const(1000);
1988 sclk.full = dfixed_const(wm->sclk);
1989 sclk.full = dfixed_div(sclk, a);
1990 a.full = dfixed_const(10);
1991 return_efficiency.full = dfixed_const(8);
1992 return_efficiency.full = dfixed_div(return_efficiency, a);
1993 a.full = dfixed_const(32);
1994 bandwidth.full = dfixed_mul(a, sclk);
1995 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1997 return dfixed_trunc(bandwidth);
2000 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2005 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
2007 /* Calculate the DMIF Request Bandwidth */
2008 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
2009 fixed20_12 disp_clk, sclk, bandwidth;
2010 fixed20_12 a, b1, b2;
2013 a.full = dfixed_const(1000);
2014 disp_clk.full = dfixed_const(wm->disp_clk);
2015 disp_clk.full = dfixed_div(disp_clk, a);
2016 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
2017 b1.full = dfixed_mul(a, disp_clk);
2019 a.full = dfixed_const(1000);
2020 sclk.full = dfixed_const(wm->sclk);
2021 sclk.full = dfixed_div(sclk, a);
2022 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
2023 b2.full = dfixed_mul(a, sclk);
2025 a.full = dfixed_const(10);
2026 disp_clk_request_efficiency.full = dfixed_const(8);
2027 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
2029 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
2031 a.full = dfixed_const(min_bandwidth);
2032 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
2034 return dfixed_trunc(bandwidth);
2037 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
2039 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
2040 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
2041 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
2042 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
2044 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
2047 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
2049 /* Calculate the display mode Average Bandwidth
2050 * DisplayMode should contain the source and destination dimensions,
2054 fixed20_12 line_time;
2055 fixed20_12 src_width;
2056 fixed20_12 bandwidth;
2059 a.full = dfixed_const(1000);
2060 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2061 line_time.full = dfixed_div(line_time, a);
2062 bpp.full = dfixed_const(wm->bytes_per_pixel);
2063 src_width.full = dfixed_const(wm->src_width);
2064 bandwidth.full = dfixed_mul(src_width, bpp);
2065 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2066 bandwidth.full = dfixed_div(bandwidth, line_time);
2068 return dfixed_trunc(bandwidth);
2071 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
2073 /* First calcualte the latency in ns */
2074 u32 mc_latency = 2000; /* 2000 ns. */
2075 u32 available_bandwidth = dce6_available_bandwidth(wm);
2076 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2077 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2078 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2079 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2080 (wm->num_heads * cursor_line_pair_return_time);
2081 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2082 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2083 u32 tmp, dmif_size = 12288;
2086 if (wm->num_heads == 0)
2089 a.full = dfixed_const(2);
2090 b.full = dfixed_const(1);
2091 if ((wm->vsc.full > a.full) ||
2092 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2094 ((wm->vsc.full >= a.full) && wm->interlaced))
2095 max_src_lines_per_dst_line = 4;
2097 max_src_lines_per_dst_line = 2;
2099 a.full = dfixed_const(available_bandwidth);
2100 b.full = dfixed_const(wm->num_heads);
2101 a.full = dfixed_div(a, b);
2103 b.full = dfixed_const(mc_latency + 512);
2104 c.full = dfixed_const(wm->disp_clk);
2105 b.full = dfixed_div(b, c);
2107 c.full = dfixed_const(dmif_size);
2108 b.full = dfixed_div(c, b);
2110 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
2112 b.full = dfixed_const(1000);
2113 c.full = dfixed_const(wm->disp_clk);
2114 b.full = dfixed_div(c, b);
2115 c.full = dfixed_const(wm->bytes_per_pixel);
2116 b.full = dfixed_mul(b, c);
2118 lb_fill_bw = min(tmp, dfixed_trunc(b));
2120 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2121 b.full = dfixed_const(1000);
2122 c.full = dfixed_const(lb_fill_bw);
2123 b.full = dfixed_div(c, b);
2124 a.full = dfixed_div(a, b);
2125 line_fill_time = dfixed_trunc(a);
2127 if (line_fill_time < wm->active_time)
2130 return latency + (line_fill_time - wm->active_time);
2134 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2136 if (dce6_average_bandwidth(wm) <=
2137 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2143 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2145 if (dce6_average_bandwidth(wm) <=
2146 (dce6_available_bandwidth(wm) / wm->num_heads))
2152 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2154 u32 lb_partitions = wm->lb_size / wm->src_width;
2155 u32 line_time = wm->active_time + wm->blank_time;
2156 u32 latency_tolerant_lines;
2160 a.full = dfixed_const(1);
2161 if (wm->vsc.full > a.full)
2162 latency_tolerant_lines = 1;
2164 if (lb_partitions <= (wm->vtaps + 1))
2165 latency_tolerant_lines = 1;
2167 latency_tolerant_lines = 2;
2170 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2172 if (dce6_latency_watermark(wm) <= latency_hiding)
2178 static void dce6_program_watermarks(struct radeon_device *rdev,
2179 struct radeon_crtc *radeon_crtc,
2180 u32 lb_size, u32 num_heads)
2182 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2183 struct dce6_wm_params wm_low, wm_high;
2187 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2188 u32 priority_a_mark = 0, priority_b_mark = 0;
2189 u32 priority_a_cnt = PRIORITY_OFF;
2190 u32 priority_b_cnt = PRIORITY_OFF;
2191 u32 tmp, arb_control3;
2194 if (radeon_crtc->base.enabled && num_heads && mode) {
2195 pixel_period = 1000000 / (u32)mode->clock;
2196 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
2200 if (rdev->family == CHIP_ARUBA)
2201 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2203 dram_channels = si_get_number_of_dram_channels(rdev);
2205 /* watermark for high clocks */
2206 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2208 radeon_dpm_get_mclk(rdev, false) * 10;
2210 radeon_dpm_get_sclk(rdev, false) * 10;
2212 wm_high.yclk = rdev->pm.current_mclk * 10;
2213 wm_high.sclk = rdev->pm.current_sclk * 10;
2216 wm_high.disp_clk = mode->clock;
2217 wm_high.src_width = mode->crtc_hdisplay;
2218 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
2219 wm_high.blank_time = line_time - wm_high.active_time;
2220 wm_high.interlaced = false;
2221 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2222 wm_high.interlaced = true;
2223 wm_high.vsc = radeon_crtc->vsc;
2225 if (radeon_crtc->rmx_type != RMX_OFF)
2227 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2228 wm_high.lb_size = lb_size;
2229 wm_high.dram_channels = dram_channels;
2230 wm_high.num_heads = num_heads;
2232 /* watermark for low clocks */
2233 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2235 radeon_dpm_get_mclk(rdev, true) * 10;
2237 radeon_dpm_get_sclk(rdev, true) * 10;
2239 wm_low.yclk = rdev->pm.current_mclk * 10;
2240 wm_low.sclk = rdev->pm.current_sclk * 10;
2243 wm_low.disp_clk = mode->clock;
2244 wm_low.src_width = mode->crtc_hdisplay;
2245 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
2246 wm_low.blank_time = line_time - wm_low.active_time;
2247 wm_low.interlaced = false;
2248 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2249 wm_low.interlaced = true;
2250 wm_low.vsc = radeon_crtc->vsc;
2252 if (radeon_crtc->rmx_type != RMX_OFF)
2254 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2255 wm_low.lb_size = lb_size;
2256 wm_low.dram_channels = dram_channels;
2257 wm_low.num_heads = num_heads;
2259 /* set for high clocks */
2260 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
2261 /* set for low clocks */
2262 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
2264 /* possibly force display priority to high */
2265 /* should really do this at mode validation time... */
2266 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2267 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2268 !dce6_check_latency_hiding(&wm_high) ||
2269 (rdev->disp_priority == 2)) {
2270 DRM_DEBUG_KMS("force priority to high\n");
2271 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2272 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2274 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2275 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2276 !dce6_check_latency_hiding(&wm_low) ||
2277 (rdev->disp_priority == 2)) {
2278 DRM_DEBUG_KMS("force priority to high\n");
2279 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2280 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2283 a.full = dfixed_const(1000);
2284 b.full = dfixed_const(mode->clock);
2285 b.full = dfixed_div(b, a);
2286 c.full = dfixed_const(latency_watermark_a);
2287 c.full = dfixed_mul(c, b);
2288 c.full = dfixed_mul(c, radeon_crtc->hsc);
2289 c.full = dfixed_div(c, a);
2290 a.full = dfixed_const(16);
2291 c.full = dfixed_div(c, a);
2292 priority_a_mark = dfixed_trunc(c);
2293 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2295 a.full = dfixed_const(1000);
2296 b.full = dfixed_const(mode->clock);
2297 b.full = dfixed_div(b, a);
2298 c.full = dfixed_const(latency_watermark_b);
2299 c.full = dfixed_mul(c, b);
2300 c.full = dfixed_mul(c, radeon_crtc->hsc);
2301 c.full = dfixed_div(c, a);
2302 a.full = dfixed_const(16);
2303 c.full = dfixed_div(c, a);
2304 priority_b_mark = dfixed_trunc(c);
2305 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2307 /* Save number of lines the linebuffer leads before the scanout */
2308 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2312 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2314 tmp &= ~LATENCY_WATERMARK_MASK(3);
2315 tmp |= LATENCY_WATERMARK_MASK(1);
2316 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2317 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2318 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2319 LATENCY_HIGH_WATERMARK(line_time)));
2321 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2322 tmp &= ~LATENCY_WATERMARK_MASK(3);
2323 tmp |= LATENCY_WATERMARK_MASK(2);
2324 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2325 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2326 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2327 LATENCY_HIGH_WATERMARK(line_time)));
2328 /* restore original selection */
2329 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2331 /* write the priority marks */
2332 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2333 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2335 /* save values for DPM */
2336 radeon_crtc->line_time = line_time;
2337 radeon_crtc->wm_high = latency_watermark_a;
2338 radeon_crtc->wm_low = latency_watermark_b;
2341 void dce6_bandwidth_update(struct radeon_device *rdev)
2343 struct drm_display_mode *mode0 = NULL;
2344 struct drm_display_mode *mode1 = NULL;
2345 u32 num_heads = 0, lb_size;
2348 if (!rdev->mode_info.mode_config_initialized)
2351 radeon_update_display_priority(rdev);
2353 for (i = 0; i < rdev->num_crtc; i++) {
2354 if (rdev->mode_info.crtcs[i]->base.enabled)
2357 for (i = 0; i < rdev->num_crtc; i += 2) {
2358 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2359 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2360 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2361 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2362 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2363 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2370 static void si_tiling_mode_table_init(struct radeon_device *rdev)
2372 const u32 num_tile_mode_states = 32;
2373 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
2375 switch (rdev->config.si.mem_row_size_in_kb) {
2377 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2381 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2384 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2388 if ((rdev->family == CHIP_TAHITI) ||
2389 (rdev->family == CHIP_PITCAIRN)) {
2390 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2391 switch (reg_offset) {
2392 case 0: /* non-AA compressed depth or any compressed stencil */
2393 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2394 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2395 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2397 NUM_BANKS(ADDR_SURF_16_BANK) |
2398 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2399 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2400 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2402 case 1: /* 2xAA/4xAA compressed depth only */
2403 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2404 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2405 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2406 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2407 NUM_BANKS(ADDR_SURF_16_BANK) |
2408 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2410 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2412 case 2: /* 8xAA compressed depth only */
2413 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2414 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2415 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2417 NUM_BANKS(ADDR_SURF_16_BANK) |
2418 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2419 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2420 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2422 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2423 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2424 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2425 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2426 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2427 NUM_BANKS(ADDR_SURF_16_BANK) |
2428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2432 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2433 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2434 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2435 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2437 NUM_BANKS(ADDR_SURF_16_BANK) |
2438 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2439 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2440 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2442 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2443 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2444 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2445 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2446 TILE_SPLIT(split_equal_to_row_size) |
2447 NUM_BANKS(ADDR_SURF_16_BANK) |
2448 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2449 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2450 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2452 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2453 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2454 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2455 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2456 TILE_SPLIT(split_equal_to_row_size) |
2457 NUM_BANKS(ADDR_SURF_16_BANK) |
2458 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2460 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2462 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2463 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2464 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2465 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2466 TILE_SPLIT(split_equal_to_row_size) |
2467 NUM_BANKS(ADDR_SURF_16_BANK) |
2468 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2470 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2472 case 8: /* 1D and 1D Array Surfaces */
2473 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2474 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2475 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2476 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2477 NUM_BANKS(ADDR_SURF_16_BANK) |
2478 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2480 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2482 case 9: /* Displayable maps. */
2483 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2484 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2485 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2487 NUM_BANKS(ADDR_SURF_16_BANK) |
2488 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2492 case 10: /* Display 8bpp. */
2493 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2494 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2495 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2496 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2497 NUM_BANKS(ADDR_SURF_16_BANK) |
2498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2502 case 11: /* Display 16bpp. */
2503 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2504 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2505 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2506 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2507 NUM_BANKS(ADDR_SURF_16_BANK) |
2508 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2512 case 12: /* Display 32bpp. */
2513 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2514 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2515 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2517 NUM_BANKS(ADDR_SURF_16_BANK) |
2518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2522 case 13: /* Thin. */
2523 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2524 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2525 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2527 NUM_BANKS(ADDR_SURF_16_BANK) |
2528 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2529 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2530 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2532 case 14: /* Thin 8 bpp. */
2533 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2534 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2535 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2536 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2537 NUM_BANKS(ADDR_SURF_16_BANK) |
2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2542 case 15: /* Thin 16 bpp. */
2543 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2544 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2545 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2546 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2547 NUM_BANKS(ADDR_SURF_16_BANK) |
2548 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2552 case 16: /* Thin 32 bpp. */
2553 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2554 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2555 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2556 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2557 NUM_BANKS(ADDR_SURF_16_BANK) |
2558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2562 case 17: /* Thin 64 bpp. */
2563 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2564 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2565 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2566 TILE_SPLIT(split_equal_to_row_size) |
2567 NUM_BANKS(ADDR_SURF_16_BANK) |
2568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2569 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2572 case 21: /* 8 bpp PRT. */
2573 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2574 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2575 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2577 NUM_BANKS(ADDR_SURF_16_BANK) |
2578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2582 case 22: /* 16 bpp PRT */
2583 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2584 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2585 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2586 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2587 NUM_BANKS(ADDR_SURF_16_BANK) |
2588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2592 case 23: /* 32 bpp PRT */
2593 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2594 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2595 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2596 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2597 NUM_BANKS(ADDR_SURF_16_BANK) |
2598 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2599 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2600 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2602 case 24: /* 64 bpp PRT */
2603 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2604 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2605 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2606 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2607 NUM_BANKS(ADDR_SURF_16_BANK) |
2608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2612 case 25: /* 128 bpp PRT */
2613 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2614 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2615 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2617 NUM_BANKS(ADDR_SURF_8_BANK) |
2618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2626 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
2627 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2629 } else if ((rdev->family == CHIP_VERDE) ||
2630 (rdev->family == CHIP_OLAND) ||
2631 (rdev->family == CHIP_HAINAN)) {
2632 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2633 switch (reg_offset) {
2634 case 0: /* non-AA compressed depth or any compressed stencil */
2635 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2636 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2637 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2638 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2639 NUM_BANKS(ADDR_SURF_16_BANK) |
2640 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2641 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2642 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2644 case 1: /* 2xAA/4xAA compressed depth only */
2645 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2646 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2647 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2648 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2649 NUM_BANKS(ADDR_SURF_16_BANK) |
2650 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2654 case 2: /* 8xAA compressed depth only */
2655 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2656 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2657 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2658 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2659 NUM_BANKS(ADDR_SURF_16_BANK) |
2660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2664 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2665 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2666 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2667 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2669 NUM_BANKS(ADDR_SURF_16_BANK) |
2670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2674 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2675 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2676 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2677 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2678 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2679 NUM_BANKS(ADDR_SURF_16_BANK) |
2680 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2681 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2682 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2684 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2685 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2686 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2687 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2688 TILE_SPLIT(split_equal_to_row_size) |
2689 NUM_BANKS(ADDR_SURF_16_BANK) |
2690 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2694 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2695 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2696 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2697 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2698 TILE_SPLIT(split_equal_to_row_size) |
2699 NUM_BANKS(ADDR_SURF_16_BANK) |
2700 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2704 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2705 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2706 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2707 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2708 TILE_SPLIT(split_equal_to_row_size) |
2709 NUM_BANKS(ADDR_SURF_16_BANK) |
2710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2714 case 8: /* 1D and 1D Array Surfaces */
2715 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2716 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2717 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2719 NUM_BANKS(ADDR_SURF_16_BANK) |
2720 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2724 case 9: /* Displayable maps. */
2725 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2726 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2727 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2728 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2729 NUM_BANKS(ADDR_SURF_16_BANK) |
2730 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2734 case 10: /* Display 8bpp. */
2735 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2736 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2737 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2738 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2739 NUM_BANKS(ADDR_SURF_16_BANK) |
2740 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2741 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2742 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2744 case 11: /* Display 16bpp. */
2745 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2746 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2747 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2749 NUM_BANKS(ADDR_SURF_16_BANK) |
2750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2754 case 12: /* Display 32bpp. */
2755 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2756 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2757 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2758 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2759 NUM_BANKS(ADDR_SURF_16_BANK) |
2760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2764 case 13: /* Thin. */
2765 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2766 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2767 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2768 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2769 NUM_BANKS(ADDR_SURF_16_BANK) |
2770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2774 case 14: /* Thin 8 bpp. */
2775 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2776 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2777 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2778 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2779 NUM_BANKS(ADDR_SURF_16_BANK) |
2780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2784 case 15: /* Thin 16 bpp. */
2785 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2786 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2787 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2789 NUM_BANKS(ADDR_SURF_16_BANK) |
2790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2794 case 16: /* Thin 32 bpp. */
2795 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2796 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2797 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2798 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2799 NUM_BANKS(ADDR_SURF_16_BANK) |
2800 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2801 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2802 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2804 case 17: /* Thin 64 bpp. */
2805 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2806 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2807 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2808 TILE_SPLIT(split_equal_to_row_size) |
2809 NUM_BANKS(ADDR_SURF_16_BANK) |
2810 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2811 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2812 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2814 case 21: /* 8 bpp PRT. */
2815 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2816 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2817 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2818 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2819 NUM_BANKS(ADDR_SURF_16_BANK) |
2820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2824 case 22: /* 16 bpp PRT */
2825 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2826 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2827 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2828 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2829 NUM_BANKS(ADDR_SURF_16_BANK) |
2830 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2831 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2832 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2834 case 23: /* 32 bpp PRT */
2835 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2836 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2837 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2839 NUM_BANKS(ADDR_SURF_16_BANK) |
2840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2844 case 24: /* 64 bpp PRT */
2845 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2846 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2847 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2848 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2849 NUM_BANKS(ADDR_SURF_16_BANK) |
2850 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2851 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2852 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2854 case 25: /* 128 bpp PRT */
2855 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2856 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2857 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2858 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2859 NUM_BANKS(ADDR_SURF_8_BANK) |
2860 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2861 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2862 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2868 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
2869 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2872 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2875 static void si_select_se_sh(struct radeon_device *rdev,
2876 u32 se_num, u32 sh_num)
2878 u32 data = INSTANCE_BROADCAST_WRITES;
2880 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2881 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2882 else if (se_num == 0xffffffff)
2883 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2884 else if (sh_num == 0xffffffff)
2885 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2887 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2888 WREG32(GRBM_GFX_INDEX, data);
2891 static u32 si_create_bitmask(u32 bit_width)
2895 for (i = 0; i < bit_width; i++) {
2902 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2906 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2908 data &= INACTIVE_CUS_MASK;
2911 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2913 data >>= INACTIVE_CUS_SHIFT;
2915 mask = si_create_bitmask(cu_per_sh);
2917 return ~data & mask;
2920 static void si_setup_spi(struct radeon_device *rdev,
2921 u32 se_num, u32 sh_per_se,
2925 u32 data, mask, active_cu;
2927 for (i = 0; i < se_num; i++) {
2928 for (j = 0; j < sh_per_se; j++) {
2929 si_select_se_sh(rdev, i, j);
2930 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
2931 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
2934 for (k = 0; k < 16; k++) {
2936 if (active_cu & mask) {
2938 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
2944 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2947 static u32 si_get_rb_disabled(struct radeon_device *rdev,
2948 u32 max_rb_num_per_se,
2953 data = RREG32(CC_RB_BACKEND_DISABLE);
2955 data &= BACKEND_DISABLE_MASK;
2958 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
2960 data >>= BACKEND_DISABLE_SHIFT;
2962 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
2967 static void si_setup_rb(struct radeon_device *rdev,
2968 u32 se_num, u32 sh_per_se,
2969 u32 max_rb_num_per_se)
2973 u32 disabled_rbs = 0;
2974 u32 enabled_rbs = 0;
2976 for (i = 0; i < se_num; i++) {
2977 for (j = 0; j < sh_per_se; j++) {
2978 si_select_se_sh(rdev, i, j);
2979 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
2980 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
2983 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2986 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2987 if (!(disabled_rbs & mask))
2988 enabled_rbs |= mask;
2992 rdev->config.si.backend_enable_mask = enabled_rbs;
2994 for (i = 0; i < se_num; i++) {
2995 si_select_se_sh(rdev, i, 0xffffffff);
2997 for (j = 0; j < sh_per_se; j++) {
2998 switch (enabled_rbs & 3) {
3000 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3003 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3007 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3012 WREG32(PA_SC_RASTER_CONFIG, data);
3014 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3017 static void si_gpu_init(struct radeon_device *rdev)
3019 u32 gb_addr_config = 0;
3020 u32 mc_shared_chmap, mc_arb_ramcfg;
3022 u32 hdp_host_path_cntl;
3026 switch (rdev->family) {
3028 rdev->config.si.max_shader_engines = 2;
3029 rdev->config.si.max_tile_pipes = 12;
3030 rdev->config.si.max_cu_per_sh = 8;
3031 rdev->config.si.max_sh_per_se = 2;
3032 rdev->config.si.max_backends_per_se = 4;
3033 rdev->config.si.max_texture_channel_caches = 12;
3034 rdev->config.si.max_gprs = 256;
3035 rdev->config.si.max_gs_threads = 32;
3036 rdev->config.si.max_hw_contexts = 8;
3038 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3039 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3040 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3041 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3042 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3045 rdev->config.si.max_shader_engines = 2;
3046 rdev->config.si.max_tile_pipes = 8;
3047 rdev->config.si.max_cu_per_sh = 5;
3048 rdev->config.si.max_sh_per_se = 2;
3049 rdev->config.si.max_backends_per_se = 4;
3050 rdev->config.si.max_texture_channel_caches = 8;
3051 rdev->config.si.max_gprs = 256;
3052 rdev->config.si.max_gs_threads = 32;
3053 rdev->config.si.max_hw_contexts = 8;
3055 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3056 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3057 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3058 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3059 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3063 rdev->config.si.max_shader_engines = 1;
3064 rdev->config.si.max_tile_pipes = 4;
3065 rdev->config.si.max_cu_per_sh = 5;
3066 rdev->config.si.max_sh_per_se = 2;
3067 rdev->config.si.max_backends_per_se = 4;
3068 rdev->config.si.max_texture_channel_caches = 4;
3069 rdev->config.si.max_gprs = 256;
3070 rdev->config.si.max_gs_threads = 32;
3071 rdev->config.si.max_hw_contexts = 8;
3073 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3074 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3075 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3076 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3077 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3080 rdev->config.si.max_shader_engines = 1;
3081 rdev->config.si.max_tile_pipes = 4;
3082 rdev->config.si.max_cu_per_sh = 6;
3083 rdev->config.si.max_sh_per_se = 1;
3084 rdev->config.si.max_backends_per_se = 2;
3085 rdev->config.si.max_texture_channel_caches = 4;
3086 rdev->config.si.max_gprs = 256;
3087 rdev->config.si.max_gs_threads = 16;
3088 rdev->config.si.max_hw_contexts = 8;
3090 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3091 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3092 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3093 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3094 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3097 rdev->config.si.max_shader_engines = 1;
3098 rdev->config.si.max_tile_pipes = 4;
3099 rdev->config.si.max_cu_per_sh = 5;
3100 rdev->config.si.max_sh_per_se = 1;
3101 rdev->config.si.max_backends_per_se = 1;
3102 rdev->config.si.max_texture_channel_caches = 2;
3103 rdev->config.si.max_gprs = 256;
3104 rdev->config.si.max_gs_threads = 16;
3105 rdev->config.si.max_hw_contexts = 8;
3107 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3108 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3109 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3110 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3111 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3115 /* Initialize HDP */
3116 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3117 WREG32((0x2c14 + j), 0x00000000);
3118 WREG32((0x2c18 + j), 0x00000000);
3119 WREG32((0x2c1c + j), 0x00000000);
3120 WREG32((0x2c20 + j), 0x00000000);
3121 WREG32((0x2c24 + j), 0x00000000);
3124 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3125 WREG32(SRBM_INT_CNTL, 1);
3126 WREG32(SRBM_INT_ACK, 1);
3128 evergreen_fix_pci_max_read_req_size(rdev);
3130 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3132 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3133 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3135 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3136 rdev->config.si.mem_max_burst_length_bytes = 256;
3137 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3138 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3139 if (rdev->config.si.mem_row_size_in_kb > 4)
3140 rdev->config.si.mem_row_size_in_kb = 4;
3141 /* XXX use MC settings? */
3142 rdev->config.si.shader_engine_tile_size = 32;
3143 rdev->config.si.num_gpus = 1;
3144 rdev->config.si.multi_gpu_tile_size = 64;
3146 /* fix up row size */
3147 gb_addr_config &= ~ROW_SIZE_MASK;
3148 switch (rdev->config.si.mem_row_size_in_kb) {
3151 gb_addr_config |= ROW_SIZE(0);
3154 gb_addr_config |= ROW_SIZE(1);
3157 gb_addr_config |= ROW_SIZE(2);
3161 /* setup tiling info dword. gb_addr_config is not adequate since it does
3162 * not have bank info, so create a custom tiling dword.
3163 * bits 3:0 num_pipes
3164 * bits 7:4 num_banks
3165 * bits 11:8 group_size
3166 * bits 15:12 row_size
3168 rdev->config.si.tile_config = 0;
3169 switch (rdev->config.si.num_tile_pipes) {
3171 rdev->config.si.tile_config |= (0 << 0);
3174 rdev->config.si.tile_config |= (1 << 0);
3177 rdev->config.si.tile_config |= (2 << 0);
3181 /* XXX what about 12? */
3182 rdev->config.si.tile_config |= (3 << 0);
3185 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3186 case 0: /* four banks */
3187 rdev->config.si.tile_config |= 0 << 4;
3189 case 1: /* eight banks */
3190 rdev->config.si.tile_config |= 1 << 4;
3192 case 2: /* sixteen banks */
3194 rdev->config.si.tile_config |= 2 << 4;
3197 rdev->config.si.tile_config |=
3198 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3199 rdev->config.si.tile_config |=
3200 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3202 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3203 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3204 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3205 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3206 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3207 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3208 if (rdev->has_uvd) {
3209 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3210 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3211 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3214 si_tiling_mode_table_init(rdev);
3216 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3217 rdev->config.si.max_sh_per_se,
3218 rdev->config.si.max_backends_per_se);
3220 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3221 rdev->config.si.max_sh_per_se,
3222 rdev->config.si.max_cu_per_sh);
3224 rdev->config.si.active_cus = 0;
3225 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3226 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3227 rdev->config.si.active_cus +=
3228 hweight32(si_get_cu_active_bitmap(rdev, i, j));
3232 /* set HW defaults for 3D engine */
3233 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3234 ROQ_IB2_START(0x2b)));
3235 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3237 sx_debug_1 = RREG32(SX_DEBUG_1);
3238 WREG32(SX_DEBUG_1, sx_debug_1);
3240 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3242 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3243 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3244 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3245 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3247 WREG32(VGT_NUM_INSTANCES, 1);
3249 WREG32(CP_PERFMON_CNTL, 0);
3251 WREG32(SQ_CONFIG, 0);
3253 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3254 FORCE_EOV_MAX_REZ_CNT(255)));
3256 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3257 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3259 WREG32(VGT_GS_VERTEX_REUSE, 16);
3260 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3262 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3263 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3264 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3265 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3266 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3267 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3268 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3269 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3271 tmp = RREG32(HDP_MISC_CNTL);
3272 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3273 WREG32(HDP_MISC_CNTL, tmp);
3275 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3276 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3278 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3284 * GPU scratch registers helpers function.
3286 static void si_scratch_init(struct radeon_device *rdev)
3290 rdev->scratch.num_reg = 7;
3291 rdev->scratch.reg_base = SCRATCH_REG0;
3292 for (i = 0; i < rdev->scratch.num_reg; i++) {
3293 rdev->scratch.free[i] = true;
3294 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3298 void si_fence_ring_emit(struct radeon_device *rdev,
3299 struct radeon_fence *fence)
3301 struct radeon_ring *ring = &rdev->ring[fence->ring];
3302 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3304 /* flush read cache over gart */
3305 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3306 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3307 radeon_ring_write(ring, 0);
3308 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3309 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3310 PACKET3_TC_ACTION_ENA |
3311 PACKET3_SH_KCACHE_ACTION_ENA |
3312 PACKET3_SH_ICACHE_ACTION_ENA);
3313 radeon_ring_write(ring, 0xFFFFFFFF);
3314 radeon_ring_write(ring, 0);
3315 radeon_ring_write(ring, 10); /* poll interval */
3316 /* EVENT_WRITE_EOP - flush caches, send int */
3317 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3318 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3319 radeon_ring_write(ring, lower_32_bits(addr));
3320 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3321 radeon_ring_write(ring, fence->seq);
3322 radeon_ring_write(ring, 0);
3328 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3330 struct radeon_ring *ring = &rdev->ring[ib->ring];
3331 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3334 if (ib->is_const_ib) {
3335 /* set switch buffer packet before const IB */
3336 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3337 radeon_ring_write(ring, 0);
3339 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3342 if (ring->rptr_save_reg) {
3343 next_rptr = ring->wptr + 3 + 4 + 8;
3344 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3345 radeon_ring_write(ring, ((ring->rptr_save_reg -
3346 PACKET3_SET_CONFIG_REG_START) >> 2));
3347 radeon_ring_write(ring, next_rptr);
3348 } else if (rdev->wb.enabled) {
3349 next_rptr = ring->wptr + 5 + 4 + 8;
3350 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3351 radeon_ring_write(ring, (1 << 8));
3352 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3353 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3354 radeon_ring_write(ring, next_rptr);
3357 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3360 radeon_ring_write(ring, header);
3361 radeon_ring_write(ring,
3365 (ib->gpu_addr & 0xFFFFFFFC));
3366 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3367 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3369 if (!ib->is_const_ib) {
3370 /* flush read cache over gart for this vmid */
3371 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3372 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3373 radeon_ring_write(ring, vm_id);
3374 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3375 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3376 PACKET3_TC_ACTION_ENA |
3377 PACKET3_SH_KCACHE_ACTION_ENA |
3378 PACKET3_SH_ICACHE_ACTION_ENA);
3379 radeon_ring_write(ring, 0xFFFFFFFF);
3380 radeon_ring_write(ring, 0);
3381 radeon_ring_write(ring, 10); /* poll interval */
3388 static void si_cp_enable(struct radeon_device *rdev, bool enable)
3391 WREG32(CP_ME_CNTL, 0);
3393 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3394 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3395 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3396 WREG32(SCRATCH_UMSK, 0);
3397 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3398 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3399 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3404 static int si_cp_load_microcode(struct radeon_device *rdev)
3408 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3411 si_cp_enable(rdev, false);
3414 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3415 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3416 const struct gfx_firmware_header_v1_0 *ce_hdr =
3417 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3418 const struct gfx_firmware_header_v1_0 *me_hdr =
3419 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3420 const __le32 *fw_data;
3423 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3424 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3425 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3428 fw_data = (const __le32 *)
3429 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3430 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3431 WREG32(CP_PFP_UCODE_ADDR, 0);
3432 for (i = 0; i < fw_size; i++)
3433 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3434 WREG32(CP_PFP_UCODE_ADDR, 0);
3437 fw_data = (const __le32 *)
3438 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3439 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3440 WREG32(CP_CE_UCODE_ADDR, 0);
3441 for (i = 0; i < fw_size; i++)
3442 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3443 WREG32(CP_CE_UCODE_ADDR, 0);
3446 fw_data = (const __be32 *)
3447 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3448 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3449 WREG32(CP_ME_RAM_WADDR, 0);
3450 for (i = 0; i < fw_size; i++)
3451 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3452 WREG32(CP_ME_RAM_WADDR, 0);
3454 const __be32 *fw_data;
3457 fw_data = (const __be32 *)rdev->pfp_fw->data;
3458 WREG32(CP_PFP_UCODE_ADDR, 0);
3459 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
3460 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3461 WREG32(CP_PFP_UCODE_ADDR, 0);
3464 fw_data = (const __be32 *)rdev->ce_fw->data;
3465 WREG32(CP_CE_UCODE_ADDR, 0);
3466 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
3467 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3468 WREG32(CP_CE_UCODE_ADDR, 0);
3471 fw_data = (const __be32 *)rdev->me_fw->data;
3472 WREG32(CP_ME_RAM_WADDR, 0);
3473 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
3474 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3475 WREG32(CP_ME_RAM_WADDR, 0);
3478 WREG32(CP_PFP_UCODE_ADDR, 0);
3479 WREG32(CP_CE_UCODE_ADDR, 0);
3480 WREG32(CP_ME_RAM_WADDR, 0);
3481 WREG32(CP_ME_RAM_RADDR, 0);
3485 static int si_cp_start(struct radeon_device *rdev)
3487 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3490 r = radeon_ring_lock(rdev, ring, 7 + 4);
3492 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3496 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3497 radeon_ring_write(ring, 0x1);
3498 radeon_ring_write(ring, 0x0);
3499 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3500 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3501 radeon_ring_write(ring, 0);
3502 radeon_ring_write(ring, 0);
3504 /* init the CE partitions */
3505 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3506 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3507 radeon_ring_write(ring, 0xc000);
3508 radeon_ring_write(ring, 0xe000);
3509 radeon_ring_unlock_commit(rdev, ring, false);
3511 si_cp_enable(rdev, true);
3513 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3515 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3519 /* setup clear context state */
3520 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3521 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3523 for (i = 0; i < si_default_size; i++)
3524 radeon_ring_write(ring, si_default_state[i]);
3526 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3527 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3529 /* set clear context state */
3530 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3531 radeon_ring_write(ring, 0);
3533 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3534 radeon_ring_write(ring, 0x00000316);
3535 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3536 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3538 radeon_ring_unlock_commit(rdev, ring, false);
3540 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3541 ring = &rdev->ring[i];
3542 r = radeon_ring_lock(rdev, ring, 2);
3544 /* clear the compute context state */
3545 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3546 radeon_ring_write(ring, 0);
3548 radeon_ring_unlock_commit(rdev, ring, false);
3554 static void si_cp_fini(struct radeon_device *rdev)
3556 struct radeon_ring *ring;
3557 si_cp_enable(rdev, false);
3559 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3560 radeon_ring_fini(rdev, ring);
3561 radeon_scratch_free(rdev, ring->rptr_save_reg);
3563 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3564 radeon_ring_fini(rdev, ring);
3565 radeon_scratch_free(rdev, ring->rptr_save_reg);
3567 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3568 radeon_ring_fini(rdev, ring);
3569 radeon_scratch_free(rdev, ring->rptr_save_reg);
3572 static int si_cp_resume(struct radeon_device *rdev)
3574 struct radeon_ring *ring;
3579 si_enable_gui_idle_interrupt(rdev, false);
3581 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3582 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3584 /* Set the write pointer delay */
3585 WREG32(CP_RB_WPTR_DELAY, 0);
3587 WREG32(CP_DEBUG, 0);
3588 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3590 /* ring 0 - compute and gfx */
3591 /* Set ring buffer size */
3592 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3593 rb_bufsz = order_base_2(ring->ring_size / 8);
3594 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3596 tmp |= BUF_SWAP_32BIT;
3598 WREG32(CP_RB0_CNTL, tmp);
3600 /* Initialize the ring buffer's read and write pointers */
3601 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3603 WREG32(CP_RB0_WPTR, ring->wptr);
3605 /* set the wb address whether it's enabled or not */
3606 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
3607 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3609 if (rdev->wb.enabled)
3610 WREG32(SCRATCH_UMSK, 0xff);
3612 tmp |= RB_NO_UPDATE;
3613 WREG32(SCRATCH_UMSK, 0);
3617 WREG32(CP_RB0_CNTL, tmp);
3619 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3621 /* ring1 - compute only */
3622 /* Set ring buffer size */
3623 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3624 rb_bufsz = order_base_2(ring->ring_size / 8);
3625 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3627 tmp |= BUF_SWAP_32BIT;
3629 WREG32(CP_RB1_CNTL, tmp);
3631 /* Initialize the ring buffer's read and write pointers */
3632 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3634 WREG32(CP_RB1_WPTR, ring->wptr);
3636 /* set the wb address whether it's enabled or not */
3637 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3638 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3641 WREG32(CP_RB1_CNTL, tmp);
3643 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3645 /* ring2 - compute only */
3646 /* Set ring buffer size */
3647 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3648 rb_bufsz = order_base_2(ring->ring_size / 8);
3649 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3651 tmp |= BUF_SWAP_32BIT;
3653 WREG32(CP_RB2_CNTL, tmp);
3655 /* Initialize the ring buffer's read and write pointers */
3656 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3658 WREG32(CP_RB2_WPTR, ring->wptr);
3660 /* set the wb address whether it's enabled or not */
3661 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3662 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3665 WREG32(CP_RB2_CNTL, tmp);
3667 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3669 /* start the rings */
3671 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3672 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3673 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3674 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3676 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3677 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3678 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3681 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3683 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3685 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3687 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3690 si_enable_gui_idle_interrupt(rdev, true);
3692 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3693 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3698 u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
3704 tmp = RREG32(GRBM_STATUS);
3705 if (tmp & (PA_BUSY | SC_BUSY |
3706 BCI_BUSY | SX_BUSY |
3707 TA_BUSY | VGT_BUSY |
3709 GDS_BUSY | SPI_BUSY |
3710 IA_BUSY | IA_BUSY_NO_DMA))
3711 reset_mask |= RADEON_RESET_GFX;
3713 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3714 CP_BUSY | CP_COHERENCY_BUSY))
3715 reset_mask |= RADEON_RESET_CP;
3717 if (tmp & GRBM_EE_BUSY)
3718 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3721 tmp = RREG32(GRBM_STATUS2);
3722 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3723 reset_mask |= RADEON_RESET_RLC;
3725 /* DMA_STATUS_REG 0 */
3726 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3727 if (!(tmp & DMA_IDLE))
3728 reset_mask |= RADEON_RESET_DMA;
3730 /* DMA_STATUS_REG 1 */
3731 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3732 if (!(tmp & DMA_IDLE))
3733 reset_mask |= RADEON_RESET_DMA1;
3736 tmp = RREG32(SRBM_STATUS2);
3738 reset_mask |= RADEON_RESET_DMA;
3740 if (tmp & DMA1_BUSY)
3741 reset_mask |= RADEON_RESET_DMA1;
3744 tmp = RREG32(SRBM_STATUS);
3747 reset_mask |= RADEON_RESET_IH;
3750 reset_mask |= RADEON_RESET_SEM;
3752 if (tmp & GRBM_RQ_PENDING)
3753 reset_mask |= RADEON_RESET_GRBM;
3756 reset_mask |= RADEON_RESET_VMC;
3758 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3759 MCC_BUSY | MCD_BUSY))
3760 reset_mask |= RADEON_RESET_MC;
3762 if (evergreen_is_display_hung(rdev))
3763 reset_mask |= RADEON_RESET_DISPLAY;
3766 tmp = RREG32(VM_L2_STATUS);
3768 reset_mask |= RADEON_RESET_VMC;
3770 /* Skip MC reset as it's mostly likely not hung, just busy */
3771 if (reset_mask & RADEON_RESET_MC) {
3772 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3773 reset_mask &= ~RADEON_RESET_MC;
3779 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3781 struct evergreen_mc_save save;
3782 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3785 if (reset_mask == 0)
3788 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3790 evergreen_print_gpu_status_regs(rdev);
3791 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3792 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3793 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3794 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3803 /* Disable CP parsing/prefetching */
3804 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3806 if (reset_mask & RADEON_RESET_DMA) {
3808 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3809 tmp &= ~DMA_RB_ENABLE;
3810 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3812 if (reset_mask & RADEON_RESET_DMA1) {
3814 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3815 tmp &= ~DMA_RB_ENABLE;
3816 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3821 evergreen_mc_stop(rdev, &save);
3822 if (evergreen_mc_wait_for_idle(rdev)) {
3823 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3826 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
3827 grbm_soft_reset = SOFT_RESET_CB |
3841 if (reset_mask & RADEON_RESET_CP) {
3842 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3844 srbm_soft_reset |= SOFT_RESET_GRBM;
3847 if (reset_mask & RADEON_RESET_DMA)
3848 srbm_soft_reset |= SOFT_RESET_DMA;
3850 if (reset_mask & RADEON_RESET_DMA1)
3851 srbm_soft_reset |= SOFT_RESET_DMA1;
3853 if (reset_mask & RADEON_RESET_DISPLAY)
3854 srbm_soft_reset |= SOFT_RESET_DC;
3856 if (reset_mask & RADEON_RESET_RLC)
3857 grbm_soft_reset |= SOFT_RESET_RLC;
3859 if (reset_mask & RADEON_RESET_SEM)
3860 srbm_soft_reset |= SOFT_RESET_SEM;
3862 if (reset_mask & RADEON_RESET_IH)
3863 srbm_soft_reset |= SOFT_RESET_IH;
3865 if (reset_mask & RADEON_RESET_GRBM)
3866 srbm_soft_reset |= SOFT_RESET_GRBM;
3868 if (reset_mask & RADEON_RESET_VMC)
3869 srbm_soft_reset |= SOFT_RESET_VMC;
3871 if (reset_mask & RADEON_RESET_MC)
3872 srbm_soft_reset |= SOFT_RESET_MC;
3874 if (grbm_soft_reset) {
3875 tmp = RREG32(GRBM_SOFT_RESET);
3876 tmp |= grbm_soft_reset;
3877 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3878 WREG32(GRBM_SOFT_RESET, tmp);
3879 tmp = RREG32(GRBM_SOFT_RESET);
3883 tmp &= ~grbm_soft_reset;
3884 WREG32(GRBM_SOFT_RESET, tmp);
3885 tmp = RREG32(GRBM_SOFT_RESET);
3888 if (srbm_soft_reset) {
3889 tmp = RREG32(SRBM_SOFT_RESET);
3890 tmp |= srbm_soft_reset;
3891 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3892 WREG32(SRBM_SOFT_RESET, tmp);
3893 tmp = RREG32(SRBM_SOFT_RESET);
3897 tmp &= ~srbm_soft_reset;
3898 WREG32(SRBM_SOFT_RESET, tmp);
3899 tmp = RREG32(SRBM_SOFT_RESET);
3902 /* Wait a little for things to settle down */
3905 evergreen_mc_resume(rdev, &save);
3908 evergreen_print_gpu_status_regs(rdev);
3911 static void si_set_clk_bypass_mode(struct radeon_device *rdev)
3915 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3916 tmp |= SPLL_BYPASS_EN;
3917 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3919 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3920 tmp |= SPLL_CTLREQ_CHG;
3921 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3923 for (i = 0; i < rdev->usec_timeout; i++) {
3924 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
3929 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3930 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
3931 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3933 tmp = RREG32(MPLL_CNTL_MODE);
3934 tmp &= ~MPLL_MCLK_SEL;
3935 WREG32(MPLL_CNTL_MODE, tmp);
3938 static void si_spll_powerdown(struct radeon_device *rdev)
3942 tmp = RREG32(SPLL_CNTL_MODE);
3943 tmp |= SPLL_SW_DIR_CONTROL;
3944 WREG32(SPLL_CNTL_MODE, tmp);
3946 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3948 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3950 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3952 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3954 tmp = RREG32(SPLL_CNTL_MODE);
3955 tmp &= ~SPLL_SW_DIR_CONTROL;
3956 WREG32(SPLL_CNTL_MODE, tmp);
3959 static void si_gpu_pci_config_reset(struct radeon_device *rdev)
3961 struct evergreen_mc_save save;
3964 dev_info(rdev->dev, "GPU pci config reset\n");
3972 /* Disable CP parsing/prefetching */
3973 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3975 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3976 tmp &= ~DMA_RB_ENABLE;
3977 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3979 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3980 tmp &= ~DMA_RB_ENABLE;
3981 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3982 /* XXX other engines? */
3984 /* halt the rlc, disable cp internal ints */
3989 /* disable mem access */
3990 evergreen_mc_stop(rdev, &save);
3991 if (evergreen_mc_wait_for_idle(rdev)) {
3992 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
3995 /* set mclk/sclk to bypass */
3996 si_set_clk_bypass_mode(rdev);
3997 /* powerdown spll */
3998 si_spll_powerdown(rdev);
4000 pci_clear_master(rdev->pdev);
4002 radeon_pci_config_reset(rdev);
4003 /* wait for asic to come out of reset */
4004 for (i = 0; i < rdev->usec_timeout; i++) {
4005 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
4011 int si_asic_reset(struct radeon_device *rdev)
4015 reset_mask = si_gpu_check_soft_reset(rdev);
4018 r600_set_bios_scratch_engine_hung(rdev, true);
4020 /* try soft reset */
4021 si_gpu_soft_reset(rdev, reset_mask);
4023 reset_mask = si_gpu_check_soft_reset(rdev);
4025 /* try pci config reset */
4026 if (reset_mask && radeon_hard_reset)
4027 si_gpu_pci_config_reset(rdev);
4029 reset_mask = si_gpu_check_soft_reset(rdev);
4032 r600_set_bios_scratch_engine_hung(rdev, false);
4038 * si_gfx_is_lockup - Check if the GFX engine is locked up
4040 * @rdev: radeon_device pointer
4041 * @ring: radeon_ring structure holding ring information
4043 * Check if the GFX engine is locked up.
4044 * Returns true if the engine appears to be locked up, false if not.
4046 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4048 u32 reset_mask = si_gpu_check_soft_reset(rdev);
4050 if (!(reset_mask & (RADEON_RESET_GFX |
4051 RADEON_RESET_COMPUTE |
4052 RADEON_RESET_CP))) {
4053 radeon_ring_lockup_update(rdev, ring);
4056 return radeon_ring_test_lockup(rdev, ring);
4060 static void si_mc_program(struct radeon_device *rdev)
4062 struct evergreen_mc_save save;
4066 /* Initialize HDP */
4067 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
4068 WREG32((0x2c14 + j), 0x00000000);
4069 WREG32((0x2c18 + j), 0x00000000);
4070 WREG32((0x2c1c + j), 0x00000000);
4071 WREG32((0x2c20 + j), 0x00000000);
4072 WREG32((0x2c24 + j), 0x00000000);
4074 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
4076 evergreen_mc_stop(rdev, &save);
4077 if (radeon_mc_wait_for_idle(rdev)) {
4078 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4080 if (!ASIC_IS_NODCE(rdev))
4081 /* Lockout access through VGA aperture*/
4082 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
4083 /* Update configuration */
4084 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
4085 rdev->mc.vram_start >> 12);
4086 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
4087 rdev->mc.vram_end >> 12);
4088 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
4089 rdev->vram_scratch.gpu_addr >> 12);
4090 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
4091 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
4092 WREG32(MC_VM_FB_LOCATION, tmp);
4093 /* XXX double check these! */
4094 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
4095 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
4096 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
4097 WREG32(MC_VM_AGP_BASE, 0);
4098 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
4099 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
4100 if (radeon_mc_wait_for_idle(rdev)) {
4101 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4103 evergreen_mc_resume(rdev, &save);
4104 if (!ASIC_IS_NODCE(rdev)) {
4105 /* we need to own VRAM, so turn off the VGA renderer here
4106 * to stop it overwriting our objects */
4107 rv515_vga_render_disable(rdev);
4111 void si_vram_gtt_location(struct radeon_device *rdev,
4112 struct radeon_mc *mc)
4114 if (mc->mc_vram_size > 0xFFC0000000ULL) {
4115 /* leave room for at least 1024M GTT */
4116 dev_warn(rdev->dev, "limiting VRAM\n");
4117 mc->real_vram_size = 0xFFC0000000ULL;
4118 mc->mc_vram_size = 0xFFC0000000ULL;
4120 radeon_vram_location(rdev, &rdev->mc, 0);
4121 rdev->mc.gtt_base_align = 0;
4122 radeon_gtt_location(rdev, mc);
4125 static int si_mc_init(struct radeon_device *rdev)
4128 int chansize, numchan;
4130 /* Get VRAM informations */
4131 rdev->mc.vram_is_ddr = true;
4132 tmp = RREG32(MC_ARB_RAMCFG);
4133 if (tmp & CHANSIZE_OVERRIDE) {
4135 } else if (tmp & CHANSIZE_MASK) {
4140 tmp = RREG32(MC_SHARED_CHMAP);
4141 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
4171 rdev->mc.vram_width = numchan * chansize;
4172 /* Could aper size report 0 ? */
4173 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4174 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4175 /* size in MB on si */
4176 tmp = RREG32(CONFIG_MEMSIZE);
4177 /* some boards may have garbage in the upper 16 bits */
4178 if (tmp & 0xffff0000) {
4179 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
4183 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
4184 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
4185 rdev->mc.visible_vram_size = rdev->mc.aper_size;
4186 si_vram_gtt_location(rdev, &rdev->mc);
4187 radeon_update_bandwidth_info(rdev);
4195 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
4197 /* flush hdp cache */
4198 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4200 /* bits 0-15 are the VM contexts0-15 */
4201 WREG32(VM_INVALIDATE_REQUEST, 1);
4204 static int si_pcie_gart_enable(struct radeon_device *rdev)
4208 if (rdev->gart.robj == NULL) {
4209 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
4212 r = radeon_gart_table_vram_pin(rdev);
4215 /* Setup TLB control */
4216 WREG32(MC_VM_MX_L1_TLB_CNTL,
4219 ENABLE_L1_FRAGMENT_PROCESSING |
4220 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4221 ENABLE_ADVANCED_DRIVER_MODEL |
4222 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4223 /* Setup L2 cache */
4224 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
4225 ENABLE_L2_FRAGMENT_PROCESSING |
4226 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4227 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4228 EFFECTIVE_L2_QUEUE_SIZE(7) |
4229 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4230 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
4231 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4233 L2_CACHE_BIGK_FRAGMENT_SIZE(4));
4234 /* setup context0 */
4235 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
4236 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
4237 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
4238 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
4239 (u32)(rdev->dummy_page.addr >> 12));
4240 WREG32(VM_CONTEXT0_CNTL2, 0);
4241 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
4242 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
4248 /* empty context1-15 */
4249 /* set vm size, must be a multiple of 4 */
4250 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
4251 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
4252 /* Assign the pt base to something valid for now; the pts used for
4253 * the VMs are determined by the application and setup and assigned
4254 * on the fly in the vm part of radeon_gart.c
4256 for (i = 1; i < 16; i++) {
4258 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
4259 rdev->vm_manager.saved_table_addr[i]);
4261 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
4262 rdev->vm_manager.saved_table_addr[i]);
4265 /* enable context1-15 */
4266 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
4267 (u32)(rdev->dummy_page.addr >> 12));
4268 WREG32(VM_CONTEXT1_CNTL2, 4);
4269 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4270 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
4271 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4272 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4273 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4274 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4275 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
4276 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
4277 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
4278 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
4279 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
4280 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
4281 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4282 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
4284 si_pcie_gart_tlb_flush(rdev);
4285 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
4286 (unsigned)(rdev->mc.gtt_size >> 20),
4287 (unsigned long long)rdev->gart.table_addr);
4288 rdev->gart.ready = true;
4292 static void si_pcie_gart_disable(struct radeon_device *rdev)
4296 for (i = 1; i < 16; ++i) {
4299 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
4301 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
4302 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
4305 /* Disable all tables */
4306 WREG32(VM_CONTEXT0_CNTL, 0);
4307 WREG32(VM_CONTEXT1_CNTL, 0);
4308 /* Setup TLB control */
4309 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4310 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4311 /* Setup L2 cache */
4312 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4313 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4314 EFFECTIVE_L2_QUEUE_SIZE(7) |
4315 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4316 WREG32(VM_L2_CNTL2, 0);
4317 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4318 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
4319 radeon_gart_table_vram_unpin(rdev);
4322 static void si_pcie_gart_fini(struct radeon_device *rdev)
4324 si_pcie_gart_disable(rdev);
4325 radeon_gart_table_vram_free(rdev);
4326 radeon_gart_fini(rdev);
4330 static bool si_vm_reg_valid(u32 reg)
4332 /* context regs are fine */
4336 /* check config regs */
4338 case GRBM_GFX_INDEX:
4339 case CP_STRMOUT_CNTL:
4340 case VGT_VTX_VECT_EJECT_REG:
4341 case VGT_CACHE_INVALIDATION:
4342 case VGT_ESGS_RING_SIZE:
4343 case VGT_GSVS_RING_SIZE:
4344 case VGT_GS_VERTEX_REUSE:
4345 case VGT_PRIMITIVE_TYPE:
4346 case VGT_INDEX_TYPE:
4347 case VGT_NUM_INDICES:
4348 case VGT_NUM_INSTANCES:
4349 case VGT_TF_RING_SIZE:
4350 case VGT_HS_OFFCHIP_PARAM:
4351 case VGT_TF_MEMORY_BASE:
4353 case PA_SU_LINE_STIPPLE_VALUE:
4354 case PA_SC_LINE_STIPPLE_STATE:
4357 case SPI_STATIC_THREAD_MGMT_1:
4358 case SPI_STATIC_THREAD_MGMT_2:
4359 case SPI_STATIC_THREAD_MGMT_3:
4360 case SPI_PS_MAX_WAVE_ID:
4361 case SPI_CONFIG_CNTL:
4362 case SPI_CONFIG_CNTL_1:
4366 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
4371 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
4372 u32 *ib, struct radeon_cs_packet *pkt)
4374 switch (pkt->opcode) {
4376 case PACKET3_SET_BASE:
4377 case PACKET3_SET_CE_DE_COUNTERS:
4378 case PACKET3_LOAD_CONST_RAM:
4379 case PACKET3_WRITE_CONST_RAM:
4380 case PACKET3_WRITE_CONST_RAM_OFFSET:
4381 case PACKET3_DUMP_CONST_RAM:
4382 case PACKET3_INCREMENT_CE_COUNTER:
4383 case PACKET3_WAIT_ON_DE_COUNTER:
4384 case PACKET3_CE_WRITE:
4387 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
4393 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
4395 u32 start_reg, reg, i;
4396 u32 command = ib[idx + 4];
4397 u32 info = ib[idx + 1];
4398 u32 idx_value = ib[idx];
4399 if (command & PACKET3_CP_DMA_CMD_SAS) {
4400 /* src address space is register */
4401 if (((info & 0x60000000) >> 29) == 0) {
4402 start_reg = idx_value << 2;
4403 if (command & PACKET3_CP_DMA_CMD_SAIC) {
4405 if (!si_vm_reg_valid(reg)) {
4406 DRM_ERROR("CP DMA Bad SRC register\n");
4410 for (i = 0; i < (command & 0x1fffff); i++) {
4411 reg = start_reg + (4 * i);
4412 if (!si_vm_reg_valid(reg)) {
4413 DRM_ERROR("CP DMA Bad SRC register\n");
4420 if (command & PACKET3_CP_DMA_CMD_DAS) {
4421 /* dst address space is register */
4422 if (((info & 0x00300000) >> 20) == 0) {
4423 start_reg = ib[idx + 2];
4424 if (command & PACKET3_CP_DMA_CMD_DAIC) {
4426 if (!si_vm_reg_valid(reg)) {
4427 DRM_ERROR("CP DMA Bad DST register\n");
4431 for (i = 0; i < (command & 0x1fffff); i++) {
4432 reg = start_reg + (4 * i);
4433 if (!si_vm_reg_valid(reg)) {
4434 DRM_ERROR("CP DMA Bad DST register\n");
4444 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
4445 u32 *ib, struct radeon_cs_packet *pkt)
4448 u32 idx = pkt->idx + 1;
4449 u32 idx_value = ib[idx];
4450 u32 start_reg, end_reg, reg, i;
4452 switch (pkt->opcode) {
4454 case PACKET3_SET_BASE:
4455 case PACKET3_CLEAR_STATE:
4456 case PACKET3_INDEX_BUFFER_SIZE:
4457 case PACKET3_DISPATCH_DIRECT:
4458 case PACKET3_DISPATCH_INDIRECT:
4459 case PACKET3_ALLOC_GDS:
4460 case PACKET3_WRITE_GDS_RAM:
4461 case PACKET3_ATOMIC_GDS:
4462 case PACKET3_ATOMIC:
4463 case PACKET3_OCCLUSION_QUERY:
4464 case PACKET3_SET_PREDICATION:
4465 case PACKET3_COND_EXEC:
4466 case PACKET3_PRED_EXEC:
4467 case PACKET3_DRAW_INDIRECT:
4468 case PACKET3_DRAW_INDEX_INDIRECT:
4469 case PACKET3_INDEX_BASE:
4470 case PACKET3_DRAW_INDEX_2:
4471 case PACKET3_CONTEXT_CONTROL:
4472 case PACKET3_INDEX_TYPE:
4473 case PACKET3_DRAW_INDIRECT_MULTI:
4474 case PACKET3_DRAW_INDEX_AUTO:
4475 case PACKET3_DRAW_INDEX_IMMD:
4476 case PACKET3_NUM_INSTANCES:
4477 case PACKET3_DRAW_INDEX_MULTI_AUTO:
4478 case PACKET3_STRMOUT_BUFFER_UPDATE:
4479 case PACKET3_DRAW_INDEX_OFFSET_2:
4480 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
4481 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
4482 case PACKET3_MPEG_INDEX:
4483 case PACKET3_WAIT_REG_MEM:
4484 case PACKET3_MEM_WRITE:
4485 case PACKET3_PFP_SYNC_ME:
4486 case PACKET3_SURFACE_SYNC:
4487 case PACKET3_EVENT_WRITE:
4488 case PACKET3_EVENT_WRITE_EOP:
4489 case PACKET3_EVENT_WRITE_EOS:
4490 case PACKET3_SET_CONTEXT_REG:
4491 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4492 case PACKET3_SET_SH_REG:
4493 case PACKET3_SET_SH_REG_OFFSET:
4494 case PACKET3_INCREMENT_DE_COUNTER:
4495 case PACKET3_WAIT_ON_CE_COUNTER:
4496 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4497 case PACKET3_ME_WRITE:
4499 case PACKET3_COPY_DATA:
4500 if ((idx_value & 0xf00) == 0) {
4501 reg = ib[idx + 3] * 4;
4502 if (!si_vm_reg_valid(reg))
4506 case PACKET3_WRITE_DATA:
4507 if ((idx_value & 0xf00) == 0) {
4508 start_reg = ib[idx + 1] * 4;
4509 if (idx_value & 0x10000) {
4510 if (!si_vm_reg_valid(start_reg))
4513 for (i = 0; i < (pkt->count - 2); i++) {
4514 reg = start_reg + (4 * i);
4515 if (!si_vm_reg_valid(reg))
4521 case PACKET3_COND_WRITE:
4522 if (idx_value & 0x100) {
4523 reg = ib[idx + 5] * 4;
4524 if (!si_vm_reg_valid(reg))
4528 case PACKET3_COPY_DW:
4529 if (idx_value & 0x2) {
4530 reg = ib[idx + 3] * 4;
4531 if (!si_vm_reg_valid(reg))
4535 case PACKET3_SET_CONFIG_REG:
4536 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4537 end_reg = 4 * pkt->count + start_reg - 4;
4538 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
4539 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
4540 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
4541 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
4544 for (i = 0; i < pkt->count; i++) {
4545 reg = start_reg + (4 * i);
4546 if (!si_vm_reg_valid(reg))
4550 case PACKET3_CP_DMA:
4551 r = si_vm_packet3_cp_dma_check(ib, idx);
4556 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
4562 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
4563 u32 *ib, struct radeon_cs_packet *pkt)
4566 u32 idx = pkt->idx + 1;
4567 u32 idx_value = ib[idx];
4568 u32 start_reg, reg, i;
4570 switch (pkt->opcode) {
4572 case PACKET3_SET_BASE:
4573 case PACKET3_CLEAR_STATE:
4574 case PACKET3_DISPATCH_DIRECT:
4575 case PACKET3_DISPATCH_INDIRECT:
4576 case PACKET3_ALLOC_GDS:
4577 case PACKET3_WRITE_GDS_RAM:
4578 case PACKET3_ATOMIC_GDS:
4579 case PACKET3_ATOMIC:
4580 case PACKET3_OCCLUSION_QUERY:
4581 case PACKET3_SET_PREDICATION:
4582 case PACKET3_COND_EXEC:
4583 case PACKET3_PRED_EXEC:
4584 case PACKET3_CONTEXT_CONTROL:
4585 case PACKET3_STRMOUT_BUFFER_UPDATE:
4586 case PACKET3_WAIT_REG_MEM:
4587 case PACKET3_MEM_WRITE:
4588 case PACKET3_PFP_SYNC_ME:
4589 case PACKET3_SURFACE_SYNC:
4590 case PACKET3_EVENT_WRITE:
4591 case PACKET3_EVENT_WRITE_EOP:
4592 case PACKET3_EVENT_WRITE_EOS:
4593 case PACKET3_SET_CONTEXT_REG:
4594 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4595 case PACKET3_SET_SH_REG:
4596 case PACKET3_SET_SH_REG_OFFSET:
4597 case PACKET3_INCREMENT_DE_COUNTER:
4598 case PACKET3_WAIT_ON_CE_COUNTER:
4599 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4600 case PACKET3_ME_WRITE:
4602 case PACKET3_COPY_DATA:
4603 if ((idx_value & 0xf00) == 0) {
4604 reg = ib[idx + 3] * 4;
4605 if (!si_vm_reg_valid(reg))
4609 case PACKET3_WRITE_DATA:
4610 if ((idx_value & 0xf00) == 0) {
4611 start_reg = ib[idx + 1] * 4;
4612 if (idx_value & 0x10000) {
4613 if (!si_vm_reg_valid(start_reg))
4616 for (i = 0; i < (pkt->count - 2); i++) {
4617 reg = start_reg + (4 * i);
4618 if (!si_vm_reg_valid(reg))
4624 case PACKET3_COND_WRITE:
4625 if (idx_value & 0x100) {
4626 reg = ib[idx + 5] * 4;
4627 if (!si_vm_reg_valid(reg))
4631 case PACKET3_COPY_DW:
4632 if (idx_value & 0x2) {
4633 reg = ib[idx + 3] * 4;
4634 if (!si_vm_reg_valid(reg))
4638 case PACKET3_CP_DMA:
4639 r = si_vm_packet3_cp_dma_check(ib, idx);
4644 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
4650 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4654 struct radeon_cs_packet pkt;
4658 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
4659 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
4662 case RADEON_PACKET_TYPE0:
4663 dev_err(rdev->dev, "Packet0 not allowed!\n");
4666 case RADEON_PACKET_TYPE2:
4669 case RADEON_PACKET_TYPE3:
4670 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
4671 if (ib->is_const_ib)
4672 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
4675 case RADEON_RING_TYPE_GFX_INDEX:
4676 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
4678 case CAYMAN_RING_TYPE_CP1_INDEX:
4679 case CAYMAN_RING_TYPE_CP2_INDEX:
4680 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
4683 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
4688 idx += pkt.count + 2;
4691 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
4696 for (i = 0; i < ib->length_dw; i++) {
4698 printk("\t0x%08x <---\n", ib->ptr[i]);
4700 printk("\t0x%08x\n", ib->ptr[i]);
4704 } while (idx < ib->length_dw);
4712 int si_vm_init(struct radeon_device *rdev)
4715 rdev->vm_manager.nvm = 16;
4716 /* base offset of vram pages */
4717 rdev->vm_manager.vram_base_offset = 0;
4722 void si_vm_fini(struct radeon_device *rdev)
4727 * si_vm_decode_fault - print human readable fault info
4729 * @rdev: radeon_device pointer
4730 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
4731 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
4733 * Print human readable fault information (SI).
4735 static void si_vm_decode_fault(struct radeon_device *rdev,
4736 u32 status, u32 addr)
4738 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4739 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4740 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4743 if (rdev->family == CHIP_TAHITI) {
4984 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
4985 protections, vmid, addr,
4986 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
4990 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
4991 unsigned vm_id, uint64_t pd_addr)
4993 /* write new base address */
4994 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4995 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4996 WRITE_DATA_DST_SEL(0)));
4999 radeon_ring_write(ring,
5000 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5002 radeon_ring_write(ring,
5003 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5005 radeon_ring_write(ring, 0);
5006 radeon_ring_write(ring, pd_addr >> 12);
5008 /* flush hdp cache */
5009 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5010 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5011 WRITE_DATA_DST_SEL(0)));
5012 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5013 radeon_ring_write(ring, 0);
5014 radeon_ring_write(ring, 0x1);
5016 /* bits 0-15 are the VM contexts0-15 */
5017 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5018 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5019 WRITE_DATA_DST_SEL(0)));
5020 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5021 radeon_ring_write(ring, 0);
5022 radeon_ring_write(ring, 1 << vm_id);
5024 /* wait for the invalidate to complete */
5025 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5026 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
5027 WAIT_REG_MEM_ENGINE(0))); /* me */
5028 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5029 radeon_ring_write(ring, 0);
5030 radeon_ring_write(ring, 0); /* ref */
5031 radeon_ring_write(ring, 0); /* mask */
5032 radeon_ring_write(ring, 0x20); /* poll interval */
5034 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5035 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5036 radeon_ring_write(ring, 0x0);
5040 * Power and clock gating
5042 static void si_wait_for_rlc_serdes(struct radeon_device *rdev)
5046 for (i = 0; i < rdev->usec_timeout; i++) {
5047 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
5052 for (i = 0; i < rdev->usec_timeout; i++) {
5053 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
5059 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
5062 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5067 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5069 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5070 WREG32(CP_INT_CNTL_RING0, tmp);
5073 /* read a gfx register */
5074 tmp = RREG32(DB_DEPTH_INFO);
5076 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
5077 for (i = 0; i < rdev->usec_timeout; i++) {
5078 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
5085 static void si_set_uvd_dcm(struct radeon_device *rdev,
5090 tmp = RREG32(UVD_CGC_CTRL);
5091 tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
5092 tmp |= DCM | CG_DT(1) | CLK_OD(4);
5096 tmp2 = DYN_OR_EN | DYN_RR_EN | G_DIV_ID(7);
5102 WREG32(UVD_CGC_CTRL, tmp);
5103 WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
5106 void si_init_uvd_internal_cg(struct radeon_device *rdev)
5108 bool hw_mode = true;
5111 si_set_uvd_dcm(rdev, false);
5113 u32 tmp = RREG32(UVD_CGC_CTRL);
5115 WREG32(UVD_CGC_CTRL, tmp);
5119 static u32 si_halt_rlc(struct radeon_device *rdev)
5123 orig = data = RREG32(RLC_CNTL);
5125 if (data & RLC_ENABLE) {
5126 data &= ~RLC_ENABLE;
5127 WREG32(RLC_CNTL, data);
5129 si_wait_for_rlc_serdes(rdev);
5135 static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
5139 tmp = RREG32(RLC_CNTL);
5141 WREG32(RLC_CNTL, rlc);
5144 static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
5148 orig = data = RREG32(DMA_PG);
5149 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
5150 data |= PG_CNTL_ENABLE;
5152 data &= ~PG_CNTL_ENABLE;
5154 WREG32(DMA_PG, data);
5157 static void si_init_dma_pg(struct radeon_device *rdev)
5161 WREG32(DMA_PGFSM_WRITE, 0x00002000);
5162 WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
5164 for (tmp = 0; tmp < 5; tmp++)
5165 WREG32(DMA_PGFSM_WRITE, 0);
5168 static void si_enable_gfx_cgpg(struct radeon_device *rdev,
5173 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
5174 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
5175 WREG32(RLC_TTOP_D, tmp);
5177 tmp = RREG32(RLC_PG_CNTL);
5178 tmp |= GFX_PG_ENABLE;
5179 WREG32(RLC_PG_CNTL, tmp);
5181 tmp = RREG32(RLC_AUTO_PG_CTRL);
5183 WREG32(RLC_AUTO_PG_CTRL, tmp);
5185 tmp = RREG32(RLC_AUTO_PG_CTRL);
5187 WREG32(RLC_AUTO_PG_CTRL, tmp);
5189 tmp = RREG32(DB_RENDER_CONTROL);
5193 static void si_init_gfx_cgpg(struct radeon_device *rdev)
5197 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5199 tmp = RREG32(RLC_PG_CNTL);
5201 WREG32(RLC_PG_CNTL, tmp);
5203 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5205 tmp = RREG32(RLC_AUTO_PG_CTRL);
5207 tmp &= ~GRBM_REG_SGIT_MASK;
5208 tmp |= GRBM_REG_SGIT(0x700);
5209 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
5210 WREG32(RLC_AUTO_PG_CTRL, tmp);
5213 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
5215 u32 mask = 0, tmp, tmp1;
5218 si_select_se_sh(rdev, se, sh);
5219 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
5220 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
5221 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5228 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {
5233 return (~tmp) & mask;
5236 static void si_init_ao_cu_mask(struct radeon_device *rdev)
5238 u32 i, j, k, active_cu_number = 0;
5239 u32 mask, counter, cu_bitmap;
5242 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
5243 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
5247 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
5248 if (si_get_cu_active_bitmap(rdev, i, j) & mask) {
5256 active_cu_number += counter;
5257 tmp |= (cu_bitmap << (i * 16 + j * 8));
5261 WREG32(RLC_PG_AO_CU_MASK, tmp);
5263 tmp = RREG32(RLC_MAX_PG_CU);
5264 tmp &= ~MAX_PU_CU_MASK;
5265 tmp |= MAX_PU_CU(active_cu_number);
5266 WREG32(RLC_MAX_PG_CU, tmp);
5269 static void si_enable_cgcg(struct radeon_device *rdev,
5272 u32 data, orig, tmp;
5274 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5276 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5277 si_enable_gui_idle_interrupt(rdev, true);
5279 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
5281 tmp = si_halt_rlc(rdev);
5283 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5284 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5285 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
5287 si_wait_for_rlc_serdes(rdev);
5289 si_update_rlc(rdev, tmp);
5291 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
5293 data |= CGCG_EN | CGLS_EN;
5295 si_enable_gui_idle_interrupt(rdev, false);
5297 RREG32(CB_CGTT_SCLK_CTRL);
5298 RREG32(CB_CGTT_SCLK_CTRL);
5299 RREG32(CB_CGTT_SCLK_CTRL);
5300 RREG32(CB_CGTT_SCLK_CTRL);
5302 data &= ~(CGCG_EN | CGLS_EN);
5306 WREG32(RLC_CGCG_CGLS_CTRL, data);
5309 static void si_enable_mgcg(struct radeon_device *rdev,
5312 u32 data, orig, tmp = 0;
5314 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5315 orig = data = RREG32(CGTS_SM_CTRL_REG);
5318 WREG32(CGTS_SM_CTRL_REG, data);
5320 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5321 orig = data = RREG32(CP_MEM_SLP_CNTL);
5322 data |= CP_MEM_LS_EN;
5324 WREG32(CP_MEM_SLP_CNTL, data);
5327 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5330 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5332 tmp = si_halt_rlc(rdev);
5334 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5335 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5336 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
5338 si_update_rlc(rdev, tmp);
5340 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5343 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5345 data = RREG32(CP_MEM_SLP_CNTL);
5346 if (data & CP_MEM_LS_EN) {
5347 data &= ~CP_MEM_LS_EN;
5348 WREG32(CP_MEM_SLP_CNTL, data);
5350 orig = data = RREG32(CGTS_SM_CTRL_REG);
5351 data |= LS_OVERRIDE | OVERRIDE;
5353 WREG32(CGTS_SM_CTRL_REG, data);
5355 tmp = si_halt_rlc(rdev);
5357 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5358 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5359 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
5361 si_update_rlc(rdev, tmp);
5365 static void si_enable_uvd_mgcg(struct radeon_device *rdev,
5368 u32 orig, data, tmp;
5370 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
5371 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5373 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5375 orig = data = RREG32(UVD_CGC_CTRL);
5378 WREG32(UVD_CGC_CTRL, data);
5380 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
5381 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
5383 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5385 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5387 orig = data = RREG32(UVD_CGC_CTRL);
5390 WREG32(UVD_CGC_CTRL, data);
5392 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
5393 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
5397 static const u32 mc_cg_registers[] =
5410 static void si_enable_mc_ls(struct radeon_device *rdev,
5416 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5417 orig = data = RREG32(mc_cg_registers[i]);
5418 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5419 data |= MC_LS_ENABLE;
5421 data &= ~MC_LS_ENABLE;
5423 WREG32(mc_cg_registers[i], data);
5427 static void si_enable_mc_mgcg(struct radeon_device *rdev,
5433 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5434 orig = data = RREG32(mc_cg_registers[i]);
5435 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5436 data |= MC_CG_ENABLE;
5438 data &= ~MC_CG_ENABLE;
5440 WREG32(mc_cg_registers[i], data);
5444 static void si_enable_dma_mgcg(struct radeon_device *rdev,
5447 u32 orig, data, offset;
5450 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5451 for (i = 0; i < 2; i++) {
5453 offset = DMA0_REGISTER_OFFSET;
5455 offset = DMA1_REGISTER_OFFSET;
5456 orig = data = RREG32(DMA_POWER_CNTL + offset);
5457 data &= ~MEM_POWER_OVERRIDE;
5459 WREG32(DMA_POWER_CNTL + offset, data);
5460 WREG32(DMA_CLK_CTRL + offset, 0x00000100);
5463 for (i = 0; i < 2; i++) {
5465 offset = DMA0_REGISTER_OFFSET;
5467 offset = DMA1_REGISTER_OFFSET;
5468 orig = data = RREG32(DMA_POWER_CNTL + offset);
5469 data |= MEM_POWER_OVERRIDE;
5471 WREG32(DMA_POWER_CNTL + offset, data);
5473 orig = data = RREG32(DMA_CLK_CTRL + offset);
5476 WREG32(DMA_CLK_CTRL + offset, data);
5481 static void si_enable_bif_mgls(struct radeon_device *rdev,
5486 orig = data = RREG32_PCIE(PCIE_CNTL2);
5488 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
5489 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
5490 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
5492 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
5493 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
5496 WREG32_PCIE(PCIE_CNTL2, data);
5499 static void si_enable_hdp_mgcg(struct radeon_device *rdev,
5504 orig = data = RREG32(HDP_HOST_PATH_CNTL);
5506 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
5507 data &= ~CLOCK_GATING_DIS;
5509 data |= CLOCK_GATING_DIS;
5512 WREG32(HDP_HOST_PATH_CNTL, data);
5515 static void si_enable_hdp_ls(struct radeon_device *rdev,
5520 orig = data = RREG32(HDP_MEM_POWER_LS);
5522 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
5523 data |= HDP_LS_ENABLE;
5525 data &= ~HDP_LS_ENABLE;
5528 WREG32(HDP_MEM_POWER_LS, data);
5531 static void si_update_cg(struct radeon_device *rdev,
5532 u32 block, bool enable)
5534 if (block & RADEON_CG_BLOCK_GFX) {
5535 si_enable_gui_idle_interrupt(rdev, false);
5536 /* order matters! */
5538 si_enable_mgcg(rdev, true);
5539 si_enable_cgcg(rdev, true);
5541 si_enable_cgcg(rdev, false);
5542 si_enable_mgcg(rdev, false);
5544 si_enable_gui_idle_interrupt(rdev, true);
5547 if (block & RADEON_CG_BLOCK_MC) {
5548 si_enable_mc_mgcg(rdev, enable);
5549 si_enable_mc_ls(rdev, enable);
5552 if (block & RADEON_CG_BLOCK_SDMA) {
5553 si_enable_dma_mgcg(rdev, enable);
5556 if (block & RADEON_CG_BLOCK_BIF) {
5557 si_enable_bif_mgls(rdev, enable);
5560 if (block & RADEON_CG_BLOCK_UVD) {
5561 if (rdev->has_uvd) {
5562 si_enable_uvd_mgcg(rdev, enable);
5566 if (block & RADEON_CG_BLOCK_HDP) {
5567 si_enable_hdp_mgcg(rdev, enable);
5568 si_enable_hdp_ls(rdev, enable);
5572 static void si_init_cg(struct radeon_device *rdev)
5574 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5575 RADEON_CG_BLOCK_MC |
5576 RADEON_CG_BLOCK_SDMA |
5577 RADEON_CG_BLOCK_BIF |
5578 RADEON_CG_BLOCK_HDP), true);
5579 if (rdev->has_uvd) {
5580 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
5581 si_init_uvd_internal_cg(rdev);
5585 static void si_fini_cg(struct radeon_device *rdev)
5587 if (rdev->has_uvd) {
5588 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
5590 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5591 RADEON_CG_BLOCK_MC |
5592 RADEON_CG_BLOCK_SDMA |
5593 RADEON_CG_BLOCK_BIF |
5594 RADEON_CG_BLOCK_HDP), false);
5597 u32 si_get_csb_size(struct radeon_device *rdev)
5600 const struct cs_section_def *sect = NULL;
5601 const struct cs_extent_def *ext = NULL;
5603 if (rdev->rlc.cs_data == NULL)
5606 /* begin clear state */
5608 /* context control state */
5611 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5612 for (ext = sect->section; ext->extent != NULL; ++ext) {
5613 if (sect->id == SECT_CONTEXT)
5614 count += 2 + ext->reg_count;
5619 /* pa_sc_raster_config */
5621 /* end clear state */
5629 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
5632 const struct cs_section_def *sect = NULL;
5633 const struct cs_extent_def *ext = NULL;
5635 if (rdev->rlc.cs_data == NULL)
5640 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5641 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5643 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5644 buffer[count++] = cpu_to_le32(0x80000000);
5645 buffer[count++] = cpu_to_le32(0x80000000);
5647 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5648 for (ext = sect->section; ext->extent != NULL; ++ext) {
5649 if (sect->id == SECT_CONTEXT) {
5651 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
5652 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
5653 for (i = 0; i < ext->reg_count; i++)
5654 buffer[count++] = cpu_to_le32(ext->extent[i]);
5661 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5662 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
5663 switch (rdev->family) {
5666 buffer[count++] = cpu_to_le32(0x2a00126a);
5669 buffer[count++] = cpu_to_le32(0x0000124a);
5672 buffer[count++] = cpu_to_le32(0x00000082);
5675 buffer[count++] = cpu_to_le32(0x00000000);
5678 buffer[count++] = cpu_to_le32(0x00000000);
5682 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5683 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
5685 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
5686 buffer[count++] = cpu_to_le32(0);
5689 static void si_init_pg(struct radeon_device *rdev)
5691 if (rdev->pg_flags) {
5692 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
5693 si_init_dma_pg(rdev);
5695 si_init_ao_cu_mask(rdev);
5696 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5697 si_init_gfx_cgpg(rdev);
5699 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5700 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5702 si_enable_dma_pg(rdev, true);
5703 si_enable_gfx_cgpg(rdev, true);
5705 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5706 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5710 static void si_fini_pg(struct radeon_device *rdev)
5712 if (rdev->pg_flags) {
5713 si_enable_dma_pg(rdev, false);
5714 si_enable_gfx_cgpg(rdev, false);
5721 void si_rlc_reset(struct radeon_device *rdev)
5723 u32 tmp = RREG32(GRBM_SOFT_RESET);
5725 tmp |= SOFT_RESET_RLC;
5726 WREG32(GRBM_SOFT_RESET, tmp);
5728 tmp &= ~SOFT_RESET_RLC;
5729 WREG32(GRBM_SOFT_RESET, tmp);
5733 static void si_rlc_stop(struct radeon_device *rdev)
5735 WREG32(RLC_CNTL, 0);
5737 si_enable_gui_idle_interrupt(rdev, false);
5739 si_wait_for_rlc_serdes(rdev);
5742 static void si_rlc_start(struct radeon_device *rdev)
5744 WREG32(RLC_CNTL, RLC_ENABLE);
5746 si_enable_gui_idle_interrupt(rdev, true);
5751 static bool si_lbpw_supported(struct radeon_device *rdev)
5755 /* Enable LBPW only for DDR3 */
5756 tmp = RREG32(MC_SEQ_MISC0);
5757 if ((tmp & 0xF0000000) == 0xB0000000)
5762 static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
5766 tmp = RREG32(RLC_LB_CNTL);
5768 tmp |= LOAD_BALANCE_ENABLE;
5770 tmp &= ~LOAD_BALANCE_ENABLE;
5771 WREG32(RLC_LB_CNTL, tmp);
5774 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5775 WREG32(SPI_LB_CU_MASK, 0x00ff);
5779 static int si_rlc_resume(struct radeon_device *rdev)
5794 WREG32(RLC_RL_BASE, 0);
5795 WREG32(RLC_RL_SIZE, 0);
5796 WREG32(RLC_LB_CNTL, 0);
5797 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
5798 WREG32(RLC_LB_CNTR_INIT, 0);
5799 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5801 WREG32(RLC_MC_CNTL, 0);
5802 WREG32(RLC_UCODE_CNTL, 0);
5805 const struct rlc_firmware_header_v1_0 *hdr =
5806 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5807 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5808 const __le32 *fw_data = (const __le32 *)
5809 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5811 radeon_ucode_print_rlc_hdr(&hdr->header);
5813 for (i = 0; i < fw_size; i++) {
5814 WREG32(RLC_UCODE_ADDR, i);
5815 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
5818 const __be32 *fw_data =
5819 (const __be32 *)rdev->rlc_fw->data;
5820 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
5821 WREG32(RLC_UCODE_ADDR, i);
5822 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
5825 WREG32(RLC_UCODE_ADDR, 0);
5827 si_enable_lbpw(rdev, si_lbpw_supported(rdev));
5834 static void si_enable_interrupts(struct radeon_device *rdev)
5836 u32 ih_cntl = RREG32(IH_CNTL);
5837 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5839 ih_cntl |= ENABLE_INTR;
5840 ih_rb_cntl |= IH_RB_ENABLE;
5841 WREG32(IH_CNTL, ih_cntl);
5842 WREG32(IH_RB_CNTL, ih_rb_cntl);
5843 rdev->ih.enabled = true;
5846 static void si_disable_interrupts(struct radeon_device *rdev)
5848 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5849 u32 ih_cntl = RREG32(IH_CNTL);
5851 ih_rb_cntl &= ~IH_RB_ENABLE;
5852 ih_cntl &= ~ENABLE_INTR;
5853 WREG32(IH_RB_CNTL, ih_rb_cntl);
5854 WREG32(IH_CNTL, ih_cntl);
5855 /* set rptr, wptr to 0 */
5856 WREG32(IH_RB_RPTR, 0);
5857 WREG32(IH_RB_WPTR, 0);
5858 rdev->ih.enabled = false;
5862 static void si_disable_interrupt_state(struct radeon_device *rdev)
5866 tmp = RREG32(CP_INT_CNTL_RING0) &
5867 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5868 WREG32(CP_INT_CNTL_RING0, tmp);
5869 WREG32(CP_INT_CNTL_RING1, 0);
5870 WREG32(CP_INT_CNTL_RING2, 0);
5871 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5872 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5873 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5874 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
5875 WREG32(GRBM_INT_CNTL, 0);
5876 WREG32(SRBM_INT_CNTL, 0);
5877 if (rdev->num_crtc >= 2) {
5878 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5879 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5881 if (rdev->num_crtc >= 4) {
5882 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5883 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5885 if (rdev->num_crtc >= 6) {
5886 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5887 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5890 if (rdev->num_crtc >= 2) {
5891 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5892 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5894 if (rdev->num_crtc >= 4) {
5895 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5896 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5898 if (rdev->num_crtc >= 6) {
5899 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5900 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5903 if (!ASIC_IS_NODCE(rdev)) {
5904 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5906 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5907 WREG32(DC_HPD1_INT_CONTROL, tmp);
5908 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5909 WREG32(DC_HPD2_INT_CONTROL, tmp);
5910 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5911 WREG32(DC_HPD3_INT_CONTROL, tmp);
5912 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5913 WREG32(DC_HPD4_INT_CONTROL, tmp);
5914 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5915 WREG32(DC_HPD5_INT_CONTROL, tmp);
5916 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5917 WREG32(DC_HPD6_INT_CONTROL, tmp);
5921 static int si_irq_init(struct radeon_device *rdev)
5925 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
5928 ret = r600_ih_ring_alloc(rdev);
5933 si_disable_interrupts(rdev);
5936 ret = si_rlc_resume(rdev);
5938 r600_ih_ring_fini(rdev);
5942 /* setup interrupt control */
5943 /* set dummy read address to dummy page address */
5944 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
5945 interrupt_cntl = RREG32(INTERRUPT_CNTL);
5946 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
5947 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
5949 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
5950 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
5951 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
5952 WREG32(INTERRUPT_CNTL, interrupt_cntl);
5954 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
5955 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
5957 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
5958 IH_WPTR_OVERFLOW_CLEAR |
5961 if (rdev->wb.enabled)
5962 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
5964 /* set the writeback address whether it's enabled or not */
5965 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
5966 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
5968 WREG32(IH_RB_CNTL, ih_rb_cntl);
5970 /* set rptr, wptr to 0 */
5971 WREG32(IH_RB_RPTR, 0);
5972 WREG32(IH_RB_WPTR, 0);
5974 /* Default settings for IH_CNTL (disabled at first) */
5975 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
5976 /* RPTR_REARM only works if msi's are enabled */
5977 if (rdev->msi_enabled)
5978 ih_cntl |= RPTR_REARM;
5979 WREG32(IH_CNTL, ih_cntl);
5981 /* force the active interrupt state to all disabled */
5982 si_disable_interrupt_state(rdev);
5984 pci_set_master(rdev->pdev);
5987 si_enable_interrupts(rdev);
5992 int si_irq_set(struct radeon_device *rdev)
5995 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
5996 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
5997 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
5998 u32 grbm_int_cntl = 0;
5999 u32 dma_cntl, dma_cntl1;
6000 u32 thermal_int = 0;
6002 if (!rdev->irq.installed) {
6003 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6006 /* don't enable anything if the ih is disabled */
6007 if (!rdev->ih.enabled) {
6008 si_disable_interrupts(rdev);
6009 /* force the active interrupt state to all disabled */
6010 si_disable_interrupt_state(rdev);
6014 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6015 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6017 if (!ASIC_IS_NODCE(rdev)) {
6018 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6019 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6020 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6021 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6022 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6023 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6026 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6027 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6029 thermal_int = RREG32(CG_THERMAL_INT) &
6030 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6032 /* enable CP interrupts on all rings */
6033 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6034 DRM_DEBUG("si_irq_set: sw int gfx\n");
6035 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6037 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6038 DRM_DEBUG("si_irq_set: sw int cp1\n");
6039 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
6041 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6042 DRM_DEBUG("si_irq_set: sw int cp2\n");
6043 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
6045 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6046 DRM_DEBUG("si_irq_set: sw int dma\n");
6047 dma_cntl |= TRAP_ENABLE;
6050 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6051 DRM_DEBUG("si_irq_set: sw int dma1\n");
6052 dma_cntl1 |= TRAP_ENABLE;
6054 if (rdev->irq.crtc_vblank_int[0] ||
6055 atomic_read(&rdev->irq.pflip[0])) {
6056 DRM_DEBUG("si_irq_set: vblank 0\n");
6057 crtc1 |= VBLANK_INT_MASK;
6059 if (rdev->irq.crtc_vblank_int[1] ||
6060 atomic_read(&rdev->irq.pflip[1])) {
6061 DRM_DEBUG("si_irq_set: vblank 1\n");
6062 crtc2 |= VBLANK_INT_MASK;
6064 if (rdev->irq.crtc_vblank_int[2] ||
6065 atomic_read(&rdev->irq.pflip[2])) {
6066 DRM_DEBUG("si_irq_set: vblank 2\n");
6067 crtc3 |= VBLANK_INT_MASK;
6069 if (rdev->irq.crtc_vblank_int[3] ||
6070 atomic_read(&rdev->irq.pflip[3])) {
6071 DRM_DEBUG("si_irq_set: vblank 3\n");
6072 crtc4 |= VBLANK_INT_MASK;
6074 if (rdev->irq.crtc_vblank_int[4] ||
6075 atomic_read(&rdev->irq.pflip[4])) {
6076 DRM_DEBUG("si_irq_set: vblank 4\n");
6077 crtc5 |= VBLANK_INT_MASK;
6079 if (rdev->irq.crtc_vblank_int[5] ||
6080 atomic_read(&rdev->irq.pflip[5])) {
6081 DRM_DEBUG("si_irq_set: vblank 5\n");
6082 crtc6 |= VBLANK_INT_MASK;
6084 if (rdev->irq.hpd[0]) {
6085 DRM_DEBUG("si_irq_set: hpd 1\n");
6086 hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6088 if (rdev->irq.hpd[1]) {
6089 DRM_DEBUG("si_irq_set: hpd 2\n");
6090 hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6092 if (rdev->irq.hpd[2]) {
6093 DRM_DEBUG("si_irq_set: hpd 3\n");
6094 hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6096 if (rdev->irq.hpd[3]) {
6097 DRM_DEBUG("si_irq_set: hpd 4\n");
6098 hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6100 if (rdev->irq.hpd[4]) {
6101 DRM_DEBUG("si_irq_set: hpd 5\n");
6102 hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6104 if (rdev->irq.hpd[5]) {
6105 DRM_DEBUG("si_irq_set: hpd 6\n");
6106 hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6109 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6110 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
6111 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
6113 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
6114 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
6116 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
6118 if (rdev->irq.dpm_thermal) {
6119 DRM_DEBUG("dpm thermal\n");
6120 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6123 if (rdev->num_crtc >= 2) {
6124 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
6125 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
6127 if (rdev->num_crtc >= 4) {
6128 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
6129 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
6131 if (rdev->num_crtc >= 6) {
6132 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
6133 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
6136 if (rdev->num_crtc >= 2) {
6137 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
6138 GRPH_PFLIP_INT_MASK);
6139 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
6140 GRPH_PFLIP_INT_MASK);
6142 if (rdev->num_crtc >= 4) {
6143 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
6144 GRPH_PFLIP_INT_MASK);
6145 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
6146 GRPH_PFLIP_INT_MASK);
6148 if (rdev->num_crtc >= 6) {
6149 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
6150 GRPH_PFLIP_INT_MASK);
6151 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
6152 GRPH_PFLIP_INT_MASK);
6155 if (!ASIC_IS_NODCE(rdev)) {
6156 WREG32(DC_HPD1_INT_CONTROL, hpd1);
6157 WREG32(DC_HPD2_INT_CONTROL, hpd2);
6158 WREG32(DC_HPD3_INT_CONTROL, hpd3);
6159 WREG32(DC_HPD4_INT_CONTROL, hpd4);
6160 WREG32(DC_HPD5_INT_CONTROL, hpd5);
6161 WREG32(DC_HPD6_INT_CONTROL, hpd6);
6164 WREG32(CG_THERMAL_INT, thermal_int);
6167 RREG32(SRBM_STATUS);
6172 static inline void si_irq_ack(struct radeon_device *rdev)
6176 if (ASIC_IS_NODCE(rdev))
6179 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
6180 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
6181 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
6182 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
6183 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
6184 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
6185 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
6186 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
6187 if (rdev->num_crtc >= 4) {
6188 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
6189 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
6191 if (rdev->num_crtc >= 6) {
6192 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
6193 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
6196 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
6197 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6198 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
6199 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6200 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
6201 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6202 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
6203 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6204 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
6205 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6206 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
6207 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
6209 if (rdev->num_crtc >= 4) {
6210 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
6211 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6212 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
6213 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6214 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
6215 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6216 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
6217 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
6218 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
6219 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6220 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
6221 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
6224 if (rdev->num_crtc >= 6) {
6225 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
6226 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6227 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
6228 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6229 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
6230 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6231 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
6232 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
6233 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
6234 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6235 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
6236 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
6239 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
6240 tmp = RREG32(DC_HPD1_INT_CONTROL);
6241 tmp |= DC_HPDx_INT_ACK;
6242 WREG32(DC_HPD1_INT_CONTROL, tmp);
6244 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
6245 tmp = RREG32(DC_HPD2_INT_CONTROL);
6246 tmp |= DC_HPDx_INT_ACK;
6247 WREG32(DC_HPD2_INT_CONTROL, tmp);
6249 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
6250 tmp = RREG32(DC_HPD3_INT_CONTROL);
6251 tmp |= DC_HPDx_INT_ACK;
6252 WREG32(DC_HPD3_INT_CONTROL, tmp);
6254 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
6255 tmp = RREG32(DC_HPD4_INT_CONTROL);
6256 tmp |= DC_HPDx_INT_ACK;
6257 WREG32(DC_HPD4_INT_CONTROL, tmp);
6259 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
6260 tmp = RREG32(DC_HPD5_INT_CONTROL);
6261 tmp |= DC_HPDx_INT_ACK;
6262 WREG32(DC_HPD5_INT_CONTROL, tmp);
6264 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
6265 tmp = RREG32(DC_HPD6_INT_CONTROL);
6266 tmp |= DC_HPDx_INT_ACK;
6267 WREG32(DC_HPD6_INT_CONTROL, tmp);
6270 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) {
6271 tmp = RREG32(DC_HPD1_INT_CONTROL);
6272 tmp |= DC_HPDx_RX_INT_ACK;
6273 WREG32(DC_HPD1_INT_CONTROL, tmp);
6275 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
6276 tmp = RREG32(DC_HPD2_INT_CONTROL);
6277 tmp |= DC_HPDx_RX_INT_ACK;
6278 WREG32(DC_HPD2_INT_CONTROL, tmp);
6280 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
6281 tmp = RREG32(DC_HPD3_INT_CONTROL);
6282 tmp |= DC_HPDx_RX_INT_ACK;
6283 WREG32(DC_HPD3_INT_CONTROL, tmp);
6285 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
6286 tmp = RREG32(DC_HPD4_INT_CONTROL);
6287 tmp |= DC_HPDx_RX_INT_ACK;
6288 WREG32(DC_HPD4_INT_CONTROL, tmp);
6290 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
6291 tmp = RREG32(DC_HPD5_INT_CONTROL);
6292 tmp |= DC_HPDx_RX_INT_ACK;
6293 WREG32(DC_HPD5_INT_CONTROL, tmp);
6295 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
6296 tmp = RREG32(DC_HPD6_INT_CONTROL);
6297 tmp |= DC_HPDx_RX_INT_ACK;
6298 WREG32(DC_HPD6_INT_CONTROL, tmp);
6302 static void si_irq_disable(struct radeon_device *rdev)
6304 si_disable_interrupts(rdev);
6305 /* Wait and acknowledge irq */
6308 si_disable_interrupt_state(rdev);
6311 static void si_irq_suspend(struct radeon_device *rdev)
6313 si_irq_disable(rdev);
6317 static void si_irq_fini(struct radeon_device *rdev)
6319 si_irq_suspend(rdev);
6320 r600_ih_ring_fini(rdev);
6323 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
6327 if (rdev->wb.enabled)
6328 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
6330 wptr = RREG32(IH_RB_WPTR);
6332 if (wptr & RB_OVERFLOW) {
6333 wptr &= ~RB_OVERFLOW;
6334 /* When a ring buffer overflow happen start parsing interrupt
6335 * from the last not overwritten vector (wptr + 16). Hopefully
6336 * this should allow us to catchup.
6338 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
6339 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
6340 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
6341 tmp = RREG32(IH_RB_CNTL);
6342 tmp |= IH_WPTR_OVERFLOW_CLEAR;
6343 WREG32(IH_RB_CNTL, tmp);
6345 return (wptr & rdev->ih.ptr_mask);
6349 * Each IV ring entry is 128 bits:
6350 * [7:0] - interrupt source id
6352 * [59:32] - interrupt source data
6353 * [63:60] - reserved
6356 * [127:80] - reserved
6358 int si_irq_process(struct radeon_device *rdev)
6362 u32 src_id, src_data, ring_id;
6364 bool queue_hotplug = false;
6365 bool queue_dp = false;
6366 bool queue_thermal = false;
6369 if (!rdev->ih.enabled || rdev->shutdown)
6372 wptr = si_get_ih_wptr(rdev);
6375 /* is somebody else already processing irqs? */
6376 if (atomic_xchg(&rdev->ih.lock, 1))
6379 rptr = rdev->ih.rptr;
6380 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
6382 /* Order reading of wptr vs. reading of IH ring data */
6385 /* display interrupts */
6388 while (rptr != wptr) {
6389 /* wptr/rptr are in bytes! */
6390 ring_index = rptr / 4;
6391 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
6392 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
6393 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
6396 case 1: /* D1 vblank/vline */
6398 case 0: /* D1 vblank */
6399 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
6400 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6402 if (rdev->irq.crtc_vblank_int[0]) {
6403 drm_handle_vblank(rdev->ddev, 0);
6404 rdev->pm.vblank_sync = true;
6405 wake_up(&rdev->irq.vblank_queue);
6407 if (atomic_read(&rdev->irq.pflip[0]))
6408 radeon_crtc_handle_vblank(rdev, 0);
6409 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
6410 DRM_DEBUG("IH: D1 vblank\n");
6413 case 1: /* D1 vline */
6414 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
6415 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6417 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
6418 DRM_DEBUG("IH: D1 vline\n");
6422 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6426 case 2: /* D2 vblank/vline */
6428 case 0: /* D2 vblank */
6429 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
6430 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6432 if (rdev->irq.crtc_vblank_int[1]) {
6433 drm_handle_vblank(rdev->ddev, 1);
6434 rdev->pm.vblank_sync = true;
6435 wake_up(&rdev->irq.vblank_queue);
6437 if (atomic_read(&rdev->irq.pflip[1]))
6438 radeon_crtc_handle_vblank(rdev, 1);
6439 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
6440 DRM_DEBUG("IH: D2 vblank\n");
6443 case 1: /* D2 vline */
6444 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
6445 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6447 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
6448 DRM_DEBUG("IH: D2 vline\n");
6452 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6456 case 3: /* D3 vblank/vline */
6458 case 0: /* D3 vblank */
6459 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
6460 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6462 if (rdev->irq.crtc_vblank_int[2]) {
6463 drm_handle_vblank(rdev->ddev, 2);
6464 rdev->pm.vblank_sync = true;
6465 wake_up(&rdev->irq.vblank_queue);
6467 if (atomic_read(&rdev->irq.pflip[2]))
6468 radeon_crtc_handle_vblank(rdev, 2);
6469 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
6470 DRM_DEBUG("IH: D3 vblank\n");
6473 case 1: /* D3 vline */
6474 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
6475 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6477 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
6478 DRM_DEBUG("IH: D3 vline\n");
6482 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6486 case 4: /* D4 vblank/vline */
6488 case 0: /* D4 vblank */
6489 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
6490 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6492 if (rdev->irq.crtc_vblank_int[3]) {
6493 drm_handle_vblank(rdev->ddev, 3);
6494 rdev->pm.vblank_sync = true;
6495 wake_up(&rdev->irq.vblank_queue);
6497 if (atomic_read(&rdev->irq.pflip[3]))
6498 radeon_crtc_handle_vblank(rdev, 3);
6499 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
6500 DRM_DEBUG("IH: D4 vblank\n");
6503 case 1: /* D4 vline */
6504 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
6505 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6507 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
6508 DRM_DEBUG("IH: D4 vline\n");
6512 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6516 case 5: /* D5 vblank/vline */
6518 case 0: /* D5 vblank */
6519 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
6520 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6522 if (rdev->irq.crtc_vblank_int[4]) {
6523 drm_handle_vblank(rdev->ddev, 4);
6524 rdev->pm.vblank_sync = true;
6525 wake_up(&rdev->irq.vblank_queue);
6527 if (atomic_read(&rdev->irq.pflip[4]))
6528 radeon_crtc_handle_vblank(rdev, 4);
6529 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
6530 DRM_DEBUG("IH: D5 vblank\n");
6533 case 1: /* D5 vline */
6534 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
6535 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6537 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
6538 DRM_DEBUG("IH: D5 vline\n");
6542 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6546 case 6: /* D6 vblank/vline */
6548 case 0: /* D6 vblank */
6549 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
6550 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6552 if (rdev->irq.crtc_vblank_int[5]) {
6553 drm_handle_vblank(rdev->ddev, 5);
6554 rdev->pm.vblank_sync = true;
6555 wake_up(&rdev->irq.vblank_queue);
6557 if (atomic_read(&rdev->irq.pflip[5]))
6558 radeon_crtc_handle_vblank(rdev, 5);
6559 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
6560 DRM_DEBUG("IH: D6 vblank\n");
6563 case 1: /* D6 vline */
6564 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
6565 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6567 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
6568 DRM_DEBUG("IH: D6 vline\n");
6572 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6576 case 8: /* D1 page flip */
6577 case 10: /* D2 page flip */
6578 case 12: /* D3 page flip */
6579 case 14: /* D4 page flip */
6580 case 16: /* D5 page flip */
6581 case 18: /* D6 page flip */
6582 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6583 if (radeon_use_pflipirq > 0)
6584 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6586 case 42: /* HPD hotplug */
6589 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
6590 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6592 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
6593 queue_hotplug = true;
6594 DRM_DEBUG("IH: HPD1\n");
6598 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
6599 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6601 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
6602 queue_hotplug = true;
6603 DRM_DEBUG("IH: HPD2\n");
6607 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
6608 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6610 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
6611 queue_hotplug = true;
6612 DRM_DEBUG("IH: HPD3\n");
6616 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
6617 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6619 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
6620 queue_hotplug = true;
6621 DRM_DEBUG("IH: HPD4\n");
6625 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
6626 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6628 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
6629 queue_hotplug = true;
6630 DRM_DEBUG("IH: HPD5\n");
6634 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
6635 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6637 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
6638 queue_hotplug = true;
6639 DRM_DEBUG("IH: HPD6\n");
6643 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
6644 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6646 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
6648 DRM_DEBUG("IH: HPD_RX 1\n");
6652 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
6653 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6655 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
6657 DRM_DEBUG("IH: HPD_RX 2\n");
6661 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
6662 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6664 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
6666 DRM_DEBUG("IH: HPD_RX 3\n");
6670 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
6671 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6673 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
6675 DRM_DEBUG("IH: HPD_RX 4\n");
6679 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
6680 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6682 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
6684 DRM_DEBUG("IH: HPD_RX 5\n");
6688 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
6689 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6691 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
6693 DRM_DEBUG("IH: HPD_RX 6\n");
6697 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6702 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
6703 WREG32(SRBM_INT_ACK, 0x1);
6706 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
6707 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
6711 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6712 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
6713 /* reset addr and status */
6714 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6715 if (addr == 0x0 && status == 0x0)
6717 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
6718 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
6720 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
6722 si_vm_decode_fault(rdev, status, addr);
6724 case 176: /* RINGID0 CP_INT */
6725 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6727 case 177: /* RINGID1 CP_INT */
6728 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6730 case 178: /* RINGID2 CP_INT */
6731 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6733 case 181: /* CP EOP event */
6734 DRM_DEBUG("IH: CP EOP\n");
6737 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6740 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6743 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6747 case 224: /* DMA trap event */
6748 DRM_DEBUG("IH: DMA trap\n");
6749 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
6751 case 230: /* thermal low to high */
6752 DRM_DEBUG("IH: thermal low to high\n");
6753 rdev->pm.dpm.thermal.high_to_low = false;
6754 queue_thermal = true;
6756 case 231: /* thermal high to low */
6757 DRM_DEBUG("IH: thermal high to low\n");
6758 rdev->pm.dpm.thermal.high_to_low = true;
6759 queue_thermal = true;
6761 case 233: /* GUI IDLE */
6762 DRM_DEBUG("IH: GUI idle\n");
6764 case 244: /* DMA trap event */
6765 DRM_DEBUG("IH: DMA1 trap\n");
6766 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6769 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6773 /* wptr/rptr are in bytes! */
6775 rptr &= rdev->ih.ptr_mask;
6776 WREG32(IH_RB_RPTR, rptr);
6779 schedule_work(&rdev->dp_work);
6781 schedule_delayed_work(&rdev->hotplug_work, 0);
6782 if (queue_thermal && rdev->pm.dpm_enabled)
6783 schedule_work(&rdev->pm.dpm.thermal.work);
6784 rdev->ih.rptr = rptr;
6785 atomic_set(&rdev->ih.lock, 0);
6787 /* make sure wptr hasn't changed while processing */
6788 wptr = si_get_ih_wptr(rdev);
6796 * startup/shutdown callbacks
6798 static int si_startup(struct radeon_device *rdev)
6800 struct radeon_ring *ring;
6803 /* enable pcie gen2/3 link */
6804 si_pcie_gen3_enable(rdev);
6806 si_program_aspm(rdev);
6808 /* scratch needs to be initialized before MC */
6809 r = r600_vram_scratch_init(rdev);
6813 si_mc_program(rdev);
6815 if (!rdev->pm.dpm_enabled) {
6816 r = si_mc_load_microcode(rdev);
6818 DRM_ERROR("Failed to load MC firmware!\n");
6823 r = si_pcie_gart_enable(rdev);
6828 /* allocate rlc buffers */
6829 if (rdev->family == CHIP_VERDE) {
6830 rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
6831 rdev->rlc.reg_list_size =
6832 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
6834 rdev->rlc.cs_data = si_cs_data;
6835 r = sumo_rlc_init(rdev);
6837 DRM_ERROR("Failed to init rlc BOs!\n");
6841 /* allocate wb buffer */
6842 r = radeon_wb_init(rdev);
6846 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
6848 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6852 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6854 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6858 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6860 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6864 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
6866 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
6870 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6872 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
6876 if (rdev->has_uvd) {
6877 r = uvd_v2_2_resume(rdev);
6879 r = radeon_fence_driver_start_ring(rdev,
6880 R600_RING_TYPE_UVD_INDEX);
6882 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
6885 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
6888 r = radeon_vce_resume(rdev);
6890 r = vce_v1_0_resume(rdev);
6892 r = radeon_fence_driver_start_ring(rdev,
6893 TN_RING_TYPE_VCE1_INDEX);
6895 r = radeon_fence_driver_start_ring(rdev,
6896 TN_RING_TYPE_VCE2_INDEX);
6899 dev_err(rdev->dev, "VCE init error (%d).\n", r);
6900 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
6901 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
6905 if (!rdev->irq.installed) {
6906 r = radeon_irq_kms_init(rdev);
6911 r = si_irq_init(rdev);
6913 DRM_ERROR("radeon: IH init failed (%d).\n", r);
6914 radeon_irq_kms_fini(rdev);
6919 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6920 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
6925 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6926 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
6931 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6932 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
6937 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6938 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
6939 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6943 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6944 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
6945 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6949 r = si_cp_load_microcode(rdev);
6952 r = si_cp_resume(rdev);
6956 r = cayman_dma_resume(rdev);
6960 if (rdev->has_uvd) {
6961 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6962 if (ring->ring_size) {
6963 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
6966 r = uvd_v1_0_init(rdev);
6968 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
6974 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
6975 if (ring->ring_size)
6976 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
6979 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
6980 if (ring->ring_size)
6981 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
6985 r = vce_v1_0_init(rdev);
6986 else if (r != -ENOENT)
6987 DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
6989 r = radeon_ib_pool_init(rdev);
6991 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
6995 r = radeon_vm_manager_init(rdev);
6997 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
7001 r = radeon_audio_init(rdev);
7008 int si_resume(struct radeon_device *rdev)
7012 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
7013 * posting will perform necessary task to bring back GPU into good
7017 atom_asic_init(rdev->mode_info.atom_context);
7019 /* init golden registers */
7020 si_init_golden_registers(rdev);
7022 if (rdev->pm.pm_method == PM_METHOD_DPM)
7023 radeon_pm_resume(rdev);
7025 rdev->accel_working = true;
7026 r = si_startup(rdev);
7028 DRM_ERROR("si startup failed on resume\n");
7029 rdev->accel_working = false;
7037 int si_suspend(struct radeon_device *rdev)
7039 radeon_pm_suspend(rdev);
7040 radeon_audio_fini(rdev);
7041 radeon_vm_manager_fini(rdev);
7042 si_cp_enable(rdev, false);
7043 cayman_dma_stop(rdev);
7044 if (rdev->has_uvd) {
7045 uvd_v1_0_fini(rdev);
7046 radeon_uvd_suspend(rdev);
7047 radeon_vce_suspend(rdev);
7051 si_irq_suspend(rdev);
7052 radeon_wb_disable(rdev);
7053 si_pcie_gart_disable(rdev);
7057 /* Plan is to move initialization in that function and use
7058 * helper function so that radeon_device_init pretty much
7059 * do nothing more than calling asic specific function. This
7060 * should also allow to remove a bunch of callback function
7063 int si_init(struct radeon_device *rdev)
7065 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7069 if (!radeon_get_bios(rdev)) {
7070 if (ASIC_IS_AVIVO(rdev))
7073 /* Must be an ATOMBIOS */
7074 if (!rdev->is_atom_bios) {
7075 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
7078 r = radeon_atombios_init(rdev);
7082 /* Post card if necessary */
7083 if (!radeon_card_posted(rdev)) {
7085 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
7088 DRM_INFO("GPU not posted. posting now...\n");
7089 atom_asic_init(rdev->mode_info.atom_context);
7091 /* init golden registers */
7092 si_init_golden_registers(rdev);
7093 /* Initialize scratch registers */
7094 si_scratch_init(rdev);
7095 /* Initialize surface registers */
7096 radeon_surface_init(rdev);
7097 /* Initialize clocks */
7098 radeon_get_clock_info(rdev->ddev);
7101 r = radeon_fence_driver_init(rdev);
7105 /* initialize memory controller */
7106 r = si_mc_init(rdev);
7109 /* Memory manager */
7110 r = radeon_bo_init(rdev);
7114 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
7115 !rdev->rlc_fw || !rdev->mc_fw) {
7116 r = si_init_microcode(rdev);
7118 DRM_ERROR("Failed to load firmware!\n");
7123 /* Initialize power management */
7124 radeon_pm_init(rdev);
7126 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7127 ring->ring_obj = NULL;
7128 r600_ring_init(rdev, ring, 1024 * 1024);
7130 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7131 ring->ring_obj = NULL;
7132 r600_ring_init(rdev, ring, 1024 * 1024);
7134 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7135 ring->ring_obj = NULL;
7136 r600_ring_init(rdev, ring, 1024 * 1024);
7138 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7139 ring->ring_obj = NULL;
7140 r600_ring_init(rdev, ring, 64 * 1024);
7142 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7143 ring->ring_obj = NULL;
7144 r600_ring_init(rdev, ring, 64 * 1024);
7146 if (rdev->has_uvd) {
7147 r = radeon_uvd_init(rdev);
7149 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
7150 ring->ring_obj = NULL;
7151 r600_ring_init(rdev, ring, 4096);
7155 r = radeon_vce_init(rdev);
7157 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
7158 ring->ring_obj = NULL;
7159 r600_ring_init(rdev, ring, 4096);
7161 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
7162 ring->ring_obj = NULL;
7163 r600_ring_init(rdev, ring, 4096);
7166 rdev->ih.ring_obj = NULL;
7167 r600_ih_ring_init(rdev, 64 * 1024);
7169 r = r600_pcie_gart_init(rdev);
7173 rdev->accel_working = true;
7174 r = si_startup(rdev);
7176 dev_err(rdev->dev, "disabling GPU acceleration\n");
7178 cayman_dma_fini(rdev);
7180 sumo_rlc_fini(rdev);
7181 radeon_wb_fini(rdev);
7182 radeon_ib_pool_fini(rdev);
7183 radeon_vm_manager_fini(rdev);
7184 radeon_irq_kms_fini(rdev);
7185 si_pcie_gart_fini(rdev);
7186 rdev->accel_working = false;
7189 /* Don't start up if the MC ucode is missing.
7190 * The default clocks and voltages before the MC ucode
7191 * is loaded are not suffient for advanced operations.
7194 DRM_ERROR("radeon: MC ucode required for NI+.\n");
7201 void si_fini(struct radeon_device *rdev)
7203 radeon_pm_fini(rdev);
7205 cayman_dma_fini(rdev);
7209 sumo_rlc_fini(rdev);
7210 radeon_wb_fini(rdev);
7211 radeon_vm_manager_fini(rdev);
7212 radeon_ib_pool_fini(rdev);
7213 radeon_irq_kms_fini(rdev);
7214 if (rdev->has_uvd) {
7215 uvd_v1_0_fini(rdev);
7216 radeon_uvd_fini(rdev);
7217 radeon_vce_fini(rdev);
7219 si_pcie_gart_fini(rdev);
7220 r600_vram_scratch_fini(rdev);
7221 radeon_gem_fini(rdev);
7222 radeon_fence_driver_fini(rdev);
7223 radeon_bo_fini(rdev);
7224 radeon_atombios_fini(rdev);
7230 * si_get_gpu_clock_counter - return GPU clock counter snapshot
7232 * @rdev: radeon_device pointer
7234 * Fetches a GPU clock counter snapshot (SI).
7235 * Returns the 64 bit clock counter snapshot.
7237 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
7241 mutex_lock(&rdev->gpu_clock_mutex);
7242 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
7243 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
7244 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
7245 mutex_unlock(&rdev->gpu_clock_mutex);
7249 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
7251 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
7254 /* bypass vclk and dclk with bclk */
7255 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7256 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
7257 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7259 /* put PLL in bypass mode */
7260 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
7262 if (!vclk || !dclk) {
7263 /* keep the Bypass mode */
7267 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
7268 16384, 0x03FFFFFF, 0, 128, 5,
7269 &fb_div, &vclk_div, &dclk_div);
7273 /* set RESET_ANTI_MUX to 0 */
7274 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7276 /* set VCO_MODE to 1 */
7277 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
7279 /* disable sleep mode */
7280 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
7282 /* deassert UPLL_RESET */
7283 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7287 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7291 /* assert UPLL_RESET again */
7292 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
7294 /* disable spread spectrum. */
7295 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7297 /* set feedback divider */
7298 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
7300 /* set ref divider to 0 */
7301 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
7303 if (fb_div < 307200)
7304 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
7306 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
7308 /* set PDIV_A and PDIV_B */
7309 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7310 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
7311 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
7313 /* give the PLL some time to settle */
7316 /* deassert PLL_RESET */
7317 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7321 /* switch from bypass mode to normal mode */
7322 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
7324 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7328 /* switch VCLK and DCLK selection */
7329 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7330 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
7331 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7338 static void si_pcie_gen3_enable(struct radeon_device *rdev)
7340 struct pci_dev *root = rdev->pdev->bus->self;
7341 int bridge_pos, gpu_pos;
7342 u32 speed_cntl, mask, current_data_rate;
7346 if (pci_is_root_bus(rdev->pdev->bus))
7349 if (radeon_pcie_gen2 == 0)
7352 if (rdev->flags & RADEON_IS_IGP)
7355 if (!(rdev->flags & RADEON_IS_PCIE))
7358 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
7362 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
7365 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7366 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
7367 LC_CURRENT_DATA_RATE_SHIFT;
7368 if (mask & DRM_PCIE_SPEED_80) {
7369 if (current_data_rate == 2) {
7370 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
7373 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
7374 } else if (mask & DRM_PCIE_SPEED_50) {
7375 if (current_data_rate == 1) {
7376 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
7379 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
7382 bridge_pos = pci_pcie_cap(root);
7386 gpu_pos = pci_pcie_cap(rdev->pdev);
7390 if (mask & DRM_PCIE_SPEED_80) {
7391 /* re-try equalization if gen3 is not already enabled */
7392 if (current_data_rate != 2) {
7393 u16 bridge_cfg, gpu_cfg;
7394 u16 bridge_cfg2, gpu_cfg2;
7395 u32 max_lw, current_lw, tmp;
7397 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7398 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7400 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7401 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7403 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7404 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7406 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7407 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
7408 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
7410 if (current_lw < max_lw) {
7411 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7412 if (tmp & LC_RENEGOTIATION_SUPPORT) {
7413 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
7414 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
7415 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
7416 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
7420 for (i = 0; i < 10; i++) {
7422 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7423 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
7426 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7427 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7429 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7430 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7432 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7433 tmp |= LC_SET_QUIESCE;
7434 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7436 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7438 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7443 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7444 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7445 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7446 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7448 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7449 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7450 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7451 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7454 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7455 tmp16 &= ~((1 << 4) | (7 << 9));
7456 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
7457 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7459 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7460 tmp16 &= ~((1 << 4) | (7 << 9));
7461 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
7462 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7464 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7465 tmp &= ~LC_SET_QUIESCE;
7466 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7471 /* set the link speed */
7472 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
7473 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
7474 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7476 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7478 if (mask & DRM_PCIE_SPEED_80)
7479 tmp16 |= 3; /* gen3 */
7480 else if (mask & DRM_PCIE_SPEED_50)
7481 tmp16 |= 2; /* gen2 */
7483 tmp16 |= 1; /* gen1 */
7484 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7486 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7487 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
7488 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7490 for (i = 0; i < rdev->usec_timeout; i++) {
7491 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7492 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
7498 static void si_program_aspm(struct radeon_device *rdev)
7501 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
7502 bool disable_clkreq = false;
7504 if (radeon_aspm == 0)
7507 if (!(rdev->flags & RADEON_IS_PCIE))
7510 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7511 data &= ~LC_XMIT_N_FTS_MASK;
7512 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
7514 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
7516 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
7517 data |= LC_GO_TO_RECOVERY;
7519 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
7521 orig = data = RREG32_PCIE(PCIE_P_CNTL);
7522 data |= P_IGNORE_EDB_ERR;
7524 WREG32_PCIE(PCIE_P_CNTL, data);
7526 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7527 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
7528 data |= LC_PMI_TO_L1_DIS;
7530 data |= LC_L0S_INACTIVITY(7);
7533 data |= LC_L1_INACTIVITY(7);
7534 data &= ~LC_PMI_TO_L1_DIS;
7536 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7538 if (!disable_plloff_in_l1) {
7539 bool clk_req_support;
7541 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7542 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7543 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7545 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7547 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7548 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7549 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7551 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7553 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7554 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7555 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7557 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7559 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7560 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7561 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7563 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7565 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {
7566 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7567 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7569 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7571 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7572 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7574 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7576 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);
7577 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7579 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);
7581 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);
7582 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7584 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);
7586 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7587 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7589 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7591 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7592 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7594 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7596 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);
7597 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7599 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);
7601 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);
7602 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7604 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);
7606 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7607 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
7608 data |= LC_DYN_LANES_PWR_STATE(3);
7610 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
7612 orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);
7613 data &= ~LS2_EXIT_TIME_MASK;
7614 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7615 data |= LS2_EXIT_TIME(5);
7617 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
7619 orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);
7620 data &= ~LS2_EXIT_TIME_MASK;
7621 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7622 data |= LS2_EXIT_TIME(5);
7624 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
7626 if (!disable_clkreq &&
7627 !pci_is_root_bus(rdev->pdev->bus)) {
7628 struct pci_dev *root = rdev->pdev->bus->self;
7631 clk_req_support = false;
7632 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
7633 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
7634 clk_req_support = true;
7636 clk_req_support = false;
7639 if (clk_req_support) {
7640 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
7641 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
7643 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
7645 orig = data = RREG32(THM_CLK_CNTL);
7646 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
7647 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
7649 WREG32(THM_CLK_CNTL, data);
7651 orig = data = RREG32(MISC_CLK_CNTL);
7652 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
7653 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
7655 WREG32(MISC_CLK_CNTL, data);
7657 orig = data = RREG32(CG_CLKPIN_CNTL);
7658 data &= ~BCLK_AS_XCLK;
7660 WREG32(CG_CLKPIN_CNTL, data);
7662 orig = data = RREG32(CG_CLKPIN_CNTL_2);
7663 data &= ~FORCE_BIF_REFCLK_EN;
7665 WREG32(CG_CLKPIN_CNTL_2, data);
7667 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
7668 data &= ~MPLL_CLKOUT_SEL_MASK;
7669 data |= MPLL_CLKOUT_SEL(4);
7671 WREG32(MPLL_BYPASSCLK_SEL, data);
7673 orig = data = RREG32(SPLL_CNTL_MODE);
7674 data &= ~SPLL_REFCLK_SEL_MASK;
7676 WREG32(SPLL_CNTL_MODE, data);
7681 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7684 orig = data = RREG32_PCIE(PCIE_CNTL2);
7685 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
7687 WREG32_PCIE(PCIE_CNTL2, data);
7690 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7691 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
7692 data = RREG32_PCIE(PCIE_LC_STATUS1);
7693 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
7694 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7695 data &= ~LC_L0S_INACTIVITY_MASK;
7697 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7703 int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev)
7707 /* make sure VCEPLL_CTLREQ is deasserted */
7708 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7712 /* assert UPLL_CTLREQ */
7713 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
7715 /* wait for CTLACK and CTLACK2 to get asserted */
7716 for (i = 0; i < 100; ++i) {
7717 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
7718 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
7723 /* deassert UPLL_CTLREQ */
7724 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7727 DRM_ERROR("Timeout setting UVD clocks!\n");
7734 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
7736 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
7739 /* bypass evclk and ecclk with bclk */
7740 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7741 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1),
7742 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
7744 /* put PLL in bypass mode */
7745 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
7746 ~VCEPLL_BYPASS_EN_MASK);
7748 if (!evclk || !ecclk) {
7749 /* keep the Bypass mode, put PLL to sleep */
7750 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7751 ~VCEPLL_SLEEP_MASK);
7755 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000,
7756 16384, 0x03FFFFFF, 0, 128, 5,
7757 &fb_div, &evclk_div, &ecclk_div);
7761 /* set RESET_ANTI_MUX to 0 */
7762 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7764 /* set VCO_MODE to 1 */
7765 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
7766 ~VCEPLL_VCO_MODE_MASK);
7768 /* toggle VCEPLL_SLEEP to 1 then back to 0 */
7769 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7770 ~VCEPLL_SLEEP_MASK);
7771 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
7773 /* deassert VCEPLL_RESET */
7774 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7778 r = si_vce_send_vcepll_ctlreq(rdev);
7782 /* assert VCEPLL_RESET again */
7783 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
7785 /* disable spread spectrum. */
7786 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7788 /* set feedback divider */
7789 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
7791 /* set ref divider to 0 */
7792 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
7794 /* set PDIV_A and PDIV_B */
7795 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7796 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div),
7797 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK));
7799 /* give the PLL some time to settle */
7802 /* deassert PLL_RESET */
7803 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7807 /* switch from bypass mode to normal mode */
7808 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
7810 r = si_vce_send_vcepll_ctlreq(rdev);
7814 /* switch VCLK and DCLK selection */
7815 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7816 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16),
7817 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
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