2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "radeon_ucode.h"
40 /* 1 second timeout */
41 #define UVD_IDLE_TIMEOUT_MS 1000
44 #define FIRMWARE_R600 "/*(DEBLOBBED)*/"
45 #define FIRMWARE_RS780 "/*(DEBLOBBED)*/"
46 #define FIRMWARE_RV770 "/*(DEBLOBBED)*/"
47 #define FIRMWARE_RV710 "/*(DEBLOBBED)*/"
48 #define FIRMWARE_CYPRESS "/*(DEBLOBBED)*/"
49 #define FIRMWARE_SUMO "/*(DEBLOBBED)*/"
50 #define FIRMWARE_TAHITI "/*(DEBLOBBED)*/"
51 #define FIRMWARE_BONAIRE_LEGACY "/*(DEBLOBBED)*/"
52 #define FIRMWARE_BONAIRE "/*(DEBLOBBED)*/"
56 static void radeon_uvd_idle_work_handler(struct work_struct *work);
58 int radeon_uvd_init(struct radeon_device *rdev)
60 unsigned long bo_size;
61 const char *fw_name = NULL, *legacy_fw_name = NULL;
64 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
66 switch (rdev->family) {
72 legacy_fw_name = FIRMWARE_R600;
77 legacy_fw_name = FIRMWARE_RS780;
81 legacy_fw_name = FIRMWARE_RV770;
87 legacy_fw_name = FIRMWARE_RV710;
95 legacy_fw_name = FIRMWARE_CYPRESS;
105 legacy_fw_name = FIRMWARE_SUMO;
113 legacy_fw_name = FIRMWARE_TAHITI;
121 legacy_fw_name = FIRMWARE_BONAIRE_LEGACY;
122 fw_name = FIRMWARE_BONAIRE;
129 rdev->uvd.fw_header_present = false;
130 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES;
132 /* Let's try to load the newer firmware first */
133 r = reject_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
135 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
138 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data;
139 unsigned version_major, version_minor, family_id;
141 r = radeon_ucode_validate(rdev->uvd_fw);
145 rdev->uvd.fw_header_present = true;
147 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
148 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
149 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
150 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
151 version_major, version_minor, family_id);
154 * Limit the number of UVD handles depending on
155 * microcode major and minor versions.
157 if ((version_major >= 0x01) && (version_minor >= 0x37))
158 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES;
163 * In case there is only legacy firmware, or we encounter an error
164 * while loading the new firmware, we fall back to loading the legacy
168 r = reject_firmware(&rdev->uvd_fw, legacy_fw_name, rdev->dev);
170 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
176 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
177 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
178 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles;
179 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
180 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
181 NULL, &rdev->uvd.vcpu_bo);
183 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
187 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
189 radeon_bo_unref(&rdev->uvd.vcpu_bo);
190 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
194 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
195 &rdev->uvd.gpu_addr);
197 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
198 radeon_bo_unref(&rdev->uvd.vcpu_bo);
199 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
203 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
205 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
209 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
211 for (i = 0; i < rdev->uvd.max_handles; ++i) {
212 atomic_set(&rdev->uvd.handles[i], 0);
213 rdev->uvd.filp[i] = NULL;
214 rdev->uvd.img_size[i] = 0;
220 void radeon_uvd_fini(struct radeon_device *rdev)
224 if (rdev->uvd.vcpu_bo == NULL)
227 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
229 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
230 radeon_bo_unpin(rdev->uvd.vcpu_bo);
231 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
234 radeon_bo_unref(&rdev->uvd.vcpu_bo);
236 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
238 release_firmware(rdev->uvd_fw);
241 int radeon_uvd_suspend(struct radeon_device *rdev)
245 if (rdev->uvd.vcpu_bo == NULL)
248 for (i = 0; i < rdev->uvd.max_handles; ++i) {
249 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
251 struct radeon_fence *fence;
253 radeon_uvd_note_usage(rdev);
255 r = radeon_uvd_get_destroy_msg(rdev,
256 R600_RING_TYPE_UVD_INDEX, handle, &fence);
258 DRM_ERROR("Error destroying UVD (%d)!\n", r);
262 radeon_fence_wait(fence, false);
263 radeon_fence_unref(&fence);
265 rdev->uvd.filp[i] = NULL;
266 atomic_set(&rdev->uvd.handles[i], 0);
273 int radeon_uvd_resume(struct radeon_device *rdev)
278 if (rdev->uvd.vcpu_bo == NULL)
281 memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
283 size = radeon_bo_size(rdev->uvd.vcpu_bo);
284 size -= rdev->uvd_fw->size;
286 ptr = rdev->uvd.cpu_addr;
287 ptr += rdev->uvd_fw->size;
289 memset_io((void __iomem *)ptr, 0, size);
294 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
295 uint32_t allowed_domains)
299 for (i = 0; i < rbo->placement.num_placement; ++i) {
300 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
301 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
304 /* If it must be in VRAM it must be in the first segment as well */
305 if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
308 /* abort if we already have more than one placement */
309 if (rbo->placement.num_placement > 1)
312 /* add another 256MB segment */
313 rbo->placements[1] = rbo->placements[0];
314 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
315 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
316 rbo->placement.num_placement++;
317 rbo->placement.num_busy_placement++;
320 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
323 for (i = 0; i < rdev->uvd.max_handles; ++i) {
324 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
325 if (handle != 0 && rdev->uvd.filp[i] == filp) {
326 struct radeon_fence *fence;
328 radeon_uvd_note_usage(rdev);
330 r = radeon_uvd_get_destroy_msg(rdev,
331 R600_RING_TYPE_UVD_INDEX, handle, &fence);
333 DRM_ERROR("Error destroying UVD (%d)!\n", r);
337 radeon_fence_wait(fence, false);
338 radeon_fence_unref(&fence);
340 rdev->uvd.filp[i] = NULL;
341 atomic_set(&rdev->uvd.handles[i], 0);
346 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
348 unsigned stream_type = msg[4];
349 unsigned width = msg[6];
350 unsigned height = msg[7];
351 unsigned dpb_size = msg[9];
352 unsigned pitch = msg[28];
354 unsigned width_in_mb = width / 16;
355 unsigned height_in_mb = ALIGN(height / 16, 2);
357 unsigned image_size, tmp, min_dpb_size;
359 image_size = width * height;
360 image_size += image_size / 2;
361 image_size = ALIGN(image_size, 1024);
363 switch (stream_type) {
366 /* reference picture buffer */
367 min_dpb_size = image_size * 17;
369 /* macroblock context buffer */
370 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
372 /* IT surface buffer */
373 min_dpb_size += width_in_mb * height_in_mb * 32;
378 /* reference picture buffer */
379 min_dpb_size = image_size * 3;
382 min_dpb_size += width_in_mb * height_in_mb * 128;
384 /* IT surface buffer */
385 min_dpb_size += width_in_mb * 64;
387 /* DB surface buffer */
388 min_dpb_size += width_in_mb * 128;
391 tmp = max(width_in_mb, height_in_mb);
392 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
397 /* reference picture buffer */
398 min_dpb_size = image_size * 3;
403 /* reference picture buffer */
404 min_dpb_size = image_size * 3;
407 min_dpb_size += width_in_mb * height_in_mb * 64;
409 /* IT surface buffer */
410 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
414 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
419 DRM_ERROR("Invalid UVD decoding target pitch!\n");
423 if (dpb_size < min_dpb_size) {
424 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
425 dpb_size, min_dpb_size);
429 buf_sizes[0x1] = dpb_size;
430 buf_sizes[0x2] = image_size;
434 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
435 unsigned stream_type)
437 switch (stream_type) {
440 /* always supported */
445 /* only since UVD 3 */
446 if (p->rdev->family >= CHIP_PALM)
451 DRM_ERROR("UVD codec not supported by hardware %d!\n",
457 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
458 unsigned offset, unsigned buf_sizes[])
460 int32_t *msg, msg_type, handle;
461 unsigned img_size = 0;
468 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
472 f = dma_resv_get_excl(bo->tbo.base.resv);
474 r = radeon_fence_wait((struct radeon_fence *)f, false);
476 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
481 r = radeon_bo_kmap(bo, &ptr);
483 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
493 DRM_ERROR("Invalid UVD handle!\n");
499 /* it's a create msg, calc image size (width * height) */
500 img_size = msg[7] * msg[8];
502 r = radeon_uvd_validate_codec(p, msg[4]);
503 radeon_bo_kunmap(bo);
507 /* try to alloc a new handle */
508 for (i = 0; i < p->rdev->uvd.max_handles; ++i) {
509 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
510 DRM_ERROR("Handle 0x%x already in use!\n", handle);
514 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
515 p->rdev->uvd.filp[i] = p->filp;
516 p->rdev->uvd.img_size[i] = img_size;
521 DRM_ERROR("No more free UVD handles!\n");
525 /* it's a decode msg, validate codec and calc buffer sizes */
526 r = radeon_uvd_validate_codec(p, msg[4]);
528 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
529 radeon_bo_kunmap(bo);
533 /* validate the handle */
534 for (i = 0; i < p->rdev->uvd.max_handles; ++i) {
535 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
536 if (p->rdev->uvd.filp[i] != p->filp) {
537 DRM_ERROR("UVD handle collision detected!\n");
544 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
548 /* it's a destroy msg, free the handle */
549 for (i = 0; i < p->rdev->uvd.max_handles; ++i)
550 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
551 radeon_bo_kunmap(bo);
556 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
564 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
565 int data0, int data1,
566 unsigned buf_sizes[], bool *has_msg_cmd)
568 struct radeon_cs_chunk *relocs_chunk;
569 struct radeon_bo_list *reloc;
570 unsigned idx, cmd, offset;
574 relocs_chunk = p->chunk_relocs;
575 offset = radeon_get_ib_value(p, data0);
576 idx = radeon_get_ib_value(p, data1);
577 if (idx >= relocs_chunk->length_dw) {
578 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
579 idx, relocs_chunk->length_dw);
583 reloc = &p->relocs[(idx / 4)];
584 start = reloc->gpu_offset;
585 end = start + radeon_bo_size(reloc->robj);
588 p->ib.ptr[data0] = start & 0xFFFFFFFF;
589 p->ib.ptr[data1] = start >> 32;
591 cmd = radeon_get_ib_value(p, p->idx) >> 1;
595 DRM_ERROR("invalid reloc offset %X!\n", offset);
598 if ((end - start) < buf_sizes[cmd]) {
599 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
600 (unsigned)(end - start), buf_sizes[cmd]);
604 } else if (cmd != 0x100) {
605 DRM_ERROR("invalid UVD command %X!\n", cmd);
609 if ((start >> 28) != ((end - 1) >> 28)) {
610 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
615 /* TODO: is this still necessary on NI+ ? */
616 if ((cmd == 0 || cmd == 0x3) &&
617 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
618 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
625 DRM_ERROR("More than one message in a UVD-IB!\n");
629 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
632 } else if (!*has_msg_cmd) {
633 DRM_ERROR("Message needed before other commands are send!\n");
640 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
641 struct radeon_cs_packet *pkt,
642 int *data0, int *data1,
643 unsigned buf_sizes[],
649 for (i = 0; i <= pkt->count; ++i) {
650 switch (pkt->reg + i*4) {
651 case UVD_GPCOM_VCPU_DATA0:
654 case UVD_GPCOM_VCPU_DATA1:
657 case UVD_GPCOM_VCPU_CMD:
658 r = radeon_uvd_cs_reloc(p, *data0, *data1,
659 buf_sizes, has_msg_cmd);
663 case UVD_ENGINE_CNTL:
667 DRM_ERROR("Invalid reg 0x%X!\n",
676 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
678 struct radeon_cs_packet pkt;
679 int r, data0 = 0, data1 = 0;
681 /* does the IB has a msg command */
682 bool has_msg_cmd = false;
684 /* minimum buffer sizes */
685 unsigned buf_sizes[] = {
687 [0x00000001] = 32 * 1024 * 1024,
688 [0x00000002] = 2048 * 1152 * 3,
692 if (p->chunk_ib->length_dw % 16) {
693 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
694 p->chunk_ib->length_dw);
698 if (p->chunk_relocs == NULL) {
699 DRM_ERROR("No relocation chunk !\n");
705 r = radeon_cs_packet_parse(p, &pkt, p->idx);
709 case RADEON_PACKET_TYPE0:
710 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
711 buf_sizes, &has_msg_cmd);
715 case RADEON_PACKET_TYPE2:
716 p->idx += pkt.count + 2;
719 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
722 } while (p->idx < p->chunk_ib->length_dw);
725 DRM_ERROR("UVD-IBs need a msg command!\n");
732 static int radeon_uvd_send_msg(struct radeon_device *rdev,
733 int ring, uint64_t addr,
734 struct radeon_fence **fence)
739 r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
743 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
745 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
746 ib.ptr[3] = addr >> 32;
747 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
749 for (i = 6; i < 16; i += 2) {
750 ib.ptr[i] = PACKET0(UVD_NO_OP, 0);
755 r = radeon_ib_schedule(rdev, &ib, NULL, false);
758 *fence = radeon_fence_ref(ib.fence);
760 radeon_ib_free(rdev, &ib);
765 * multiple fence commands without any stream commands in between can
766 * crash the vcpu so just try to emmit a dummy create/destroy msg to
769 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
770 uint32_t handle, struct radeon_fence **fence)
772 /* we use the last page of the vcpu bo for the UVD message */
773 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
774 RADEON_GPU_PAGE_SIZE;
776 uint32_t *msg = rdev->uvd.cpu_addr + offs;
777 uint64_t addr = rdev->uvd.gpu_addr + offs;
781 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
785 /* stitch together an UVD create msg */
786 msg[0] = cpu_to_le32(0x00000de4);
787 msg[1] = cpu_to_le32(0x00000000);
788 msg[2] = cpu_to_le32(handle);
789 msg[3] = cpu_to_le32(0x00000000);
790 msg[4] = cpu_to_le32(0x00000000);
791 msg[5] = cpu_to_le32(0x00000000);
792 msg[6] = cpu_to_le32(0x00000000);
793 msg[7] = cpu_to_le32(0x00000780);
794 msg[8] = cpu_to_le32(0x00000440);
795 msg[9] = cpu_to_le32(0x00000000);
796 msg[10] = cpu_to_le32(0x01b37000);
797 for (i = 11; i < 1024; ++i)
798 msg[i] = cpu_to_le32(0x0);
800 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
801 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
805 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
806 uint32_t handle, struct radeon_fence **fence)
808 /* we use the last page of the vcpu bo for the UVD message */
809 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
810 RADEON_GPU_PAGE_SIZE;
812 uint32_t *msg = rdev->uvd.cpu_addr + offs;
813 uint64_t addr = rdev->uvd.gpu_addr + offs;
817 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
821 /* stitch together an UVD destroy msg */
822 msg[0] = cpu_to_le32(0x00000de4);
823 msg[1] = cpu_to_le32(0x00000002);
824 msg[2] = cpu_to_le32(handle);
825 msg[3] = cpu_to_le32(0x00000000);
826 for (i = 4; i < 1024; ++i)
827 msg[i] = cpu_to_le32(0x0);
829 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
830 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
835 * radeon_uvd_count_handles - count number of open streams
837 * @rdev: radeon_device pointer
838 * @sd: number of SD streams
839 * @hd: number of HD streams
841 * Count the number of open SD/HD streams as a hint for power mangement
843 static void radeon_uvd_count_handles(struct radeon_device *rdev,
844 unsigned *sd, unsigned *hd)
851 for (i = 0; i < rdev->uvd.max_handles; ++i) {
852 if (!atomic_read(&rdev->uvd.handles[i]))
855 if (rdev->uvd.img_size[i] >= 720*576)
862 static void radeon_uvd_idle_work_handler(struct work_struct *work)
864 struct radeon_device *rdev =
865 container_of(work, struct radeon_device, uvd.idle_work.work);
867 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
868 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
869 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
871 radeon_dpm_enable_uvd(rdev, false);
873 radeon_set_uvd_clocks(rdev, 0, 0);
876 schedule_delayed_work(&rdev->uvd.idle_work,
877 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
881 void radeon_uvd_note_usage(struct radeon_device *rdev)
883 bool streams_changed = false;
884 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
885 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
886 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
888 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
889 unsigned hd = 0, sd = 0;
890 radeon_uvd_count_handles(rdev, &sd, &hd);
891 if ((rdev->pm.dpm.sd != sd) ||
892 (rdev->pm.dpm.hd != hd)) {
893 rdev->pm.dpm.sd = sd;
894 rdev->pm.dpm.hd = hd;
895 /* disable this for now */
896 /*streams_changed = true;*/
900 if (set_clocks || streams_changed) {
901 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
902 radeon_dpm_enable_uvd(rdev, true);
904 radeon_set_uvd_clocks(rdev, 53300, 40000);
909 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
910 unsigned target_freq,
914 unsigned post_div = vco_freq / target_freq;
916 /* adjust to post divider minimum value */
917 if (post_div < pd_min)
920 /* we alway need a frequency less than or equal the target */
921 if ((vco_freq / post_div) > target_freq)
924 /* post dividers above a certain value must be even */
925 if (post_div > pd_even && post_div % 2)
932 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
934 * @rdev: radeon_device pointer
937 * @vco_min: minimum VCO frequency
938 * @vco_max: maximum VCO frequency
939 * @fb_factor: factor to multiply vco freq with
940 * @fb_mask: limit and bitmask for feedback divider
941 * @pd_min: post divider minimum
942 * @pd_max: post divider maximum
943 * @pd_even: post divider must be even above this value
944 * @optimal_fb_div: resulting feedback divider
945 * @optimal_vclk_div: resulting vclk post divider
946 * @optimal_dclk_div: resulting dclk post divider
948 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
949 * Returns zero on success -EINVAL on error.
951 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
952 unsigned vclk, unsigned dclk,
953 unsigned vco_min, unsigned vco_max,
954 unsigned fb_factor, unsigned fb_mask,
955 unsigned pd_min, unsigned pd_max,
957 unsigned *optimal_fb_div,
958 unsigned *optimal_vclk_div,
959 unsigned *optimal_dclk_div)
961 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
963 /* start off with something large */
964 unsigned optimal_score = ~0;
966 /* loop through vco from low to high */
967 vco_min = max(max(vco_min, vclk), dclk);
968 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
970 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
971 unsigned vclk_div, dclk_div, score;
973 do_div(fb_div, ref_freq);
975 /* fb div out of range ? */
976 if (fb_div > fb_mask)
977 break; /* it can oly get worse */
981 /* calc vclk divider with current vco freq */
982 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
984 if (vclk_div > pd_max)
985 break; /* vco is too big, it has to stop */
987 /* calc dclk divider with current vco freq */
988 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
990 if (dclk_div > pd_max)
991 break; /* vco is too big, it has to stop */
993 /* calc score with current vco freq */
994 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
996 /* determine if this vco setting is better than current optimal settings */
997 if (score < optimal_score) {
998 *optimal_fb_div = fb_div;
999 *optimal_vclk_div = vclk_div;
1000 *optimal_dclk_div = dclk_div;
1001 optimal_score = score;
1002 if (optimal_score == 0)
1003 break; /* it can't get better than this */
1007 /* did we found a valid setup ? */
1008 if (optimal_score == ~0)
1014 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1015 unsigned cg_upll_func_cntl)
1019 /* make sure UPLL_CTLREQ is deasserted */
1020 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1024 /* assert UPLL_CTLREQ */
1025 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
1027 /* wait for CTLACK and CTLACK2 to get asserted */
1028 for (i = 0; i < 100; ++i) {
1029 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
1030 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
1035 /* deassert UPLL_CTLREQ */
1036 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1039 DRM_ERROR("Timeout setting UVD clocks!\n");