drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "radeon_ucode.h"
  38 #include "r600d.h"
  39
  40 /* 1 second timeout */
  41 #define UVD_IDLE_TIMEOUT_MS     1000
  42
  43 /* Firmware Names */
  44 #define FIRMWARE_R600           "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_RS780          "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_RV770          "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_RV710          "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_CYPRESS        "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_SUMO           "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_TAHITI         "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_BONAIRE_LEGACY "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  53
  54 /*(DEBLOBBED)*/
  55
  56 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  57
  58 int radeon_uvd_init(struct radeon_device *rdev)
  59 {
  60         unsigned long bo_size;
  61         const char *fw_name = NULL, *legacy_fw_name = NULL;
  62         int i, r;
  63
  64         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  65
  66         switch (rdev->family) {
  67         case CHIP_RV610:
  68         case CHIP_RV630:
  69         case CHIP_RV670:
  70         case CHIP_RV620:
  71         case CHIP_RV635:
  72                 legacy_fw_name = FIRMWARE_R600;
  73                 break;
  74
  75         case CHIP_RS780:
  76         case CHIP_RS880:
  77                 legacy_fw_name = FIRMWARE_RS780;
  78                 break;
  79
  80         case CHIP_RV770:
  81                 legacy_fw_name = FIRMWARE_RV770;
  82                 break;
  83
  84         case CHIP_RV710:
  85         case CHIP_RV730:
  86         case CHIP_RV740:
  87                 legacy_fw_name = FIRMWARE_RV710;
  88                 break;
  89
  90         case CHIP_CYPRESS:
  91         case CHIP_HEMLOCK:
  92         case CHIP_JUNIPER:
  93         case CHIP_REDWOOD:
  94         case CHIP_CEDAR:
  95                 legacy_fw_name = FIRMWARE_CYPRESS;
  96                 break;
  97
  98         case CHIP_SUMO:
  99         case CHIP_SUMO2:
 100         case CHIP_PALM:
 101         case CHIP_CAYMAN:
 102         case CHIP_BARTS:
 103         case CHIP_TURKS:
 104         case CHIP_CAICOS:
 105                 legacy_fw_name = FIRMWARE_SUMO;
 106                 break;
 107
 108         case CHIP_TAHITI:
 109         case CHIP_VERDE:
 110         case CHIP_PITCAIRN:
 111         case CHIP_ARUBA:
 112         case CHIP_OLAND:
 113                 legacy_fw_name = FIRMWARE_TAHITI;
 114                 break;
 115
 116         case CHIP_BONAIRE:
 117         case CHIP_KABINI:
 118         case CHIP_KAVERI:
 119         case CHIP_HAWAII:
 120         case CHIP_MULLINS:
 121                 legacy_fw_name = FIRMWARE_BONAIRE_LEGACY;
 122                 fw_name = FIRMWARE_BONAIRE;
 123                 break;
 124
 125         default:
 126                 return -EINVAL;
 127         }
 128
 129         rdev->uvd.fw_header_present = false;
 130         rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES;
 131         if (fw_name) {
 132                 /* Let's try to load the newer firmware first */
 133                 r = reject_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 134                 if (r) {
 135                         dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 136                                 fw_name);
 137                 } else {
 138                         struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data;
 139                         unsigned version_major, version_minor, family_id;
 140
 141                         r = radeon_ucode_validate(rdev->uvd_fw);
 142                         if (r)
 143                                 return r;
 144
 145                         rdev->uvd.fw_header_present = true;
 146
 147                         family_id = (__force u32)(hdr->ucode_version) & 0xff;
 148                         version_major = (le32_to_cpu((__force __le32)(hdr->ucode_version))
 149                                                          >> 24) & 0xff;
 150                         version_minor = (le32_to_cpu((__force __le32)(hdr->ucode_version))
 151                                                          >> 8) & 0xff;
 152                         DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",
 153                                  version_major, version_minor, family_id);
 154
 155                         /*
 156                          * Limit the number of UVD handles depending on
 157                          * microcode major and minor versions.
 158                          */
 159                         if ((version_major >= 0x01) && (version_minor >= 0x37))
 160                                 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES;
 161                 }
 162         }
 163
 164         /*
 165          * In case there is only legacy firmware, or we encounter an error
 166          * while loading the new firmware, we fall back to loading the legacy
 167          * firmware now.
 168          */
 169         if (!fw_name || r) {
 170                 r = reject_firmware(&rdev->uvd_fw, legacy_fw_name, rdev->dev);
 171                 if (r) {
 172                         dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 173                                 legacy_fw_name);
 174                         return r;
 175                 }
 176         }
 177
 178         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 179                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
 180                   RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles;
 181         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 182                              RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 183                              NULL, &rdev->uvd.vcpu_bo);
 184         if (r) {
 185                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 186                 return r;
 187         }
 188
 189         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 190         if (r) {
 191                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 192                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 193                 return r;
 194         }
 195
 196         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 197                           &rdev->uvd.gpu_addr);
 198         if (r) {
 199                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 200                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 201                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 202                 return r;
 203         }
 204
 205         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 206         if (r) {
 207                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 208                 return r;
 209         }
 210
 211         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 212
 213         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 214                 atomic_set(&rdev->uvd.handles[i], 0);
 215                 rdev->uvd.filp[i] = NULL;
 216                 rdev->uvd.img_size[i] = 0;
 217         }
 218
 219         return 0;
 220 }
 221
 222 void radeon_uvd_fini(struct radeon_device *rdev)
 223 {
 224         int r;
 225
 226         if (rdev->uvd.vcpu_bo == NULL)
 227                 return;
 228
 229         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 230         if (!r) {
 231                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 232                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 233                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 234         }
 235
 236         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 237
 238         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
 239
 240         release_firmware(rdev->uvd_fw);
 241 }
 242
 243 int radeon_uvd_suspend(struct radeon_device *rdev)
 244 {
 245         int i, r;
 246
 247         if (rdev->uvd.vcpu_bo == NULL)
 248                 return 0;
 249
 250         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 251                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 252                 if (handle != 0) {
 253                         struct radeon_fence *fence;
 254
 255                         radeon_uvd_note_usage(rdev);
 256
 257                         r = radeon_uvd_get_destroy_msg(rdev,
 258                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 259                         if (r) {
 260                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 261                                 continue;
 262                         }
 263
 264                         radeon_fence_wait(fence, false);
 265                         radeon_fence_unref(&fence);
 266
 267                         rdev->uvd.filp[i] = NULL;
 268                         atomic_set(&rdev->uvd.handles[i], 0);
 269                 }
 270         }
 271
 272         return 0;
 273 }
 274
 275 int radeon_uvd_resume(struct radeon_device *rdev)
 276 {
 277         unsigned size;
 278         void *ptr;
 279
 280         if (rdev->uvd.vcpu_bo == NULL)
 281                 return -EINVAL;
 282
 283         memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 284
 285         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 286         size -= rdev->uvd_fw->size;
 287
 288         ptr = rdev->uvd.cpu_addr;
 289         ptr += rdev->uvd_fw->size;
 290
 291         memset_io((void __iomem *)ptr, 0, size);
 292
 293         return 0;
 294 }
 295
 296 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
 297                                        uint32_t allowed_domains)
 298 {
 299         int i;
 300
 301         for (i = 0; i < rbo->placement.num_placement; ++i) {
 302                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 303                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 304         }
 305
 306         /* If it must be in VRAM it must be in the first segment as well */
 307         if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
 308                 return;
 309
 310         /* abort if we already have more than one placement */
 311         if (rbo->placement.num_placement > 1)
 312                 return;
 313
 314         /* add another 256MB segment */
 315         rbo->placements[1] = rbo->placements[0];
 316         rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
 317         rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
 318         rbo->placement.num_placement++;
 319         rbo->placement.num_busy_placement++;
 320 }
 321
 322 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 323 {
 324         int i, r;
 325         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 326                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 327                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 328                         struct radeon_fence *fence;
 329
 330                         radeon_uvd_note_usage(rdev);
 331
 332                         r = radeon_uvd_get_destroy_msg(rdev,
 333                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 334                         if (r) {
 335                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 336                                 continue;
 337                         }
 338
 339                         radeon_fence_wait(fence, false);
 340                         radeon_fence_unref(&fence);
 341
 342                         rdev->uvd.filp[i] = NULL;
 343                         atomic_set(&rdev->uvd.handles[i], 0);
 344                 }
 345         }
 346 }
 347
 348 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 349 {
 350         unsigned stream_type = msg[4];
 351         unsigned width = msg[6];
 352         unsigned height = msg[7];
 353         unsigned dpb_size = msg[9];
 354         unsigned pitch = msg[28];
 355
 356         unsigned width_in_mb = width / 16;
 357         unsigned height_in_mb = ALIGN(height / 16, 2);
 358
 359         unsigned image_size, tmp, min_dpb_size;
 360
 361         image_size = width * height;
 362         image_size += image_size / 2;
 363         image_size = ALIGN(image_size, 1024);
 364
 365         switch (stream_type) {
 366         case 0: /* H264 */
 367
 368                 /* reference picture buffer */
 369                 min_dpb_size = image_size * 17;
 370
 371                 /* macroblock context buffer */
 372                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 373
 374                 /* IT surface buffer */
 375                 min_dpb_size += width_in_mb * height_in_mb * 32;
 376                 break;
 377
 378         case 1: /* VC1 */
 379
 380                 /* reference picture buffer */
 381                 min_dpb_size = image_size * 3;
 382
 383                 /* CONTEXT_BUFFER */
 384                 min_dpb_size += width_in_mb * height_in_mb * 128;
 385
 386                 /* IT surface buffer */
 387                 min_dpb_size += width_in_mb * 64;
 388
 389                 /* DB surface buffer */
 390                 min_dpb_size += width_in_mb * 128;
 391
 392                 /* BP */
 393                 tmp = max(width_in_mb, height_in_mb);
 394                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 395                 break;
 396
 397         case 3: /* MPEG2 */
 398
 399                 /* reference picture buffer */
 400                 min_dpb_size = image_size * 3;
 401                 break;
 402
 403         case 4: /* MPEG4 */
 404
 405                 /* reference picture buffer */
 406                 min_dpb_size = image_size * 3;
 407
 408                 /* CM */
 409                 min_dpb_size += width_in_mb * height_in_mb * 64;
 410
 411                 /* IT surface buffer */
 412                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 413                 break;
 414
 415         default:
 416                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 417                 return -EINVAL;
 418         }
 419
 420         if (width > pitch) {
 421                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 422                 return -EINVAL;
 423         }
 424
 425         if (dpb_size < min_dpb_size) {
 426                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 427                           dpb_size, min_dpb_size);
 428                 return -EINVAL;
 429         }
 430
 431         buf_sizes[0x1] = dpb_size;
 432         buf_sizes[0x2] = image_size;
 433         return 0;
 434 }
 435
 436 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
 437                                      unsigned stream_type)
 438 {
 439         switch (stream_type) {
 440         case 0: /* H264 */
 441         case 1: /* VC1 */
 442                 /* always supported */
 443                 return 0;
 444
 445         case 3: /* MPEG2 */
 446         case 4: /* MPEG4 */
 447                 /* only since UVD 3 */
 448                 if (p->rdev->family >= CHIP_PALM)
 449                         return 0;
 450
 451                 fallthrough;
 452         default:
 453                 DRM_ERROR("UVD codec not supported by hardware %d!\n",
 454                           stream_type);
 455                 return -EINVAL;
 456         }
 457 }
 458
 459 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 460                              unsigned offset, unsigned buf_sizes[])
 461 {
 462         int32_t *msg, msg_type, handle;
 463         unsigned img_size = 0;
 464         void *ptr;
 465         int i, r;
 466
 467         if (offset & 0x3F) {
 468                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 469                 return -EINVAL;
 470         }
 471
 472         r = radeon_bo_kmap(bo, &ptr);
 473         if (r) {
 474                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 475                 return r;
 476         }
 477
 478         msg = ptr + offset;
 479
 480         msg_type = msg[1];
 481         handle = msg[2];
 482
 483         if (handle == 0) {
 484                 radeon_bo_kunmap(bo);
 485                 DRM_ERROR("Invalid UVD handle!\n");
 486                 return -EINVAL;
 487         }
 488
 489         switch (msg_type) {
 490         case 0:
 491                 /* it's a create msg, calc image size (width * height) */
 492                 img_size = msg[7] * msg[8];
 493
 494                 r = radeon_uvd_validate_codec(p, msg[4]);
 495                 radeon_bo_kunmap(bo);
 496                 if (r)
 497                         return r;
 498
 499                 /* try to alloc a new handle */
 500                 for (i = 0; i < p->rdev->uvd.max_handles; ++i) {
 501                         if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
 502                                 DRM_ERROR("Handle 0x%x already in use!\n", handle);
 503                                 return -EINVAL;
 504                         }
 505
 506                         if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 507                                 p->rdev->uvd.filp[i] = p->filp;
 508                                 p->rdev->uvd.img_size[i] = img_size;
 509                                 return 0;
 510                         }
 511                 }
 512
 513                 DRM_ERROR("No more free UVD handles!\n");
 514                 return -EINVAL;
 515
 516         case 1:
 517                 /* it's a decode msg, validate codec and calc buffer sizes */
 518                 r = radeon_uvd_validate_codec(p, msg[4]);
 519                 if (!r)
 520                         r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 521                 radeon_bo_kunmap(bo);
 522                 if (r)
 523                         return r;
 524
 525                 /* validate the handle */
 526                 for (i = 0; i < p->rdev->uvd.max_handles; ++i) {
 527                         if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
 528                                 if (p->rdev->uvd.filp[i] != p->filp) {
 529                                         DRM_ERROR("UVD handle collision detected!\n");
 530                                         return -EINVAL;
 531                                 }
 532                                 return 0;
 533                         }
 534                 }
 535
 536                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 537                 return -ENOENT;
 538
 539         case 2:
 540                 /* it's a destroy msg, free the handle */
 541                 for (i = 0; i < p->rdev->uvd.max_handles; ++i)
 542                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 543                 radeon_bo_kunmap(bo);
 544                 return 0;
 545
 546         default:
 547                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 548         }
 549
 550         radeon_bo_kunmap(bo);
 551         return -EINVAL;
 552 }
 553
 554 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 555                                int data0, int data1,
 556                                unsigned buf_sizes[], bool *has_msg_cmd)
 557 {
 558         struct radeon_cs_chunk *relocs_chunk;
 559         struct radeon_bo_list *reloc;
 560         unsigned idx, cmd, offset;
 561         uint64_t start, end;
 562         int r;
 563
 564         relocs_chunk = p->chunk_relocs;
 565         offset = radeon_get_ib_value(p, data0);
 566         idx = radeon_get_ib_value(p, data1);
 567         if (idx >= relocs_chunk->length_dw) {
 568                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 569                           idx, relocs_chunk->length_dw);
 570                 return -EINVAL;
 571         }
 572
 573         reloc = &p->relocs[(idx / 4)];
 574         start = reloc->gpu_offset;
 575         end = start + radeon_bo_size(reloc->robj);
 576         start += offset;
 577
 578         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 579         p->ib.ptr[data1] = start >> 32;
 580
 581         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 582
 583         if (cmd < 0x4) {
 584                 if (end <= start) {
 585                         DRM_ERROR("invalid reloc offset %X!\n", offset);
 586                         return -EINVAL;
 587                 }
 588                 if ((end - start) < buf_sizes[cmd]) {
 589                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 590                                   (unsigned)(end - start), buf_sizes[cmd]);
 591                         return -EINVAL;
 592                 }
 593
 594         } else if (cmd != 0x100) {
 595                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 596                 return -EINVAL;
 597         }
 598
 599         if ((start >> 28) != ((end - 1) >> 28)) {
 600                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 601                           start, end);
 602                 return -EINVAL;
 603         }
 604
 605         /* TODO: is this still necessary on NI+ ? */
 606         if ((cmd == 0 || cmd == 0x3) &&
 607             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 608                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 609                           start, end);
 610                 return -EINVAL;
 611         }
 612
 613         if (cmd == 0) {
 614                 if (*has_msg_cmd) {
 615                         DRM_ERROR("More than one message in a UVD-IB!\n");
 616                         return -EINVAL;
 617                 }
 618                 *has_msg_cmd = true;
 619                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 620                 if (r)
 621                         return r;
 622         } else if (!*has_msg_cmd) {
 623                 DRM_ERROR("Message needed before other commands are send!\n");
 624                 return -EINVAL;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 631                              struct radeon_cs_packet *pkt,
 632                              int *data0, int *data1,
 633                              unsigned buf_sizes[],
 634                              bool *has_msg_cmd)
 635 {
 636         int i, r;
 637
 638         p->idx++;
 639         for (i = 0; i <= pkt->count; ++i) {
 640                 switch (pkt->reg + i*4) {
 641                 case UVD_GPCOM_VCPU_DATA0:
 642                         *data0 = p->idx;
 643                         break;
 644                 case UVD_GPCOM_VCPU_DATA1:
 645                         *data1 = p->idx;
 646                         break;
 647                 case UVD_GPCOM_VCPU_CMD:
 648                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 649                                                 buf_sizes, has_msg_cmd);
 650                         if (r)
 651                                 return r;
 652                         break;
 653                 case UVD_ENGINE_CNTL:
 654                 case UVD_NO_OP:
 655                         break;
 656                 default:
 657                         DRM_ERROR("Invalid reg 0x%X!\n",
 658                                   pkt->reg + i*4);
 659                         return -EINVAL;
 660                 }
 661                 p->idx++;
 662         }
 663         return 0;
 664 }
 665
 666 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 667 {
 668         struct radeon_cs_packet pkt;
 669         int r, data0 = 0, data1 = 0;
 670
 671         /* does the IB has a msg command */
 672         bool has_msg_cmd = false;
 673
 674         /* minimum buffer sizes */
 675         unsigned buf_sizes[] = {
 676                 [0x00000000]    =       2048,
 677                 [0x00000001]    =       32 * 1024 * 1024,
 678                 [0x00000002]    =       2048 * 1152 * 3,
 679                 [0x00000003]    =       2048,
 680         };
 681
 682         if (p->chunk_ib->length_dw % 16) {
 683                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 684                           p->chunk_ib->length_dw);
 685                 return -EINVAL;
 686         }
 687
 688         if (p->chunk_relocs == NULL) {
 689                 DRM_ERROR("No relocation chunk !\n");
 690                 return -EINVAL;
 691         }
 692
 693
 694         do {
 695                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 696                 if (r)
 697                         return r;
 698                 switch (pkt.type) {
 699                 case RADEON_PACKET_TYPE0:
 700                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 701                                               buf_sizes, &has_msg_cmd);
 702                         if (r)
 703                                 return r;
 704                         break;
 705                 case RADEON_PACKET_TYPE2:
 706                         p->idx += pkt.count + 2;
 707                         break;
 708                 default:
 709                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 710                         return -EINVAL;
 711                 }
 712         } while (p->idx < p->chunk_ib->length_dw);
 713
 714         if (!has_msg_cmd) {
 715                 DRM_ERROR("UVD-IBs need a msg command!\n");
 716                 return -EINVAL;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 723                                int ring, uint64_t addr,
 724                                struct radeon_fence **fence)
 725 {
 726         struct radeon_ib ib;
 727         int i, r;
 728
 729         r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
 730         if (r)
 731                 return r;
 732
 733         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 734         ib.ptr[1] = addr;
 735         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 736         ib.ptr[3] = addr >> 32;
 737         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 738         ib.ptr[5] = 0;
 739         for (i = 6; i < 16; i += 2) {
 740                 ib.ptr[i] = PACKET0(UVD_NO_OP, 0);
 741                 ib.ptr[i+1] = 0;
 742         }
 743         ib.length_dw = 16;
 744
 745         r = radeon_ib_schedule(rdev, &ib, NULL, false);
 746
 747         if (fence)
 748                 *fence = radeon_fence_ref(ib.fence);
 749
 750         radeon_ib_free(rdev, &ib);
 751         return r;
 752 }
 753
 754 /*
 755  * multiple fence commands without any stream commands in between can
 756  * crash the vcpu so just try to emmit a dummy create/destroy msg to
 757  * avoid this
 758  */
 759 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 760                               uint32_t handle, struct radeon_fence **fence)
 761 {
 762         /* we use the last page of the vcpu bo for the UVD message */
 763         uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
 764                 RADEON_GPU_PAGE_SIZE;
 765
 766         uint32_t __iomem *msg = (void __iomem *)(rdev->uvd.cpu_addr + offs);
 767         uint64_t addr = rdev->uvd.gpu_addr + offs;
 768
 769         int r, i;
 770
 771         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
 772         if (r)
 773                 return r;
 774
 775         /* stitch together an UVD create msg */
 776         writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
 777         writel(0x0, (void __iomem *)&msg[1]);
 778         writel((__force u32)cpu_to_le32(handle), &msg[2]);
 779         writel(0x0, &msg[3]);
 780         writel(0x0, &msg[4]);
 781         writel(0x0, &msg[5]);
 782         writel(0x0, &msg[6]);
 783         writel((__force u32)cpu_to_le32(0x00000780), &msg[7]);
 784         writel((__force u32)cpu_to_le32(0x00000440), &msg[8]);
 785         writel(0x0, &msg[9]);
 786         writel((__force u32)cpu_to_le32(0x01b37000), &msg[10]);
 787         for (i = 11; i < 1024; ++i)
 788                 writel(0x0, &msg[i]);
 789
 790         r = radeon_uvd_send_msg(rdev, ring, addr, fence);
 791         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 792         return r;
 793 }
 794
 795 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 796                                uint32_t handle, struct radeon_fence **fence)
 797 {
 798         /* we use the last page of the vcpu bo for the UVD message */
 799         uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
 800                 RADEON_GPU_PAGE_SIZE;
 801
 802         uint32_t __iomem *msg = (void __iomem *)(rdev->uvd.cpu_addr + offs);
 803         uint64_t addr = rdev->uvd.gpu_addr + offs;
 804
 805         int r, i;
 806
 807         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
 808         if (r)
 809                 return r;
 810
 811         /* stitch together an UVD destroy msg */
 812         writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
 813         writel((__force u32)cpu_to_le32(0x00000002), &msg[1]);
 814         writel((__force u32)cpu_to_le32(handle), &msg[2]);
 815         writel(0x0, &msg[3]);
 816         for (i = 4; i < 1024; ++i)
 817                 writel(0x0, &msg[i]);
 818
 819         r = radeon_uvd_send_msg(rdev, ring, addr, fence);
 820         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 821         return r;
 822 }
 823
 824 /**
 825  * radeon_uvd_count_handles - count number of open streams
 826  *
 827  * @rdev: radeon_device pointer
 828  * @sd: number of SD streams
 829  * @hd: number of HD streams
 830  *
 831  * Count the number of open SD/HD streams as a hint for power mangement
 832  */
 833 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 834                                      unsigned *sd, unsigned *hd)
 835 {
 836         unsigned i;
 837
 838         *sd = 0;
 839         *hd = 0;
 840
 841         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 842                 if (!atomic_read(&rdev->uvd.handles[i]))
 843                         continue;
 844
 845                 if (rdev->uvd.img_size[i] >= 720*576)
 846                         ++(*hd);
 847                 else
 848                         ++(*sd);
 849         }
 850 }
 851
 852 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 853 {
 854         struct radeon_device *rdev =
 855                 container_of(work, struct radeon_device, uvd.idle_work.work);
 856
 857         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 858                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 859                         radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
 860                                                  &rdev->pm.dpm.hd);
 861                         radeon_dpm_enable_uvd(rdev, false);
 862                 } else {
 863                         radeon_set_uvd_clocks(rdev, 0, 0);
 864                 }
 865         } else {
 866                 schedule_delayed_work(&rdev->uvd.idle_work,
 867                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 868         }
 869 }
 870
 871 void radeon_uvd_note_usage(struct radeon_device *rdev)
 872 {
 873         bool streams_changed = false;
 874         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 875         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 876                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 877
 878         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 879                 unsigned hd = 0, sd = 0;
 880                 radeon_uvd_count_handles(rdev, &sd, &hd);
 881                 if ((rdev->pm.dpm.sd != sd) ||
 882                     (rdev->pm.dpm.hd != hd)) {
 883                         rdev->pm.dpm.sd = sd;
 884                         rdev->pm.dpm.hd = hd;
 885                         /* disable this for now */
 886                         /*streams_changed = true;*/
 887                 }
 888         }
 889
 890         if (set_clocks || streams_changed) {
 891                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 892                         radeon_dpm_enable_uvd(rdev, true);
 893                 } else {
 894                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 895                 }
 896         }
 897 }
 898
 899 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 900                                               unsigned target_freq,
 901                                               unsigned pd_min,
 902                                               unsigned pd_even)
 903 {
 904         unsigned post_div = vco_freq / target_freq;
 905
 906         /* adjust to post divider minimum value */
 907         if (post_div < pd_min)
 908                 post_div = pd_min;
 909
 910         /* we alway need a frequency less than or equal the target */
 911         if ((vco_freq / post_div) > target_freq)
 912                 post_div += 1;
 913
 914         /* post dividers above a certain value must be even */
 915         if (post_div > pd_even && post_div % 2)
 916                 post_div += 1;
 917
 918         return post_div;
 919 }
 920
 921 /**
 922  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 923  *
 924  * @rdev: radeon_device pointer
 925  * @vclk: wanted VCLK
 926  * @dclk: wanted DCLK
 927  * @vco_min: minimum VCO frequency
 928  * @vco_max: maximum VCO frequency
 929  * @fb_factor: factor to multiply vco freq with
 930  * @fb_mask: limit and bitmask for feedback divider
 931  * @pd_min: post divider minimum
 932  * @pd_max: post divider maximum
 933  * @pd_even: post divider must be even above this value
 934  * @optimal_fb_div: resulting feedback divider
 935  * @optimal_vclk_div: resulting vclk post divider
 936  * @optimal_dclk_div: resulting dclk post divider
 937  *
 938  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 939  * Returns zero on success -EINVAL on error.
 940  */
 941 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 942                                   unsigned vclk, unsigned dclk,
 943                                   unsigned vco_min, unsigned vco_max,
 944                                   unsigned fb_factor, unsigned fb_mask,
 945                                   unsigned pd_min, unsigned pd_max,
 946                                   unsigned pd_even,
 947                                   unsigned *optimal_fb_div,
 948                                   unsigned *optimal_vclk_div,
 949                                   unsigned *optimal_dclk_div)
 950 {
 951         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 952
 953         /* start off with something large */
 954         unsigned optimal_score = ~0;
 955
 956         /* loop through vco from low to high */
 957         vco_min = max(max(vco_min, vclk), dclk);
 958         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 959
 960                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 961                 unsigned vclk_div, dclk_div, score;
 962
 963                 do_div(fb_div, ref_freq);
 964
 965                 /* fb div out of range ? */
 966                 if (fb_div > fb_mask)
 967                         break; /* it can oly get worse */
 968
 969                 fb_div &= fb_mask;
 970
 971                 /* calc vclk divider with current vco freq */
 972                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 973                                                          pd_min, pd_even);
 974                 if (vclk_div > pd_max)
 975                         break; /* vco is too big, it has to stop */
 976
 977                 /* calc dclk divider with current vco freq */
 978                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 979                                                          pd_min, pd_even);
 980                 if (dclk_div > pd_max)
 981                         break; /* vco is too big, it has to stop */
 982
 983                 /* calc score with current vco freq */
 984                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 985
 986                 /* determine if this vco setting is better than current optimal settings */
 987                 if (score < optimal_score) {
 988                         *optimal_fb_div = fb_div;
 989                         *optimal_vclk_div = vclk_div;
 990                         *optimal_dclk_div = dclk_div;
 991                         optimal_score = score;
 992                         if (optimal_score == 0)
 993                                 break; /* it can't get better than this */
 994                 }
 995         }
 996
 997         /* did we found a valid setup ? */
 998         if (optimal_score == ~0)
 999                 return -EINVAL;
1000
1001         return 0;
1002 }
1003
1004 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1005                                 unsigned cg_upll_func_cntl)
1006 {
1007         unsigned i;
1008
1009         /* make sure UPLL_CTLREQ is deasserted */
1010         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1011
1012         mdelay(10);
1013
1014         /* assert UPLL_CTLREQ */
1015         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
1016
1017         /* wait for CTLACK and CTLACK2 to get asserted */
1018         for (i = 0; i < 100; ++i) {
1019                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
1020                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
1021                         break;
1022                 mdelay(10);
1023         }
1024
1025         /* deassert UPLL_CTLREQ */
1026         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1027
1028         if (i == 100) {
1029                 DRM_ERROR("Timeout setting UVD clocks!\n");
1030                 return -ETIMEDOUT;
1031         }
1032
1033         return 0;
1034 }