drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/pci.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/slab.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_file.h>
  37 #include <drm/drm_ioctl.h>
  38 #include <drm/radeon_drm.h>
  39
  40 #include "radeon.h"
  41 #include "radeon_asic.h"
  42 #include "radeon_drv.h"
  43 #include "radeon_kms.h"
  44
  45 #if defined(CONFIG_VGA_SWITCHEROO)
  46 bool radeon_has_atpx(void);
  47 #else
  48 static inline bool radeon_has_atpx(void) { return false; }
  49 #endif
  50
  51 /**
  52  * radeon_driver_unload_kms - Main unload function for KMS.
  53  *
  54  * @dev: drm dev pointer
  55  *
  56  * This is the main unload function for KMS (all asics).
  57  * It calls radeon_modeset_fini() to tear down the
  58  * displays, and radeon_device_fini() to tear down
  59  * the rest of the device (CP, writeback, etc.).
  60  * Returns 0 on success.
  61  */
  62 void radeon_driver_unload_kms(struct drm_device *dev)
  63 {
  64         struct radeon_device *rdev = dev->dev_private;
  65
  66         if (rdev == NULL)
  67                 return;
  68
  69         if (rdev->rmmio == NULL)
  70                 goto done_free;
  71
  72         if (radeon_is_px(dev)) {
  73                 pm_runtime_get_sync(dev->dev);
  74                 pm_runtime_forbid(dev->dev);
  75         }
  76
  77         radeon_acpi_fini(rdev);
  78
  79         radeon_modeset_fini(rdev);
  80         radeon_device_fini(rdev);
  81
  82         if (rdev->agp)
  83                 arch_phys_wc_del(rdev->agp->agp_mtrr);
  84         kfree(rdev->agp);
  85         rdev->agp = NULL;
  86
  87 done_free:
  88         kfree(rdev);
  89         dev->dev_private = NULL;
  90 }
  91
  92 /**
  93  * radeon_driver_load_kms - Main load function for KMS.
  94  *
  95  * @dev: drm dev pointer
  96  * @flags: device flags
  97  *
  98  * This is the main load function for KMS (all asics).
  99  * It calls radeon_device_init() to set up the non-display
 100  * parts of the chip (asic init, CP, writeback, etc.), and
 101  * radeon_modeset_init() to set up the display parts
 102  * (crtcs, encoders, hotplug detect, etc.).
 103  * Returns 0 on success, error on failure.
 104  */
 105 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
 106 {
 107         struct pci_dev *pdev = to_pci_dev(dev->dev);
 108         struct radeon_device *rdev;
 109         int r, acpi_status;
 110
 111         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
 112         if (rdev == NULL) {
 113                 return -ENOMEM;
 114         }
 115         dev->dev_private = (void *)rdev;
 116
 117 #ifdef __alpha__
 118         rdev->hose = pdev->sysdata;
 119 #endif
 120
 121         if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
 122                 rdev->agp = radeon_agp_head_init(dev);
 123         if (rdev->agp) {
 124                 rdev->agp->agp_mtrr = arch_phys_wc_add(
 125                         rdev->agp->agp_info.aper_base,
 126                         rdev->agp->agp_info.aper_size *
 127                         1024 * 1024);
 128         }
 129
 130         /* update BUS flag */
 131         if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
 132                 flags |= RADEON_IS_AGP;
 133         } else if (pci_is_pcie(pdev)) {
 134                 flags |= RADEON_IS_PCIE;
 135         } else {
 136                 flags |= RADEON_IS_PCI;
 137         }
 138
 139         if ((radeon_runtime_pm != 0) &&
 140             radeon_has_atpx() &&
 141             ((flags & RADEON_IS_IGP) == 0) &&
 142             !pci_is_thunderbolt_attached(pdev))
 143                 flags |= RADEON_IS_PX;
 144
 145         /* radeon_device_init should report only fatal error
 146          * like memory allocation failure or iomapping failure,
 147          * or memory manager initialization failure, it must
 148          * properly initialize the GPU MC controller and permit
 149          * VRAM allocation
 150          */
 151         r = radeon_device_init(rdev, dev, pdev, flags);
 152         if (r) {
 153                 dev_err(dev->dev, "Fatal error during GPU init\n");
 154                 goto out;
 155         }
 156
 157         /* Again modeset_init should fail only on fatal error
 158          * otherwise it should provide enough functionalities
 159          * for shadowfb to run
 160          */
 161         r = radeon_modeset_init(rdev);
 162         if (r)
 163                 dev_err(dev->dev, "Fatal error during modeset init\n");
 164
 165         /* Call ACPI methods: require modeset init
 166          * but failure is not fatal
 167          */
 168         if (!r) {
 169                 acpi_status = radeon_acpi_init(rdev);
 170                 if (acpi_status)
 171                         dev_dbg(dev->dev, "Error during ACPI methods call\n");
 172         }
 173
 174         if (radeon_is_px(dev)) {
 175                 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 176                 pm_runtime_use_autosuspend(dev->dev);
 177                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 178                 pm_runtime_set_active(dev->dev);
 179                 pm_runtime_allow(dev->dev);
 180                 pm_runtime_mark_last_busy(dev->dev);
 181                 pm_runtime_put_autosuspend(dev->dev);
 182         }
 183
 184 out:
 185         if (r)
 186                 radeon_driver_unload_kms(dev);
 187
 188
 189         return r;
 190 }
 191
 192 /**
 193  * radeon_set_filp_rights - Set filp right.
 194  *
 195  * @dev: drm dev pointer
 196  * @owner: drm file
 197  * @applier: drm file
 198  * @value: value
 199  *
 200  * Sets the filp rights for the device (all asics).
 201  */
 202 static void radeon_set_filp_rights(struct drm_device *dev,
 203                                    struct drm_file **owner,
 204                                    struct drm_file *applier,
 205                                    uint32_t *value)
 206 {
 207         struct radeon_device *rdev = dev->dev_private;
 208
 209         mutex_lock(&rdev->gem.mutex);
 210         if (*value == 1) {
 211                 /* wants rights */
 212                 if (!*owner)
 213                         *owner = applier;
 214         } else if (*value == 0) {
 215                 /* revokes rights */
 216                 if (*owner == applier)
 217                         *owner = NULL;
 218         }
 219         *value = *owner == applier ? 1 : 0;
 220         mutex_unlock(&rdev->gem.mutex);
 221 }
 222
 223 /*
 224  * Userspace get information ioctl
 225  */
 226 /**
 227  * radeon_info_ioctl - answer a device specific request.
 228  *
 229  * @dev: drm device pointer
 230  * @data: request object
 231  * @filp: drm filp
 232  *
 233  * This function is used to pass device specific parameters to the userspace
 234  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 235  * etc. (all asics).
 236  * Returns 0 on success, -EINVAL on failure.
 237  */
 238 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 239 {
 240         struct radeon_device *rdev = dev->dev_private;
 241         struct drm_radeon_info *info = data;
 242         struct radeon_mode_info *minfo = &rdev->mode_info;
 243         uint32_t *value, value_tmp, *value_ptr, value_size;
 244         struct ttm_resource_manager *man;
 245         uint64_t value64;
 246         struct drm_crtc *crtc;
 247         int i, found;
 248
 249         value_ptr = (uint32_t *)((unsigned long)info->value);
 250         value = &value_tmp;
 251         value_size = sizeof(uint32_t);
 252
 253         switch (info->request) {
 254         case RADEON_INFO_DEVICE_ID:
 255                 *value = to_pci_dev(dev->dev)->device;
 256                 break;
 257         case RADEON_INFO_NUM_GB_PIPES:
 258                 *value = rdev->num_gb_pipes;
 259                 break;
 260         case RADEON_INFO_NUM_Z_PIPES:
 261                 *value = rdev->num_z_pipes;
 262                 break;
 263         case RADEON_INFO_ACCEL_WORKING:
 264                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 265                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 266                         *value = false;
 267                 else
 268                         *value = rdev->accel_working;
 269                 break;
 270         case RADEON_INFO_CRTC_FROM_ID:
 271                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 272                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 273                         return -EFAULT;
 274                 }
 275                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 276                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 277                         if (crtc && crtc->base.id == *value) {
 278                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 279                                 *value = radeon_crtc->crtc_id;
 280                                 found = 1;
 281                                 break;
 282                         }
 283                 }
 284                 if (!found) {
 285                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 286                         return -EINVAL;
 287                 }
 288                 break;
 289         case RADEON_INFO_ACCEL_WORKING2:
 290                 if (rdev->family == CHIP_HAWAII) {
 291                         if (rdev->accel_working) {
 292                                 if (rdev->new_fw)
 293                                         *value = 3;
 294                                 else
 295                                         *value = 2;
 296                         } else {
 297                                 *value = 0;
 298                         }
 299                 } else {
 300                         *value = rdev->accel_working;
 301                 }
 302                 break;
 303         case RADEON_INFO_TILING_CONFIG:
 304                 if (rdev->family >= CHIP_BONAIRE)
 305                         *value = rdev->config.cik.tile_config;
 306                 else if (rdev->family >= CHIP_TAHITI)
 307                         *value = rdev->config.si.tile_config;
 308                 else if (rdev->family >= CHIP_CAYMAN)
 309                         *value = rdev->config.cayman.tile_config;
 310                 else if (rdev->family >= CHIP_CEDAR)
 311                         *value = rdev->config.evergreen.tile_config;
 312                 else if (rdev->family >= CHIP_RV770)
 313                         *value = rdev->config.rv770.tile_config;
 314                 else if (rdev->family >= CHIP_R600)
 315                         *value = rdev->config.r600.tile_config;
 316                 else {
 317                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 318                         return -EINVAL;
 319                 }
 320                 break;
 321         case RADEON_INFO_WANT_HYPERZ:
 322                 /* The "value" here is both an input and output parameter.
 323                  * If the input value is 1, filp requests hyper-z access.
 324                  * If the input value is 0, filp revokes its hyper-z access.
 325                  *
 326                  * When returning, the value is 1 if filp owns hyper-z access,
 327                  * 0 otherwise. */
 328                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 329                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 330                         return -EFAULT;
 331                 }
 332                 if (*value >= 2) {
 333                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 334                         return -EINVAL;
 335                 }
 336                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 337                 break;
 338         case RADEON_INFO_WANT_CMASK:
 339                 /* The same logic as Hyper-Z. */
 340                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 341                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 342                         return -EFAULT;
 343                 }
 344                 if (*value >= 2) {
 345                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 346                         return -EINVAL;
 347                 }
 348                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 349                 break;
 350         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 351                 /* return clock value in KHz */
 352                 if (rdev->asic->get_xclk)
 353                         *value = radeon_get_xclk(rdev) * 10;
 354                 else
 355                         *value = rdev->clock.spll.reference_freq * 10;
 356                 break;
 357         case RADEON_INFO_NUM_BACKENDS:
 358                 if (rdev->family >= CHIP_BONAIRE)
 359                         *value = rdev->config.cik.max_backends_per_se *
 360                                 rdev->config.cik.max_shader_engines;
 361                 else if (rdev->family >= CHIP_TAHITI)
 362                         *value = rdev->config.si.max_backends_per_se *
 363                                 rdev->config.si.max_shader_engines;
 364                 else if (rdev->family >= CHIP_CAYMAN)
 365                         *value = rdev->config.cayman.max_backends_per_se *
 366                                 rdev->config.cayman.max_shader_engines;
 367                 else if (rdev->family >= CHIP_CEDAR)
 368                         *value = rdev->config.evergreen.max_backends;
 369                 else if (rdev->family >= CHIP_RV770)
 370                         *value = rdev->config.rv770.max_backends;
 371                 else if (rdev->family >= CHIP_R600)
 372                         *value = rdev->config.r600.max_backends;
 373                 else {
 374                         return -EINVAL;
 375                 }
 376                 break;
 377         case RADEON_INFO_NUM_TILE_PIPES:
 378                 if (rdev->family >= CHIP_BONAIRE)
 379                         *value = rdev->config.cik.max_tile_pipes;
 380                 else if (rdev->family >= CHIP_TAHITI)
 381                         *value = rdev->config.si.max_tile_pipes;
 382                 else if (rdev->family >= CHIP_CAYMAN)
 383                         *value = rdev->config.cayman.max_tile_pipes;
 384                 else if (rdev->family >= CHIP_CEDAR)
 385                         *value = rdev->config.evergreen.max_tile_pipes;
 386                 else if (rdev->family >= CHIP_RV770)
 387                         *value = rdev->config.rv770.max_tile_pipes;
 388                 else if (rdev->family >= CHIP_R600)
 389                         *value = rdev->config.r600.max_tile_pipes;
 390                 else {
 391                         return -EINVAL;
 392                 }
 393                 break;
 394         case RADEON_INFO_FUSION_GART_WORKING:
 395                 *value = 1;
 396                 break;
 397         case RADEON_INFO_BACKEND_MAP:
 398                 if (rdev->family >= CHIP_BONAIRE)
 399                         *value = rdev->config.cik.backend_map;
 400                 else if (rdev->family >= CHIP_TAHITI)
 401                         *value = rdev->config.si.backend_map;
 402                 else if (rdev->family >= CHIP_CAYMAN)
 403                         *value = rdev->config.cayman.backend_map;
 404                 else if (rdev->family >= CHIP_CEDAR)
 405                         *value = rdev->config.evergreen.backend_map;
 406                 else if (rdev->family >= CHIP_RV770)
 407                         *value = rdev->config.rv770.backend_map;
 408                 else if (rdev->family >= CHIP_R600)
 409                         *value = rdev->config.r600.backend_map;
 410                 else {
 411                         return -EINVAL;
 412                 }
 413                 break;
 414         case RADEON_INFO_VA_START:
 415                 /* this is where we report if vm is supported or not */
 416                 if (rdev->family < CHIP_CAYMAN)
 417                         return -EINVAL;
 418                 *value = RADEON_VA_RESERVED_SIZE;
 419                 break;
 420         case RADEON_INFO_IB_VM_MAX_SIZE:
 421                 /* this is where we report if vm is supported or not */
 422                 if (rdev->family < CHIP_CAYMAN)
 423                         return -EINVAL;
 424                 *value = RADEON_IB_VM_MAX_SIZE;
 425                 break;
 426         case RADEON_INFO_MAX_PIPES:
 427                 if (rdev->family >= CHIP_BONAIRE)
 428                         *value = rdev->config.cik.max_cu_per_sh;
 429                 else if (rdev->family >= CHIP_TAHITI)
 430                         *value = rdev->config.si.max_cu_per_sh;
 431                 else if (rdev->family >= CHIP_CAYMAN)
 432                         *value = rdev->config.cayman.max_pipes_per_simd;
 433                 else if (rdev->family >= CHIP_CEDAR)
 434                         *value = rdev->config.evergreen.max_pipes;
 435                 else if (rdev->family >= CHIP_RV770)
 436                         *value = rdev->config.rv770.max_pipes;
 437                 else if (rdev->family >= CHIP_R600)
 438                         *value = rdev->config.r600.max_pipes;
 439                 else {
 440                         return -EINVAL;
 441                 }
 442                 break;
 443         case RADEON_INFO_TIMESTAMP:
 444                 if (rdev->family < CHIP_R600) {
 445                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 446                         return -EINVAL;
 447                 }
 448                 value = (uint32_t*)&value64;
 449                 value_size = sizeof(uint64_t);
 450                 value64 = radeon_get_gpu_clock_counter(rdev);
 451                 break;
 452         case RADEON_INFO_MAX_SE:
 453                 if (rdev->family >= CHIP_BONAIRE)
 454                         *value = rdev->config.cik.max_shader_engines;
 455                 else if (rdev->family >= CHIP_TAHITI)
 456                         *value = rdev->config.si.max_shader_engines;
 457                 else if (rdev->family >= CHIP_CAYMAN)
 458                         *value = rdev->config.cayman.max_shader_engines;
 459                 else if (rdev->family >= CHIP_CEDAR)
 460                         *value = rdev->config.evergreen.num_ses;
 461                 else
 462                         *value = 1;
 463                 break;
 464         case RADEON_INFO_MAX_SH_PER_SE:
 465                 if (rdev->family >= CHIP_BONAIRE)
 466                         *value = rdev->config.cik.max_sh_per_se;
 467                 else if (rdev->family >= CHIP_TAHITI)
 468                         *value = rdev->config.si.max_sh_per_se;
 469                 else
 470                         return -EINVAL;
 471                 break;
 472         case RADEON_INFO_FASTFB_WORKING:
 473                 *value = rdev->fastfb_working;
 474                 break;
 475         case RADEON_INFO_RING_WORKING:
 476                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 477                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 478                         return -EFAULT;
 479                 }
 480                 switch (*value) {
 481                 case RADEON_CS_RING_GFX:
 482                 case RADEON_CS_RING_COMPUTE:
 483                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 484                         break;
 485                 case RADEON_CS_RING_DMA:
 486                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 487                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 488                         break;
 489                 case RADEON_CS_RING_UVD:
 490                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 491                         break;
 492                 case RADEON_CS_RING_VCE:
 493                         *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
 494                         break;
 495                 default:
 496                         return -EINVAL;
 497                 }
 498                 break;
 499         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 500                 if (rdev->family >= CHIP_BONAIRE) {
 501                         value = rdev->config.cik.tile_mode_array;
 502                         value_size = sizeof(uint32_t)*32;
 503                 } else if (rdev->family >= CHIP_TAHITI) {
 504                         value = rdev->config.si.tile_mode_array;
 505                         value_size = sizeof(uint32_t)*32;
 506                 } else {
 507                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 508                         return -EINVAL;
 509                 }
 510                 break;
 511         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 512                 if (rdev->family >= CHIP_BONAIRE) {
 513                         value = rdev->config.cik.macrotile_mode_array;
 514                         value_size = sizeof(uint32_t)*16;
 515                 } else {
 516                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 517                         return -EINVAL;
 518                 }
 519                 break;
 520         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 521                 *value = 1;
 522                 break;
 523         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 524                 if (rdev->family >= CHIP_BONAIRE) {
 525                         *value = rdev->config.cik.backend_enable_mask;
 526                 } else if (rdev->family >= CHIP_TAHITI) {
 527                         *value = rdev->config.si.backend_enable_mask;
 528                 } else {
 529                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 530                         return -EINVAL;
 531                 }
 532                 break;
 533         case RADEON_INFO_MAX_SCLK:
 534                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 535                     rdev->pm.dpm_enabled)
 536                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 537                 else
 538                         *value = rdev->pm.default_sclk * 10;
 539                 break;
 540         case RADEON_INFO_VCE_FW_VERSION:
 541                 *value = rdev->vce.fw_version;
 542                 break;
 543         case RADEON_INFO_VCE_FB_VERSION:
 544                 *value = rdev->vce.fb_version;
 545                 break;
 546         case RADEON_INFO_NUM_BYTES_MOVED:
 547                 value = (uint32_t*)&value64;
 548                 value_size = sizeof(uint64_t);
 549                 value64 = atomic64_read(&rdev->num_bytes_moved);
 550                 break;
 551         case RADEON_INFO_VRAM_USAGE:
 552                 value = (uint32_t*)&value64;
 553                 value_size = sizeof(uint64_t);
 554                 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
 555                 value64 = ttm_resource_manager_usage(man);
 556                 break;
 557         case RADEON_INFO_GTT_USAGE:
 558                 value = (uint32_t*)&value64;
 559                 value_size = sizeof(uint64_t);
 560                 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT);
 561                 value64 = ttm_resource_manager_usage(man);
 562                 break;
 563         case RADEON_INFO_ACTIVE_CU_COUNT:
 564                 if (rdev->family >= CHIP_BONAIRE)
 565                         *value = rdev->config.cik.active_cus;
 566                 else if (rdev->family >= CHIP_TAHITI)
 567                         *value = rdev->config.si.active_cus;
 568                 else if (rdev->family >= CHIP_CAYMAN)
 569                         *value = rdev->config.cayman.active_simds;
 570                 else if (rdev->family >= CHIP_CEDAR)
 571                         *value = rdev->config.evergreen.active_simds;
 572                 else if (rdev->family >= CHIP_RV770)
 573                         *value = rdev->config.rv770.active_simds;
 574                 else if (rdev->family >= CHIP_R600)
 575                         *value = rdev->config.r600.active_simds;
 576                 else
 577                         *value = 1;
 578                 break;
 579         case RADEON_INFO_CURRENT_GPU_TEMP:
 580                 /* get temperature in millidegrees C */
 581                 if (rdev->asic->pm.get_temperature)
 582                         *value = radeon_get_temperature(rdev);
 583                 else
 584                         *value = 0;
 585                 break;
 586         case RADEON_INFO_CURRENT_GPU_SCLK:
 587                 /* get sclk in Mhz */
 588                 if (rdev->pm.dpm_enabled)
 589                         *value = radeon_dpm_get_current_sclk(rdev) / 100;
 590                 else
 591                         *value = rdev->pm.current_sclk / 100;
 592                 break;
 593         case RADEON_INFO_CURRENT_GPU_MCLK:
 594                 /* get mclk in Mhz */
 595                 if (rdev->pm.dpm_enabled)
 596                         *value = radeon_dpm_get_current_mclk(rdev) / 100;
 597                 else
 598                         *value = rdev->pm.current_mclk / 100;
 599                 break;
 600         case RADEON_INFO_READ_REG:
 601                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 602                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 603                         return -EFAULT;
 604                 }
 605                 if (radeon_get_allowed_info_register(rdev, *value, value))
 606                         return -EINVAL;
 607                 break;
 608         case RADEON_INFO_VA_UNMAP_WORKING:
 609                 *value = true;
 610                 break;
 611         case RADEON_INFO_GPU_RESET_COUNTER:
 612                 *value = atomic_read(&rdev->gpu_reset_counter);
 613                 break;
 614         default:
 615                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 616                 return -EINVAL;
 617         }
 618         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 619                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 620                 return -EFAULT;
 621         }
 622         return 0;
 623 }
 624
 625
 626 /*
 627  * Outdated mess for old drm with Xorg being in charge (void function now).
 628  */
 629 /**
 630  * radeon_driver_lastclose_kms - drm callback for last close
 631  *
 632  * @dev: drm dev pointer
 633  *
 634  * Switch vga_switcheroo state after last close (all asics).
 635  */
 636 void radeon_driver_lastclose_kms(struct drm_device *dev)
 637 {
 638         drm_fb_helper_lastclose(dev);
 639         vga_switcheroo_process_delayed_switch();
 640 }
 641
 642 /**
 643  * radeon_driver_open_kms - drm callback for open
 644  *
 645  * @dev: drm dev pointer
 646  * @file_priv: drm file
 647  *
 648  * On device open, init vm on cayman+ (all asics).
 649  * Returns 0 on success, error on failure.
 650  */
 651 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 652 {
 653         struct radeon_device *rdev = dev->dev_private;
 654         struct radeon_fpriv *fpriv;
 655         struct radeon_vm *vm;
 656         int r;
 657
 658         file_priv->driver_priv = NULL;
 659
 660         r = pm_runtime_get_sync(dev->dev);
 661         if (r < 0) {
 662                 pm_runtime_put_autosuspend(dev->dev);
 663                 return r;
 664         }
 665
 666         /* new gpu have virtual address space support */
 667         if (rdev->family >= CHIP_CAYMAN) {
 668
 669                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 670                 if (unlikely(!fpriv)) {
 671                         r = -ENOMEM;
 672                         goto err_suspend;
 673                 }
 674
 675                 if (rdev->accel_working) {
 676                         vm = &fpriv->vm;
 677                         r = radeon_vm_init(rdev, vm);
 678                         if (r)
 679                                 goto err_fpriv;
 680
 681                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 682                         if (r)
 683                                 goto err_vm_fini;
 684
 685                         /* map the ib pool buffer read only into
 686                          * virtual address space */
 687                         vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
 688                                                         rdev->ring_tmp_bo.bo);
 689                         if (!vm->ib_bo_va) {
 690                                 r = -ENOMEM;
 691                                 goto err_vm_fini;
 692                         }
 693
 694                         r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
 695                                                   RADEON_VA_IB_OFFSET,
 696                                                   RADEON_VM_PAGE_READABLE |
 697                                                   RADEON_VM_PAGE_SNOOPED);
 698                         if (r)
 699                                 goto err_vm_fini;
 700                 }
 701                 file_priv->driver_priv = fpriv;
 702         }
 703
 704         pm_runtime_mark_last_busy(dev->dev);
 705         pm_runtime_put_autosuspend(dev->dev);
 706         return 0;
 707
 708 err_vm_fini:
 709         radeon_vm_fini(rdev, vm);
 710 err_fpriv:
 711         kfree(fpriv);
 712
 713 err_suspend:
 714         pm_runtime_mark_last_busy(dev->dev);
 715         pm_runtime_put_autosuspend(dev->dev);
 716         return r;
 717 }
 718
 719 /**
 720  * radeon_driver_postclose_kms - drm callback for post close
 721  *
 722  * @dev: drm dev pointer
 723  * @file_priv: drm file
 724  *
 725  * On device close, tear down hyperz and cmask filps on r1xx-r5xx
 726  * (all asics).  And tear down vm on cayman+ (all asics).
 727  */
 728 void radeon_driver_postclose_kms(struct drm_device *dev,
 729                                  struct drm_file *file_priv)
 730 {
 731         struct radeon_device *rdev = dev->dev_private;
 732
 733         pm_runtime_get_sync(dev->dev);
 734
 735         mutex_lock(&rdev->gem.mutex);
 736         if (rdev->hyperz_filp == file_priv)
 737                 rdev->hyperz_filp = NULL;
 738         if (rdev->cmask_filp == file_priv)
 739                 rdev->cmask_filp = NULL;
 740         mutex_unlock(&rdev->gem.mutex);
 741
 742         radeon_uvd_free_handles(rdev, file_priv);
 743         radeon_vce_free_handles(rdev, file_priv);
 744
 745         /* new gpu have virtual address space support */
 746         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 747                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 748                 struct radeon_vm *vm = &fpriv->vm;
 749                 int r;
 750
 751                 if (rdev->accel_working) {
 752                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 753                         if (!r) {
 754                                 if (vm->ib_bo_va)
 755                                         radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
 756                                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 757                         }
 758                         radeon_vm_fini(rdev, vm);
 759                 }
 760
 761                 kfree(fpriv);
 762                 file_priv->driver_priv = NULL;
 763         }
 764         pm_runtime_mark_last_busy(dev->dev);
 765         pm_runtime_put_autosuspend(dev->dev);
 766 }
 767
 768 /*
 769  * VBlank related functions.
 770  */
 771 /**
 772  * radeon_get_vblank_counter_kms - get frame count
 773  *
 774  * @crtc: crtc to get the frame count from
 775  *
 776  * Gets the frame count on the requested crtc (all asics).
 777  * Returns frame count on success, -EINVAL on failure.
 778  */
 779 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
 780 {
 781         struct drm_device *dev = crtc->dev;
 782         unsigned int pipe = crtc->index;
 783         int vpos, hpos, stat;
 784         u32 count;
 785         struct radeon_device *rdev = dev->dev_private;
 786
 787         if (pipe >= rdev->num_crtc) {
 788                 DRM_ERROR("Invalid crtc %u\n", pipe);
 789                 return -EINVAL;
 790         }
 791
 792         /* The hw increments its frame counter at start of vsync, not at start
 793          * of vblank, as is required by DRM core vblank counter handling.
 794          * Cook the hw count here to make it appear to the caller as if it
 795          * incremented at start of vblank. We measure distance to start of
 796          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 797          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 798          * result by 1 to give the proper appearance to caller.
 799          */
 800         if (rdev->mode_info.crtcs[pipe]) {
 801                 /* Repeat readout if needed to provide stable result if
 802                  * we cross start of vsync during the queries.
 803                  */
 804                 do {
 805                         count = radeon_get_vblank_counter(rdev, pipe);
 806                         /* Ask radeon_get_crtc_scanoutpos to return vpos as
 807                          * distance to start of vblank, instead of regular
 808                          * vertical scanout pos.
 809                          */
 810                         stat = radeon_get_crtc_scanoutpos(
 811                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 812                                 &vpos, &hpos, NULL, NULL,
 813                                 &rdev->mode_info.crtcs[pipe]->base.hwmode);
 814                 } while (count != radeon_get_vblank_counter(rdev, pipe));
 815
 816                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 817                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 818                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 819                 }
 820                 else {
 821                         DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
 822                                       pipe, vpos);
 823
 824                         /* Bump counter if we are at >= leading edge of vblank,
 825                          * but before vsync where vpos would turn negative and
 826                          * the hw counter really increments.
 827                          */
 828                         if (vpos >= 0)
 829                                 count++;
 830                 }
 831         }
 832         else {
 833             /* Fallback to use value as is. */
 834             count = radeon_get_vblank_counter(rdev, pipe);
 835             DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 836         }
 837
 838         return count;
 839 }
 840
 841 /**
 842  * radeon_enable_vblank_kms - enable vblank interrupt
 843  *
 844  * @crtc: crtc to enable vblank interrupt for
 845  *
 846  * Enable the interrupt on the requested crtc (all asics).
 847  * Returns 0 on success, -EINVAL on failure.
 848  */
 849 int radeon_enable_vblank_kms(struct drm_crtc *crtc)
 850 {
 851         struct drm_device *dev = crtc->dev;
 852         unsigned int pipe = crtc->index;
 853         struct radeon_device *rdev = dev->dev_private;
 854         unsigned long irqflags;
 855         int r;
 856
 857         if (pipe >= rdev->num_crtc) {
 858                 DRM_ERROR("Invalid crtc %d\n", pipe);
 859                 return -EINVAL;
 860         }
 861
 862         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 863         rdev->irq.crtc_vblank_int[pipe] = true;
 864         r = radeon_irq_set(rdev);
 865         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 866         return r;
 867 }
 868
 869 /**
 870  * radeon_disable_vblank_kms - disable vblank interrupt
 871  *
 872  * @crtc: crtc to disable vblank interrupt for
 873  *
 874  * Disable the interrupt on the requested crtc (all asics).
 875  */
 876 void radeon_disable_vblank_kms(struct drm_crtc *crtc)
 877 {
 878         struct drm_device *dev = crtc->dev;
 879         unsigned int pipe = crtc->index;
 880         struct radeon_device *rdev = dev->dev_private;
 881         unsigned long irqflags;
 882
 883         if (pipe >= rdev->num_crtc) {
 884                 DRM_ERROR("Invalid crtc %d\n", pipe);
 885                 return;
 886         }
 887
 888         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 889         rdev->irq.crtc_vblank_int[pipe] = false;
 890         radeon_irq_set(rdev);
 891         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 892 }