drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/drm_fb_helper.h>
  30 #include "radeon.h"
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_asic.h"
  33
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/slab.h>
  36 #include <linux/pm_runtime.h>
  37
  38 #if defined(CONFIG_VGA_SWITCHEROO)
  39 bool radeon_has_atpx(void);
  40 #else
  41 static inline bool radeon_has_atpx(void) { return false; }
  42 #endif
  43
  44 /**
  45  * radeon_driver_unload_kms - Main unload function for KMS.
  46  *
  47  * @dev: drm dev pointer
  48  *
  49  * This is the main unload function for KMS (all asics).
  50  * It calls radeon_modeset_fini() to tear down the
  51  * displays, and radeon_device_fini() to tear down
  52  * the rest of the device (CP, writeback, etc.).
  53  * Returns 0 on success.
  54  */
  55 void radeon_driver_unload_kms(struct drm_device *dev)
  56 {
  57         struct radeon_device *rdev = dev->dev_private;
  58
  59         if (rdev == NULL)
  60                 return;
  61
  62         if (rdev->rmmio == NULL)
  63                 goto done_free;
  64
  65         if (radeon_is_px(dev)) {
  66                 pm_runtime_get_sync(dev->dev);
  67                 pm_runtime_forbid(dev->dev);
  68         }
  69
  70         radeon_acpi_fini(rdev);
  71
  72         radeon_modeset_fini(rdev);
  73         radeon_device_fini(rdev);
  74
  75 done_free:
  76         kfree(rdev);
  77         dev->dev_private = NULL;
  78 }
  79
  80 /**
  81  * radeon_driver_load_kms - Main load function for KMS.
  82  *
  83  * @dev: drm dev pointer
  84  * @flags: device flags
  85  *
  86  * This is the main load function for KMS (all asics).
  87  * It calls radeon_device_init() to set up the non-display
  88  * parts of the chip (asic init, CP, writeback, etc.), and
  89  * radeon_modeset_init() to set up the display parts
  90  * (crtcs, encoders, hotplug detect, etc.).
  91  * Returns 0 on success, error on failure.
  92  */
  93 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  94 {
  95         struct radeon_device *rdev;
  96         int r, acpi_status;
  97
  98         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  99         if (rdev == NULL) {
 100                 return -ENOMEM;
 101         }
 102         dev->dev_private = (void *)rdev;
 103
 104         /* update BUS flag */
 105         if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
 106                 flags |= RADEON_IS_AGP;
 107         } else if (pci_is_pcie(dev->pdev)) {
 108                 flags |= RADEON_IS_PCIE;
 109         } else {
 110                 flags |= RADEON_IS_PCI;
 111         }
 112
 113         if ((radeon_runtime_pm != 0) &&
 114             radeon_has_atpx() &&
 115             ((flags & RADEON_IS_IGP) == 0) &&
 116             !pci_is_thunderbolt_attached(dev->pdev))
 117                 flags |= RADEON_IS_PX;
 118
 119         /* radeon_device_init should report only fatal error
 120          * like memory allocation failure or iomapping failure,
 121          * or memory manager initialization failure, it must
 122          * properly initialize the GPU MC controller and permit
 123          * VRAM allocation
 124          */
 125         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 126         if (r) {
 127                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 128                 goto out;
 129         }
 130
 131         /* Again modeset_init should fail only on fatal error
 132          * otherwise it should provide enough functionalities
 133          * for shadowfb to run
 134          */
 135         r = radeon_modeset_init(rdev);
 136         if (r)
 137                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 138
 139         /* Call ACPI methods: require modeset init
 140          * but failure is not fatal
 141          */
 142         if (!r) {
 143                 acpi_status = radeon_acpi_init(rdev);
 144                 if (acpi_status)
 145                 dev_dbg(&dev->pdev->dev,
 146                                 "Error during ACPI methods call\n");
 147         }
 148
 149         if (radeon_is_px(dev)) {
 150                 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
 151                 pm_runtime_use_autosuspend(dev->dev);
 152                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 153                 pm_runtime_set_active(dev->dev);
 154                 pm_runtime_allow(dev->dev);
 155                 pm_runtime_mark_last_busy(dev->dev);
 156                 pm_runtime_put_autosuspend(dev->dev);
 157         }
 158
 159 out:
 160         if (r)
 161                 radeon_driver_unload_kms(dev);
 162
 163
 164         return r;
 165 }
 166
 167 /**
 168  * radeon_set_filp_rights - Set filp right.
 169  *
 170  * @dev: drm dev pointer
 171  * @owner: drm file
 172  * @applier: drm file
 173  * @value: value
 174  *
 175  * Sets the filp rights for the device (all asics).
 176  */
 177 static void radeon_set_filp_rights(struct drm_device *dev,
 178                                    struct drm_file **owner,
 179                                    struct drm_file *applier,
 180                                    uint32_t *value)
 181 {
 182         struct radeon_device *rdev = dev->dev_private;
 183
 184         mutex_lock(&rdev->gem.mutex);
 185         if (*value == 1) {
 186                 /* wants rights */
 187                 if (!*owner)
 188                         *owner = applier;
 189         } else if (*value == 0) {
 190                 /* revokes rights */
 191                 if (*owner == applier)
 192                         *owner = NULL;
 193         }
 194         *value = *owner == applier ? 1 : 0;
 195         mutex_unlock(&rdev->gem.mutex);
 196 }
 197
 198 /*
 199  * Userspace get information ioctl
 200  */
 201 /**
 202  * radeon_info_ioctl - answer a device specific request.
 203  *
 204  * @rdev: radeon device pointer
 205  * @data: request object
 206  * @filp: drm filp
 207  *
 208  * This function is used to pass device specific parameters to the userspace
 209  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 210  * etc. (all asics).
 211  * Returns 0 on success, -EINVAL on failure.
 212  */
 213 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 214 {
 215         struct radeon_device *rdev = dev->dev_private;
 216         struct drm_radeon_info *info = data;
 217         struct radeon_mode_info *minfo = &rdev->mode_info;
 218         uint32_t *value, value_tmp, *value_ptr, value_size;
 219         uint64_t value64;
 220         struct drm_crtc *crtc;
 221         int i, found;
 222
 223         value_ptr = (uint32_t *)((unsigned long)info->value);
 224         value = &value_tmp;
 225         value_size = sizeof(uint32_t);
 226
 227         switch (info->request) {
 228         case RADEON_INFO_DEVICE_ID:
 229                 *value = dev->pdev->device;
 230                 break;
 231         case RADEON_INFO_NUM_GB_PIPES:
 232                 *value = rdev->num_gb_pipes;
 233                 break;
 234         case RADEON_INFO_NUM_Z_PIPES:
 235                 *value = rdev->num_z_pipes;
 236                 break;
 237         case RADEON_INFO_ACCEL_WORKING:
 238                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 239                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 240                         *value = false;
 241                 else
 242                         *value = rdev->accel_working;
 243                 break;
 244         case RADEON_INFO_CRTC_FROM_ID:
 245                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 246                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 247                         return -EFAULT;
 248                 }
 249                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 250                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 251                         if (crtc && crtc->base.id == *value) {
 252                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 253                                 *value = radeon_crtc->crtc_id;
 254                                 found = 1;
 255                                 break;
 256                         }
 257                 }
 258                 if (!found) {
 259                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 260                         return -EINVAL;
 261                 }
 262                 break;
 263         case RADEON_INFO_ACCEL_WORKING2:
 264                 if (rdev->family == CHIP_HAWAII) {
 265                         if (rdev->accel_working) {
 266                                 if (rdev->new_fw)
 267                                         *value = 3;
 268                                 else
 269                                         *value = 2;
 270                         } else {
 271                                 *value = 0;
 272                         }
 273                 } else {
 274                         *value = rdev->accel_working;
 275                 }
 276                 break;
 277         case RADEON_INFO_TILING_CONFIG:
 278                 if (rdev->family >= CHIP_BONAIRE)
 279                         *value = rdev->config.cik.tile_config;
 280                 else if (rdev->family >= CHIP_TAHITI)
 281                         *value = rdev->config.si.tile_config;
 282                 else if (rdev->family >= CHIP_CAYMAN)
 283                         *value = rdev->config.cayman.tile_config;
 284                 else if (rdev->family >= CHIP_CEDAR)
 285                         *value = rdev->config.evergreen.tile_config;
 286                 else if (rdev->family >= CHIP_RV770)
 287                         *value = rdev->config.rv770.tile_config;
 288                 else if (rdev->family >= CHIP_R600)
 289                         *value = rdev->config.r600.tile_config;
 290                 else {
 291                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 292                         return -EINVAL;
 293                 }
 294                 break;
 295         case RADEON_INFO_WANT_HYPERZ:
 296                 /* The "value" here is both an input and output parameter.
 297                  * If the input value is 1, filp requests hyper-z access.
 298                  * If the input value is 0, filp revokes its hyper-z access.
 299                  *
 300                  * When returning, the value is 1 if filp owns hyper-z access,
 301                  * 0 otherwise. */
 302                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 303                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 304                         return -EFAULT;
 305                 }
 306                 if (*value >= 2) {
 307                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 308                         return -EINVAL;
 309                 }
 310                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 311                 break;
 312         case RADEON_INFO_WANT_CMASK:
 313                 /* The same logic as Hyper-Z. */
 314                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 315                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 316                         return -EFAULT;
 317                 }
 318                 if (*value >= 2) {
 319                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 320                         return -EINVAL;
 321                 }
 322                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 323                 break;
 324         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 325                 /* return clock value in KHz */
 326                 if (rdev->asic->get_xclk)
 327                         *value = radeon_get_xclk(rdev) * 10;
 328                 else
 329                         *value = rdev->clock.spll.reference_freq * 10;
 330                 break;
 331         case RADEON_INFO_NUM_BACKENDS:
 332                 if (rdev->family >= CHIP_BONAIRE)
 333                         *value = rdev->config.cik.max_backends_per_se *
 334                                 rdev->config.cik.max_shader_engines;
 335                 else if (rdev->family >= CHIP_TAHITI)
 336                         *value = rdev->config.si.max_backends_per_se *
 337                                 rdev->config.si.max_shader_engines;
 338                 else if (rdev->family >= CHIP_CAYMAN)
 339                         *value = rdev->config.cayman.max_backends_per_se *
 340                                 rdev->config.cayman.max_shader_engines;
 341                 else if (rdev->family >= CHIP_CEDAR)
 342                         *value = rdev->config.evergreen.max_backends;
 343                 else if (rdev->family >= CHIP_RV770)
 344                         *value = rdev->config.rv770.max_backends;
 345                 else if (rdev->family >= CHIP_R600)
 346                         *value = rdev->config.r600.max_backends;
 347                 else {
 348                         return -EINVAL;
 349                 }
 350                 break;
 351         case RADEON_INFO_NUM_TILE_PIPES:
 352                 if (rdev->family >= CHIP_BONAIRE)
 353                         *value = rdev->config.cik.max_tile_pipes;
 354                 else if (rdev->family >= CHIP_TAHITI)
 355                         *value = rdev->config.si.max_tile_pipes;
 356                 else if (rdev->family >= CHIP_CAYMAN)
 357                         *value = rdev->config.cayman.max_tile_pipes;
 358                 else if (rdev->family >= CHIP_CEDAR)
 359                         *value = rdev->config.evergreen.max_tile_pipes;
 360                 else if (rdev->family >= CHIP_RV770)
 361                         *value = rdev->config.rv770.max_tile_pipes;
 362                 else if (rdev->family >= CHIP_R600)
 363                         *value = rdev->config.r600.max_tile_pipes;
 364                 else {
 365                         return -EINVAL;
 366                 }
 367                 break;
 368         case RADEON_INFO_FUSION_GART_WORKING:
 369                 *value = 1;
 370                 break;
 371         case RADEON_INFO_BACKEND_MAP:
 372                 if (rdev->family >= CHIP_BONAIRE)
 373                         *value = rdev->config.cik.backend_map;
 374                 else if (rdev->family >= CHIP_TAHITI)
 375                         *value = rdev->config.si.backend_map;
 376                 else if (rdev->family >= CHIP_CAYMAN)
 377                         *value = rdev->config.cayman.backend_map;
 378                 else if (rdev->family >= CHIP_CEDAR)
 379                         *value = rdev->config.evergreen.backend_map;
 380                 else if (rdev->family >= CHIP_RV770)
 381                         *value = rdev->config.rv770.backend_map;
 382                 else if (rdev->family >= CHIP_R600)
 383                         *value = rdev->config.r600.backend_map;
 384                 else {
 385                         return -EINVAL;
 386                 }
 387                 break;
 388         case RADEON_INFO_VA_START:
 389                 /* this is where we report if vm is supported or not */
 390                 if (rdev->family < CHIP_CAYMAN)
 391                         return -EINVAL;
 392                 *value = RADEON_VA_RESERVED_SIZE;
 393                 break;
 394         case RADEON_INFO_IB_VM_MAX_SIZE:
 395                 /* this is where we report if vm is supported or not */
 396                 if (rdev->family < CHIP_CAYMAN)
 397                         return -EINVAL;
 398                 *value = RADEON_IB_VM_MAX_SIZE;
 399                 break;
 400         case RADEON_INFO_MAX_PIPES:
 401                 if (rdev->family >= CHIP_BONAIRE)
 402                         *value = rdev->config.cik.max_cu_per_sh;
 403                 else if (rdev->family >= CHIP_TAHITI)
 404                         *value = rdev->config.si.max_cu_per_sh;
 405                 else if (rdev->family >= CHIP_CAYMAN)
 406                         *value = rdev->config.cayman.max_pipes_per_simd;
 407                 else if (rdev->family >= CHIP_CEDAR)
 408                         *value = rdev->config.evergreen.max_pipes;
 409                 else if (rdev->family >= CHIP_RV770)
 410                         *value = rdev->config.rv770.max_pipes;
 411                 else if (rdev->family >= CHIP_R600)
 412                         *value = rdev->config.r600.max_pipes;
 413                 else {
 414                         return -EINVAL;
 415                 }
 416                 break;
 417         case RADEON_INFO_TIMESTAMP:
 418                 if (rdev->family < CHIP_R600) {
 419                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 420                         return -EINVAL;
 421                 }
 422                 value = (uint32_t*)&value64;
 423                 value_size = sizeof(uint64_t);
 424                 value64 = radeon_get_gpu_clock_counter(rdev);
 425                 break;
 426         case RADEON_INFO_MAX_SE:
 427                 if (rdev->family >= CHIP_BONAIRE)
 428                         *value = rdev->config.cik.max_shader_engines;
 429                 else if (rdev->family >= CHIP_TAHITI)
 430                         *value = rdev->config.si.max_shader_engines;
 431                 else if (rdev->family >= CHIP_CAYMAN)
 432                         *value = rdev->config.cayman.max_shader_engines;
 433                 else if (rdev->family >= CHIP_CEDAR)
 434                         *value = rdev->config.evergreen.num_ses;
 435                 else
 436                         *value = 1;
 437                 break;
 438         case RADEON_INFO_MAX_SH_PER_SE:
 439                 if (rdev->family >= CHIP_BONAIRE)
 440                         *value = rdev->config.cik.max_sh_per_se;
 441                 else if (rdev->family >= CHIP_TAHITI)
 442                         *value = rdev->config.si.max_sh_per_se;
 443                 else
 444                         return -EINVAL;
 445                 break;
 446         case RADEON_INFO_FASTFB_WORKING:
 447                 *value = rdev->fastfb_working;
 448                 break;
 449         case RADEON_INFO_RING_WORKING:
 450                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 451                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 452                         return -EFAULT;
 453                 }
 454                 switch (*value) {
 455                 case RADEON_CS_RING_GFX:
 456                 case RADEON_CS_RING_COMPUTE:
 457                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 458                         break;
 459                 case RADEON_CS_RING_DMA:
 460                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 461                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 462                         break;
 463                 case RADEON_CS_RING_UVD:
 464                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 465                         break;
 466                 case RADEON_CS_RING_VCE:
 467                         *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
 468                         break;
 469                 default:
 470                         return -EINVAL;
 471                 }
 472                 break;
 473         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 474                 if (rdev->family >= CHIP_BONAIRE) {
 475                         value = rdev->config.cik.tile_mode_array;
 476                         value_size = sizeof(uint32_t)*32;
 477                 } else if (rdev->family >= CHIP_TAHITI) {
 478                         value = rdev->config.si.tile_mode_array;
 479                         value_size = sizeof(uint32_t)*32;
 480                 } else {
 481                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 482                         return -EINVAL;
 483                 }
 484                 break;
 485         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 486                 if (rdev->family >= CHIP_BONAIRE) {
 487                         value = rdev->config.cik.macrotile_mode_array;
 488                         value_size = sizeof(uint32_t)*16;
 489                 } else {
 490                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 491                         return -EINVAL;
 492                 }
 493                 break;
 494         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 495                 *value = 1;
 496                 break;
 497         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 498                 if (rdev->family >= CHIP_BONAIRE) {
 499                         *value = rdev->config.cik.backend_enable_mask;
 500                 } else if (rdev->family >= CHIP_TAHITI) {
 501                         *value = rdev->config.si.backend_enable_mask;
 502                 } else {
 503                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 504                         return -EINVAL;
 505                 }
 506                 break;
 507         case RADEON_INFO_MAX_SCLK:
 508                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 509                     rdev->pm.dpm_enabled)
 510                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 511                 else
 512                         *value = rdev->pm.default_sclk * 10;
 513                 break;
 514         case RADEON_INFO_VCE_FW_VERSION:
 515                 *value = rdev->vce.fw_version;
 516                 break;
 517         case RADEON_INFO_VCE_FB_VERSION:
 518                 *value = rdev->vce.fb_version;
 519                 break;
 520         case RADEON_INFO_NUM_BYTES_MOVED:
 521                 value = (uint32_t*)&value64;
 522                 value_size = sizeof(uint64_t);
 523                 value64 = atomic64_read(&rdev->num_bytes_moved);
 524                 break;
 525         case RADEON_INFO_VRAM_USAGE:
 526                 value = (uint32_t*)&value64;
 527                 value_size = sizeof(uint64_t);
 528                 value64 = atomic64_read(&rdev->vram_usage);
 529                 break;
 530         case RADEON_INFO_GTT_USAGE:
 531                 value = (uint32_t*)&value64;
 532                 value_size = sizeof(uint64_t);
 533                 value64 = atomic64_read(&rdev->gtt_usage);
 534                 break;
 535         case RADEON_INFO_ACTIVE_CU_COUNT:
 536                 if (rdev->family >= CHIP_BONAIRE)
 537                         *value = rdev->config.cik.active_cus;
 538                 else if (rdev->family >= CHIP_TAHITI)
 539                         *value = rdev->config.si.active_cus;
 540                 else if (rdev->family >= CHIP_CAYMAN)
 541                         *value = rdev->config.cayman.active_simds;
 542                 else if (rdev->family >= CHIP_CEDAR)
 543                         *value = rdev->config.evergreen.active_simds;
 544                 else if (rdev->family >= CHIP_RV770)
 545                         *value = rdev->config.rv770.active_simds;
 546                 else if (rdev->family >= CHIP_R600)
 547                         *value = rdev->config.r600.active_simds;
 548                 else
 549                         *value = 1;
 550                 break;
 551         case RADEON_INFO_CURRENT_GPU_TEMP:
 552                 /* get temperature in millidegrees C */
 553                 if (rdev->asic->pm.get_temperature)
 554                         *value = radeon_get_temperature(rdev);
 555                 else
 556                         *value = 0;
 557                 break;
 558         case RADEON_INFO_CURRENT_GPU_SCLK:
 559                 /* get sclk in Mhz */
 560                 if (rdev->pm.dpm_enabled)
 561                         *value = radeon_dpm_get_current_sclk(rdev) / 100;
 562                 else
 563                         *value = rdev->pm.current_sclk / 100;
 564                 break;
 565         case RADEON_INFO_CURRENT_GPU_MCLK:
 566                 /* get mclk in Mhz */
 567                 if (rdev->pm.dpm_enabled)
 568                         *value = radeon_dpm_get_current_mclk(rdev) / 100;
 569                 else
 570                         *value = rdev->pm.current_mclk / 100;
 571                 break;
 572         case RADEON_INFO_READ_REG:
 573                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 574                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 575                         return -EFAULT;
 576                 }
 577                 if (radeon_get_allowed_info_register(rdev, *value, value))
 578                         return -EINVAL;
 579                 break;
 580         case RADEON_INFO_VA_UNMAP_WORKING:
 581                 *value = true;
 582                 break;
 583         case RADEON_INFO_GPU_RESET_COUNTER:
 584                 *value = atomic_read(&rdev->gpu_reset_counter);
 585                 break;
 586         default:
 587                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 588                 return -EINVAL;
 589         }
 590         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 591                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 592                 return -EFAULT;
 593         }
 594         return 0;
 595 }
 596
 597
 598 /*
 599  * Outdated mess for old drm with Xorg being in charge (void function now).
 600  */
 601 /**
 602  * radeon_driver_lastclose_kms - drm callback for last close
 603  *
 604  * @dev: drm dev pointer
 605  *
 606  * Switch vga_switcheroo state after last close (all asics).
 607  */
 608 void radeon_driver_lastclose_kms(struct drm_device *dev)
 609 {
 610         drm_fb_helper_lastclose(dev);
 611         vga_switcheroo_process_delayed_switch();
 612 }
 613
 614 /**
 615  * radeon_driver_open_kms - drm callback for open
 616  *
 617  * @dev: drm dev pointer
 618  * @file_priv: drm file
 619  *
 620  * On device open, init vm on cayman+ (all asics).
 621  * Returns 0 on success, error on failure.
 622  */
 623 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 624 {
 625         struct radeon_device *rdev = dev->dev_private;
 626         struct radeon_fpriv *fpriv;
 627         struct radeon_vm *vm;
 628         int r;
 629
 630         file_priv->driver_priv = NULL;
 631
 632         r = pm_runtime_get_sync(dev->dev);
 633         if (r < 0) {
 634                 pm_runtime_put_autosuspend(dev->dev);
 635                 return r;
 636         }
 637
 638         /* new gpu have virtual address space support */
 639         if (rdev->family >= CHIP_CAYMAN) {
 640
 641                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 642                 if (unlikely(!fpriv)) {
 643                         r = -ENOMEM;
 644                         goto err_suspend;
 645                 }
 646
 647                 if (rdev->accel_working) {
 648                         vm = &fpriv->vm;
 649                         r = radeon_vm_init(rdev, vm);
 650                         if (r)
 651                                 goto err_fpriv;
 652
 653                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 654                         if (r)
 655                                 goto err_vm_fini;
 656
 657                         /* map the ib pool buffer read only into
 658                          * virtual address space */
 659                         vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
 660                                                         rdev->ring_tmp_bo.bo);
 661                         if (!vm->ib_bo_va) {
 662                                 r = -ENOMEM;
 663                                 goto err_vm_fini;
 664                         }
 665
 666                         r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
 667                                                   RADEON_VA_IB_OFFSET,
 668                                                   RADEON_VM_PAGE_READABLE |
 669                                                   RADEON_VM_PAGE_SNOOPED);
 670                         if (r)
 671                                 goto err_vm_fini;
 672                 }
 673                 file_priv->driver_priv = fpriv;
 674         }
 675
 676         pm_runtime_mark_last_busy(dev->dev);
 677         pm_runtime_put_autosuspend(dev->dev);
 678         return 0;
 679
 680 err_vm_fini:
 681         radeon_vm_fini(rdev, vm);
 682 err_fpriv:
 683         kfree(fpriv);
 684
 685 err_suspend:
 686         pm_runtime_mark_last_busy(dev->dev);
 687         pm_runtime_put_autosuspend(dev->dev);
 688         return r;
 689 }
 690
 691 /**
 692  * radeon_driver_postclose_kms - drm callback for post close
 693  *
 694  * @dev: drm dev pointer
 695  * @file_priv: drm file
 696  *
 697  * On device close, tear down hyperz and cmask filps on r1xx-r5xx
 698  * (all asics).  And tear down vm on cayman+ (all asics).
 699  */
 700 void radeon_driver_postclose_kms(struct drm_device *dev,
 701                                  struct drm_file *file_priv)
 702 {
 703         struct radeon_device *rdev = dev->dev_private;
 704
 705         pm_runtime_get_sync(dev->dev);
 706
 707         mutex_lock(&rdev->gem.mutex);
 708         if (rdev->hyperz_filp == file_priv)
 709                 rdev->hyperz_filp = NULL;
 710         if (rdev->cmask_filp == file_priv)
 711                 rdev->cmask_filp = NULL;
 712         mutex_unlock(&rdev->gem.mutex);
 713
 714         radeon_uvd_free_handles(rdev, file_priv);
 715         radeon_vce_free_handles(rdev, file_priv);
 716
 717         /* new gpu have virtual address space support */
 718         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 719                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 720                 struct radeon_vm *vm = &fpriv->vm;
 721                 int r;
 722
 723                 if (rdev->accel_working) {
 724                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 725                         if (!r) {
 726                                 if (vm->ib_bo_va)
 727                                         radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
 728                                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 729                         }
 730                         radeon_vm_fini(rdev, vm);
 731                 }
 732
 733                 kfree(fpriv);
 734                 file_priv->driver_priv = NULL;
 735         }
 736         pm_runtime_mark_last_busy(dev->dev);
 737         pm_runtime_put_autosuspend(dev->dev);
 738 }
 739
 740 /*
 741  * VBlank related functions.
 742  */
 743 /**
 744  * radeon_get_vblank_counter_kms - get frame count
 745  *
 746  * @dev: drm dev pointer
 747  * @pipe: crtc to get the frame count from
 748  *
 749  * Gets the frame count on the requested crtc (all asics).
 750  * Returns frame count on success, -EINVAL on failure.
 751  */
 752 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 753 {
 754         int vpos, hpos, stat;
 755         u32 count;
 756         struct radeon_device *rdev = dev->dev_private;
 757
 758         if (pipe >= rdev->num_crtc) {
 759                 DRM_ERROR("Invalid crtc %u\n", pipe);
 760                 return -EINVAL;
 761         }
 762
 763         /* The hw increments its frame counter at start of vsync, not at start
 764          * of vblank, as is required by DRM core vblank counter handling.
 765          * Cook the hw count here to make it appear to the caller as if it
 766          * incremented at start of vblank. We measure distance to start of
 767          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 768          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 769          * result by 1 to give the proper appearance to caller.
 770          */
 771         if (rdev->mode_info.crtcs[pipe]) {
 772                 /* Repeat readout if needed to provide stable result if
 773                  * we cross start of vsync during the queries.
 774                  */
 775                 do {
 776                         count = radeon_get_vblank_counter(rdev, pipe);
 777                         /* Ask radeon_get_crtc_scanoutpos to return vpos as
 778                          * distance to start of vblank, instead of regular
 779                          * vertical scanout pos.
 780                          */
 781                         stat = radeon_get_crtc_scanoutpos(
 782                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 783                                 &vpos, &hpos, NULL, NULL,
 784                                 &rdev->mode_info.crtcs[pipe]->base.hwmode);
 785                 } while (count != radeon_get_vblank_counter(rdev, pipe));
 786
 787                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 788                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 789                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 790                 }
 791                 else {
 792                         DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
 793                                       pipe, vpos);
 794
 795                         /* Bump counter if we are at >= leading edge of vblank,
 796                          * but before vsync where vpos would turn negative and
 797                          * the hw counter really increments.
 798                          */
 799                         if (vpos >= 0)
 800                                 count++;
 801                 }
 802         }
 803         else {
 804             /* Fallback to use value as is. */
 805             count = radeon_get_vblank_counter(rdev, pipe);
 806             DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 807         }
 808
 809         return count;
 810 }
 811
 812 /**
 813  * radeon_enable_vblank_kms - enable vblank interrupt
 814  *
 815  * @dev: drm dev pointer
 816  * @crtc: crtc to enable vblank interrupt for
 817  *
 818  * Enable the interrupt on the requested crtc (all asics).
 819  * Returns 0 on success, -EINVAL on failure.
 820  */
 821 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 822 {
 823         struct radeon_device *rdev = dev->dev_private;
 824         unsigned long irqflags;
 825         int r;
 826
 827         if (crtc < 0 || crtc >= rdev->num_crtc) {
 828                 DRM_ERROR("Invalid crtc %d\n", crtc);
 829                 return -EINVAL;
 830         }
 831
 832         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 833         rdev->irq.crtc_vblank_int[crtc] = true;
 834         r = radeon_irq_set(rdev);
 835         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 836         return r;
 837 }
 838
 839 /**
 840  * radeon_disable_vblank_kms - disable vblank interrupt
 841  *
 842  * @dev: drm dev pointer
 843  * @crtc: crtc to disable vblank interrupt for
 844  *
 845  * Disable the interrupt on the requested crtc (all asics).
 846  */
 847 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 848 {
 849         struct radeon_device *rdev = dev->dev_private;
 850         unsigned long irqflags;
 851
 852         if (crtc < 0 || crtc >= rdev->num_crtc) {
 853                 DRM_ERROR("Invalid crtc %d\n", crtc);
 854                 return;
 855         }
 856
 857         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 858         rdev->irq.crtc_vblank_int[crtc] = false;
 859         radeon_irq_set(rdev);
 860         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 861 }
 862
 863 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
 864         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 865         DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 866         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 867         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 868         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
 869         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
 870         DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
 871         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
 872         DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
 873         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
 874         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
 875         DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
 876         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
 877         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
 878         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 879         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
 880         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
 881         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
 882         DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
 883         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
 884         DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
 885         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 886         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
 887         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
 888         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
 889         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
 890         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
 891         /* KMS */
 892         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 893         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 894         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 895         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 896         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
 897         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
 898         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 899         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 900         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 901         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 902         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 903         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 904         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 905         DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 906         DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 907 };
 908 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);