drivers/gpu/drm/radeon/radeon_dp_mst.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <drm/drmP.h>
   4 #include <drm/drm_dp_mst_helper.h>
   5 #include <drm/drm_fb_helper.h>
   6
   7 #include "radeon.h"
   8 #include "atom.h"
   9 #include "ni_reg.h"
  10
  11 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
  12
  13 static int radeon_atom_set_enc_offset(int id)
  14 {
  15         static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
  16                                        EVERGREEN_CRTC1_REGISTER_OFFSET,
  17                                        EVERGREEN_CRTC2_REGISTER_OFFSET,
  18                                        EVERGREEN_CRTC3_REGISTER_OFFSET,
  19                                        EVERGREEN_CRTC4_REGISTER_OFFSET,
  20                                        EVERGREEN_CRTC5_REGISTER_OFFSET,
  21                                        0x13830 - 0x7030 };
  22
  23         return offsets[id];
  24 }
  25
  26 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
  27                                      struct radeon_encoder_mst *mst_enc,
  28                                      enum radeon_hpd_id hpd, bool enable)
  29 {
  30         struct drm_device *dev = primary->base.dev;
  31         struct radeon_device *rdev = dev->dev_private;
  32         uint32_t reg;
  33         int retries = 0;
  34         uint32_t temp;
  35
  36         reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
  37
  38         /* set MST mode */
  39         reg &= ~NI_DIG_FE_DIG_MODE(7);
  40         reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
  41
  42         if (enable)
  43                 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  44         else
  45                 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  46
  47         reg |= NI_DIG_HPD_SELECT(hpd);
  48         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
  49         WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
  50
  51         if (enable) {
  52                 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
  53
  54                 do {
  55                         temp = RREG32(NI_DIG_FE_CNTL + offset);
  56                 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
  57                 if (retries == 10000)
  58                         DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
  59         }
  60         return 0;
  61 }
  62
  63 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
  64                                            int stream_number,
  65                                            int fe,
  66                                            int slots)
  67 {
  68         struct drm_device *dev = primary->base.dev;
  69         struct radeon_device *rdev = dev->dev_private;
  70         u32 temp, val;
  71         int retries  = 0;
  72         int satreg, satidx;
  73
  74         satreg = stream_number >> 1;
  75         satidx = stream_number & 1;
  76
  77         temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
  78
  79         val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
  80
  81         val <<= (16 * satidx);
  82
  83         temp &= ~(0xffff << (16 * satidx));
  84
  85         temp |= val;
  86
  87         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  88         WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  89
  90         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
  91
  92         do {
  93                 unsigned value1, value2;
  94                 udelay(10);
  95                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
  96
  97                 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
  98                 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
  99
 100                 if (!value1 && !value2)
 101                         break;
 102         } while (retries++ < 50);
 103
 104         if (retries == 10000)
 105                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
 106
 107         /* MTP 16 ? */
 108         return 0;
 109 }
 110
 111 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
 112                                                struct radeon_encoder *primary)
 113 {
 114         struct drm_device *dev = mst_conn->base.dev;
 115         struct stream_attribs new_attribs[6];
 116         int i;
 117         int idx = 0;
 118         struct radeon_connector *radeon_connector;
 119         struct drm_connector *connector;
 120
 121         memset(new_attribs, 0, sizeof(new_attribs));
 122         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 123                 struct radeon_encoder *subenc;
 124                 struct radeon_encoder_mst *mst_enc;
 125
 126                 radeon_connector = to_radeon_connector(connector);
 127                 if (!radeon_connector->is_mst_connector)
 128                         continue;
 129
 130                 if (radeon_connector->mst_port != mst_conn)
 131                         continue;
 132
 133                 subenc = radeon_connector->mst_encoder;
 134                 mst_enc = subenc->enc_priv;
 135
 136                 if (!mst_enc->enc_active)
 137                         continue;
 138
 139                 new_attribs[idx].fe = mst_enc->fe;
 140                 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
 141                 idx++;
 142         }
 143
 144         for (i = 0; i < idx; i++) {
 145                 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
 146                     new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
 147                         radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
 148                         mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
 149                         mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
 150                 }
 151         }
 152
 153         for (i = idx; i < mst_conn->enabled_attribs; i++) {
 154                 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
 155                 mst_conn->cur_stream_attribs[i].fe = 0;
 156                 mst_conn->cur_stream_attribs[i].slots = 0;
 157         }
 158         mst_conn->enabled_attribs = idx;
 159         return 0;
 160 }
 161
 162 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 163 {
 164         struct drm_device *dev = mst->base.dev;
 165         struct radeon_device *rdev = dev->dev_private;
 166         struct radeon_encoder_mst *mst_enc = mst->enc_priv;
 167         uint32_t val, temp;
 168         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 169         int retries = 0;
 170         uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
 171         uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 172
 173         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 174
 175         WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
 176
 177         do {
 178                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
 179                 udelay(10);
 180         } while ((temp & 0x1) && (retries++ < 10000));
 181
 182         if (retries >= 10000)
 183                 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
 184         return 0;
 185 }
 186
 187 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
 188 {
 189         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 190         struct radeon_connector *master = radeon_connector->mst_port;
 191         struct edid *edid;
 192         int ret = 0;
 193
 194         edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
 195         radeon_connector->edid = edid;
 196         DRM_DEBUG_KMS("edid retrieved %p\n", edid);
 197         if (radeon_connector->edid) {
 198                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 199                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 200                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 201                 return ret;
 202         }
 203         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 204
 205         return ret;
 206 }
 207
 208 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
 209 {
 210         return radeon_dp_mst_get_ddc_modes(connector);
 211 }
 212
 213 static enum drm_mode_status
 214 radeon_dp_mst_mode_valid(struct drm_connector *connector,
 215                         struct drm_display_mode *mode)
 216 {
 217         /* TODO - validate mode against available PBN for link */
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static struct
 228 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
 229 {
 230         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 231
 232         return &radeon_connector->mst_encoder->base;
 233 }
 234
 235 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
 236         .get_modes = radeon_dp_mst_get_modes,
 237         .mode_valid = radeon_dp_mst_mode_valid,
 238         .best_encoder = radeon_mst_best_encoder,
 239 };
 240
 241 static enum drm_connector_status
 242 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
 243 {
 244         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 245         struct radeon_connector *master = radeon_connector->mst_port;
 246
 247         return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
 248 }
 249
 250 static void
 251 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 252 {
 253         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 254         struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
 255
 256         drm_encoder_cleanup(&radeon_encoder->base);
 257         kfree(radeon_encoder);
 258         drm_connector_cleanup(connector);
 259         kfree(radeon_connector);
 260 }
 261
 262 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
 263         .dpms = drm_helper_connector_dpms,
 264         .detect = radeon_dp_mst_detect,
 265         .fill_modes = drm_helper_probe_single_connector_modes,
 266         .destroy = radeon_dp_mst_connector_destroy,
 267 };
 268
 269 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 270                                                          struct drm_dp_mst_port *port,
 271                                                          const char *pathprop)
 272 {
 273         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 274         struct drm_device *dev = master->base.dev;
 275         struct radeon_connector *radeon_connector;
 276         struct drm_connector *connector;
 277
 278         radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
 279         if (!radeon_connector)
 280                 return NULL;
 281
 282         radeon_connector->is_mst_connector = true;
 283         connector = &radeon_connector->base;
 284         radeon_connector->port = port;
 285         radeon_connector->mst_port = master;
 286         DRM_DEBUG_KMS("\n");
 287
 288         drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
 289         drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
 290         radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
 291
 292         drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
 293         drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
 294         drm_mode_connector_set_path_property(connector, pathprop);
 295
 296         return connector;
 297 }
 298
 299 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
 300 {
 301         struct drm_device *dev = connector->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303
 304         radeon_fb_add_connector(rdev, connector);
 305
 306         drm_connector_register(connector);
 307 }
 308
 309 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 310                                             struct drm_connector *connector)
 311 {
 312         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 313         struct drm_device *dev = master->base.dev;
 314         struct radeon_device *rdev = dev->dev_private;
 315
 316         drm_connector_unregister(connector);
 317         radeon_fb_remove_connector(rdev, connector);
 318         drm_connector_cleanup(connector);
 319
 320         kfree(connector);
 321         DRM_DEBUG_KMS("\n");
 322 }
 323
 324 static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
 325 {
 326         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 327         struct drm_device *dev = master->base.dev;
 328
 329         drm_kms_helper_hotplug_event(dev);
 330 }
 331
 332 const struct drm_dp_mst_topology_cbs mst_cbs = {
 333         .add_connector = radeon_dp_add_mst_connector,
 334         .register_connector = radeon_dp_register_mst_connector,
 335         .destroy_connector = radeon_dp_destroy_mst_connector,
 336         .hotplug = radeon_dp_mst_hotplug,
 337 };
 338
 339 static struct
 340 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
 341 {
 342         struct drm_device *dev = encoder->dev;
 343         struct drm_connector *connector;
 344
 345         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 346                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 347                 if (!connector->encoder)
 348                         continue;
 349                 if (!radeon_connector->is_mst_connector)
 350                         continue;
 351
 352                 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
 353                 if (connector->encoder == encoder)
 354                         return radeon_connector;
 355         }
 356         return NULL;
 357 }
 358
 359 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 360 {
 361         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 362         struct drm_device *dev = crtc->dev;
 363         struct radeon_device *rdev = dev->dev_private;
 364         struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
 365         struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 366         struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
 367         int dp_clock;
 368         struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 369
 370         if (radeon_connector) {
 371                 radeon_connector->pixelclock_for_modeset = mode->clock;
 372                 if (radeon_connector->base.display_info.bpc)
 373                         radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
 374                 else
 375                         radeon_crtc->bpc = 8;
 376         }
 377
 378         DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
 379         dp_clock = dig_connector->dp_clock;
 380         radeon_crtc->ss_enabled =
 381                 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 382                                                  ASIC_INTERNAL_SS_ON_DP,
 383                                                  dp_clock);
 384 }
 385
 386 static void
 387 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 388 {
 389         struct drm_device *dev = encoder->dev;
 390         struct radeon_device *rdev = dev->dev_private;
 391         struct radeon_encoder *radeon_encoder, *primary;
 392         struct radeon_encoder_mst *mst_enc;
 393         struct radeon_encoder_atom_dig *dig_enc;
 394         struct radeon_connector *radeon_connector;
 395         struct drm_crtc *crtc;
 396         struct radeon_crtc *radeon_crtc;
 397         int ret, slots;
 398         s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 399         if (!ASIC_IS_DCE5(rdev)) {
 400                 DRM_ERROR("got mst dpms on non-DCE5\n");
 401                 return;
 402         }
 403
 404         radeon_connector = radeon_mst_find_connector(encoder);
 405         if (!radeon_connector)
 406                 return;
 407
 408         radeon_encoder = to_radeon_encoder(encoder);
 409
 410         mst_enc = radeon_encoder->enc_priv;
 411
 412         primary = mst_enc->primary;
 413
 414         dig_enc = primary->enc_priv;
 415
 416         crtc = encoder->crtc;
 417         DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
 418
 419         switch (mode) {
 420         case DRM_MODE_DPMS_ON:
 421                 dig_enc->active_mst_links++;
 422
 423                 radeon_crtc = to_radeon_crtc(crtc);
 424
 425                 if (dig_enc->active_mst_links == 1) {
 426                         mst_enc->fe = dig_enc->dig_encoder;
 427                         mst_enc->fe_from_be = true;
 428                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 429
 430                         atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
 431                         atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
 432                                                         0, 0, dig_enc->dig_encoder);
 433
 434                         if (radeon_dp_needs_link_train(mst_enc->connector) ||
 435                             dig_enc->active_mst_links == 1) {
 436                                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
 437                         }
 438
 439                 } else {
 440                         mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
 441                         if (mst_enc->fe == -1)
 442                                 DRM_ERROR("failed to get frontend for dig encoder\n");
 443                         mst_enc->fe_from_be = false;
 444                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 445                 }
 446
 447                 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
 448                               dig_enc->linkb, radeon_crtc->crtc_id);
 449
 450                 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
 451                                                mst_enc->pbn);
 452                 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
 453                                                radeon_connector->port,
 454                                                mst_enc->pbn, slots);
 455                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 456
 457                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 458                                           radeon_connector->mst_port->hpd.hpd, true);
 459
 460                 mst_enc->enc_active = true;
 461                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 462
 463                 fixed_pbn = drm_int2fixp(mst_enc->pbn);
 464                 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
 465                 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
 466                 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 467
 468                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 469                                             mst_enc->fe);
 470                 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 471
 472                 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 473
 474                 break;
 475         case DRM_MODE_DPMS_STANDBY:
 476         case DRM_MODE_DPMS_SUSPEND:
 477         case DRM_MODE_DPMS_OFF:
 478                 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
 479
 480                 if (!mst_enc->enc_active)
 481                         return;
 482
 483                 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 484                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 485
 486                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 487                 /* and this can also fail */
 488                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 489
 490                 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 491
 492                 mst_enc->enc_active = false;
 493                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 494
 495                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 496                                           radeon_connector->mst_port->hpd.hpd, false);
 497                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
 498                                             mst_enc->fe);
 499
 500                 if (!mst_enc->fe_from_be)
 501                         radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
 502
 503                 mst_enc->fe_from_be = false;
 504                 dig_enc->active_mst_links--;
 505                 if (dig_enc->active_mst_links == 0) {
 506                         /* drop link */
 507                 }
 508
 509                 break;
 510         }
 511
 512 }
 513
 514 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 515                                    const struct drm_display_mode *mode,
 516                                    struct drm_display_mode *adjusted_mode)
 517 {
 518         struct radeon_encoder_mst *mst_enc;
 519         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 520         struct radeon_connector_atom_dig *dig_connector;
 521         int bpp = 24;
 522
 523         mst_enc = radeon_encoder->enc_priv;
 524
 525         mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
 526
 527         mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
 528         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 529                       mst_enc->primary->active_device, mst_enc->primary->devices,
 530                       mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
 531
 532
 533         drm_mode_set_crtcinfo(adjusted_mode, 0);
 534         dig_connector = mst_enc->connector->con_priv;
 535         dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 536         dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 537         DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 538                       dig_connector->dp_lane_count, dig_connector->dp_clock);
 539         return true;
 540 }
 541
 542 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
 543 {
 544         struct radeon_connector *radeon_connector;
 545         struct radeon_encoder *radeon_encoder, *primary;
 546         struct radeon_encoder_mst *mst_enc;
 547         struct radeon_encoder_atom_dig *dig_enc;
 548
 549         radeon_connector = radeon_mst_find_connector(encoder);
 550         if (!radeon_connector) {
 551                 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
 552                 return;
 553         }
 554         radeon_encoder = to_radeon_encoder(encoder);
 555
 556         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 557
 558         mst_enc = radeon_encoder->enc_priv;
 559
 560         primary = mst_enc->primary;
 561
 562         dig_enc = primary->enc_priv;
 563
 564         mst_enc->port = radeon_connector->port;
 565
 566         if (dig_enc->dig_encoder == -1) {
 567                 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
 568                 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
 569                 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
 570
 571
 572         }
 573         DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
 574 }
 575
 576 static void
 577 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
 578                              struct drm_display_mode *mode,
 579                              struct drm_display_mode *adjusted_mode)
 580 {
 581         DRM_DEBUG_KMS("\n");
 582 }
 583
 584 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
 585 {
 586         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 587         DRM_DEBUG_KMS("\n");
 588 }
 589
 590 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
 591         .dpms = radeon_mst_encoder_dpms,
 592         .mode_fixup = radeon_mst_mode_fixup,
 593         .prepare = radeon_mst_encoder_prepare,
 594         .mode_set = radeon_mst_encoder_mode_set,
 595         .commit = radeon_mst_encoder_commit,
 596 };
 597
 598 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 599 {
 600         drm_encoder_cleanup(encoder);
 601         kfree(encoder);
 602 }
 603
 604 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
 605         .destroy = radeon_dp_mst_encoder_destroy,
 606 };
 607
 608 static struct radeon_encoder *
 609 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
 610 {
 611         struct drm_device *dev = connector->base.dev;
 612         struct radeon_device *rdev = dev->dev_private;
 613         struct radeon_encoder *radeon_encoder;
 614         struct radeon_encoder_mst *mst_enc;
 615         struct drm_encoder *encoder;
 616         const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
 617         struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
 618
 619         DRM_DEBUG_KMS("enc master is %p\n", enc_master);
 620         radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
 621         if (!radeon_encoder)
 622                 return NULL;
 623
 624         radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
 625         if (!radeon_encoder->enc_priv) {
 626                 kfree(radeon_encoder);
 627                 return NULL;
 628         }
 629         encoder = &radeon_encoder->base;
 630         switch (rdev->num_crtc) {
 631         case 1:
 632                 encoder->possible_crtcs = 0x1;
 633                 break;
 634         case 2:
 635         default:
 636                 encoder->possible_crtcs = 0x3;
 637                 break;
 638         case 4:
 639                 encoder->possible_crtcs = 0xf;
 640                 break;
 641         case 6:
 642                 encoder->possible_crtcs = 0x3f;
 643                 break;
 644         }
 645
 646         drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
 647                          DRM_MODE_ENCODER_DPMST, NULL);
 648         drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
 649
 650         mst_enc = radeon_encoder->enc_priv;
 651         mst_enc->connector = connector;
 652         mst_enc->primary = to_radeon_encoder(enc_master);
 653         radeon_encoder->is_mst_encoder = true;
 654         return radeon_encoder;
 655 }
 656
 657 int
 658 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
 659 {
 660         struct drm_device *dev = radeon_connector->base.dev;
 661
 662         if (!radeon_connector->ddc_bus->has_aux)
 663                 return 0;
 664
 665         radeon_connector->mst_mgr.cbs = &mst_cbs;
 666         return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
 667                                             &radeon_connector->ddc_bus->aux, 16, 6,
 668                                             radeon_connector->base.base.id);
 669 }
 670
 671 int
 672 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
 673 {
 674         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 675         struct drm_device *dev = radeon_connector->base.dev;
 676         struct radeon_device *rdev = dev->dev_private;
 677         int ret;
 678         u8 msg[1];
 679
 680         if (!radeon_mst)
 681                 return 0;
 682
 683         if (!ASIC_IS_DCE5(rdev))
 684                 return 0;
 685
 686         if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
 687                 return 0;
 688
 689         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
 690                                1);
 691         if (ret) {
 692                 if (msg[0] & DP_MST_CAP) {
 693                         DRM_DEBUG_KMS("Sink is MST capable\n");
 694                         dig_connector->is_mst = true;
 695                 } else {
 696                         DRM_DEBUG_KMS("Sink is not MST capable\n");
 697                         dig_connector->is_mst = false;
 698                 }
 699
 700         }
 701         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 702                                         dig_connector->is_mst);
 703         return dig_connector->is_mst;
 704 }
 705
 706 int
 707 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
 708 {
 709         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 710         int retry;
 711
 712         if (dig_connector->is_mst) {
 713                 u8 esi[16] = { 0 };
 714                 int dret;
 715                 int ret = 0;
 716                 bool handled;
 717
 718                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 719                                        DP_SINK_COUNT_ESI, esi, 8);
 720 go_again:
 721                 if (dret == 8) {
 722                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 723                         ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
 724
 725                         if (handled) {
 726                                 for (retry = 0; retry < 3; retry++) {
 727                                         int wret;
 728                                         wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
 729                                                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
 730                                         if (wret == 3)
 731                                                 break;
 732                                 }
 733
 734                                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 735                                                         DP_SINK_COUNT_ESI, esi, 8);
 736                                 if (dret == 8) {
 737                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 738                                         goto go_again;
 739                                 }
 740                         } else
 741                                 ret = 0;
 742
 743                         return ret;
 744                 } else {
 745                         DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
 746                         dig_connector->is_mst = false;
 747                         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 748                                                         dig_connector->is_mst);
 749                         /* send a hotplug event */
 750                 }
 751         }
 752         return -EINVAL;
 753 }
 754
 755 #if defined(CONFIG_DEBUG_FS)
 756
 757 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
 758 {
 759         struct drm_info_node *node = (struct drm_info_node *)m->private;
 760         struct drm_device *dev = node->minor->dev;
 761         struct drm_connector *connector;
 762         struct radeon_connector *radeon_connector;
 763         struct radeon_connector_atom_dig *dig_connector;
 764         int i;
 765
 766         drm_modeset_lock_all(dev);
 767         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 768                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 769                         continue;
 770
 771                 radeon_connector = to_radeon_connector(connector);
 772                 dig_connector = radeon_connector->con_priv;
 773                 if (radeon_connector->is_mst_connector)
 774                         continue;
 775                 if (!dig_connector->is_mst)
 776                         continue;
 777                 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
 778
 779                 for (i = 0; i < radeon_connector->enabled_attribs; i++)
 780                         seq_printf(m, "attrib %d: %d %d\n", i,
 781                                    radeon_connector->cur_stream_attribs[i].fe,
 782                                    radeon_connector->cur_stream_attribs[i].slots);
 783         }
 784         drm_modeset_unlock_all(dev);
 785         return 0;
 786 }
 787
 788 static struct drm_info_list radeon_debugfs_mst_list[] = {
 789         {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
 790 };
 791 #endif
 792
 793 int radeon_mst_debugfs_init(struct radeon_device *rdev)
 794 {
 795 #if defined(CONFIG_DEBUG_FS)
 796         return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
 797 #endif
 798         return 0;
 799 }