drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include <linux/gcd.h>
  39
  40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  41 {
  42         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  43         struct drm_device *dev = crtc->dev;
  44         struct radeon_device *rdev = dev->dev_private;
  45         int i;
  46
  47         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  48         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  52         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  53
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  56         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  57
  58         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  59         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  60         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  61
  62         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  63         for (i = 0; i < 256; i++) {
  64                 WREG32(AVIVO_DC_LUT_30_COLOR,
  65                              (radeon_crtc->lut_r[i] << 20) |
  66                              (radeon_crtc->lut_g[i] << 10) |
  67                              (radeon_crtc->lut_b[i] << 0));
  68         }
  69
  70         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  71         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  72 }
  73
  74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  75 {
  76         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  77         struct drm_device *dev = crtc->dev;
  78         struct radeon_device *rdev = dev->dev_private;
  79         int i;
  80
  81         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  82         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  83
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  85         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  86         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  87
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  89         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  90         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  93         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  94
  95         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  96         for (i = 0; i < 256; i++) {
  97                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  98                        (radeon_crtc->lut_r[i] << 20) |
  99                        (radeon_crtc->lut_g[i] << 10) |
 100                        (radeon_crtc->lut_b[i] << 0));
 101         }
 102 }
 103
 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 105 {
 106         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 107         struct drm_device *dev = crtc->dev;
 108         struct radeon_device *rdev = dev->dev_private;
 109         int i;
 110
 111         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 112
 113         msleep(10);
 114
 115         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 116                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 117                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 118         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 119                NI_GRPH_PRESCALE_BYPASS);
 120         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 121                NI_OVL_PRESCALE_BYPASS);
 122         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 123                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 124                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 125
 126         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 129         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 130         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 131
 132         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 133         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 134         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 135
 136         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 137         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 138
 139         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 140         for (i = 0; i < 256; i++) {
 141                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 142                        (radeon_crtc->lut_r[i] << 20) |
 143                        (radeon_crtc->lut_g[i] << 10) |
 144                        (radeon_crtc->lut_b[i] << 0));
 145         }
 146
 147         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 148                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 149                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 150                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 151                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 152         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 153                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 154                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 155         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 156                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 157                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 158         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 159                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 160                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 161         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 162         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 163         if (ASIC_IS_DCE8(rdev)) {
 164                 /* XXX this only needs to be programmed once per crtc at startup,
 165                  * not sure where the best place for it is
 166                  */
 167                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 168                        CIK_CURSOR_ALPHA_BLND_ENA);
 169         }
 170 }
 171
 172 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 173 {
 174         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 175         struct drm_device *dev = crtc->dev;
 176         struct radeon_device *rdev = dev->dev_private;
 177         int i;
 178         uint32_t dac2_cntl;
 179
 180         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 181         if (radeon_crtc->crtc_id == 0)
 182                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 183         else
 184                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 185         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 186
 187         WREG8(RADEON_PALETTE_INDEX, 0);
 188         for (i = 0; i < 256; i++) {
 189                 WREG32(RADEON_PALETTE_30_DATA,
 190                              (radeon_crtc->lut_r[i] << 20) |
 191                              (radeon_crtc->lut_g[i] << 10) |
 192                              (radeon_crtc->lut_b[i] << 0));
 193         }
 194 }
 195
 196 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 197 {
 198         struct drm_device *dev = crtc->dev;
 199         struct radeon_device *rdev = dev->dev_private;
 200
 201         if (!crtc->enabled)
 202                 return;
 203
 204         if (ASIC_IS_DCE5(rdev))
 205                 dce5_crtc_load_lut(crtc);
 206         else if (ASIC_IS_DCE4(rdev))
 207                 dce4_crtc_load_lut(crtc);
 208         else if (ASIC_IS_AVIVO(rdev))
 209                 avivo_crtc_load_lut(crtc);
 210         else
 211                 legacy_crtc_load_lut(crtc);
 212 }
 213
 214 /** Sets the color ramps on behalf of fbcon */
 215 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 216                               u16 blue, int regno)
 217 {
 218         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 219
 220         radeon_crtc->lut_r[regno] = red >> 6;
 221         radeon_crtc->lut_g[regno] = green >> 6;
 222         radeon_crtc->lut_b[regno] = blue >> 6;
 223 }
 224
 225 /** Gets the color ramps on behalf of fbcon */
 226 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 227                               u16 *blue, int regno)
 228 {
 229         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 230
 231         *red = radeon_crtc->lut_r[regno] << 6;
 232         *green = radeon_crtc->lut_g[regno] << 6;
 233         *blue = radeon_crtc->lut_b[regno] << 6;
 234 }
 235
 236 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 237                                  u16 *blue, uint32_t size)
 238 {
 239         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 240         int i;
 241
 242         /* userspace palettes are always correct as is */
 243         for (i = 0; i < size; i++) {
 244                 radeon_crtc->lut_r[i] = red[i] >> 6;
 245                 radeon_crtc->lut_g[i] = green[i] >> 6;
 246                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 247         }
 248         radeon_crtc_load_lut(crtc);
 249
 250         return 0;
 251 }
 252
 253 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 254 {
 255         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 256
 257         drm_crtc_cleanup(crtc);
 258         destroy_workqueue(radeon_crtc->flip_queue);
 259         kfree(radeon_crtc);
 260 }
 261
 262 /**
 263  * radeon_unpin_work_func - unpin old buffer object
 264  *
 265  * @__work - kernel work item
 266  *
 267  * Unpin the old frame buffer object outside of the interrupt handler
 268  */
 269 static void radeon_unpin_work_func(struct work_struct *__work)
 270 {
 271         struct radeon_flip_work *work =
 272                 container_of(__work, struct radeon_flip_work, unpin_work);
 273         int r;
 274
 275         /* unpin of the old buffer */
 276         r = radeon_bo_reserve(work->old_rbo, false);
 277         if (likely(r == 0)) {
 278                 r = radeon_bo_unpin(work->old_rbo);
 279                 if (unlikely(r != 0)) {
 280                         DRM_ERROR("failed to unpin buffer after flip\n");
 281                 }
 282                 radeon_bo_unreserve(work->old_rbo);
 283         } else
 284                 DRM_ERROR("failed to reserve buffer after flip\n");
 285
 286         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 287         kfree(work);
 288 }
 289
 290 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 291 {
 292         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 293         unsigned long flags;
 294         u32 update_pending;
 295         int vpos, hpos;
 296
 297         /* can happen during initialization */
 298         if (radeon_crtc == NULL)
 299                 return;
 300
 301         /* Skip the pageflip completion check below (based on polling) on
 302          * asics which reliably support hw pageflip completion irqs. pflip
 303          * irqs are a reliable and race-free method of handling pageflip
 304          * completion detection. A use_pflipirq module parameter < 2 allows
 305          * to override this in case of asics with faulty pflip irqs.
 306          * A module parameter of 0 would only use this polling based path,
 307          * a parameter of 1 would use pflip irq only as a backup to this
 308          * path, as in Linux 3.16.
 309          */
 310         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 311                 return;
 312
 313         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 314         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 315                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 316                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 317                                  radeon_crtc->flip_status,
 318                                  RADEON_FLIP_SUBMITTED);
 319                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 320                 return;
 321         }
 322
 323         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 324
 325         /* Has the pageflip already completed in crtc, or is it certain
 326          * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
 327          * distance to start of "fudged earlier" vblank in vpos, distance to
 328          * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
 329          * the last few scanlines before start of real vblank, where the vblank
 330          * irq can fire, so we have sampled update_pending a bit too early and
 331          * know the flip will complete at leading edge of the upcoming real
 332          * vblank. On pre-AVIVO hardware, flips also complete inside the real
 333          * vblank, not only at leading edge, so if update_pending for hpos >= 0
 334          *  == inside real vblank, the flip will complete almost immediately.
 335          * Note that this method of completion handling is still not 100% race
 336          * free, as we could execute before the radeon_flip_work_func managed
 337          * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
 338          * but the flip still gets programmed into hw and completed during
 339          * vblank, leading to a delayed emission of the flip completion event.
 340          * This applies at least to pre-AVIVO hardware, where flips are always
 341          * completing inside vblank, not only at leading edge of vblank.
 342          */
 343         if (update_pending &&
 344             (DRM_SCANOUTPOS_VALID &
 345              radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 346                                         GET_DISTANCE_TO_VBLANKSTART,
 347                                         &vpos, &hpos, NULL, NULL,
 348                                         &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 349             ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
 350                 /* crtc didn't flip in this target vblank interval,
 351                  * but flip is pending in crtc. Based on the current
 352                  * scanout position we know that the current frame is
 353                  * (nearly) complete and the flip will (likely)
 354                  * complete before the start of the next frame.
 355                  */
 356                 update_pending = 0;
 357         }
 358         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 359         if (!update_pending)
 360                 radeon_crtc_handle_flip(rdev, crtc_id);
 361 }
 362
 363 /**
 364  * radeon_crtc_handle_flip - page flip completed
 365  *
 366  * @rdev: radeon device pointer
 367  * @crtc_id: crtc number this event is for
 368  *
 369  * Called when we are sure that a page flip for this crtc is completed.
 370  */
 371 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 372 {
 373         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 374         struct radeon_flip_work *work;
 375         unsigned long flags;
 376
 377         /* this can happen at init */
 378         if (radeon_crtc == NULL)
 379                 return;
 380
 381         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 382         work = radeon_crtc->flip_work;
 383         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 384                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 385                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 386                                  radeon_crtc->flip_status,
 387                                  RADEON_FLIP_SUBMITTED);
 388                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 389                 return;
 390         }
 391
 392         /* Pageflip completed. Clean up. */
 393         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 394         radeon_crtc->flip_work = NULL;
 395
 396         /* wakeup userspace */
 397         if (work->event)
 398                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 399
 400         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 401
 402         drm_crtc_vblank_put(&radeon_crtc->base);
 403         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 404         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 405 }
 406
 407 /**
 408  * radeon_flip_work_func - page flip framebuffer
 409  *
 410  * @work - kernel work item
 411  *
 412  * Wait for the buffer object to become idle and do the actual page flip
 413  */
 414 static void radeon_flip_work_func(struct work_struct *__work)
 415 {
 416         struct radeon_flip_work *work =
 417                 container_of(__work, struct radeon_flip_work, flip_work);
 418         struct radeon_device *rdev = work->rdev;
 419         struct drm_device *dev = rdev->ddev;
 420         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 421
 422         struct drm_crtc *crtc = &radeon_crtc->base;
 423         unsigned long flags;
 424         int r;
 425         int vpos, hpos;
 426
 427         down_read(&rdev->exclusive_lock);
 428         if (work->fence) {
 429                 struct radeon_fence *fence;
 430
 431                 fence = to_radeon_fence(work->fence);
 432                 if (fence && fence->rdev == rdev) {
 433                         r = radeon_fence_wait(fence, false);
 434                         if (r == -EDEADLK) {
 435                                 up_read(&rdev->exclusive_lock);
 436                                 do {
 437                                         r = radeon_gpu_reset(rdev);
 438                                 } while (r == -EAGAIN);
 439                                 down_read(&rdev->exclusive_lock);
 440                         }
 441                 } else
 442                         r = fence_wait(work->fence, false);
 443
 444                 if (r)
 445                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 446
 447                 /* We continue with the page flip even if we failed to wait on
 448                  * the fence, otherwise the DRM core and userspace will be
 449                  * confused about which BO the CRTC is scanning out
 450                  */
 451
 452                 fence_put(work->fence);
 453                 work->fence = NULL;
 454         }
 455
 456         /* Wait until we're out of the vertical blank period before the one
 457          * targeted by the flip. Always wait on pre DCE4 to avoid races with
 458          * flip completion handling from vblank irq, as these old asics don't
 459          * have reliable pageflip completion interrupts.
 460          */
 461         while (radeon_crtc->enabled &&
 462                 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 463                                             &vpos, &hpos, NULL, NULL,
 464                                             &crtc->hwmode)
 465                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 466                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 467                 (!ASIC_IS_AVIVO(rdev) ||
 468                 ((int) (work->target_vblank -
 469                 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)))
 470                 usleep_range(1000, 2000);
 471
 472         /* We borrow the event spin lock for protecting flip_status */
 473         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 474
 475         /* set the proper interrupt */
 476         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 477
 478         /* do the flip (mmio) */
 479         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 480
 481         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 482         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 483         up_read(&rdev->exclusive_lock);
 484 }
 485
 486 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 487                                         struct drm_framebuffer *fb,
 488                                         struct drm_pending_vblank_event *event,
 489                                         uint32_t page_flip_flags,
 490                                         uint32_t target)
 491 {
 492         struct drm_device *dev = crtc->dev;
 493         struct radeon_device *rdev = dev->dev_private;
 494         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 495         struct radeon_framebuffer *old_radeon_fb;
 496         struct radeon_framebuffer *new_radeon_fb;
 497         struct drm_gem_object *obj;
 498         struct radeon_flip_work *work;
 499         struct radeon_bo *new_rbo;
 500         uint32_t tiling_flags, pitch_pixels;
 501         uint64_t base;
 502         unsigned long flags;
 503         int r;
 504
 505         work = kzalloc(sizeof *work, GFP_KERNEL);
 506         if (work == NULL)
 507                 return -ENOMEM;
 508
 509         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 510         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 511
 512         work->rdev = rdev;
 513         work->crtc_id = radeon_crtc->crtc_id;
 514         work->event = event;
 515         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 516
 517         /* schedule unpin of the old buffer */
 518         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 519         obj = old_radeon_fb->obj;
 520
 521         /* take a reference to the old object */
 522         drm_gem_object_reference(obj);
 523         work->old_rbo = gem_to_radeon_bo(obj);
 524
 525         new_radeon_fb = to_radeon_framebuffer(fb);
 526         obj = new_radeon_fb->obj;
 527         new_rbo = gem_to_radeon_bo(obj);
 528
 529         /* pin the new buffer */
 530         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 531                          work->old_rbo, new_rbo);
 532
 533         r = radeon_bo_reserve(new_rbo, false);
 534         if (unlikely(r != 0)) {
 535                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 536                 goto cleanup;
 537         }
 538         /* Only 27 bit offset for legacy CRTC */
 539         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 540                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 541         if (unlikely(r != 0)) {
 542                 radeon_bo_unreserve(new_rbo);
 543                 r = -EINVAL;
 544                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 545                 goto cleanup;
 546         }
 547         work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
 548         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 549         radeon_bo_unreserve(new_rbo);
 550
 551         if (!ASIC_IS_AVIVO(rdev)) {
 552                 /* crtc offset is from display base addr not FB location */
 553                 base -= radeon_crtc->legacy_display_base_addr;
 554                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 555
 556                 if (tiling_flags & RADEON_TILING_MACRO) {
 557                         if (ASIC_IS_R300(rdev)) {
 558                                 base &= ~0x7ff;
 559                         } else {
 560                                 int byteshift = fb->bits_per_pixel >> 4;
 561                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 562                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 563                         }
 564                 } else {
 565                         int offset = crtc->y * pitch_pixels + crtc->x;
 566                         switch (fb->bits_per_pixel) {
 567                         case 8:
 568                         default:
 569                                 offset *= 1;
 570                                 break;
 571                         case 15:
 572                         case 16:
 573                                 offset *= 2;
 574                                 break;
 575                         case 24:
 576                                 offset *= 3;
 577                                 break;
 578                         case 32:
 579                                 offset *= 4;
 580                                 break;
 581                         }
 582                         base += offset;
 583                 }
 584                 base &= ~7;
 585         }
 586         work->base = base;
 587         work->target_vblank = target - drm_crtc_vblank_count(crtc) +
 588                 dev->driver->get_vblank_counter(dev, work->crtc_id);
 589
 590         /* We borrow the event spin lock for protecting flip_work */
 591         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 592
 593         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 594                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 595                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 596                 r = -EBUSY;
 597                 goto pflip_cleanup;
 598         }
 599         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 600         radeon_crtc->flip_work = work;
 601
 602         /* update crtc fb */
 603         crtc->primary->fb = fb;
 604
 605         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 606
 607         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 608         return 0;
 609
 610 pflip_cleanup:
 611         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 612                 DRM_ERROR("failed to reserve new rbo in error path\n");
 613                 goto cleanup;
 614         }
 615         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 616                 DRM_ERROR("failed to unpin new rbo in error path\n");
 617         }
 618         radeon_bo_unreserve(new_rbo);
 619
 620 cleanup:
 621         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 622         fence_put(work->fence);
 623         kfree(work);
 624         return r;
 625 }
 626
 627 static int
 628 radeon_crtc_set_config(struct drm_mode_set *set)
 629 {
 630         struct drm_device *dev;
 631         struct radeon_device *rdev;
 632         struct drm_crtc *crtc;
 633         bool active = false;
 634         int ret;
 635
 636         if (!set || !set->crtc)
 637                 return -EINVAL;
 638
 639         dev = set->crtc->dev;
 640
 641         ret = pm_runtime_get_sync(dev->dev);
 642         if (ret < 0) {
 643                 pm_runtime_put_autosuspend(dev->dev);
 644                 return ret;
 645         }
 646
 647         ret = drm_crtc_helper_set_config(set);
 648
 649         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 650                 if (crtc->enabled)
 651                         active = true;
 652
 653         pm_runtime_mark_last_busy(dev->dev);
 654
 655         rdev = dev->dev_private;
 656         /* if we have active crtcs and we don't have a power ref,
 657            take the current one */
 658         if (active && !rdev->have_disp_power_ref) {
 659                 rdev->have_disp_power_ref = true;
 660                 return ret;
 661         }
 662         /* if we have no active crtcs, then drop the power ref
 663            we got before */
 664         if (!active && rdev->have_disp_power_ref) {
 665                 pm_runtime_put_autosuspend(dev->dev);
 666                 rdev->have_disp_power_ref = false;
 667         }
 668
 669         /* drop the power reference we got coming in here */
 670         pm_runtime_put_autosuspend(dev->dev);
 671         return ret;
 672 }
 673
 674 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 675         .cursor_set2 = radeon_crtc_cursor_set2,
 676         .cursor_move = radeon_crtc_cursor_move,
 677         .gamma_set = radeon_crtc_gamma_set,
 678         .set_config = radeon_crtc_set_config,
 679         .destroy = radeon_crtc_destroy,
 680         .page_flip_target = radeon_crtc_page_flip_target,
 681 };
 682
 683 static void radeon_crtc_init(struct drm_device *dev, int index)
 684 {
 685         struct radeon_device *rdev = dev->dev_private;
 686         struct radeon_crtc *radeon_crtc;
 687         int i;
 688
 689         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 690         if (radeon_crtc == NULL)
 691                 return;
 692
 693         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 694
 695         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 696         radeon_crtc->crtc_id = index;
 697         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 698         rdev->mode_info.crtcs[index] = radeon_crtc;
 699
 700         if (rdev->family >= CHIP_BONAIRE) {
 701                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 702                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 703         } else {
 704                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 705                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 706         }
 707         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 708         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 709
 710 #if 0
 711         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 712         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 713         radeon_crtc->mode_set.num_connectors = 0;
 714 #endif
 715
 716         for (i = 0; i < 256; i++) {
 717                 radeon_crtc->lut_r[i] = i << 2;
 718                 radeon_crtc->lut_g[i] = i << 2;
 719                 radeon_crtc->lut_b[i] = i << 2;
 720         }
 721
 722         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 723                 radeon_atombios_init_crtc(dev, radeon_crtc);
 724         else
 725                 radeon_legacy_init_crtc(dev, radeon_crtc);
 726 }
 727
 728 static const char *encoder_names[38] = {
 729         "NONE",
 730         "INTERNAL_LVDS",
 731         "INTERNAL_TMDS1",
 732         "INTERNAL_TMDS2",
 733         "INTERNAL_DAC1",
 734         "INTERNAL_DAC2",
 735         "INTERNAL_SDVOA",
 736         "INTERNAL_SDVOB",
 737         "SI170B",
 738         "CH7303",
 739         "CH7301",
 740         "INTERNAL_DVO1",
 741         "EXTERNAL_SDVOA",
 742         "EXTERNAL_SDVOB",
 743         "TITFP513",
 744         "INTERNAL_LVTM1",
 745         "VT1623",
 746         "HDMI_SI1930",
 747         "HDMI_INTERNAL",
 748         "INTERNAL_KLDSCP_TMDS1",
 749         "INTERNAL_KLDSCP_DVO1",
 750         "INTERNAL_KLDSCP_DAC1",
 751         "INTERNAL_KLDSCP_DAC2",
 752         "SI178",
 753         "MVPU_FPGA",
 754         "INTERNAL_DDI",
 755         "VT1625",
 756         "HDMI_SI1932",
 757         "DP_AN9801",
 758         "DP_DP501",
 759         "INTERNAL_UNIPHY",
 760         "INTERNAL_KLDSCP_LVTMA",
 761         "INTERNAL_UNIPHY1",
 762         "INTERNAL_UNIPHY2",
 763         "NUTMEG",
 764         "TRAVIS",
 765         "INTERNAL_VCE",
 766         "INTERNAL_UNIPHY3",
 767 };
 768
 769 static const char *hpd_names[6] = {
 770         "HPD1",
 771         "HPD2",
 772         "HPD3",
 773         "HPD4",
 774         "HPD5",
 775         "HPD6",
 776 };
 777
 778 static void radeon_print_display_setup(struct drm_device *dev)
 779 {
 780         struct drm_connector *connector;
 781         struct radeon_connector *radeon_connector;
 782         struct drm_encoder *encoder;
 783         struct radeon_encoder *radeon_encoder;
 784         uint32_t devices;
 785         int i = 0;
 786
 787         DRM_INFO("Radeon Display Connectors\n");
 788         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 789                 radeon_connector = to_radeon_connector(connector);
 790                 DRM_INFO("Connector %d:\n", i);
 791                 DRM_INFO("  %s\n", connector->name);
 792                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 793                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 794                 if (radeon_connector->ddc_bus) {
 795                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 796                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 797                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 798                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 799                                  radeon_connector->ddc_bus->rec.a_data_reg,
 800                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 801                                  radeon_connector->ddc_bus->rec.en_data_reg,
 802                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 803                                  radeon_connector->ddc_bus->rec.y_data_reg);
 804                         if (radeon_connector->router.ddc_valid)
 805                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 806                                          radeon_connector->router.ddc_mux_control_pin,
 807                                          radeon_connector->router.ddc_mux_state);
 808                         if (radeon_connector->router.cd_valid)
 809                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 810                                          radeon_connector->router.cd_mux_control_pin,
 811                                          radeon_connector->router.cd_mux_state);
 812                 } else {
 813                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 814                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 815                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 816                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 817                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 818                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 819                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 820                 }
 821                 DRM_INFO("  Encoders:\n");
 822                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 823                         radeon_encoder = to_radeon_encoder(encoder);
 824                         devices = radeon_encoder->devices & radeon_connector->devices;
 825                         if (devices) {
 826                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 827                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 828                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 829                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 830                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 831                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 832                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 833                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 834                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 835                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 836                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 837                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 838                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 839                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 840                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 841                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 842                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 843                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 844                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 845                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 846                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 847                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 848                         }
 849                 }
 850                 i++;
 851         }
 852 }
 853
 854 static bool radeon_setup_enc_conn(struct drm_device *dev)
 855 {
 856         struct radeon_device *rdev = dev->dev_private;
 857         bool ret = false;
 858
 859         if (rdev->bios) {
 860                 if (rdev->is_atom_bios) {
 861                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 862                         if (ret == false)
 863                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 864                 } else {
 865                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 866                         if (ret == false)
 867                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 868                 }
 869         } else {
 870                 if (!ASIC_IS_AVIVO(rdev))
 871                         ret = radeon_get_legacy_connector_info_from_table(dev);
 872         }
 873         if (ret) {
 874                 radeon_setup_encoder_clones(dev);
 875                 radeon_print_display_setup(dev);
 876         }
 877
 878         return ret;
 879 }
 880
 881 /* avivo */
 882
 883 /**
 884  * avivo_reduce_ratio - fractional number reduction
 885  *
 886  * @nom: nominator
 887  * @den: denominator
 888  * @nom_min: minimum value for nominator
 889  * @den_min: minimum value for denominator
 890  *
 891  * Find the greatest common divisor and apply it on both nominator and
 892  * denominator, but make nominator and denominator are at least as large
 893  * as their minimum values.
 894  */
 895 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 896                                unsigned nom_min, unsigned den_min)
 897 {
 898         unsigned tmp;
 899
 900         /* reduce the numbers to a simpler ratio */
 901         tmp = gcd(*nom, *den);
 902         *nom /= tmp;
 903         *den /= tmp;
 904
 905         /* make sure nominator is large enough */
 906         if (*nom < nom_min) {
 907                 tmp = DIV_ROUND_UP(nom_min, *nom);
 908                 *nom *= tmp;
 909                 *den *= tmp;
 910         }
 911
 912         /* make sure the denominator is large enough */
 913         if (*den < den_min) {
 914                 tmp = DIV_ROUND_UP(den_min, *den);
 915                 *nom *= tmp;
 916                 *den *= tmp;
 917         }
 918 }
 919
 920 /**
 921  * avivo_get_fb_ref_div - feedback and ref divider calculation
 922  *
 923  * @nom: nominator
 924  * @den: denominator
 925  * @post_div: post divider
 926  * @fb_div_max: feedback divider maximum
 927  * @ref_div_max: reference divider maximum
 928  * @fb_div: resulting feedback divider
 929  * @ref_div: resulting reference divider
 930  *
 931  * Calculate feedback and reference divider for a given post divider. Makes
 932  * sure we stay within the limits.
 933  */
 934 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 935                                  unsigned fb_div_max, unsigned ref_div_max,
 936                                  unsigned *fb_div, unsigned *ref_div)
 937 {
 938         /* limit reference * post divider to a maximum */
 939         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 940
 941         /* get matching reference and feedback divider */
 942         *ref_div = min(max(den/post_div, 1u), ref_div_max);
 943         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 944
 945         /* limit fb divider to its maximum */
 946         if (*fb_div > fb_div_max) {
 947                 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
 948                 *fb_div = fb_div_max;
 949         }
 950 }
 951
 952 /**
 953  * radeon_compute_pll_avivo - compute PLL paramaters
 954  *
 955  * @pll: information about the PLL
 956  * @dot_clock_p: resulting pixel clock
 957  * fb_div_p: resulting feedback divider
 958  * frac_fb_div_p: fractional part of the feedback divider
 959  * ref_div_p: resulting reference divider
 960  * post_div_p: resulting reference divider
 961  *
 962  * Try to calculate the PLL parameters to generate the given frequency:
 963  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 964  */
 965 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 966                               u32 freq,
 967                               u32 *dot_clock_p,
 968                               u32 *fb_div_p,
 969                               u32 *frac_fb_div_p,
 970                               u32 *ref_div_p,
 971                               u32 *post_div_p)
 972 {
 973         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 974                 freq : freq / 10;
 975
 976         unsigned fb_div_min, fb_div_max, fb_div;
 977         unsigned post_div_min, post_div_max, post_div;
 978         unsigned ref_div_min, ref_div_max, ref_div;
 979         unsigned post_div_best, diff_best;
 980         unsigned nom, den;
 981
 982         /* determine allowed feedback divider range */
 983         fb_div_min = pll->min_feedback_div;
 984         fb_div_max = pll->max_feedback_div;
 985
 986         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 987                 fb_div_min *= 10;
 988                 fb_div_max *= 10;
 989         }
 990
 991         /* determine allowed ref divider range */
 992         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 993                 ref_div_min = pll->reference_div;
 994         else
 995                 ref_div_min = pll->min_ref_div;
 996
 997         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 998             pll->flags & RADEON_PLL_USE_REF_DIV)
 999                 ref_div_max = pll->reference_div;
1000         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1001                 /* fix for problems on RS880 */
1002                 ref_div_max = min(pll->max_ref_div, 7u);
1003         else
1004                 ref_div_max = pll->max_ref_div;
1005
1006         /* determine allowed post divider range */
1007         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1008                 post_div_min = pll->post_div;
1009                 post_div_max = pll->post_div;
1010         } else {
1011                 unsigned vco_min, vco_max;
1012
1013                 if (pll->flags & RADEON_PLL_IS_LCD) {
1014                         vco_min = pll->lcd_pll_out_min;
1015                         vco_max = pll->lcd_pll_out_max;
1016                 } else {
1017                         vco_min = pll->pll_out_min;
1018                         vco_max = pll->pll_out_max;
1019                 }
1020
1021                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1022                         vco_min *= 10;
1023                         vco_max *= 10;
1024                 }
1025
1026                 post_div_min = vco_min / target_clock;
1027                 if ((target_clock * post_div_min) < vco_min)
1028                         ++post_div_min;
1029                 if (post_div_min < pll->min_post_div)
1030                         post_div_min = pll->min_post_div;
1031
1032                 post_div_max = vco_max / target_clock;
1033                 if ((target_clock * post_div_max) > vco_max)
1034                         --post_div_max;
1035                 if (post_div_max > pll->max_post_div)
1036                         post_div_max = pll->max_post_div;
1037         }
1038
1039         /* represent the searched ratio as fractional number */
1040         nom = target_clock;
1041         den = pll->reference_freq;
1042
1043         /* reduce the numbers to a simpler ratio */
1044         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1045
1046         /* now search for a post divider */
1047         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1048                 post_div_best = post_div_min;
1049         else
1050                 post_div_best = post_div_max;
1051         diff_best = ~0;
1052
1053         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1054                 unsigned diff;
1055                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1056                                      ref_div_max, &fb_div, &ref_div);
1057                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1058                         (ref_div * post_div));
1059
1060                 if (diff < diff_best || (diff == diff_best &&
1061                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1062
1063                         post_div_best = post_div;
1064                         diff_best = diff;
1065                 }
1066         }
1067         post_div = post_div_best;
1068
1069         /* get the feedback and reference divider for the optimal value */
1070         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1071                              &fb_div, &ref_div);
1072
1073         /* reduce the numbers to a simpler ratio once more */
1074         /* this also makes sure that the reference divider is large enough */
1075         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1076
1077         /* avoid high jitter with small fractional dividers */
1078         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1079                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1080                 if (fb_div < fb_div_min) {
1081                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1082                         fb_div *= tmp;
1083                         ref_div *= tmp;
1084                 }
1085         }
1086
1087         /* and finally save the result */
1088         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1089                 *fb_div_p = fb_div / 10;
1090                 *frac_fb_div_p = fb_div % 10;
1091         } else {
1092                 *fb_div_p = fb_div;
1093                 *frac_fb_div_p = 0;
1094         }
1095
1096         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1097                         (pll->reference_freq * *frac_fb_div_p)) /
1098                        (ref_div * post_div * 10);
1099         *ref_div_p = ref_div;
1100         *post_div_p = post_div;
1101
1102         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1103                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1104                       ref_div, post_div);
1105 }
1106
1107 /* pre-avivo */
1108 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1109 {
1110         uint64_t mod;
1111
1112         n += d / 2;
1113
1114         mod = do_div(n, d);
1115         return n;
1116 }
1117
1118 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1119                                uint64_t freq,
1120                                uint32_t *dot_clock_p,
1121                                uint32_t *fb_div_p,
1122                                uint32_t *frac_fb_div_p,
1123                                uint32_t *ref_div_p,
1124                                uint32_t *post_div_p)
1125 {
1126         uint32_t min_ref_div = pll->min_ref_div;
1127         uint32_t max_ref_div = pll->max_ref_div;
1128         uint32_t min_post_div = pll->min_post_div;
1129         uint32_t max_post_div = pll->max_post_div;
1130         uint32_t min_fractional_feed_div = 0;
1131         uint32_t max_fractional_feed_div = 0;
1132         uint32_t best_vco = pll->best_vco;
1133         uint32_t best_post_div = 1;
1134         uint32_t best_ref_div = 1;
1135         uint32_t best_feedback_div = 1;
1136         uint32_t best_frac_feedback_div = 0;
1137         uint32_t best_freq = -1;
1138         uint32_t best_error = 0xffffffff;
1139         uint32_t best_vco_diff = 1;
1140         uint32_t post_div;
1141         u32 pll_out_min, pll_out_max;
1142
1143         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1144         freq = freq * 1000;
1145
1146         if (pll->flags & RADEON_PLL_IS_LCD) {
1147                 pll_out_min = pll->lcd_pll_out_min;
1148                 pll_out_max = pll->lcd_pll_out_max;
1149         } else {
1150                 pll_out_min = pll->pll_out_min;
1151                 pll_out_max = pll->pll_out_max;
1152         }
1153
1154         if (pll_out_min > 64800)
1155                 pll_out_min = 64800;
1156
1157         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1158                 min_ref_div = max_ref_div = pll->reference_div;
1159         else {
1160                 while (min_ref_div < max_ref_div-1) {
1161                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1162                         uint32_t pll_in = pll->reference_freq / mid;
1163                         if (pll_in < pll->pll_in_min)
1164                                 max_ref_div = mid;
1165                         else if (pll_in > pll->pll_in_max)
1166                                 min_ref_div = mid;
1167                         else
1168                                 break;
1169                 }
1170         }
1171
1172         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1173                 min_post_div = max_post_div = pll->post_div;
1174
1175         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1176                 min_fractional_feed_div = pll->min_frac_feedback_div;
1177                 max_fractional_feed_div = pll->max_frac_feedback_div;
1178         }
1179
1180         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1181                 uint32_t ref_div;
1182
1183                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1184                         continue;
1185
1186                 /* legacy radeons only have a few post_divs */
1187                 if (pll->flags & RADEON_PLL_LEGACY) {
1188                         if ((post_div == 5) ||
1189                             (post_div == 7) ||
1190                             (post_div == 9) ||
1191                             (post_div == 10) ||
1192                             (post_div == 11) ||
1193                             (post_div == 13) ||
1194                             (post_div == 14) ||
1195                             (post_div == 15))
1196                                 continue;
1197                 }
1198
1199                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1200                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1201                         uint32_t pll_in = pll->reference_freq / ref_div;
1202                         uint32_t min_feed_div = pll->min_feedback_div;
1203                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1204
1205                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1206                                 continue;
1207
1208                         while (min_feed_div < max_feed_div) {
1209                                 uint32_t vco;
1210                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1211                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1212                                 uint32_t frac_feedback_div;
1213                                 uint64_t tmp;
1214
1215                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1216
1217                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1218                                 vco = radeon_div(tmp, ref_div);
1219
1220                                 if (vco < pll_out_min) {
1221                                         min_feed_div = feedback_div + 1;
1222                                         continue;
1223                                 } else if (vco > pll_out_max) {
1224                                         max_feed_div = feedback_div;
1225                                         continue;
1226                                 }
1227
1228                                 while (min_frac_feed_div < max_frac_feed_div) {
1229                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1230                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1231                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1232                                         current_freq = radeon_div(tmp, ref_div * post_div);
1233
1234                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1235                                                 if (freq < current_freq)
1236                                                         error = 0xffffffff;
1237                                                 else
1238                                                         error = freq - current_freq;
1239                                         } else
1240                                                 error = abs(current_freq - freq);
1241                                         vco_diff = abs(vco - best_vco);
1242
1243                                         if ((best_vco == 0 && error < best_error) ||
1244                                             (best_vco != 0 &&
1245                                              ((best_error > 100 && error < best_error - 100) ||
1246                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1247                                                 best_post_div = post_div;
1248                                                 best_ref_div = ref_div;
1249                                                 best_feedback_div = feedback_div;
1250                                                 best_frac_feedback_div = frac_feedback_div;
1251                                                 best_freq = current_freq;
1252                                                 best_error = error;
1253                                                 best_vco_diff = vco_diff;
1254                                         } else if (current_freq == freq) {
1255                                                 if (best_freq == -1) {
1256                                                         best_post_div = post_div;
1257                                                         best_ref_div = ref_div;
1258                                                         best_feedback_div = feedback_div;
1259                                                         best_frac_feedback_div = frac_feedback_div;
1260                                                         best_freq = current_freq;
1261                                                         best_error = error;
1262                                                         best_vco_diff = vco_diff;
1263                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1264                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1265                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1266                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1267                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1268                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1269                                                         best_post_div = post_div;
1270                                                         best_ref_div = ref_div;
1271                                                         best_feedback_div = feedback_div;
1272                                                         best_frac_feedback_div = frac_feedback_div;
1273                                                         best_freq = current_freq;
1274                                                         best_error = error;
1275                                                         best_vco_diff = vco_diff;
1276                                                 }
1277                                         }
1278                                         if (current_freq < freq)
1279                                                 min_frac_feed_div = frac_feedback_div + 1;
1280                                         else
1281                                                 max_frac_feed_div = frac_feedback_div;
1282                                 }
1283                                 if (current_freq < freq)
1284                                         min_feed_div = feedback_div + 1;
1285                                 else
1286                                         max_feed_div = feedback_div;
1287                         }
1288                 }
1289         }
1290
1291         *dot_clock_p = best_freq / 10000;
1292         *fb_div_p = best_feedback_div;
1293         *frac_fb_div_p = best_frac_feedback_div;
1294         *ref_div_p = best_ref_div;
1295         *post_div_p = best_post_div;
1296         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1297                       (long long)freq,
1298                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1299                       best_ref_div, best_post_div);
1300
1301 }
1302
1303 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1304 {
1305         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1306
1307         drm_gem_object_unreference_unlocked(radeon_fb->obj);
1308         drm_framebuffer_cleanup(fb);
1309         kfree(radeon_fb);
1310 }
1311
1312 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1313                                                   struct drm_file *file_priv,
1314                                                   unsigned int *handle)
1315 {
1316         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1317
1318         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1319 }
1320
1321 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1322         .destroy = radeon_user_framebuffer_destroy,
1323         .create_handle = radeon_user_framebuffer_create_handle,
1324 };
1325
1326 int
1327 radeon_framebuffer_init(struct drm_device *dev,
1328                         struct radeon_framebuffer *rfb,
1329                         const struct drm_mode_fb_cmd2 *mode_cmd,
1330                         struct drm_gem_object *obj)
1331 {
1332         int ret;
1333         rfb->obj = obj;
1334         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1335         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1336         if (ret) {
1337                 rfb->obj = NULL;
1338                 return ret;
1339         }
1340         return 0;
1341 }
1342
1343 static struct drm_framebuffer *
1344 radeon_user_framebuffer_create(struct drm_device *dev,
1345                                struct drm_file *file_priv,
1346                                const struct drm_mode_fb_cmd2 *mode_cmd)
1347 {
1348         struct drm_gem_object *obj;
1349         struct radeon_framebuffer *radeon_fb;
1350         int ret;
1351
1352         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1353         if (obj ==  NULL) {
1354                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1355                         "can't create framebuffer\n", mode_cmd->handles[0]);
1356                 return ERR_PTR(-ENOENT);
1357         }
1358
1359         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1360         if (obj->import_attach) {
1361                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1362                 return ERR_PTR(-EINVAL);
1363         }
1364
1365         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1366         if (radeon_fb == NULL) {
1367                 drm_gem_object_unreference_unlocked(obj);
1368                 return ERR_PTR(-ENOMEM);
1369         }
1370
1371         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1372         if (ret) {
1373                 kfree(radeon_fb);
1374                 drm_gem_object_unreference_unlocked(obj);
1375                 return ERR_PTR(ret);
1376         }
1377
1378         return &radeon_fb->base;
1379 }
1380
1381 static void radeon_output_poll_changed(struct drm_device *dev)
1382 {
1383         struct radeon_device *rdev = dev->dev_private;
1384         radeon_fb_output_poll_changed(rdev);
1385 }
1386
1387 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1388         .fb_create = radeon_user_framebuffer_create,
1389         .output_poll_changed = radeon_output_poll_changed
1390 };
1391
1392 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1393 {       { 0, "driver" },
1394         { 1, "bios" },
1395 };
1396
1397 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1398 {       { TV_STD_NTSC, "ntsc" },
1399         { TV_STD_PAL, "pal" },
1400         { TV_STD_PAL_M, "pal-m" },
1401         { TV_STD_PAL_60, "pal-60" },
1402         { TV_STD_NTSC_J, "ntsc-j" },
1403         { TV_STD_SCART_PAL, "scart-pal" },
1404         { TV_STD_PAL_CN, "pal-cn" },
1405         { TV_STD_SECAM, "secam" },
1406 };
1407
1408 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1409 {       { UNDERSCAN_OFF, "off" },
1410         { UNDERSCAN_ON, "on" },
1411         { UNDERSCAN_AUTO, "auto" },
1412 };
1413
1414 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1415 {       { RADEON_AUDIO_DISABLE, "off" },
1416         { RADEON_AUDIO_ENABLE, "on" },
1417         { RADEON_AUDIO_AUTO, "auto" },
1418 };
1419
1420 /* XXX support different dither options? spatial, temporal, both, etc. */
1421 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1422 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1423         { RADEON_FMT_DITHER_ENABLE, "on" },
1424 };
1425
1426 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1427 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1428         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1429         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1430         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1431 };
1432
1433 static int radeon_modeset_create_props(struct radeon_device *rdev)
1434 {
1435         int sz;
1436
1437         if (rdev->is_atom_bios) {
1438                 rdev->mode_info.coherent_mode_property =
1439                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1440                 if (!rdev->mode_info.coherent_mode_property)
1441                         return -ENOMEM;
1442         }
1443
1444         if (!ASIC_IS_AVIVO(rdev)) {
1445                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1446                 rdev->mode_info.tmds_pll_property =
1447                         drm_property_create_enum(rdev->ddev, 0,
1448                                             "tmds_pll",
1449                                             radeon_tmds_pll_enum_list, sz);
1450         }
1451
1452         rdev->mode_info.load_detect_property =
1453                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1454         if (!rdev->mode_info.load_detect_property)
1455                 return -ENOMEM;
1456
1457         drm_mode_create_scaling_mode_property(rdev->ddev);
1458
1459         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1460         rdev->mode_info.tv_std_property =
1461                 drm_property_create_enum(rdev->ddev, 0,
1462                                     "tv standard",
1463                                     radeon_tv_std_enum_list, sz);
1464
1465         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1466         rdev->mode_info.underscan_property =
1467                 drm_property_create_enum(rdev->ddev, 0,
1468                                     "underscan",
1469                                     radeon_underscan_enum_list, sz);
1470
1471         rdev->mode_info.underscan_hborder_property =
1472                 drm_property_create_range(rdev->ddev, 0,
1473                                         "underscan hborder", 0, 128);
1474         if (!rdev->mode_info.underscan_hborder_property)
1475                 return -ENOMEM;
1476
1477         rdev->mode_info.underscan_vborder_property =
1478                 drm_property_create_range(rdev->ddev, 0,
1479                                         "underscan vborder", 0, 128);
1480         if (!rdev->mode_info.underscan_vborder_property)
1481                 return -ENOMEM;
1482
1483         sz = ARRAY_SIZE(radeon_audio_enum_list);
1484         rdev->mode_info.audio_property =
1485                 drm_property_create_enum(rdev->ddev, 0,
1486                                          "audio",
1487                                          radeon_audio_enum_list, sz);
1488
1489         sz = ARRAY_SIZE(radeon_dither_enum_list);
1490         rdev->mode_info.dither_property =
1491                 drm_property_create_enum(rdev->ddev, 0,
1492                                          "dither",
1493                                          radeon_dither_enum_list, sz);
1494
1495         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1496         rdev->mode_info.output_csc_property =
1497                 drm_property_create_enum(rdev->ddev, 0,
1498                                          "output_csc",
1499                                          radeon_output_csc_enum_list, sz);
1500
1501         return 0;
1502 }
1503
1504 void radeon_update_display_priority(struct radeon_device *rdev)
1505 {
1506         /* adjustment options for the display watermarks */
1507         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1508                 /* set display priority to high for r3xx, rv515 chips
1509                  * this avoids flickering due to underflow to the
1510                  * display controllers during heavy acceleration.
1511                  * Don't force high on rs4xx igp chips as it seems to
1512                  * affect the sound card.  See kernel bug 15982.
1513                  */
1514                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1515                     !(rdev->flags & RADEON_IS_IGP))
1516                         rdev->disp_priority = 2;
1517                 else
1518                         rdev->disp_priority = 0;
1519         } else
1520                 rdev->disp_priority = radeon_disp_priority;
1521
1522 }
1523
1524 /*
1525  * Allocate hdmi structs and determine register offsets
1526  */
1527 static void radeon_afmt_init(struct radeon_device *rdev)
1528 {
1529         int i;
1530
1531         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1532                 rdev->mode_info.afmt[i] = NULL;
1533
1534         if (ASIC_IS_NODCE(rdev)) {
1535                 /* nothing to do */
1536         } else if (ASIC_IS_DCE4(rdev)) {
1537                 static uint32_t eg_offsets[] = {
1538                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1539                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1540                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1541                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1542                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1543                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1544                         0x13830 - 0x7030,
1545                 };
1546                 int num_afmt;
1547
1548                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1549                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1550                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1551                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1552                 if (ASIC_IS_DCE8(rdev))
1553                         num_afmt = 7;
1554                 else if (ASIC_IS_DCE6(rdev))
1555                         num_afmt = 6;
1556                 else if (ASIC_IS_DCE5(rdev))
1557                         num_afmt = 6;
1558                 else if (ASIC_IS_DCE41(rdev))
1559                         num_afmt = 2;
1560                 else /* DCE4 */
1561                         num_afmt = 6;
1562
1563                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1564                 for (i = 0; i < num_afmt; i++) {
1565                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1566                         if (rdev->mode_info.afmt[i]) {
1567                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1568                                 rdev->mode_info.afmt[i]->id = i;
1569                         }
1570                 }
1571         } else if (ASIC_IS_DCE3(rdev)) {
1572                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1573                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1574                 if (rdev->mode_info.afmt[0]) {
1575                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1576                         rdev->mode_info.afmt[0]->id = 0;
1577                 }
1578                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1579                 if (rdev->mode_info.afmt[1]) {
1580                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1581                         rdev->mode_info.afmt[1]->id = 1;
1582                 }
1583         } else if (ASIC_IS_DCE2(rdev)) {
1584                 /* DCE2 has at least 1 routable audio block */
1585                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1586                 if (rdev->mode_info.afmt[0]) {
1587                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1588                         rdev->mode_info.afmt[0]->id = 0;
1589                 }
1590                 /* r6xx has 2 routable audio blocks */
1591                 if (rdev->family >= CHIP_R600) {
1592                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1593                         if (rdev->mode_info.afmt[1]) {
1594                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1595                                 rdev->mode_info.afmt[1]->id = 1;
1596                         }
1597                 }
1598         }
1599 }
1600
1601 static void radeon_afmt_fini(struct radeon_device *rdev)
1602 {
1603         int i;
1604
1605         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1606                 kfree(rdev->mode_info.afmt[i]);
1607                 rdev->mode_info.afmt[i] = NULL;
1608         }
1609 }
1610
1611 int radeon_modeset_init(struct radeon_device *rdev)
1612 {
1613         int i;
1614         int ret;
1615
1616         drm_mode_config_init(rdev->ddev);
1617         rdev->mode_info.mode_config_initialized = true;
1618
1619         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1620
1621         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1622                 rdev->ddev->mode_config.async_page_flip = true;
1623
1624         if (ASIC_IS_DCE5(rdev)) {
1625                 rdev->ddev->mode_config.max_width = 16384;
1626                 rdev->ddev->mode_config.max_height = 16384;
1627         } else if (ASIC_IS_AVIVO(rdev)) {
1628                 rdev->ddev->mode_config.max_width = 8192;
1629                 rdev->ddev->mode_config.max_height = 8192;
1630         } else {
1631                 rdev->ddev->mode_config.max_width = 4096;
1632                 rdev->ddev->mode_config.max_height = 4096;
1633         }
1634
1635         rdev->ddev->mode_config.preferred_depth = 24;
1636         rdev->ddev->mode_config.prefer_shadow = 1;
1637
1638         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1639
1640         ret = radeon_modeset_create_props(rdev);
1641         if (ret) {
1642                 return ret;
1643         }
1644
1645         /* init i2c buses */
1646         radeon_i2c_init(rdev);
1647
1648         /* check combios for a valid hardcoded EDID - Sun servers */
1649         if (!rdev->is_atom_bios) {
1650                 /* check for hardcoded EDID in BIOS */
1651                 radeon_combios_check_hardcoded_edid(rdev);
1652         }
1653
1654         /* allocate crtcs */
1655         for (i = 0; i < rdev->num_crtc; i++) {
1656                 radeon_crtc_init(rdev->ddev, i);
1657         }
1658
1659         /* okay we should have all the bios connectors */
1660         ret = radeon_setup_enc_conn(rdev->ddev);
1661         if (!ret) {
1662                 return ret;
1663         }
1664
1665         /* init dig PHYs, disp eng pll */
1666         if (rdev->is_atom_bios) {
1667                 radeon_atom_encoder_init(rdev);
1668                 radeon_atom_disp_eng_pll_init(rdev);
1669         }
1670
1671         /* initialize hpd */
1672         radeon_hpd_init(rdev);
1673
1674         /* setup afmt */
1675         radeon_afmt_init(rdev);
1676
1677         radeon_fbdev_init(rdev);
1678         drm_kms_helper_poll_init(rdev->ddev);
1679
1680         /* do pm late init */
1681         ret = radeon_pm_late_init(rdev);
1682
1683         return 0;
1684 }
1685
1686 void radeon_modeset_fini(struct radeon_device *rdev)
1687 {
1688         if (rdev->mode_info.mode_config_initialized) {
1689                 drm_kms_helper_poll_fini(rdev->ddev);
1690                 radeon_hpd_fini(rdev);
1691                 drm_crtc_force_disable_all(rdev->ddev);
1692                 radeon_fbdev_fini(rdev);
1693                 radeon_afmt_fini(rdev);
1694                 drm_mode_config_cleanup(rdev->ddev);
1695                 rdev->mode_info.mode_config_initialized = false;
1696         }
1697
1698         kfree(rdev->mode_info.bios_hardcoded_edid);
1699
1700         /* free i2c buses */
1701         radeon_i2c_fini(rdev);
1702 }
1703
1704 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1705 {
1706         /* try and guess if this is a tv or a monitor */
1707         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1708             (mode->vdisplay == 576) || /* 576p */
1709             (mode->vdisplay == 720) || /* 720p */
1710             (mode->vdisplay == 1080)) /* 1080p */
1711                 return true;
1712         else
1713                 return false;
1714 }
1715
1716 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1717                                 const struct drm_display_mode *mode,
1718                                 struct drm_display_mode *adjusted_mode)
1719 {
1720         struct drm_device *dev = crtc->dev;
1721         struct radeon_device *rdev = dev->dev_private;
1722         struct drm_encoder *encoder;
1723         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1724         struct radeon_encoder *radeon_encoder;
1725         struct drm_connector *connector;
1726         struct radeon_connector *radeon_connector;
1727         bool first = true;
1728         u32 src_v = 1, dst_v = 1;
1729         u32 src_h = 1, dst_h = 1;
1730
1731         radeon_crtc->h_border = 0;
1732         radeon_crtc->v_border = 0;
1733
1734         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1735                 if (encoder->crtc != crtc)
1736                         continue;
1737                 radeon_encoder = to_radeon_encoder(encoder);
1738                 connector = radeon_get_connector_for_encoder(encoder);
1739                 radeon_connector = to_radeon_connector(connector);
1740
1741                 if (first) {
1742                         /* set scaling */
1743                         if (radeon_encoder->rmx_type == RMX_OFF)
1744                                 radeon_crtc->rmx_type = RMX_OFF;
1745                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1746                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1747                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1748                         else
1749                                 radeon_crtc->rmx_type = RMX_OFF;
1750                         /* copy native mode */
1751                         memcpy(&radeon_crtc->native_mode,
1752                                &radeon_encoder->native_mode,
1753                                 sizeof(struct drm_display_mode));
1754                         src_v = crtc->mode.vdisplay;
1755                         dst_v = radeon_crtc->native_mode.vdisplay;
1756                         src_h = crtc->mode.hdisplay;
1757                         dst_h = radeon_crtc->native_mode.hdisplay;
1758
1759                         /* fix up for overscan on hdmi */
1760                         if (ASIC_IS_AVIVO(rdev) &&
1761                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1762                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1763                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1764                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1765                               is_hdtv_mode(mode)))) {
1766                                 if (radeon_encoder->underscan_hborder != 0)
1767                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1768                                 else
1769                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1770                                 if (radeon_encoder->underscan_vborder != 0)
1771                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1772                                 else
1773                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1774                                 radeon_crtc->rmx_type = RMX_FULL;
1775                                 src_v = crtc->mode.vdisplay;
1776                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1777                                 src_h = crtc->mode.hdisplay;
1778                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1779                         }
1780                         first = false;
1781                 } else {
1782                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1783                                 /* WARNING: Right now this can't happen but
1784                                  * in the future we need to check that scaling
1785                                  * are consistent across different encoder
1786                                  * (ie all encoder can work with the same
1787                                  *  scaling).
1788                                  */
1789                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1790                                 return false;
1791                         }
1792                 }
1793         }
1794         if (radeon_crtc->rmx_type != RMX_OFF) {
1795                 fixed20_12 a, b;
1796                 a.full = dfixed_const(src_v);
1797                 b.full = dfixed_const(dst_v);
1798                 radeon_crtc->vsc.full = dfixed_div(a, b);
1799                 a.full = dfixed_const(src_h);
1800                 b.full = dfixed_const(dst_h);
1801                 radeon_crtc->hsc.full = dfixed_div(a, b);
1802         } else {
1803                 radeon_crtc->vsc.full = dfixed_const(1);
1804                 radeon_crtc->hsc.full = dfixed_const(1);
1805         }
1806         return true;
1807 }
1808
1809 /*
1810  * Retrieve current video scanout position of crtc on a given gpu, and
1811  * an optional accurate timestamp of when query happened.
1812  *
1813  * \param dev Device to query.
1814  * \param crtc Crtc to query.
1815  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1816  *              For driver internal use only also supports these flags:
1817  *
1818  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1819  *              of a fudged earlier start of vblank.
1820  *
1821  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1822  *              fudged earlier start of vblank in *vpos and the distance
1823  *              to true start of vblank in *hpos.
1824  *
1825  * \param *vpos Location where vertical scanout position should be stored.
1826  * \param *hpos Location where horizontal scanout position should go.
1827  * \param *stime Target location for timestamp taken immediately before
1828  *               scanout position query. Can be NULL to skip timestamp.
1829  * \param *etime Target location for timestamp taken immediately after
1830  *               scanout position query. Can be NULL to skip timestamp.
1831  *
1832  * Returns vpos as a positive number while in active scanout area.
1833  * Returns vpos as a negative number inside vblank, counting the number
1834  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1835  * until start of active scanout / end of vblank."
1836  *
1837  * \return Flags, or'ed together as follows:
1838  *
1839  * DRM_SCANOUTPOS_VALID = Query successful.
1840  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1841  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1842  * this flag means that returned position may be offset by a constant but
1843  * unknown small number of scanlines wrt. real scanout position.
1844  *
1845  */
1846 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1847                                unsigned int flags, int *vpos, int *hpos,
1848                                ktime_t *stime, ktime_t *etime,
1849                                const struct drm_display_mode *mode)
1850 {
1851         u32 stat_crtc = 0, vbl = 0, position = 0;
1852         int vbl_start, vbl_end, vtotal, ret = 0;
1853         bool in_vbl = true;
1854
1855         struct radeon_device *rdev = dev->dev_private;
1856
1857         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1858
1859         /* Get optional system timestamp before query. */
1860         if (stime)
1861                 *stime = ktime_get();
1862
1863         if (ASIC_IS_DCE4(rdev)) {
1864                 if (pipe == 0) {
1865                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1866                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1867                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1868                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1869                         ret |= DRM_SCANOUTPOS_VALID;
1870                 }
1871                 if (pipe == 1) {
1872                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1873                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1874                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1875                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1876                         ret |= DRM_SCANOUTPOS_VALID;
1877                 }
1878                 if (pipe == 2) {
1879                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1880                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1881                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1882                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1883                         ret |= DRM_SCANOUTPOS_VALID;
1884                 }
1885                 if (pipe == 3) {
1886                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1887                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1888                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1889                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1890                         ret |= DRM_SCANOUTPOS_VALID;
1891                 }
1892                 if (pipe == 4) {
1893                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1894                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1895                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1896                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1897                         ret |= DRM_SCANOUTPOS_VALID;
1898                 }
1899                 if (pipe == 5) {
1900                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1901                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1902                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1903                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1904                         ret |= DRM_SCANOUTPOS_VALID;
1905                 }
1906         } else if (ASIC_IS_AVIVO(rdev)) {
1907                 if (pipe == 0) {
1908                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1909                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1910                         ret |= DRM_SCANOUTPOS_VALID;
1911                 }
1912                 if (pipe == 1) {
1913                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1914                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1915                         ret |= DRM_SCANOUTPOS_VALID;
1916                 }
1917         } else {
1918                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1919                 if (pipe == 0) {
1920                         /* Assume vbl_end == 0, get vbl_start from
1921                          * upper 16 bits.
1922                          */
1923                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1924                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1925                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1926                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1927                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1928                         if (!(stat_crtc & 1))
1929                                 in_vbl = false;
1930
1931                         ret |= DRM_SCANOUTPOS_VALID;
1932                 }
1933                 if (pipe == 1) {
1934                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1935                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1936                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1937                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1938                         if (!(stat_crtc & 1))
1939                                 in_vbl = false;
1940
1941                         ret |= DRM_SCANOUTPOS_VALID;
1942                 }
1943         }
1944
1945         /* Get optional system timestamp after query. */
1946         if (etime)
1947                 *etime = ktime_get();
1948
1949         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1950
1951         /* Decode into vertical and horizontal scanout position. */
1952         *vpos = position & 0x1fff;
1953         *hpos = (position >> 16) & 0x1fff;
1954
1955         /* Valid vblank area boundaries from gpu retrieved? */
1956         if (vbl > 0) {
1957                 /* Yes: Decode. */
1958                 ret |= DRM_SCANOUTPOS_ACCURATE;
1959                 vbl_start = vbl & 0x1fff;
1960                 vbl_end = (vbl >> 16) & 0x1fff;
1961         }
1962         else {
1963                 /* No: Fake something reasonable which gives at least ok results. */
1964                 vbl_start = mode->crtc_vdisplay;
1965                 vbl_end = 0;
1966         }
1967
1968         /* Called from driver internal vblank counter query code? */
1969         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1970             /* Caller wants distance from real vbl_start in *hpos */
1971             *hpos = *vpos - vbl_start;
1972         }
1973
1974         /* Fudge vblank to start a few scanlines earlier to handle the
1975          * problem that vblank irqs fire a few scanlines before start
1976          * of vblank. Some driver internal callers need the true vblank
1977          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1978          *
1979          * The cause of the "early" vblank irq is that the irq is triggered
1980          * by the line buffer logic when the line buffer read position enters
1981          * the vblank, whereas our crtc scanout position naturally lags the
1982          * line buffer read position.
1983          */
1984         if (!(flags & USE_REAL_VBLANKSTART))
1985                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1986
1987         /* Test scanout position against vblank region. */
1988         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1989                 in_vbl = false;
1990
1991         /* In vblank? */
1992         if (in_vbl)
1993             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1994
1995         /* Called from driver internal vblank counter query code? */
1996         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1997                 /* Caller wants distance from fudged earlier vbl_start */
1998                 *vpos -= vbl_start;
1999                 return ret;
2000         }
2001
2002         /* Check if inside vblank area and apply corrective offsets:
2003          * vpos will then be >=0 in video scanout area, but negative
2004          * within vblank area, counting down the number of lines until
2005          * start of scanout.
2006          */
2007
2008         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
2009         if (in_vbl && (*vpos >= vbl_start)) {
2010                 vtotal = mode->crtc_vtotal;
2011                 *vpos = *vpos - vtotal;
2012         }
2013
2014         /* Correct for shifted end of vbl at vbl_end. */
2015         *vpos = *vpos - vbl_end;
2016
2017         return ret;
2018 }