2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_edid.h>
38 #include <linux/gcd.h>
40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
59 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
63 for (i = 0; i < 256; i++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR,
65 (radeon_crtc->lut_r[i] << 20) |
66 (radeon_crtc->lut_g[i] << 10) |
67 (radeon_crtc->lut_b[i] << 0));
70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
77 struct drm_device *dev = crtc->dev;
78 struct radeon_device *rdev = dev->dev_private;
81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
96 for (i = 0; i < 256; i++) {
97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
98 (radeon_crtc->lut_r[i] << 20) |
99 (radeon_crtc->lut_g[i] << 10) |
100 (radeon_crtc->lut_b[i] << 0));
104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
107 struct drm_device *dev = crtc->dev;
108 struct radeon_device *rdev = dev->dev_private;
111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
115 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
116 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
117 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
118 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
119 NI_GRPH_PRESCALE_BYPASS);
120 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
121 NI_OVL_PRESCALE_BYPASS);
122 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
123 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
124 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
126 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
129 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
133 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
134 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
136 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
137 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
139 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
140 for (i = 0; i < 256; i++) {
141 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
142 (radeon_crtc->lut_r[i] << 20) |
143 (radeon_crtc->lut_g[i] << 10) |
144 (radeon_crtc->lut_b[i] << 0));
147 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
148 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
149 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
150 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
151 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
152 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
154 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
155 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
156 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
157 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
158 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
159 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
160 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
161 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
162 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
163 if (ASIC_IS_DCE8(rdev)) {
164 /* XXX this only needs to be programmed once per crtc at startup,
165 * not sure where the best place for it is
167 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
168 CIK_CURSOR_ALPHA_BLND_ENA);
172 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
174 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
175 struct drm_device *dev = crtc->dev;
176 struct radeon_device *rdev = dev->dev_private;
180 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
181 if (radeon_crtc->crtc_id == 0)
182 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
184 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
185 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
187 WREG8(RADEON_PALETTE_INDEX, 0);
188 for (i = 0; i < 256; i++) {
189 WREG32(RADEON_PALETTE_30_DATA,
190 (radeon_crtc->lut_r[i] << 20) |
191 (radeon_crtc->lut_g[i] << 10) |
192 (radeon_crtc->lut_b[i] << 0));
196 void radeon_crtc_load_lut(struct drm_crtc *crtc)
198 struct drm_device *dev = crtc->dev;
199 struct radeon_device *rdev = dev->dev_private;
204 if (ASIC_IS_DCE5(rdev))
205 dce5_crtc_load_lut(crtc);
206 else if (ASIC_IS_DCE4(rdev))
207 dce4_crtc_load_lut(crtc);
208 else if (ASIC_IS_AVIVO(rdev))
209 avivo_crtc_load_lut(crtc);
211 legacy_crtc_load_lut(crtc);
214 /** Sets the color ramps on behalf of fbcon */
215 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
220 radeon_crtc->lut_r[regno] = red >> 6;
221 radeon_crtc->lut_g[regno] = green >> 6;
222 radeon_crtc->lut_b[regno] = blue >> 6;
225 /** Gets the color ramps on behalf of fbcon */
226 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
227 u16 *blue, int regno)
229 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
231 *red = radeon_crtc->lut_r[regno] << 6;
232 *green = radeon_crtc->lut_g[regno] << 6;
233 *blue = radeon_crtc->lut_b[regno] << 6;
236 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
237 u16 *blue, uint32_t size)
239 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
242 /* userspace palettes are always correct as is */
243 for (i = 0; i < size; i++) {
244 radeon_crtc->lut_r[i] = red[i] >> 6;
245 radeon_crtc->lut_g[i] = green[i] >> 6;
246 radeon_crtc->lut_b[i] = blue[i] >> 6;
248 radeon_crtc_load_lut(crtc);
253 static void radeon_crtc_destroy(struct drm_crtc *crtc)
255 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
257 drm_crtc_cleanup(crtc);
258 destroy_workqueue(radeon_crtc->flip_queue);
263 * radeon_unpin_work_func - unpin old buffer object
265 * @__work - kernel work item
267 * Unpin the old frame buffer object outside of the interrupt handler
269 static void radeon_unpin_work_func(struct work_struct *__work)
271 struct radeon_flip_work *work =
272 container_of(__work, struct radeon_flip_work, unpin_work);
275 /* unpin of the old buffer */
276 r = radeon_bo_reserve(work->old_rbo, false);
277 if (likely(r == 0)) {
278 r = radeon_bo_unpin(work->old_rbo);
279 if (unlikely(r != 0)) {
280 DRM_ERROR("failed to unpin buffer after flip\n");
282 radeon_bo_unreserve(work->old_rbo);
284 DRM_ERROR("failed to reserve buffer after flip\n");
286 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
290 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
292 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
297 /* can happen during initialization */
298 if (radeon_crtc == NULL)
301 /* Skip the pageflip completion check below (based on polling) on
302 * asics which reliably support hw pageflip completion irqs. pflip
303 * irqs are a reliable and race-free method of handling pageflip
304 * completion detection. A use_pflipirq module parameter < 2 allows
305 * to override this in case of asics with faulty pflip irqs.
306 * A module parameter of 0 would only use this polling based path,
307 * a parameter of 1 would use pflip irq only as a backup to this
308 * path, as in Linux 3.16.
310 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
313 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
314 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
315 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
316 "RADEON_FLIP_SUBMITTED(%d)\n",
317 radeon_crtc->flip_status,
318 RADEON_FLIP_SUBMITTED);
319 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
323 update_pending = radeon_page_flip_pending(rdev, crtc_id);
325 /* Has the pageflip already completed in crtc, or is it certain
326 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
327 * distance to start of "fudged earlier" vblank in vpos, distance to
328 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
329 * the last few scanlines before start of real vblank, where the vblank
330 * irq can fire, so we have sampled update_pending a bit too early and
331 * know the flip will complete at leading edge of the upcoming real
332 * vblank. On pre-AVIVO hardware, flips also complete inside the real
333 * vblank, not only at leading edge, so if update_pending for hpos >= 0
334 * == inside real vblank, the flip will complete almost immediately.
335 * Note that this method of completion handling is still not 100% race
336 * free, as we could execute before the radeon_flip_work_func managed
337 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
338 * but the flip still gets programmed into hw and completed during
339 * vblank, leading to a delayed emission of the flip completion event.
340 * This applies at least to pre-AVIVO hardware, where flips are always
341 * completing inside vblank, not only at leading edge of vblank.
343 if (update_pending &&
344 (DRM_SCANOUTPOS_VALID &
345 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
346 GET_DISTANCE_TO_VBLANKSTART,
347 &vpos, &hpos, NULL, NULL,
348 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
349 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
350 /* crtc didn't flip in this target vblank interval,
351 * but flip is pending in crtc. Based on the current
352 * scanout position we know that the current frame is
353 * (nearly) complete and the flip will (likely)
354 * complete before the start of the next frame.
358 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
360 radeon_crtc_handle_flip(rdev, crtc_id);
364 * radeon_crtc_handle_flip - page flip completed
366 * @rdev: radeon device pointer
367 * @crtc_id: crtc number this event is for
369 * Called when we are sure that a page flip for this crtc is completed.
371 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
373 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
374 struct radeon_flip_work *work;
377 /* this can happen at init */
378 if (radeon_crtc == NULL)
381 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
382 work = radeon_crtc->flip_work;
383 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
384 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
385 "RADEON_FLIP_SUBMITTED(%d)\n",
386 radeon_crtc->flip_status,
387 RADEON_FLIP_SUBMITTED);
388 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
392 /* Pageflip completed. Clean up. */
393 radeon_crtc->flip_status = RADEON_FLIP_NONE;
394 radeon_crtc->flip_work = NULL;
396 /* wakeup userspace */
398 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
400 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
402 drm_crtc_vblank_put(&radeon_crtc->base);
403 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
404 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
408 * radeon_flip_work_func - page flip framebuffer
410 * @work - kernel work item
412 * Wait for the buffer object to become idle and do the actual page flip
414 static void radeon_flip_work_func(struct work_struct *__work)
416 struct radeon_flip_work *work =
417 container_of(__work, struct radeon_flip_work, flip_work);
418 struct radeon_device *rdev = work->rdev;
419 struct drm_device *dev = rdev->ddev;
420 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
422 struct drm_crtc *crtc = &radeon_crtc->base;
427 down_read(&rdev->exclusive_lock);
429 struct radeon_fence *fence;
431 fence = to_radeon_fence(work->fence);
432 if (fence && fence->rdev == rdev) {
433 r = radeon_fence_wait(fence, false);
435 up_read(&rdev->exclusive_lock);
437 r = radeon_gpu_reset(rdev);
438 } while (r == -EAGAIN);
439 down_read(&rdev->exclusive_lock);
442 r = fence_wait(work->fence, false);
445 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
447 /* We continue with the page flip even if we failed to wait on
448 * the fence, otherwise the DRM core and userspace will be
449 * confused about which BO the CRTC is scanning out
452 fence_put(work->fence);
456 /* Wait until we're out of the vertical blank period before the one
457 * targeted by the flip. Always wait on pre DCE4 to avoid races with
458 * flip completion handling from vblank irq, as these old asics don't
459 * have reliable pageflip completion interrupts.
461 while (radeon_crtc->enabled &&
462 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
463 &vpos, &hpos, NULL, NULL,
465 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
466 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
467 (!ASIC_IS_AVIVO(rdev) ||
468 ((int) (work->target_vblank -
469 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)))
470 usleep_range(1000, 2000);
472 /* We borrow the event spin lock for protecting flip_status */
473 spin_lock_irqsave(&crtc->dev->event_lock, flags);
475 /* set the proper interrupt */
476 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
478 /* do the flip (mmio) */
479 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
481 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
482 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
483 up_read(&rdev->exclusive_lock);
486 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
487 struct drm_framebuffer *fb,
488 struct drm_pending_vblank_event *event,
489 uint32_t page_flip_flags,
492 struct drm_device *dev = crtc->dev;
493 struct radeon_device *rdev = dev->dev_private;
494 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
495 struct radeon_framebuffer *old_radeon_fb;
496 struct radeon_framebuffer *new_radeon_fb;
497 struct drm_gem_object *obj;
498 struct radeon_flip_work *work;
499 struct radeon_bo *new_rbo;
500 uint32_t tiling_flags, pitch_pixels;
505 work = kzalloc(sizeof *work, GFP_KERNEL);
509 INIT_WORK(&work->flip_work, radeon_flip_work_func);
510 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
513 work->crtc_id = radeon_crtc->crtc_id;
515 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
517 /* schedule unpin of the old buffer */
518 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
519 obj = old_radeon_fb->obj;
521 /* take a reference to the old object */
522 drm_gem_object_reference(obj);
523 work->old_rbo = gem_to_radeon_bo(obj);
525 new_radeon_fb = to_radeon_framebuffer(fb);
526 obj = new_radeon_fb->obj;
527 new_rbo = gem_to_radeon_bo(obj);
529 /* pin the new buffer */
530 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
531 work->old_rbo, new_rbo);
533 r = radeon_bo_reserve(new_rbo, false);
534 if (unlikely(r != 0)) {
535 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
538 /* Only 27 bit offset for legacy CRTC */
539 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
540 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
541 if (unlikely(r != 0)) {
542 radeon_bo_unreserve(new_rbo);
544 DRM_ERROR("failed to pin new rbo buffer before flip\n");
547 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
548 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
549 radeon_bo_unreserve(new_rbo);
551 if (!ASIC_IS_AVIVO(rdev)) {
552 /* crtc offset is from display base addr not FB location */
553 base -= radeon_crtc->legacy_display_base_addr;
554 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
556 if (tiling_flags & RADEON_TILING_MACRO) {
557 if (ASIC_IS_R300(rdev)) {
560 int byteshift = fb->bits_per_pixel >> 4;
561 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
562 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
565 int offset = crtc->y * pitch_pixels + crtc->x;
566 switch (fb->bits_per_pixel) {
587 work->target_vblank = target - drm_crtc_vblank_count(crtc) +
588 dev->driver->get_vblank_counter(dev, work->crtc_id);
590 /* We borrow the event spin lock for protecting flip_work */
591 spin_lock_irqsave(&crtc->dev->event_lock, flags);
593 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
594 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
595 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
599 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
600 radeon_crtc->flip_work = work;
603 crtc->primary->fb = fb;
605 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
607 queue_work(radeon_crtc->flip_queue, &work->flip_work);
611 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
612 DRM_ERROR("failed to reserve new rbo in error path\n");
615 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
616 DRM_ERROR("failed to unpin new rbo in error path\n");
618 radeon_bo_unreserve(new_rbo);
621 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
622 fence_put(work->fence);
628 radeon_crtc_set_config(struct drm_mode_set *set)
630 struct drm_device *dev;
631 struct radeon_device *rdev;
632 struct drm_crtc *crtc;
636 if (!set || !set->crtc)
639 dev = set->crtc->dev;
641 ret = pm_runtime_get_sync(dev->dev);
643 pm_runtime_put_autosuspend(dev->dev);
647 ret = drm_crtc_helper_set_config(set);
649 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
653 pm_runtime_mark_last_busy(dev->dev);
655 rdev = dev->dev_private;
656 /* if we have active crtcs and we don't have a power ref,
657 take the current one */
658 if (active && !rdev->have_disp_power_ref) {
659 rdev->have_disp_power_ref = true;
662 /* if we have no active crtcs, then drop the power ref
664 if (!active && rdev->have_disp_power_ref) {
665 pm_runtime_put_autosuspend(dev->dev);
666 rdev->have_disp_power_ref = false;
669 /* drop the power reference we got coming in here */
670 pm_runtime_put_autosuspend(dev->dev);
674 static const struct drm_crtc_funcs radeon_crtc_funcs = {
675 .cursor_set2 = radeon_crtc_cursor_set2,
676 .cursor_move = radeon_crtc_cursor_move,
677 .gamma_set = radeon_crtc_gamma_set,
678 .set_config = radeon_crtc_set_config,
679 .destroy = radeon_crtc_destroy,
680 .page_flip_target = radeon_crtc_page_flip_target,
683 static void radeon_crtc_init(struct drm_device *dev, int index)
685 struct radeon_device *rdev = dev->dev_private;
686 struct radeon_crtc *radeon_crtc;
689 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
690 if (radeon_crtc == NULL)
693 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
695 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
696 radeon_crtc->crtc_id = index;
697 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
698 rdev->mode_info.crtcs[index] = radeon_crtc;
700 if (rdev->family >= CHIP_BONAIRE) {
701 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
702 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
704 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
705 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
707 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
708 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
711 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
712 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
713 radeon_crtc->mode_set.num_connectors = 0;
716 for (i = 0; i < 256; i++) {
717 radeon_crtc->lut_r[i] = i << 2;
718 radeon_crtc->lut_g[i] = i << 2;
719 radeon_crtc->lut_b[i] = i << 2;
722 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
723 radeon_atombios_init_crtc(dev, radeon_crtc);
725 radeon_legacy_init_crtc(dev, radeon_crtc);
728 static const char *encoder_names[38] = {
748 "INTERNAL_KLDSCP_TMDS1",
749 "INTERNAL_KLDSCP_DVO1",
750 "INTERNAL_KLDSCP_DAC1",
751 "INTERNAL_KLDSCP_DAC2",
760 "INTERNAL_KLDSCP_LVTMA",
769 static const char *hpd_names[6] = {
778 static void radeon_print_display_setup(struct drm_device *dev)
780 struct drm_connector *connector;
781 struct radeon_connector *radeon_connector;
782 struct drm_encoder *encoder;
783 struct radeon_encoder *radeon_encoder;
787 DRM_INFO("Radeon Display Connectors\n");
788 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
789 radeon_connector = to_radeon_connector(connector);
790 DRM_INFO("Connector %d:\n", i);
791 DRM_INFO(" %s\n", connector->name);
792 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
793 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
794 if (radeon_connector->ddc_bus) {
795 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
796 radeon_connector->ddc_bus->rec.mask_clk_reg,
797 radeon_connector->ddc_bus->rec.mask_data_reg,
798 radeon_connector->ddc_bus->rec.a_clk_reg,
799 radeon_connector->ddc_bus->rec.a_data_reg,
800 radeon_connector->ddc_bus->rec.en_clk_reg,
801 radeon_connector->ddc_bus->rec.en_data_reg,
802 radeon_connector->ddc_bus->rec.y_clk_reg,
803 radeon_connector->ddc_bus->rec.y_data_reg);
804 if (radeon_connector->router.ddc_valid)
805 DRM_INFO(" DDC Router 0x%x/0x%x\n",
806 radeon_connector->router.ddc_mux_control_pin,
807 radeon_connector->router.ddc_mux_state);
808 if (radeon_connector->router.cd_valid)
809 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
810 radeon_connector->router.cd_mux_control_pin,
811 radeon_connector->router.cd_mux_state);
813 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
814 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
815 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
816 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
817 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
818 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
819 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
821 DRM_INFO(" Encoders:\n");
822 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
823 radeon_encoder = to_radeon_encoder(encoder);
824 devices = radeon_encoder->devices & radeon_connector->devices;
826 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
827 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
828 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
829 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
830 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
831 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
832 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
833 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
834 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
835 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
836 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
837 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
838 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
839 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
840 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
841 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
842 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
843 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
844 if (devices & ATOM_DEVICE_TV1_SUPPORT)
845 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
846 if (devices & ATOM_DEVICE_CV_SUPPORT)
847 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
854 static bool radeon_setup_enc_conn(struct drm_device *dev)
856 struct radeon_device *rdev = dev->dev_private;
860 if (rdev->is_atom_bios) {
861 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
863 ret = radeon_get_atom_connector_info_from_object_table(dev);
865 ret = radeon_get_legacy_connector_info_from_bios(dev);
867 ret = radeon_get_legacy_connector_info_from_table(dev);
870 if (!ASIC_IS_AVIVO(rdev))
871 ret = radeon_get_legacy_connector_info_from_table(dev);
874 radeon_setup_encoder_clones(dev);
875 radeon_print_display_setup(dev);
884 * avivo_reduce_ratio - fractional number reduction
888 * @nom_min: minimum value for nominator
889 * @den_min: minimum value for denominator
891 * Find the greatest common divisor and apply it on both nominator and
892 * denominator, but make nominator and denominator are at least as large
893 * as their minimum values.
895 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
896 unsigned nom_min, unsigned den_min)
900 /* reduce the numbers to a simpler ratio */
901 tmp = gcd(*nom, *den);
905 /* make sure nominator is large enough */
906 if (*nom < nom_min) {
907 tmp = DIV_ROUND_UP(nom_min, *nom);
912 /* make sure the denominator is large enough */
913 if (*den < den_min) {
914 tmp = DIV_ROUND_UP(den_min, *den);
921 * avivo_get_fb_ref_div - feedback and ref divider calculation
925 * @post_div: post divider
926 * @fb_div_max: feedback divider maximum
927 * @ref_div_max: reference divider maximum
928 * @fb_div: resulting feedback divider
929 * @ref_div: resulting reference divider
931 * Calculate feedback and reference divider for a given post divider. Makes
932 * sure we stay within the limits.
934 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
935 unsigned fb_div_max, unsigned ref_div_max,
936 unsigned *fb_div, unsigned *ref_div)
938 /* limit reference * post divider to a maximum */
939 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
941 /* get matching reference and feedback divider */
942 *ref_div = min(max(den/post_div, 1u), ref_div_max);
943 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
945 /* limit fb divider to its maximum */
946 if (*fb_div > fb_div_max) {
947 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
948 *fb_div = fb_div_max;
953 * radeon_compute_pll_avivo - compute PLL paramaters
955 * @pll: information about the PLL
956 * @dot_clock_p: resulting pixel clock
957 * fb_div_p: resulting feedback divider
958 * frac_fb_div_p: fractional part of the feedback divider
959 * ref_div_p: resulting reference divider
960 * post_div_p: resulting reference divider
962 * Try to calculate the PLL parameters to generate the given frequency:
963 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
965 void radeon_compute_pll_avivo(struct radeon_pll *pll,
973 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
976 unsigned fb_div_min, fb_div_max, fb_div;
977 unsigned post_div_min, post_div_max, post_div;
978 unsigned ref_div_min, ref_div_max, ref_div;
979 unsigned post_div_best, diff_best;
982 /* determine allowed feedback divider range */
983 fb_div_min = pll->min_feedback_div;
984 fb_div_max = pll->max_feedback_div;
986 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
991 /* determine allowed ref divider range */
992 if (pll->flags & RADEON_PLL_USE_REF_DIV)
993 ref_div_min = pll->reference_div;
995 ref_div_min = pll->min_ref_div;
997 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
998 pll->flags & RADEON_PLL_USE_REF_DIV)
999 ref_div_max = pll->reference_div;
1000 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1001 /* fix for problems on RS880 */
1002 ref_div_max = min(pll->max_ref_div, 7u);
1004 ref_div_max = pll->max_ref_div;
1006 /* determine allowed post divider range */
1007 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1008 post_div_min = pll->post_div;
1009 post_div_max = pll->post_div;
1011 unsigned vco_min, vco_max;
1013 if (pll->flags & RADEON_PLL_IS_LCD) {
1014 vco_min = pll->lcd_pll_out_min;
1015 vco_max = pll->lcd_pll_out_max;
1017 vco_min = pll->pll_out_min;
1018 vco_max = pll->pll_out_max;
1021 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1026 post_div_min = vco_min / target_clock;
1027 if ((target_clock * post_div_min) < vco_min)
1029 if (post_div_min < pll->min_post_div)
1030 post_div_min = pll->min_post_div;
1032 post_div_max = vco_max / target_clock;
1033 if ((target_clock * post_div_max) > vco_max)
1035 if (post_div_max > pll->max_post_div)
1036 post_div_max = pll->max_post_div;
1039 /* represent the searched ratio as fractional number */
1041 den = pll->reference_freq;
1043 /* reduce the numbers to a simpler ratio */
1044 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1046 /* now search for a post divider */
1047 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1048 post_div_best = post_div_min;
1050 post_div_best = post_div_max;
1053 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1055 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1056 ref_div_max, &fb_div, &ref_div);
1057 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1058 (ref_div * post_div));
1060 if (diff < diff_best || (diff == diff_best &&
1061 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1063 post_div_best = post_div;
1067 post_div = post_div_best;
1069 /* get the feedback and reference divider for the optimal value */
1070 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1073 /* reduce the numbers to a simpler ratio once more */
1074 /* this also makes sure that the reference divider is large enough */
1075 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1077 /* avoid high jitter with small fractional dividers */
1078 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1079 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1080 if (fb_div < fb_div_min) {
1081 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1087 /* and finally save the result */
1088 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1089 *fb_div_p = fb_div / 10;
1090 *frac_fb_div_p = fb_div % 10;
1096 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1097 (pll->reference_freq * *frac_fb_div_p)) /
1098 (ref_div * post_div * 10);
1099 *ref_div_p = ref_div;
1100 *post_div_p = post_div;
1102 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1103 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1108 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1118 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1120 uint32_t *dot_clock_p,
1122 uint32_t *frac_fb_div_p,
1123 uint32_t *ref_div_p,
1124 uint32_t *post_div_p)
1126 uint32_t min_ref_div = pll->min_ref_div;
1127 uint32_t max_ref_div = pll->max_ref_div;
1128 uint32_t min_post_div = pll->min_post_div;
1129 uint32_t max_post_div = pll->max_post_div;
1130 uint32_t min_fractional_feed_div = 0;
1131 uint32_t max_fractional_feed_div = 0;
1132 uint32_t best_vco = pll->best_vco;
1133 uint32_t best_post_div = 1;
1134 uint32_t best_ref_div = 1;
1135 uint32_t best_feedback_div = 1;
1136 uint32_t best_frac_feedback_div = 0;
1137 uint32_t best_freq = -1;
1138 uint32_t best_error = 0xffffffff;
1139 uint32_t best_vco_diff = 1;
1141 u32 pll_out_min, pll_out_max;
1143 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1146 if (pll->flags & RADEON_PLL_IS_LCD) {
1147 pll_out_min = pll->lcd_pll_out_min;
1148 pll_out_max = pll->lcd_pll_out_max;
1150 pll_out_min = pll->pll_out_min;
1151 pll_out_max = pll->pll_out_max;
1154 if (pll_out_min > 64800)
1155 pll_out_min = 64800;
1157 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1158 min_ref_div = max_ref_div = pll->reference_div;
1160 while (min_ref_div < max_ref_div-1) {
1161 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1162 uint32_t pll_in = pll->reference_freq / mid;
1163 if (pll_in < pll->pll_in_min)
1165 else if (pll_in > pll->pll_in_max)
1172 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1173 min_post_div = max_post_div = pll->post_div;
1175 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1176 min_fractional_feed_div = pll->min_frac_feedback_div;
1177 max_fractional_feed_div = pll->max_frac_feedback_div;
1180 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1183 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1186 /* legacy radeons only have a few post_divs */
1187 if (pll->flags & RADEON_PLL_LEGACY) {
1188 if ((post_div == 5) ||
1199 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1200 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1201 uint32_t pll_in = pll->reference_freq / ref_div;
1202 uint32_t min_feed_div = pll->min_feedback_div;
1203 uint32_t max_feed_div = pll->max_feedback_div + 1;
1205 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1208 while (min_feed_div < max_feed_div) {
1210 uint32_t min_frac_feed_div = min_fractional_feed_div;
1211 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1212 uint32_t frac_feedback_div;
1215 feedback_div = (min_feed_div + max_feed_div) / 2;
1217 tmp = (uint64_t)pll->reference_freq * feedback_div;
1218 vco = radeon_div(tmp, ref_div);
1220 if (vco < pll_out_min) {
1221 min_feed_div = feedback_div + 1;
1223 } else if (vco > pll_out_max) {
1224 max_feed_div = feedback_div;
1228 while (min_frac_feed_div < max_frac_feed_div) {
1229 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1230 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1231 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1232 current_freq = radeon_div(tmp, ref_div * post_div);
1234 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1235 if (freq < current_freq)
1238 error = freq - current_freq;
1240 error = abs(current_freq - freq);
1241 vco_diff = abs(vco - best_vco);
1243 if ((best_vco == 0 && error < best_error) ||
1245 ((best_error > 100 && error < best_error - 100) ||
1246 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1247 best_post_div = post_div;
1248 best_ref_div = ref_div;
1249 best_feedback_div = feedback_div;
1250 best_frac_feedback_div = frac_feedback_div;
1251 best_freq = current_freq;
1253 best_vco_diff = vco_diff;
1254 } else if (current_freq == freq) {
1255 if (best_freq == -1) {
1256 best_post_div = post_div;
1257 best_ref_div = ref_div;
1258 best_feedback_div = feedback_div;
1259 best_frac_feedback_div = frac_feedback_div;
1260 best_freq = current_freq;
1262 best_vco_diff = vco_diff;
1263 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1264 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1265 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1266 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1267 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1268 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1269 best_post_div = post_div;
1270 best_ref_div = ref_div;
1271 best_feedback_div = feedback_div;
1272 best_frac_feedback_div = frac_feedback_div;
1273 best_freq = current_freq;
1275 best_vco_diff = vco_diff;
1278 if (current_freq < freq)
1279 min_frac_feed_div = frac_feedback_div + 1;
1281 max_frac_feed_div = frac_feedback_div;
1283 if (current_freq < freq)
1284 min_feed_div = feedback_div + 1;
1286 max_feed_div = feedback_div;
1291 *dot_clock_p = best_freq / 10000;
1292 *fb_div_p = best_feedback_div;
1293 *frac_fb_div_p = best_frac_feedback_div;
1294 *ref_div_p = best_ref_div;
1295 *post_div_p = best_post_div;
1296 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1298 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1299 best_ref_div, best_post_div);
1303 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1305 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1307 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1308 drm_framebuffer_cleanup(fb);
1312 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1313 struct drm_file *file_priv,
1314 unsigned int *handle)
1316 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1318 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1321 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1322 .destroy = radeon_user_framebuffer_destroy,
1323 .create_handle = radeon_user_framebuffer_create_handle,
1327 radeon_framebuffer_init(struct drm_device *dev,
1328 struct radeon_framebuffer *rfb,
1329 const struct drm_mode_fb_cmd2 *mode_cmd,
1330 struct drm_gem_object *obj)
1334 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1335 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1343 static struct drm_framebuffer *
1344 radeon_user_framebuffer_create(struct drm_device *dev,
1345 struct drm_file *file_priv,
1346 const struct drm_mode_fb_cmd2 *mode_cmd)
1348 struct drm_gem_object *obj;
1349 struct radeon_framebuffer *radeon_fb;
1352 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1354 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1355 "can't create framebuffer\n", mode_cmd->handles[0]);
1356 return ERR_PTR(-ENOENT);
1359 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1360 if (obj->import_attach) {
1361 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1362 return ERR_PTR(-EINVAL);
1365 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1366 if (radeon_fb == NULL) {
1367 drm_gem_object_unreference_unlocked(obj);
1368 return ERR_PTR(-ENOMEM);
1371 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1374 drm_gem_object_unreference_unlocked(obj);
1375 return ERR_PTR(ret);
1378 return &radeon_fb->base;
1381 static void radeon_output_poll_changed(struct drm_device *dev)
1383 struct radeon_device *rdev = dev->dev_private;
1384 radeon_fb_output_poll_changed(rdev);
1387 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1388 .fb_create = radeon_user_framebuffer_create,
1389 .output_poll_changed = radeon_output_poll_changed
1392 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1397 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1398 { { TV_STD_NTSC, "ntsc" },
1399 { TV_STD_PAL, "pal" },
1400 { TV_STD_PAL_M, "pal-m" },
1401 { TV_STD_PAL_60, "pal-60" },
1402 { TV_STD_NTSC_J, "ntsc-j" },
1403 { TV_STD_SCART_PAL, "scart-pal" },
1404 { TV_STD_PAL_CN, "pal-cn" },
1405 { TV_STD_SECAM, "secam" },
1408 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1409 { { UNDERSCAN_OFF, "off" },
1410 { UNDERSCAN_ON, "on" },
1411 { UNDERSCAN_AUTO, "auto" },
1414 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1415 { { RADEON_AUDIO_DISABLE, "off" },
1416 { RADEON_AUDIO_ENABLE, "on" },
1417 { RADEON_AUDIO_AUTO, "auto" },
1420 /* XXX support different dither options? spatial, temporal, both, etc. */
1421 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1422 { { RADEON_FMT_DITHER_DISABLE, "off" },
1423 { RADEON_FMT_DITHER_ENABLE, "on" },
1426 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1427 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1428 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1429 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1430 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1433 static int radeon_modeset_create_props(struct radeon_device *rdev)
1437 if (rdev->is_atom_bios) {
1438 rdev->mode_info.coherent_mode_property =
1439 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1440 if (!rdev->mode_info.coherent_mode_property)
1444 if (!ASIC_IS_AVIVO(rdev)) {
1445 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1446 rdev->mode_info.tmds_pll_property =
1447 drm_property_create_enum(rdev->ddev, 0,
1449 radeon_tmds_pll_enum_list, sz);
1452 rdev->mode_info.load_detect_property =
1453 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1454 if (!rdev->mode_info.load_detect_property)
1457 drm_mode_create_scaling_mode_property(rdev->ddev);
1459 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1460 rdev->mode_info.tv_std_property =
1461 drm_property_create_enum(rdev->ddev, 0,
1463 radeon_tv_std_enum_list, sz);
1465 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1466 rdev->mode_info.underscan_property =
1467 drm_property_create_enum(rdev->ddev, 0,
1469 radeon_underscan_enum_list, sz);
1471 rdev->mode_info.underscan_hborder_property =
1472 drm_property_create_range(rdev->ddev, 0,
1473 "underscan hborder", 0, 128);
1474 if (!rdev->mode_info.underscan_hborder_property)
1477 rdev->mode_info.underscan_vborder_property =
1478 drm_property_create_range(rdev->ddev, 0,
1479 "underscan vborder", 0, 128);
1480 if (!rdev->mode_info.underscan_vborder_property)
1483 sz = ARRAY_SIZE(radeon_audio_enum_list);
1484 rdev->mode_info.audio_property =
1485 drm_property_create_enum(rdev->ddev, 0,
1487 radeon_audio_enum_list, sz);
1489 sz = ARRAY_SIZE(radeon_dither_enum_list);
1490 rdev->mode_info.dither_property =
1491 drm_property_create_enum(rdev->ddev, 0,
1493 radeon_dither_enum_list, sz);
1495 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1496 rdev->mode_info.output_csc_property =
1497 drm_property_create_enum(rdev->ddev, 0,
1499 radeon_output_csc_enum_list, sz);
1504 void radeon_update_display_priority(struct radeon_device *rdev)
1506 /* adjustment options for the display watermarks */
1507 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1508 /* set display priority to high for r3xx, rv515 chips
1509 * this avoids flickering due to underflow to the
1510 * display controllers during heavy acceleration.
1511 * Don't force high on rs4xx igp chips as it seems to
1512 * affect the sound card. See kernel bug 15982.
1514 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1515 !(rdev->flags & RADEON_IS_IGP))
1516 rdev->disp_priority = 2;
1518 rdev->disp_priority = 0;
1520 rdev->disp_priority = radeon_disp_priority;
1525 * Allocate hdmi structs and determine register offsets
1527 static void radeon_afmt_init(struct radeon_device *rdev)
1531 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1532 rdev->mode_info.afmt[i] = NULL;
1534 if (ASIC_IS_NODCE(rdev)) {
1536 } else if (ASIC_IS_DCE4(rdev)) {
1537 static uint32_t eg_offsets[] = {
1538 EVERGREEN_CRTC0_REGISTER_OFFSET,
1539 EVERGREEN_CRTC1_REGISTER_OFFSET,
1540 EVERGREEN_CRTC2_REGISTER_OFFSET,
1541 EVERGREEN_CRTC3_REGISTER_OFFSET,
1542 EVERGREEN_CRTC4_REGISTER_OFFSET,
1543 EVERGREEN_CRTC5_REGISTER_OFFSET,
1548 /* DCE8 has 7 audio blocks tied to DIG encoders */
1549 /* DCE6 has 6 audio blocks tied to DIG encoders */
1550 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1551 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1552 if (ASIC_IS_DCE8(rdev))
1554 else if (ASIC_IS_DCE6(rdev))
1556 else if (ASIC_IS_DCE5(rdev))
1558 else if (ASIC_IS_DCE41(rdev))
1563 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1564 for (i = 0; i < num_afmt; i++) {
1565 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1566 if (rdev->mode_info.afmt[i]) {
1567 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1568 rdev->mode_info.afmt[i]->id = i;
1571 } else if (ASIC_IS_DCE3(rdev)) {
1572 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1573 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1574 if (rdev->mode_info.afmt[0]) {
1575 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1576 rdev->mode_info.afmt[0]->id = 0;
1578 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1579 if (rdev->mode_info.afmt[1]) {
1580 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1581 rdev->mode_info.afmt[1]->id = 1;
1583 } else if (ASIC_IS_DCE2(rdev)) {
1584 /* DCE2 has at least 1 routable audio block */
1585 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1586 if (rdev->mode_info.afmt[0]) {
1587 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1588 rdev->mode_info.afmt[0]->id = 0;
1590 /* r6xx has 2 routable audio blocks */
1591 if (rdev->family >= CHIP_R600) {
1592 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1593 if (rdev->mode_info.afmt[1]) {
1594 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1595 rdev->mode_info.afmt[1]->id = 1;
1601 static void radeon_afmt_fini(struct radeon_device *rdev)
1605 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1606 kfree(rdev->mode_info.afmt[i]);
1607 rdev->mode_info.afmt[i] = NULL;
1611 int radeon_modeset_init(struct radeon_device *rdev)
1616 drm_mode_config_init(rdev->ddev);
1617 rdev->mode_info.mode_config_initialized = true;
1619 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1621 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1622 rdev->ddev->mode_config.async_page_flip = true;
1624 if (ASIC_IS_DCE5(rdev)) {
1625 rdev->ddev->mode_config.max_width = 16384;
1626 rdev->ddev->mode_config.max_height = 16384;
1627 } else if (ASIC_IS_AVIVO(rdev)) {
1628 rdev->ddev->mode_config.max_width = 8192;
1629 rdev->ddev->mode_config.max_height = 8192;
1631 rdev->ddev->mode_config.max_width = 4096;
1632 rdev->ddev->mode_config.max_height = 4096;
1635 rdev->ddev->mode_config.preferred_depth = 24;
1636 rdev->ddev->mode_config.prefer_shadow = 1;
1638 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1640 ret = radeon_modeset_create_props(rdev);
1645 /* init i2c buses */
1646 radeon_i2c_init(rdev);
1648 /* check combios for a valid hardcoded EDID - Sun servers */
1649 if (!rdev->is_atom_bios) {
1650 /* check for hardcoded EDID in BIOS */
1651 radeon_combios_check_hardcoded_edid(rdev);
1654 /* allocate crtcs */
1655 for (i = 0; i < rdev->num_crtc; i++) {
1656 radeon_crtc_init(rdev->ddev, i);
1659 /* okay we should have all the bios connectors */
1660 ret = radeon_setup_enc_conn(rdev->ddev);
1665 /* init dig PHYs, disp eng pll */
1666 if (rdev->is_atom_bios) {
1667 radeon_atom_encoder_init(rdev);
1668 radeon_atom_disp_eng_pll_init(rdev);
1671 /* initialize hpd */
1672 radeon_hpd_init(rdev);
1675 radeon_afmt_init(rdev);
1677 radeon_fbdev_init(rdev);
1678 drm_kms_helper_poll_init(rdev->ddev);
1680 /* do pm late init */
1681 ret = radeon_pm_late_init(rdev);
1686 void radeon_modeset_fini(struct radeon_device *rdev)
1688 if (rdev->mode_info.mode_config_initialized) {
1689 drm_kms_helper_poll_fini(rdev->ddev);
1690 radeon_hpd_fini(rdev);
1691 drm_crtc_force_disable_all(rdev->ddev);
1692 radeon_fbdev_fini(rdev);
1693 radeon_afmt_fini(rdev);
1694 drm_mode_config_cleanup(rdev->ddev);
1695 rdev->mode_info.mode_config_initialized = false;
1698 kfree(rdev->mode_info.bios_hardcoded_edid);
1700 /* free i2c buses */
1701 radeon_i2c_fini(rdev);
1704 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1706 /* try and guess if this is a tv or a monitor */
1707 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1708 (mode->vdisplay == 576) || /* 576p */
1709 (mode->vdisplay == 720) || /* 720p */
1710 (mode->vdisplay == 1080)) /* 1080p */
1716 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1717 const struct drm_display_mode *mode,
1718 struct drm_display_mode *adjusted_mode)
1720 struct drm_device *dev = crtc->dev;
1721 struct radeon_device *rdev = dev->dev_private;
1722 struct drm_encoder *encoder;
1723 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1724 struct radeon_encoder *radeon_encoder;
1725 struct drm_connector *connector;
1726 struct radeon_connector *radeon_connector;
1728 u32 src_v = 1, dst_v = 1;
1729 u32 src_h = 1, dst_h = 1;
1731 radeon_crtc->h_border = 0;
1732 radeon_crtc->v_border = 0;
1734 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1735 if (encoder->crtc != crtc)
1737 radeon_encoder = to_radeon_encoder(encoder);
1738 connector = radeon_get_connector_for_encoder(encoder);
1739 radeon_connector = to_radeon_connector(connector);
1743 if (radeon_encoder->rmx_type == RMX_OFF)
1744 radeon_crtc->rmx_type = RMX_OFF;
1745 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1746 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1747 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1749 radeon_crtc->rmx_type = RMX_OFF;
1750 /* copy native mode */
1751 memcpy(&radeon_crtc->native_mode,
1752 &radeon_encoder->native_mode,
1753 sizeof(struct drm_display_mode));
1754 src_v = crtc->mode.vdisplay;
1755 dst_v = radeon_crtc->native_mode.vdisplay;
1756 src_h = crtc->mode.hdisplay;
1757 dst_h = radeon_crtc->native_mode.hdisplay;
1759 /* fix up for overscan on hdmi */
1760 if (ASIC_IS_AVIVO(rdev) &&
1761 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1762 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1763 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1764 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1765 is_hdtv_mode(mode)))) {
1766 if (radeon_encoder->underscan_hborder != 0)
1767 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1769 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1770 if (radeon_encoder->underscan_vborder != 0)
1771 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1773 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1774 radeon_crtc->rmx_type = RMX_FULL;
1775 src_v = crtc->mode.vdisplay;
1776 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1777 src_h = crtc->mode.hdisplay;
1778 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1782 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1783 /* WARNING: Right now this can't happen but
1784 * in the future we need to check that scaling
1785 * are consistent across different encoder
1786 * (ie all encoder can work with the same
1789 DRM_ERROR("Scaling not consistent across encoder.\n");
1794 if (radeon_crtc->rmx_type != RMX_OFF) {
1796 a.full = dfixed_const(src_v);
1797 b.full = dfixed_const(dst_v);
1798 radeon_crtc->vsc.full = dfixed_div(a, b);
1799 a.full = dfixed_const(src_h);
1800 b.full = dfixed_const(dst_h);
1801 radeon_crtc->hsc.full = dfixed_div(a, b);
1803 radeon_crtc->vsc.full = dfixed_const(1);
1804 radeon_crtc->hsc.full = dfixed_const(1);
1810 * Retrieve current video scanout position of crtc on a given gpu, and
1811 * an optional accurate timestamp of when query happened.
1813 * \param dev Device to query.
1814 * \param crtc Crtc to query.
1815 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1816 * For driver internal use only also supports these flags:
1818 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1819 * of a fudged earlier start of vblank.
1821 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1822 * fudged earlier start of vblank in *vpos and the distance
1823 * to true start of vblank in *hpos.
1825 * \param *vpos Location where vertical scanout position should be stored.
1826 * \param *hpos Location where horizontal scanout position should go.
1827 * \param *stime Target location for timestamp taken immediately before
1828 * scanout position query. Can be NULL to skip timestamp.
1829 * \param *etime Target location for timestamp taken immediately after
1830 * scanout position query. Can be NULL to skip timestamp.
1832 * Returns vpos as a positive number while in active scanout area.
1833 * Returns vpos as a negative number inside vblank, counting the number
1834 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1835 * until start of active scanout / end of vblank."
1837 * \return Flags, or'ed together as follows:
1839 * DRM_SCANOUTPOS_VALID = Query successful.
1840 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1841 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1842 * this flag means that returned position may be offset by a constant but
1843 * unknown small number of scanlines wrt. real scanout position.
1846 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1847 unsigned int flags, int *vpos, int *hpos,
1848 ktime_t *stime, ktime_t *etime,
1849 const struct drm_display_mode *mode)
1851 u32 stat_crtc = 0, vbl = 0, position = 0;
1852 int vbl_start, vbl_end, vtotal, ret = 0;
1855 struct radeon_device *rdev = dev->dev_private;
1857 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1859 /* Get optional system timestamp before query. */
1861 *stime = ktime_get();
1863 if (ASIC_IS_DCE4(rdev)) {
1865 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1866 EVERGREEN_CRTC0_REGISTER_OFFSET);
1867 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1868 EVERGREEN_CRTC0_REGISTER_OFFSET);
1869 ret |= DRM_SCANOUTPOS_VALID;
1872 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1873 EVERGREEN_CRTC1_REGISTER_OFFSET);
1874 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1875 EVERGREEN_CRTC1_REGISTER_OFFSET);
1876 ret |= DRM_SCANOUTPOS_VALID;
1879 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1880 EVERGREEN_CRTC2_REGISTER_OFFSET);
1881 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1882 EVERGREEN_CRTC2_REGISTER_OFFSET);
1883 ret |= DRM_SCANOUTPOS_VALID;
1886 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1887 EVERGREEN_CRTC3_REGISTER_OFFSET);
1888 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1889 EVERGREEN_CRTC3_REGISTER_OFFSET);
1890 ret |= DRM_SCANOUTPOS_VALID;
1893 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1894 EVERGREEN_CRTC4_REGISTER_OFFSET);
1895 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1896 EVERGREEN_CRTC4_REGISTER_OFFSET);
1897 ret |= DRM_SCANOUTPOS_VALID;
1900 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1901 EVERGREEN_CRTC5_REGISTER_OFFSET);
1902 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1903 EVERGREEN_CRTC5_REGISTER_OFFSET);
1904 ret |= DRM_SCANOUTPOS_VALID;
1906 } else if (ASIC_IS_AVIVO(rdev)) {
1908 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1909 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1910 ret |= DRM_SCANOUTPOS_VALID;
1913 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1914 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1915 ret |= DRM_SCANOUTPOS_VALID;
1918 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1920 /* Assume vbl_end == 0, get vbl_start from
1923 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1924 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1925 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1926 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1927 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1928 if (!(stat_crtc & 1))
1931 ret |= DRM_SCANOUTPOS_VALID;
1934 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1935 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1936 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1937 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1938 if (!(stat_crtc & 1))
1941 ret |= DRM_SCANOUTPOS_VALID;
1945 /* Get optional system timestamp after query. */
1947 *etime = ktime_get();
1949 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1951 /* Decode into vertical and horizontal scanout position. */
1952 *vpos = position & 0x1fff;
1953 *hpos = (position >> 16) & 0x1fff;
1955 /* Valid vblank area boundaries from gpu retrieved? */
1958 ret |= DRM_SCANOUTPOS_ACCURATE;
1959 vbl_start = vbl & 0x1fff;
1960 vbl_end = (vbl >> 16) & 0x1fff;
1963 /* No: Fake something reasonable which gives at least ok results. */
1964 vbl_start = mode->crtc_vdisplay;
1968 /* Called from driver internal vblank counter query code? */
1969 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1970 /* Caller wants distance from real vbl_start in *hpos */
1971 *hpos = *vpos - vbl_start;
1974 /* Fudge vblank to start a few scanlines earlier to handle the
1975 * problem that vblank irqs fire a few scanlines before start
1976 * of vblank. Some driver internal callers need the true vblank
1977 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1979 * The cause of the "early" vblank irq is that the irq is triggered
1980 * by the line buffer logic when the line buffer read position enters
1981 * the vblank, whereas our crtc scanout position naturally lags the
1982 * line buffer read position.
1984 if (!(flags & USE_REAL_VBLANKSTART))
1985 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1987 /* Test scanout position against vblank region. */
1988 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1993 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1995 /* Called from driver internal vblank counter query code? */
1996 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1997 /* Caller wants distance from fudged earlier vbl_start */
2002 /* Check if inside vblank area and apply corrective offsets:
2003 * vpos will then be >=0 in video scanout area, but negative
2004 * within vblank area, counting down the number of lines until
2008 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
2009 if (in_vbl && (*vpos >= vbl_start)) {
2010 vtotal = mode->crtc_vtotal;
2011 *vpos = *vpos - vtotal;
2014 /* Correct for shifted end of vbl at vbl_end. */
2015 *vpos = *vpos - vbl_end;