drivers/gpu/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *
  31  * ------------------------ This file is DEPRECATED! -------------------------
  32  */
  33
  34 #include <linux/module.h>
  35
  36 #include <drm/drmP.h>
  37 #include <drm/radeon_drm.h>
  38 #include "radeon_drv.h"
  39 #include "r300_reg.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 /* Firmware Names */
  44 #define FIRMWARE_R100           "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_R200           "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_R300           "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_R420           "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_RS690          "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_RS600          "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_R520           "/*(DEBLOBBED)*/"
  51
  52 /*(DEBLOBBED)*/
  53
  54 static int radeon_do_cleanup_cp(struct drm_device * dev);
  55 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  56
  57 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  58 {
  59         u32 val;
  60
  61         if (dev_priv->flags & RADEON_IS_AGP) {
  62                 val = DRM_READ32(dev_priv->ring_rptr, off);
  63         } else {
  64                 val = *(((volatile u32 *)
  65                          dev_priv->ring_rptr->handle) +
  66                         (off / sizeof(u32)));
  67                 val = le32_to_cpu(val);
  68         }
  69         return val;
  70 }
  71
  72 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  73 {
  74         if (dev_priv->writeback_works)
  75                 return radeon_read_ring_rptr(dev_priv, 0);
  76         else {
  77                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  78                         return RADEON_READ(R600_CP_RB_RPTR);
  79                 else
  80                         return RADEON_READ(RADEON_CP_RB_RPTR);
  81         }
  82 }
  83
  84 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  85 {
  86         if (dev_priv->flags & RADEON_IS_AGP)
  87                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  88         else
  89                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  90                   (off / sizeof(u32))) = cpu_to_le32(val);
  91 }
  92
  93 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  94 {
  95         radeon_write_ring_rptr(dev_priv, 0, val);
  96 }
  97
  98 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  99 {
 100         if (dev_priv->writeback_works) {
 101                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 102                         return radeon_read_ring_rptr(dev_priv,
 103                                                      R600_SCRATCHOFF(index));
 104                 else
 105                         return radeon_read_ring_rptr(dev_priv,
 106                                                      RADEON_SCRATCHOFF(index));
 107         } else {
 108                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 109                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 110                 else
 111                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 112         }
 113 }
 114
 115 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 116 {
 117         u32 ret;
 118         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 119         ret = RADEON_READ(R520_MC_IND_DATA);
 120         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 121         return ret;
 122 }
 123
 124 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 125 {
 126         u32 ret;
 127         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 128         ret = RADEON_READ(RS480_NB_MC_DATA);
 129         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 130         return ret;
 131 }
 132
 133 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 134 {
 135         u32 ret;
 136         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 137         ret = RADEON_READ(RS690_MC_DATA);
 138         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 139         return ret;
 140 }
 141
 142 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 143 {
 144         u32 ret;
 145         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 146                                       RS600_MC_IND_CITF_ARB0));
 147         ret = RADEON_READ(RS600_MC_DATA);
 148         return ret;
 149 }
 150
 151 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 152 {
 153         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 154             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 155                 return RS690_READ_MCIND(dev_priv, addr);
 156         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 157                 return RS600_READ_MCIND(dev_priv, addr);
 158         else
 159                 return RS480_READ_MCIND(dev_priv, addr);
 160 }
 161
 162 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 163 {
 164
 165         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 166                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 167         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 168                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 169         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 170                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 171         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 172                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 173                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 175                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 176         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 177                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 178         else
 179                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 180 }
 181
 182 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 183 {
 184         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 185                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 186         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 187                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 188         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 189                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 190         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 191                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 192                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 193         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 194                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 195         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 196                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 197         else
 198                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 199 }
 200
 201 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 202 {
 203         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 204         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 205                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 206                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 207         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 208                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 209                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 210         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 211                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 212         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 213                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 214                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 215         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 216                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 217         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 218                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 219         else
 220                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 221 }
 222
 223 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 224 {
 225         u32 agp_base_hi = upper_32_bits(agp_base);
 226         u32 agp_base_lo = agp_base & 0xffffffff;
 227         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 228
 229         /* R6xx/R7xx must be aligned to a 4MB boundary */
 230         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 231                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 232         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 233                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 234         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 235                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 236                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 237         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 238                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 239                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 240                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 241         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 242                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 243                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 244         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 245                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 246                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 247         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 248                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 249                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 250                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 251         } else {
 252                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 253                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 254                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 255         }
 256 }
 257
 258 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 259 {
 260         u32 tmp;
 261         /* Turn on bus mastering */
 262         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 263             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 264                 /* rs600/rs690/rs740 */
 265                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 266                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 267         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 268                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 269                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 270                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 271                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 272                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 273                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 274         } /* PCIE cards appears to not need this */
 275 }
 276
 277 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 278 {
 279         drm_radeon_private_t *dev_priv = dev->dev_private;
 280
 281         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 282         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 283 }
 284
 285 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 286 {
 287         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 288         return RADEON_READ(RADEON_PCIE_DATA);
 289 }
 290
 291 #if RADEON_FIFO_DEBUG
 292 static void radeon_status(drm_radeon_private_t * dev_priv)
 293 {
 294         printk("%s:\n", __func__);
 295         printk("RBBM_STATUS = 0x%08x\n",
 296                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 297         printk("CP_RB_RTPR = 0x%08x\n",
 298                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 299         printk("CP_RB_WTPR = 0x%08x\n",
 300                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 301         printk("AIC_CNTL = 0x%08x\n",
 302                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 303         printk("AIC_STAT = 0x%08x\n",
 304                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 305         printk("AIC_PT_BASE = 0x%08x\n",
 306                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 307         printk("TLB_ADDR = 0x%08x\n",
 308                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 309         printk("TLB_DATA = 0x%08x\n",
 310                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 311 }
 312 #endif
 313
 314 /* ================================================================
 315  * Engine, FIFO control
 316  */
 317
 318 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 319 {
 320         u32 tmp;
 321         int i;
 322
 323         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 324
 325         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 326                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 327                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 328                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 329
 330                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 331                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 332                               & RADEON_RB3D_DC_BUSY)) {
 333                                 return 0;
 334                         }
 335                         DRM_UDELAY(1);
 336                 }
 337         } else {
 338                 /* don't flush or purge cache here or lockup */
 339                 return 0;
 340         }
 341
 342 #if RADEON_FIFO_DEBUG
 343         DRM_ERROR("failed!\n");
 344         radeon_status(dev_priv);
 345 #endif
 346         return -EBUSY;
 347 }
 348
 349 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 350 {
 351         int i;
 352
 353         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 354
 355         for (i = 0; i < dev_priv->usec_timeout; i++) {
 356                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 357                              & RADEON_RBBM_FIFOCNT_MASK);
 358                 if (slots >= entries)
 359                         return 0;
 360                 DRM_UDELAY(1);
 361         }
 362         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 363                  RADEON_READ(RADEON_RBBM_STATUS),
 364                  RADEON_READ(R300_VAP_CNTL_STATUS));
 365
 366 #if RADEON_FIFO_DEBUG
 367         DRM_ERROR("failed!\n");
 368         radeon_status(dev_priv);
 369 #endif
 370         return -EBUSY;
 371 }
 372
 373 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 374 {
 375         int i, ret;
 376
 377         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 378
 379         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 380         if (ret)
 381                 return ret;
 382
 383         for (i = 0; i < dev_priv->usec_timeout; i++) {
 384                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 385                       & RADEON_RBBM_ACTIVE)) {
 386                         radeon_do_pixcache_flush(dev_priv);
 387                         return 0;
 388                 }
 389                 DRM_UDELAY(1);
 390         }
 391         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 392                  RADEON_READ(RADEON_RBBM_STATUS),
 393                  RADEON_READ(R300_VAP_CNTL_STATUS));
 394
 395 #if RADEON_FIFO_DEBUG
 396         DRM_ERROR("failed!\n");
 397         radeon_status(dev_priv);
 398 #endif
 399         return -EBUSY;
 400 }
 401
 402 static void radeon_init_pipes(struct drm_device *dev)
 403 {
 404         drm_radeon_private_t *dev_priv = dev->dev_private;
 405         uint32_t gb_tile_config, gb_pipe_sel = 0;
 406
 407         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 408                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 409                 if ((z_pipe_sel & 3) == 3)
 410                         dev_priv->num_z_pipes = 2;
 411                 else
 412                         dev_priv->num_z_pipes = 1;
 413         } else
 414                 dev_priv->num_z_pipes = 1;
 415
 416         /* RS4xx/RS6xx/R4xx/R5xx */
 417         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 418                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 419                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 420                 /* SE cards have 1 pipe */
 421                 if ((dev->pdev->device == 0x5e4c) ||
 422                     (dev->pdev->device == 0x5e4f))
 423                         dev_priv->num_gb_pipes = 1;
 424         } else {
 425                 /* R3xx */
 426                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
 427                      dev->pdev->device != 0x4144) ||
 428                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
 429                      dev->pdev->device != 0x4148)) {
 430                         dev_priv->num_gb_pipes = 2;
 431                 } else {
 432                         /* RV3xx/R300 AD/R350 AH */
 433                         dev_priv->num_gb_pipes = 1;
 434                 }
 435         }
 436         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 437
 438         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 439
 440         switch (dev_priv->num_gb_pipes) {
 441         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 442         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 443         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 444         default:
 445         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 446         }
 447
 448         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 449                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 450                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 451         }
 452         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 453         radeon_do_wait_for_idle(dev_priv);
 454         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 455         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 456                                                R300_DC_AUTOFLUSH_ENABLE |
 457                                                R300_DC_DC_DISABLE_IGNORE_PE));
 458
 459
 460 }
 461
 462 /* ================================================================
 463  * CP control, initialization
 464  */
 465
 466 /* Load the microcode for the CP */
 467 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 468 {
 469         struct platform_device *pdev;
 470         const char *fw_name = NULL;
 471         int err;
 472
 473         DRM_DEBUG("\n");
 474
 475         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 476         err = IS_ERR(pdev);
 477         if (err) {
 478                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 479                 return -EINVAL;
 480         }
 481
 482         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 483             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 484             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 485             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 486             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 487                 DRM_INFO("Loading R100 Microcode\n");
 488                 fw_name = FIRMWARE_R100;
 489         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 490                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 491                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 492                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 493                 DRM_INFO("Loading R200 Microcode\n");
 494                 fw_name = FIRMWARE_R200;
 495         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 496                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 497                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 498                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 499                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 500                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 501                 DRM_INFO("Loading R300 Microcode\n");
 502                 fw_name = FIRMWARE_R300;
 503         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 504                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 505                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 506                 DRM_INFO("Loading R400 Microcode\n");
 507                 fw_name = FIRMWARE_R420;
 508         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 509                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 510                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 511                 fw_name = FIRMWARE_RS690;
 512         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 513                 DRM_INFO("Loading RS600 Microcode\n");
 514                 fw_name = FIRMWARE_RS600;
 515         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 516                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 517                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 518                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 519                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 520                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 521                 DRM_INFO("Loading R500 Microcode\n");
 522                 fw_name = FIRMWARE_R520;
 523         }
 524
 525         err = reject_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
 526         platform_device_unregister(pdev);
 527         if (err) {
 528                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 529                        fw_name);
 530         } else if (dev_priv->me_fw->size % 8) {
 531                 printk(KERN_ERR
 532                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 533                        dev_priv->me_fw->size, fw_name);
 534                 err = -EINVAL;
 535                 release_firmware(dev_priv->me_fw);
 536                 dev_priv->me_fw = NULL;
 537         }
 538         return err;
 539 }
 540
 541 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
 542 {
 543         const __be32 *fw_data;
 544         int i, size;
 545
 546         radeon_do_wait_for_idle(dev_priv);
 547
 548         if (dev_priv->me_fw) {
 549                 size = dev_priv->me_fw->size / 4;
 550                 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
 551                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 552                 for (i = 0; i < size; i += 2) {
 553                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 554                                      be32_to_cpup(&fw_data[i]));
 555                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 556                                      be32_to_cpup(&fw_data[i + 1]));
 557                 }
 558         }
 559 }
 560
 561 /* Flush any pending commands to the CP.  This should only be used just
 562  * prior to a wait for idle, as it informs the engine that the command
 563  * stream is ending.
 564  */
 565 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 566 {
 567         DRM_DEBUG("\n");
 568 #if 0
 569         u32 tmp;
 570
 571         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 572         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 573 #endif
 574 }
 575
 576 /* Wait for the CP to go idle.
 577  */
 578 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 579 {
 580         RING_LOCALS;
 581         DRM_DEBUG("\n");
 582
 583         BEGIN_RING(6);
 584
 585         RADEON_PURGE_CACHE();
 586         RADEON_PURGE_ZCACHE();
 587         RADEON_WAIT_UNTIL_IDLE();
 588
 589         ADVANCE_RING();
 590         COMMIT_RING();
 591
 592         return radeon_do_wait_for_idle(dev_priv);
 593 }
 594
 595 /* Start the Command Processor.
 596  */
 597 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 598 {
 599         RING_LOCALS;
 600         DRM_DEBUG("\n");
 601
 602         radeon_do_wait_for_idle(dev_priv);
 603
 604         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 605
 606         dev_priv->cp_running = 1;
 607
 608         /* on r420, any DMA from CP to system memory while 2D is active
 609          * can cause a hang.  workaround is to queue a CP RESYNC token
 610          */
 611         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 612                 BEGIN_RING(3);
 613                 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
 614                 OUT_RING(5); /* scratch reg 5 */
 615                 OUT_RING(0xdeadbeef);
 616                 ADVANCE_RING();
 617                 COMMIT_RING();
 618         }
 619
 620         BEGIN_RING(8);
 621         /* isync can only be written through cp on r5xx write it here */
 622         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 623         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 624                  RADEON_ISYNC_ANY3D_IDLE2D |
 625                  RADEON_ISYNC_WAIT_IDLEGUI |
 626                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 627         RADEON_PURGE_CACHE();
 628         RADEON_PURGE_ZCACHE();
 629         RADEON_WAIT_UNTIL_IDLE();
 630         ADVANCE_RING();
 631         COMMIT_RING();
 632
 633         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 634 }
 635
 636 /* Reset the Command Processor.  This will not flush any pending
 637  * commands, so you must wait for the CP command stream to complete
 638  * before calling this routine.
 639  */
 640 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 641 {
 642         u32 cur_read_ptr;
 643         DRM_DEBUG("\n");
 644
 645         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 646         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 647         SET_RING_HEAD(dev_priv, cur_read_ptr);
 648         dev_priv->ring.tail = cur_read_ptr;
 649 }
 650
 651 /* Stop the Command Processor.  This will not flush any pending
 652  * commands, so you must flush the command stream and wait for the CP
 653  * to go idle before calling this routine.
 654  */
 655 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 656 {
 657         RING_LOCALS;
 658         DRM_DEBUG("\n");
 659
 660         /* finish the pending CP_RESYNC token */
 661         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
 662                 BEGIN_RING(2);
 663                 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 664                 OUT_RING(R300_RB3D_DC_FINISH);
 665                 ADVANCE_RING();
 666                 COMMIT_RING();
 667                 radeon_do_wait_for_idle(dev_priv);
 668         }
 669
 670         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 671
 672         dev_priv->cp_running = 0;
 673 }
 674
 675 /* Reset the engine.  This will stop the CP if it is running.
 676  */
 677 static int radeon_do_engine_reset(struct drm_device * dev)
 678 {
 679         drm_radeon_private_t *dev_priv = dev->dev_private;
 680         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 681         DRM_DEBUG("\n");
 682
 683         radeon_do_pixcache_flush(dev_priv);
 684
 685         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 686                 /* may need something similar for newer chips */
 687                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 688                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 689
 690                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 691                                                     RADEON_FORCEON_MCLKA |
 692                                                     RADEON_FORCEON_MCLKB |
 693                                                     RADEON_FORCEON_YCLKA |
 694                                                     RADEON_FORCEON_YCLKB |
 695                                                     RADEON_FORCEON_MC |
 696                                                     RADEON_FORCEON_AIC));
 697         }
 698
 699         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 700
 701         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 702                                               RADEON_SOFT_RESET_CP |
 703                                               RADEON_SOFT_RESET_HI |
 704                                               RADEON_SOFT_RESET_SE |
 705                                               RADEON_SOFT_RESET_RE |
 706                                               RADEON_SOFT_RESET_PP |
 707                                               RADEON_SOFT_RESET_E2 |
 708                                               RADEON_SOFT_RESET_RB));
 709         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 710         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 711                                               ~(RADEON_SOFT_RESET_CP |
 712                                                 RADEON_SOFT_RESET_HI |
 713                                                 RADEON_SOFT_RESET_SE |
 714                                                 RADEON_SOFT_RESET_RE |
 715                                                 RADEON_SOFT_RESET_PP |
 716                                                 RADEON_SOFT_RESET_E2 |
 717                                                 RADEON_SOFT_RESET_RB)));
 718         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 719
 720         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 721                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 722                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 723                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 724         }
 725
 726         /* setup the raster pipes */
 727         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 728             radeon_init_pipes(dev);
 729
 730         /* Reset the CP ring */
 731         radeon_do_cp_reset(dev_priv);
 732
 733         /* The CP is no longer running after an engine reset */
 734         dev_priv->cp_running = 0;
 735
 736         /* Reset any pending vertex, indirect buffers */
 737         radeon_freelist_reset(dev);
 738
 739         return 0;
 740 }
 741
 742 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 743                                        drm_radeon_private_t *dev_priv,
 744                                        struct drm_file *file_priv)
 745 {
 746         struct drm_radeon_master_private *master_priv;
 747         u32 ring_start, cur_read_ptr;
 748
 749         /* Initialize the memory controller. With new memory map, the fb location
 750          * is not changed, it should have been properly initialized already. Part
 751          * of the problem is that the code below is bogus, assuming the GART is
 752          * always appended to the fb which is not necessarily the case
 753          */
 754         if (!dev_priv->new_memmap)
 755                 radeon_write_fb_location(dev_priv,
 756                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 757                              | (dev_priv->fb_location >> 16));
 758
 759 #if IS_ENABLED(CONFIG_AGP)
 760         if (dev_priv->flags & RADEON_IS_AGP) {
 761                 radeon_write_agp_base(dev_priv, dev->agp->base);
 762
 763                 radeon_write_agp_location(dev_priv,
 764                              (((dev_priv->gart_vm_start - 1 +
 765                                 dev_priv->gart_size) & 0xffff0000) |
 766                               (dev_priv->gart_vm_start >> 16)));
 767
 768                 ring_start = (dev_priv->cp_ring->offset
 769                               - dev->agp->base
 770                               + dev_priv->gart_vm_start);
 771         } else
 772 #endif
 773                 ring_start = (dev_priv->cp_ring->offset
 774                               - (unsigned long)dev->sg->virtual
 775                               + dev_priv->gart_vm_start);
 776
 777         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 778
 779         /* Set the write pointer delay */
 780         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 781
 782         /* Initialize the ring buffer's read and write pointers */
 783         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 784         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 785         SET_RING_HEAD(dev_priv, cur_read_ptr);
 786         dev_priv->ring.tail = cur_read_ptr;
 787
 788 #if IS_ENABLED(CONFIG_AGP)
 789         if (dev_priv->flags & RADEON_IS_AGP) {
 790                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 791                              dev_priv->ring_rptr->offset
 792                              - dev->agp->base + dev_priv->gart_vm_start);
 793         } else
 794 #endif
 795         {
 796                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 797                              dev_priv->ring_rptr->offset
 798                              - ((unsigned long) dev->sg->virtual)
 799                              + dev_priv->gart_vm_start);
 800         }
 801
 802         /* Set ring buffer size */
 803 #ifdef __BIG_ENDIAN
 804         RADEON_WRITE(RADEON_CP_RB_CNTL,
 805                      RADEON_BUF_SWAP_32BIT |
 806                      (dev_priv->ring.fetch_size_l2ow << 18) |
 807                      (dev_priv->ring.rptr_update_l2qw << 8) |
 808                      dev_priv->ring.size_l2qw);
 809 #else
 810         RADEON_WRITE(RADEON_CP_RB_CNTL,
 811                      (dev_priv->ring.fetch_size_l2ow << 18) |
 812                      (dev_priv->ring.rptr_update_l2qw << 8) |
 813                      dev_priv->ring.size_l2qw);
 814 #endif
 815
 816
 817         /* Initialize the scratch register pointer.  This will cause
 818          * the scratch register values to be written out to memory
 819          * whenever they are updated.
 820          *
 821          * We simply put this behind the ring read pointer, this works
 822          * with PCI GART as well as (whatever kind of) AGP GART
 823          */
 824         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 825                      + RADEON_SCRATCH_REG_OFFSET);
 826
 827         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 828
 829         radeon_enable_bm(dev_priv);
 830
 831         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 832         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 833
 834         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 835         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 836
 837         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 838         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 839
 840         /* reset sarea copies of these */
 841         master_priv = file_priv->master->driver_priv;
 842         if (master_priv->sarea_priv) {
 843                 master_priv->sarea_priv->last_frame = 0;
 844                 master_priv->sarea_priv->last_dispatch = 0;
 845                 master_priv->sarea_priv->last_clear = 0;
 846         }
 847
 848         radeon_do_wait_for_idle(dev_priv);
 849
 850         /* Sync everything up */
 851         RADEON_WRITE(RADEON_ISYNC_CNTL,
 852                      (RADEON_ISYNC_ANY2D_IDLE3D |
 853                       RADEON_ISYNC_ANY3D_IDLE2D |
 854                       RADEON_ISYNC_WAIT_IDLEGUI |
 855                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 856
 857 }
 858
 859 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 860 {
 861         u32 tmp;
 862
 863         /* Start with assuming that writeback doesn't work */
 864         dev_priv->writeback_works = 0;
 865
 866         /* Writeback doesn't seem to work everywhere, test it here and possibly
 867          * enable it if it appears to work
 868          */
 869         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 870
 871         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 872
 873         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 874                 u32 val;
 875
 876                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 877                 if (val == 0xdeadbeef)
 878                         break;
 879                 DRM_UDELAY(1);
 880         }
 881
 882         if (tmp < dev_priv->usec_timeout) {
 883                 dev_priv->writeback_works = 1;
 884                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 885         } else {
 886                 dev_priv->writeback_works = 0;
 887                 DRM_INFO("writeback test failed\n");
 888         }
 889         if (radeon_no_wb == 1) {
 890                 dev_priv->writeback_works = 0;
 891                 DRM_INFO("writeback forced off\n");
 892         }
 893
 894         if (!dev_priv->writeback_works) {
 895                 /* Disable writeback to avoid unnecessary bus master transfer */
 896                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 897                              RADEON_RB_NO_UPDATE);
 898                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 899         }
 900 }
 901
 902 /* Enable or disable IGP GART on the chip */
 903 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 904 {
 905         u32 temp;
 906
 907         if (on) {
 908                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 909                           dev_priv->gart_vm_start,
 910                           (long)dev_priv->gart_info.bus_addr,
 911                           dev_priv->gart_size);
 912
 913                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 914                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 915                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 916                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 917                                                              RS690_BLOCK_GFX_D3_EN));
 918                 else
 919                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 920
 921                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 922                                                                RS480_VA_SIZE_32MB));
 923
 924                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 925                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 926                                                         RS480_TLB_ENABLE |
 927                                                         RS480_GTW_LAC_EN |
 928                                                         RS480_1LEVEL_GART));
 929
 930                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 931                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 932                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 933
 934                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 935                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 936                                                       RS480_REQ_TYPE_SNOOP_DIS));
 937
 938                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 939
 940                 dev_priv->gart_size = 32*1024*1024;
 941                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 942                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 943
 944                 radeon_write_agp_location(dev_priv, temp);
 945
 946                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 947                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 948                                                                RS480_VA_SIZE_32MB));
 949
 950                 do {
 951                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 952                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 953                                 break;
 954                         DRM_UDELAY(1);
 955                 } while (1);
 956
 957                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 958                                 RS480_GART_CACHE_INVALIDATE);
 959
 960                 do {
 961                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 962                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 963                                 break;
 964                         DRM_UDELAY(1);
 965                 } while (1);
 966
 967                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 968         } else {
 969                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 970         }
 971 }
 972
 973 /* Enable or disable IGP GART on the chip */
 974 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 975 {
 976         u32 temp;
 977         int i;
 978
 979         if (on) {
 980                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 981                          dev_priv->gart_vm_start,
 982                          (long)dev_priv->gart_info.bus_addr,
 983                          dev_priv->gart_size);
 984
 985                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 986                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 987
 988                 for (i = 0; i < 19; i++)
 989                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 990                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 991                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 992                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 993                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 994                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 995                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 996
 997                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 998                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 999
1000                 /* disable all other contexts */
1001                 for (i = 1; i < 8; i++)
1002                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1003
1004                 /* setup the page table aperture */
1005                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1006                                 dev_priv->gart_info.bus_addr);
1007                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1008                                 dev_priv->gart_vm_start);
1009                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1010                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1011                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1012
1013                 /* setup the system aperture */
1014                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1015                                 dev_priv->gart_vm_start);
1016                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1017                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1018
1019                 /* enable page tables */
1020                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1021                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1022
1023                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1024                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1025
1026                 /* invalidate the cache */
1027                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1028
1029                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1030                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1031                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1032
1033                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1034                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1035                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1036
1037                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1038                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1039                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1040
1041         } else {
1042                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1043                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1044                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1045                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1046         }
1047 }
1048
1049 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1050 {
1051         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1052         if (on) {
1053
1054                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1055                           dev_priv->gart_vm_start,
1056                           (long)dev_priv->gart_info.bus_addr,
1057                           dev_priv->gart_size);
1058                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1059                                   dev_priv->gart_vm_start);
1060                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1061                                   dev_priv->gart_info.bus_addr);
1062                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1063                                   dev_priv->gart_vm_start);
1064                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1065                                   dev_priv->gart_vm_start +
1066                                   dev_priv->gart_size - 1);
1067
1068                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1069
1070                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1071                                   RADEON_PCIE_TX_GART_EN);
1072         } else {
1073                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1074                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1075         }
1076 }
1077
1078 /* Enable or disable PCI GART on the chip */
1079 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1080 {
1081         u32 tmp;
1082
1083         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1084             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1085             (dev_priv->flags & RADEON_IS_IGPGART)) {
1086                 radeon_set_igpgart(dev_priv, on);
1087                 return;
1088         }
1089
1090         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1091                 rs600_set_igpgart(dev_priv, on);
1092                 return;
1093         }
1094
1095         if (dev_priv->flags & RADEON_IS_PCIE) {
1096                 radeon_set_pciegart(dev_priv, on);
1097                 return;
1098         }
1099
1100         tmp = RADEON_READ(RADEON_AIC_CNTL);
1101
1102         if (on) {
1103                 RADEON_WRITE(RADEON_AIC_CNTL,
1104                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1105
1106                 /* set PCI GART page-table base address
1107                  */
1108                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1109
1110                 /* set address range for PCI address translate
1111                  */
1112                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1113                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1114                              + dev_priv->gart_size - 1);
1115
1116                 /* Turn off AGP aperture -- is this required for PCI GART?
1117                  */
1118                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1119                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1120         } else {
1121                 RADEON_WRITE(RADEON_AIC_CNTL,
1122                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1123         }
1124 }
1125
1126 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1127 {
1128         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1129         struct radeon_virt_surface *vp;
1130         int i;
1131
1132         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1133                 if (!dev_priv->virt_surfaces[i].file_priv ||
1134                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1135                         break;
1136         }
1137         if (i >= 2 * RADEON_MAX_SURFACES)
1138                 return -ENOMEM;
1139         vp = &dev_priv->virt_surfaces[i];
1140
1141         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1142                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1143                 if (sp->refcount)
1144                         continue;
1145
1146                 vp->surface_index = i;
1147                 vp->lower = gart_info->bus_addr;
1148                 vp->upper = vp->lower + gart_info->table_size;
1149                 vp->flags = 0;
1150                 vp->file_priv = PCIGART_FILE_PRIV;
1151
1152                 sp->refcount = 1;
1153                 sp->lower = vp->lower;
1154                 sp->upper = vp->upper;
1155                 sp->flags = 0;
1156
1157                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1158                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1159                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1160                 return 0;
1161         }
1162
1163         return -ENOMEM;
1164 }
1165
1166 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1167                              struct drm_file *file_priv)
1168 {
1169         drm_radeon_private_t *dev_priv = dev->dev_private;
1170         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1171
1172         DRM_DEBUG("\n");
1173
1174         /* if we require new memory map but we don't have it fail */
1175         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1176                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1177                 radeon_do_cleanup_cp(dev);
1178                 return -EINVAL;
1179         }
1180
1181         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1182                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1183                 dev_priv->flags &= ~RADEON_IS_AGP;
1184         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1185                    && !init->is_pci) {
1186                 DRM_DEBUG("Restoring AGP flag\n");
1187                 dev_priv->flags |= RADEON_IS_AGP;
1188         }
1189
1190         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1191                 DRM_ERROR("PCI GART memory not allocated!\n");
1192                 radeon_do_cleanup_cp(dev);
1193                 return -EINVAL;
1194         }
1195
1196         dev_priv->usec_timeout = init->usec_timeout;
1197         if (dev_priv->usec_timeout < 1 ||
1198             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1199                 DRM_DEBUG("TIMEOUT problem!\n");
1200                 radeon_do_cleanup_cp(dev);
1201                 return -EINVAL;
1202         }
1203
1204         /* Enable vblank on CRTC1 for older X servers
1205          */
1206         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1207
1208         switch(init->func) {
1209         case RADEON_INIT_R200_CP:
1210                 dev_priv->microcode_version = UCODE_R200;
1211                 break;
1212         case RADEON_INIT_R300_CP:
1213                 dev_priv->microcode_version = UCODE_R300;
1214                 break;
1215         default:
1216                 dev_priv->microcode_version = UCODE_R100;
1217         }
1218
1219         dev_priv->do_boxes = 0;
1220         dev_priv->cp_mode = init->cp_mode;
1221
1222         /* We don't support anything other than bus-mastering ring mode,
1223          * but the ring can be in either AGP or PCI space for the ring
1224          * read pointer.
1225          */
1226         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1227             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1228                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1229                 radeon_do_cleanup_cp(dev);
1230                 return -EINVAL;
1231         }
1232
1233         switch (init->fb_bpp) {
1234         case 16:
1235                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1236                 break;
1237         case 32:
1238         default:
1239                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1240                 break;
1241         }
1242         dev_priv->front_offset = init->front_offset;
1243         dev_priv->front_pitch = init->front_pitch;
1244         dev_priv->back_offset = init->back_offset;
1245         dev_priv->back_pitch = init->back_pitch;
1246
1247         switch (init->depth_bpp) {
1248         case 16:
1249                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1250                 break;
1251         case 32:
1252         default:
1253                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1254                 break;
1255         }
1256         dev_priv->depth_offset = init->depth_offset;
1257         dev_priv->depth_pitch = init->depth_pitch;
1258
1259         /* Hardware state for depth clears.  Remove this if/when we no
1260          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1261          * all values to prevent unwanted 3D state from slipping through
1262          * and screwing with the clear operation.
1263          */
1264         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1265                                            (dev_priv->color_fmt << 10) |
1266                                            (dev_priv->microcode_version ==
1267                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1268
1269         dev_priv->depth_clear.rb3d_zstencilcntl =
1270             (dev_priv->depth_fmt |
1271              RADEON_Z_TEST_ALWAYS |
1272              RADEON_STENCIL_TEST_ALWAYS |
1273              RADEON_STENCIL_S_FAIL_REPLACE |
1274              RADEON_STENCIL_ZPASS_REPLACE |
1275              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1276
1277         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1278                                          RADEON_BFACE_SOLID |
1279                                          RADEON_FFACE_SOLID |
1280                                          RADEON_FLAT_SHADE_VTX_LAST |
1281                                          RADEON_DIFFUSE_SHADE_FLAT |
1282                                          RADEON_ALPHA_SHADE_FLAT |
1283                                          RADEON_SPECULAR_SHADE_FLAT |
1284                                          RADEON_FOG_SHADE_FLAT |
1285                                          RADEON_VTX_PIX_CENTER_OGL |
1286                                          RADEON_ROUND_MODE_TRUNC |
1287                                          RADEON_ROUND_PREC_8TH_PIX);
1288
1289
1290         dev_priv->ring_offset = init->ring_offset;
1291         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1292         dev_priv->buffers_offset = init->buffers_offset;
1293         dev_priv->gart_textures_offset = init->gart_textures_offset;
1294
1295         master_priv->sarea = drm_legacy_getsarea(dev);
1296         if (!master_priv->sarea) {
1297                 DRM_ERROR("could not find sarea!\n");
1298                 radeon_do_cleanup_cp(dev);
1299                 return -EINVAL;
1300         }
1301
1302         dev_priv->cp_ring = drm_legacy_findmap(dev, init->ring_offset);
1303         if (!dev_priv->cp_ring) {
1304                 DRM_ERROR("could not find cp ring region!\n");
1305                 radeon_do_cleanup_cp(dev);
1306                 return -EINVAL;
1307         }
1308         dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
1309         if (!dev_priv->ring_rptr) {
1310                 DRM_ERROR("could not find ring read pointer!\n");
1311                 radeon_do_cleanup_cp(dev);
1312                 return -EINVAL;
1313         }
1314         dev->agp_buffer_token = init->buffers_offset;
1315         dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
1316         if (!dev->agp_buffer_map) {
1317                 DRM_ERROR("could not find dma buffer region!\n");
1318                 radeon_do_cleanup_cp(dev);
1319                 return -EINVAL;
1320         }
1321
1322         if (init->gart_textures_offset) {
1323                 dev_priv->gart_textures =
1324                     drm_legacy_findmap(dev, init->gart_textures_offset);
1325                 if (!dev_priv->gart_textures) {
1326                         DRM_ERROR("could not find GART texture region!\n");
1327                         radeon_do_cleanup_cp(dev);
1328                         return -EINVAL;
1329                 }
1330         }
1331
1332 #if IS_ENABLED(CONFIG_AGP)
1333         if (dev_priv->flags & RADEON_IS_AGP) {
1334                 drm_legacy_ioremap_wc(dev_priv->cp_ring, dev);
1335                 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
1336                 drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
1337                 if (!dev_priv->cp_ring->handle ||
1338                     !dev_priv->ring_rptr->handle ||
1339                     !dev->agp_buffer_map->handle) {
1340                         DRM_ERROR("could not find ioremap agp regions!\n");
1341                         radeon_do_cleanup_cp(dev);
1342                         return -EINVAL;
1343                 }
1344         } else
1345 #endif
1346         {
1347                 dev_priv->cp_ring->handle =
1348                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1349                 dev_priv->ring_rptr->handle =
1350                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1351                 dev->agp_buffer_map->handle =
1352                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1353
1354                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1355                           dev_priv->cp_ring->handle);
1356                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1357                           dev_priv->ring_rptr->handle);
1358                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1359                           dev->agp_buffer_map->handle);
1360         }
1361
1362         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1363         dev_priv->fb_size =
1364                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1365                 - dev_priv->fb_location;
1366
1367         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1368                                         ((dev_priv->front_offset
1369                                           + dev_priv->fb_location) >> 10));
1370
1371         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1372                                        ((dev_priv->back_offset
1373                                          + dev_priv->fb_location) >> 10));
1374
1375         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1376                                         ((dev_priv->depth_offset
1377                                           + dev_priv->fb_location) >> 10));
1378
1379         dev_priv->gart_size = init->gart_size;
1380
1381         /* New let's set the memory map ... */
1382         if (dev_priv->new_memmap) {
1383                 u32 base = 0;
1384
1385                 DRM_INFO("Setting GART location based on new memory map\n");
1386
1387                 /* If using AGP, try to locate the AGP aperture at the same
1388                  * location in the card and on the bus, though we have to
1389                  * align it down.
1390                  */
1391 #if IS_ENABLED(CONFIG_AGP)
1392                 if (dev_priv->flags & RADEON_IS_AGP) {
1393                         base = dev->agp->base;
1394                         /* Check if valid */
1395                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1396                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1397                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1398                                          dev->agp->base);
1399                                 base = 0;
1400                         }
1401                 }
1402 #endif
1403                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1404                 if (base == 0) {
1405                         base = dev_priv->fb_location + dev_priv->fb_size;
1406                         if (base < dev_priv->fb_location ||
1407                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1408                                 base = dev_priv->fb_location
1409                                         - dev_priv->gart_size;
1410                 }
1411                 dev_priv->gart_vm_start = base & 0xffc00000u;
1412                 if (dev_priv->gart_vm_start != base)
1413                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1414                                  base, dev_priv->gart_vm_start);
1415         } else {
1416                 DRM_INFO("Setting GART location based on old memory map\n");
1417                 dev_priv->gart_vm_start = dev_priv->fb_location +
1418                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1419         }
1420
1421 #if IS_ENABLED(CONFIG_AGP)
1422         if (dev_priv->flags & RADEON_IS_AGP)
1423                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1424                                                  - dev->agp->base
1425                                                  + dev_priv->gart_vm_start);
1426         else
1427 #endif
1428                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1429                                         - (unsigned long)dev->sg->virtual
1430                                         + dev_priv->gart_vm_start);
1431
1432         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1433         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1434         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1435                   dev_priv->gart_buffers_offset);
1436
1437         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1438         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1439                               + init->ring_size / sizeof(u32));
1440         dev_priv->ring.size = init->ring_size;
1441         dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
1442
1443         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1444         dev_priv->ring.rptr_update_l2qw = order_base_2( /* init->rptr_update */ 4096 / 8);
1445
1446         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1447         dev_priv->ring.fetch_size_l2ow = order_base_2( /* init->fetch_size */ 32 / 16);
1448         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1449
1450         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1451
1452 #if IS_ENABLED(CONFIG_AGP)
1453         if (dev_priv->flags & RADEON_IS_AGP) {
1454                 /* Turn off PCI GART */
1455                 radeon_set_pcigart(dev_priv, 0);
1456         } else
1457 #endif
1458         {
1459                 u32 sctrl;
1460                 int ret;
1461
1462                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1463                 /* if we have an offset set from userspace */
1464                 if (dev_priv->pcigart_offset_set) {
1465                         dev_priv->gart_info.bus_addr =
1466                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1467                         dev_priv->gart_info.mapping.offset =
1468                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1469                         dev_priv->gart_info.mapping.size =
1470                             dev_priv->gart_info.table_size;
1471
1472                         drm_legacy_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1473                         dev_priv->gart_info.addr =
1474                             dev_priv->gart_info.mapping.handle;
1475
1476                         if (dev_priv->flags & RADEON_IS_PCIE)
1477                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1478                         else
1479                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1480                         dev_priv->gart_info.gart_table_location =
1481                             DRM_ATI_GART_FB;
1482
1483                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1484                                   dev_priv->gart_info.addr,
1485                                   dev_priv->pcigart_offset);
1486                 } else {
1487                         if (dev_priv->flags & RADEON_IS_IGPGART)
1488                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1489                         else
1490                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1491                         dev_priv->gart_info.gart_table_location =
1492                             DRM_ATI_GART_MAIN;
1493                         dev_priv->gart_info.addr = NULL;
1494                         dev_priv->gart_info.bus_addr = 0;
1495                         if (dev_priv->flags & RADEON_IS_PCIE) {
1496                                 DRM_ERROR
1497                                     ("Cannot use PCI Express without GART in FB memory\n");
1498                                 radeon_do_cleanup_cp(dev);
1499                                 return -EINVAL;
1500                         }
1501                 }
1502
1503                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1504                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1505                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1506                         ret = r600_page_table_init(dev);
1507                 else
1508                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1509                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1510
1511                 if (!ret) {
1512                         DRM_ERROR("failed to init PCI GART!\n");
1513                         radeon_do_cleanup_cp(dev);
1514                         return -ENOMEM;
1515                 }
1516
1517                 ret = radeon_setup_pcigart_surface(dev_priv);
1518                 if (ret) {
1519                         DRM_ERROR("failed to setup GART surface!\n");
1520                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1521                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1522                         else
1523                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1524                         radeon_do_cleanup_cp(dev);
1525                         return ret;
1526                 }
1527
1528                 /* Turn on PCI GART */
1529                 radeon_set_pcigart(dev_priv, 1);
1530         }
1531
1532         if (!dev_priv->me_fw) {
1533                 int err = radeon_cp_init_microcode(dev_priv);
1534                 if (err) {
1535                         DRM_ERROR("Failed to load firmware!\n");
1536                         radeon_do_cleanup_cp(dev);
1537                         return err;
1538                 }
1539         }
1540         radeon_cp_load_microcode(dev_priv);
1541         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1542
1543         dev_priv->last_buf = 0;
1544
1545         radeon_do_engine_reset(dev);
1546         radeon_test_writeback(dev_priv);
1547
1548         return 0;
1549 }
1550
1551 static int radeon_do_cleanup_cp(struct drm_device * dev)
1552 {
1553         drm_radeon_private_t *dev_priv = dev->dev_private;
1554         DRM_DEBUG("\n");
1555
1556         /* Make sure interrupts are disabled here because the uninstall ioctl
1557          * may not have been called from userspace and after dev_private
1558          * is freed, it's too late.
1559          */
1560         if (dev->irq_enabled)
1561                 drm_irq_uninstall(dev);
1562
1563 #if IS_ENABLED(CONFIG_AGP)
1564         if (dev_priv->flags & RADEON_IS_AGP) {
1565                 if (dev_priv->cp_ring != NULL) {
1566                         drm_legacy_ioremapfree(dev_priv->cp_ring, dev);
1567                         dev_priv->cp_ring = NULL;
1568                 }
1569                 if (dev_priv->ring_rptr != NULL) {
1570                         drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
1571                         dev_priv->ring_rptr = NULL;
1572                 }
1573                 if (dev->agp_buffer_map != NULL) {
1574                         drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
1575                         dev->agp_buffer_map = NULL;
1576                 }
1577         } else
1578 #endif
1579         {
1580
1581                 if (dev_priv->gart_info.bus_addr) {
1582                         /* Turn off PCI GART */
1583                         radeon_set_pcigart(dev_priv, 0);
1584                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1585                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1586                         else {
1587                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1588                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1589                         }
1590                 }
1591
1592                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1593                 {
1594                         drm_legacy_ioremapfree(&dev_priv->gart_info.mapping, dev);
1595                         dev_priv->gart_info.addr = NULL;
1596                 }
1597         }
1598         /* only clear to the start of flags */
1599         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1600
1601         return 0;
1602 }
1603
1604 /* This code will reinit the Radeon CP hardware after a resume from disc.
1605  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1606  * here we make sure that all Radeon hardware initialisation is re-done without
1607  * affecting running applications.
1608  *
1609  * Charl P. Botha <http://cpbotha.net>
1610  */
1611 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1612 {
1613         drm_radeon_private_t *dev_priv = dev->dev_private;
1614
1615         if (!dev_priv) {
1616                 DRM_ERROR("Called with no initialization\n");
1617                 return -EINVAL;
1618         }
1619
1620         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1621
1622 #if IS_ENABLED(CONFIG_AGP)
1623         if (dev_priv->flags & RADEON_IS_AGP) {
1624                 /* Turn off PCI GART */
1625                 radeon_set_pcigart(dev_priv, 0);
1626         } else
1627 #endif
1628         {
1629                 /* Turn on PCI GART */
1630                 radeon_set_pcigart(dev_priv, 1);
1631         }
1632
1633         radeon_cp_load_microcode(dev_priv);
1634         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1635
1636         dev_priv->have_z_offset = 0;
1637         radeon_do_engine_reset(dev);
1638         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1639
1640         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1641
1642         return 0;
1643 }
1644
1645 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1646 {
1647         drm_radeon_private_t *dev_priv = dev->dev_private;
1648         drm_radeon_init_t *init = data;
1649
1650         LOCK_TEST_WITH_RETURN(dev, file_priv);
1651
1652         if (init->func == RADEON_INIT_R300_CP)
1653                 r300_init_reg_flags(dev);
1654
1655         switch (init->func) {
1656         case RADEON_INIT_CP:
1657         case RADEON_INIT_R200_CP:
1658         case RADEON_INIT_R300_CP:
1659                 return radeon_do_init_cp(dev, init, file_priv);
1660         case RADEON_INIT_R600_CP:
1661                 return r600_do_init_cp(dev, init, file_priv);
1662         case RADEON_CLEANUP_CP:
1663                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1664                         return r600_do_cleanup_cp(dev);
1665                 else
1666                         return radeon_do_cleanup_cp(dev);
1667         }
1668
1669         return -EINVAL;
1670 }
1671
1672 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1673 {
1674         drm_radeon_private_t *dev_priv = dev->dev_private;
1675         DRM_DEBUG("\n");
1676
1677         LOCK_TEST_WITH_RETURN(dev, file_priv);
1678
1679         if (dev_priv->cp_running) {
1680                 DRM_DEBUG("while CP running\n");
1681                 return 0;
1682         }
1683         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1684                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1685                           dev_priv->cp_mode);
1686                 return 0;
1687         }
1688
1689         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1690                 r600_do_cp_start(dev_priv);
1691         else
1692                 radeon_do_cp_start(dev_priv);
1693
1694         return 0;
1695 }
1696
1697 /* Stop the CP.  The engine must have been idled before calling this
1698  * routine.
1699  */
1700 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1701 {
1702         drm_radeon_private_t *dev_priv = dev->dev_private;
1703         drm_radeon_cp_stop_t *stop = data;
1704         int ret;
1705         DRM_DEBUG("\n");
1706
1707         LOCK_TEST_WITH_RETURN(dev, file_priv);
1708
1709         if (!dev_priv->cp_running)
1710                 return 0;
1711
1712         /* Flush any pending CP commands.  This ensures any outstanding
1713          * commands are exectuted by the engine before we turn it off.
1714          */
1715         if (stop->flush) {
1716                 radeon_do_cp_flush(dev_priv);
1717         }
1718
1719         /* If we fail to make the engine go idle, we return an error
1720          * code so that the DRM ioctl wrapper can try again.
1721          */
1722         if (stop->idle) {
1723                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1724                         ret = r600_do_cp_idle(dev_priv);
1725                 else
1726                         ret = radeon_do_cp_idle(dev_priv);
1727                 if (ret)
1728                         return ret;
1729         }
1730
1731         /* Finally, we can turn off the CP.  If the engine isn't idle,
1732          * we will get some dropped triangles as they won't be fully
1733          * rendered before the CP is shut down.
1734          */
1735         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1736                 r600_do_cp_stop(dev_priv);
1737         else
1738                 radeon_do_cp_stop(dev_priv);
1739
1740         /* Reset the engine */
1741         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1742                 r600_do_engine_reset(dev);
1743         else
1744                 radeon_do_engine_reset(dev);
1745
1746         return 0;
1747 }
1748
1749 void radeon_do_release(struct drm_device * dev)
1750 {
1751         drm_radeon_private_t *dev_priv = dev->dev_private;
1752         int i, ret;
1753
1754         if (dev_priv) {
1755                 if (dev_priv->cp_running) {
1756                         /* Stop the cp */
1757                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1758                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1759                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1760 #ifdef __linux__
1761                                         schedule();
1762 #else
1763                                         tsleep(&ret, PZERO, "rdnrel", 1);
1764 #endif
1765                                 }
1766                         } else {
1767                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1768                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1769 #ifdef __linux__
1770                                         schedule();
1771 #else
1772                                         tsleep(&ret, PZERO, "rdnrel", 1);
1773 #endif
1774                                 }
1775                         }
1776                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1777                                 r600_do_cp_stop(dev_priv);
1778                                 r600_do_engine_reset(dev);
1779                         } else {
1780                                 radeon_do_cp_stop(dev_priv);
1781                                 radeon_do_engine_reset(dev);
1782                         }
1783                 }
1784
1785                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1786                         /* Disable *all* interrupts */
1787                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1788                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1789
1790                         if (dev_priv->mmio) {   /* remove all surfaces */
1791                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1792                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1793                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1794                                                      16 * i, 0);
1795                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1796                                                      16 * i, 0);
1797                                 }
1798                         }
1799                 }
1800
1801                 /* Free memory heap structures */
1802                 radeon_mem_takedown(&(dev_priv->gart_heap));
1803                 radeon_mem_takedown(&(dev_priv->fb_heap));
1804
1805                 /* deallocate kernel resources */
1806                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1807                         r600_do_cleanup_cp(dev);
1808                 else
1809                         radeon_do_cleanup_cp(dev);
1810                 release_firmware(dev_priv->me_fw);
1811                 dev_priv->me_fw = NULL;
1812                 release_firmware(dev_priv->pfp_fw);
1813                 dev_priv->pfp_fw = NULL;
1814         }
1815 }
1816
1817 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1818  */
1819 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1820 {
1821         drm_radeon_private_t *dev_priv = dev->dev_private;
1822         DRM_DEBUG("\n");
1823
1824         LOCK_TEST_WITH_RETURN(dev, file_priv);
1825
1826         if (!dev_priv) {
1827                 DRM_DEBUG("called before init done\n");
1828                 return -EINVAL;
1829         }
1830
1831         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1832                 r600_do_cp_reset(dev_priv);
1833         else
1834                 radeon_do_cp_reset(dev_priv);
1835
1836         /* The CP is no longer running after an engine reset */
1837         dev_priv->cp_running = 0;
1838
1839         return 0;
1840 }
1841
1842 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1843 {
1844         drm_radeon_private_t *dev_priv = dev->dev_private;
1845         DRM_DEBUG("\n");
1846
1847         LOCK_TEST_WITH_RETURN(dev, file_priv);
1848
1849         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1850                 return r600_do_cp_idle(dev_priv);
1851         else
1852                 return radeon_do_cp_idle(dev_priv);
1853 }
1854
1855 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1856  */
1857 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1858 {
1859         drm_radeon_private_t *dev_priv = dev->dev_private;
1860         DRM_DEBUG("\n");
1861
1862         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1863                 return r600_do_resume_cp(dev, file_priv);
1864         else
1865                 return radeon_do_resume_cp(dev, file_priv);
1866 }
1867
1868 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1869 {
1870         drm_radeon_private_t *dev_priv = dev->dev_private;
1871         DRM_DEBUG("\n");
1872
1873         LOCK_TEST_WITH_RETURN(dev, file_priv);
1874
1875         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1876                 return r600_do_engine_reset(dev);
1877         else
1878                 return radeon_do_engine_reset(dev);
1879 }
1880
1881 /* ================================================================
1882  * Fullscreen mode
1883  */
1884
1885 /* KW: Deprecated to say the least:
1886  */
1887 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1888 {
1889         return 0;
1890 }
1891
1892 /* ================================================================
1893  * Freelist management
1894  */
1895
1896 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1897  *   bufs until freelist code is used.  Note this hides a problem with
1898  *   the scratch register * (used to keep track of last buffer
1899  *   completed) being written to before * the last buffer has actually
1900  *   completed rendering.
1901  *
1902  * KW:  It's also a good way to find free buffers quickly.
1903  *
1904  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1905  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1906  * we essentially have to do this, else old clients will break.
1907  *
1908  * However, it does leave open a potential deadlock where all the
1909  * buffers are held by other clients, which can't release them because
1910  * they can't get the lock.
1911  */
1912
1913 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1914 {
1915         struct drm_device_dma *dma = dev->dma;
1916         drm_radeon_private_t *dev_priv = dev->dev_private;
1917         drm_radeon_buf_priv_t *buf_priv;
1918         struct drm_buf *buf;
1919         int i, t;
1920         int start;
1921
1922         if (++dev_priv->last_buf >= dma->buf_count)
1923                 dev_priv->last_buf = 0;
1924
1925         start = dev_priv->last_buf;
1926
1927         for (t = 0; t < dev_priv->usec_timeout; t++) {
1928                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1929                 DRM_DEBUG("done_age = %d\n", done_age);
1930                 for (i = 0; i < dma->buf_count; i++) {
1931                         buf = dma->buflist[start];
1932                         buf_priv = buf->dev_private;
1933                         if (buf->file_priv == NULL || (buf->pending &&
1934                                                        buf_priv->age <=
1935                                                        done_age)) {
1936                                 dev_priv->stats.requested_bufs++;
1937                                 buf->pending = 0;
1938                                 return buf;
1939                         }
1940                         if (++start >= dma->buf_count)
1941                                 start = 0;
1942                 }
1943
1944                 if (t) {
1945                         DRM_UDELAY(1);
1946                         dev_priv->stats.freelist_loops++;
1947                 }
1948         }
1949
1950         return NULL;
1951 }
1952
1953 void radeon_freelist_reset(struct drm_device * dev)
1954 {
1955         struct drm_device_dma *dma = dev->dma;
1956         drm_radeon_private_t *dev_priv = dev->dev_private;
1957         int i;
1958
1959         dev_priv->last_buf = 0;
1960         for (i = 0; i < dma->buf_count; i++) {
1961                 struct drm_buf *buf = dma->buflist[i];
1962                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1963                 buf_priv->age = 0;
1964         }
1965 }
1966
1967 /* ================================================================
1968  * CP command submission
1969  */
1970
1971 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1972 {
1973         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1974         int i;
1975         u32 last_head = GET_RING_HEAD(dev_priv);
1976
1977         for (i = 0; i < dev_priv->usec_timeout; i++) {
1978                 u32 head = GET_RING_HEAD(dev_priv);
1979
1980                 ring->space = (head - ring->tail) * sizeof(u32);
1981                 if (ring->space <= 0)
1982                         ring->space += ring->size;
1983                 if (ring->space > n)
1984                         return 0;
1985
1986                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1987
1988                 if (head != last_head)
1989                         i = 0;
1990                 last_head = head;
1991
1992                 DRM_UDELAY(1);
1993         }
1994
1995         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1996 #if RADEON_FIFO_DEBUG
1997         radeon_status(dev_priv);
1998         DRM_ERROR("failed!\n");
1999 #endif
2000         return -EBUSY;
2001 }
2002
2003 static int radeon_cp_get_buffers(struct drm_device *dev,
2004                                  struct drm_file *file_priv,
2005                                  struct drm_dma * d)
2006 {
2007         int i;
2008         struct drm_buf *buf;
2009
2010         for (i = d->granted_count; i < d->request_count; i++) {
2011                 buf = radeon_freelist_get(dev);
2012                 if (!buf)
2013                         return -EBUSY;  /* NOTE: broken client */
2014
2015                 buf->file_priv = file_priv;
2016
2017                 if (copy_to_user(&d->request_indices[i], &buf->idx,
2018                                      sizeof(buf->idx)))
2019                         return -EFAULT;
2020                 if (copy_to_user(&d->request_sizes[i], &buf->total,
2021                                      sizeof(buf->total)))
2022                         return -EFAULT;
2023
2024                 d->granted_count++;
2025         }
2026         return 0;
2027 }
2028
2029 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2030 {
2031         struct drm_device_dma *dma = dev->dma;
2032         int ret = 0;
2033         struct drm_dma *d = data;
2034
2035         LOCK_TEST_WITH_RETURN(dev, file_priv);
2036
2037         /* Please don't send us buffers.
2038          */
2039         if (d->send_count != 0) {
2040                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2041                           DRM_CURRENTPID, d->send_count);
2042                 return -EINVAL;
2043         }
2044
2045         /* We'll send you buffers.
2046          */
2047         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2048                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2049                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2050                 return -EINVAL;
2051         }
2052
2053         d->granted_count = 0;
2054
2055         if (d->request_count) {
2056                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2057         }
2058
2059         return ret;
2060 }
2061
2062 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2063 {
2064         drm_radeon_private_t *dev_priv;
2065         int ret = 0;
2066
2067         dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2068         if (dev_priv == NULL)
2069                 return -ENOMEM;
2070
2071         dev->dev_private = (void *)dev_priv;
2072         dev_priv->flags = flags;
2073
2074         switch (flags & RADEON_FAMILY_MASK) {
2075         case CHIP_R100:
2076         case CHIP_RV200:
2077         case CHIP_R200:
2078         case CHIP_R300:
2079         case CHIP_R350:
2080         case CHIP_R420:
2081         case CHIP_R423:
2082         case CHIP_RV410:
2083         case CHIP_RV515:
2084         case CHIP_R520:
2085         case CHIP_RV570:
2086         case CHIP_R580:
2087                 dev_priv->flags |= RADEON_HAS_HIERZ;
2088                 break;
2089         default:
2090                 /* all other chips have no hierarchical z buffer */
2091                 break;
2092         }
2093
2094         pci_set_master(dev->pdev);
2095
2096         if (drm_pci_device_is_agp(dev))
2097                 dev_priv->flags |= RADEON_IS_AGP;
2098         else if (pci_is_pcie(dev->pdev))
2099                 dev_priv->flags |= RADEON_IS_PCIE;
2100         else
2101                 dev_priv->flags |= RADEON_IS_PCI;
2102
2103         ret = drm_legacy_addmap(dev, pci_resource_start(dev->pdev, 2),
2104                                 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2105                                 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2106         if (ret != 0)
2107                 return ret;
2108
2109         ret = drm_vblank_init(dev, 2);
2110         if (ret) {
2111                 radeon_driver_unload(dev);
2112                 return ret;
2113         }
2114
2115         DRM_DEBUG("%s card detected\n",
2116                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2117         return ret;
2118 }
2119
2120 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2121 {
2122         struct drm_radeon_master_private *master_priv;
2123         unsigned long sareapage;
2124         int ret;
2125
2126         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2127         if (!master_priv)
2128                 return -ENOMEM;
2129
2130         /* prebuild the SAREA */
2131         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2132         ret = drm_legacy_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2133                                 &master_priv->sarea);
2134         if (ret) {
2135                 DRM_ERROR("SAREA setup failed\n");
2136                 kfree(master_priv);
2137                 return ret;
2138         }
2139         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2140         master_priv->sarea_priv->pfCurrentPage = 0;
2141
2142         master->driver_priv = master_priv;
2143         return 0;
2144 }
2145
2146 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2147 {
2148         struct drm_radeon_master_private *master_priv = master->driver_priv;
2149
2150         if (!master_priv)
2151                 return;
2152
2153         if (master_priv->sarea_priv &&
2154             master_priv->sarea_priv->pfCurrentPage != 0)
2155                 radeon_cp_dispatch_flip(dev, master);
2156
2157         master_priv->sarea_priv = NULL;
2158         if (master_priv->sarea)
2159                 drm_legacy_rmmap_locked(dev, master_priv->sarea);
2160
2161         kfree(master_priv);
2162
2163         master->driver_priv = NULL;
2164 }
2165
2166 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2167  * have to find them.
2168  */
2169 int radeon_driver_firstopen(struct drm_device *dev)
2170 {
2171         int ret;
2172         drm_local_map_t *map;
2173         drm_radeon_private_t *dev_priv = dev->dev_private;
2174
2175         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2176
2177         dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2178         ret = drm_legacy_addmap(dev, dev_priv->fb_aper_offset,
2179                                 pci_resource_len(dev->pdev, 0),
2180                                 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map);
2181         if (ret != 0)
2182                 return ret;
2183
2184         return 0;
2185 }
2186
2187 int radeon_driver_unload(struct drm_device *dev)
2188 {
2189         drm_radeon_private_t *dev_priv = dev->dev_private;
2190
2191         DRM_DEBUG("\n");
2192
2193         drm_legacy_rmmap(dev, dev_priv->mmio);
2194
2195         kfree(dev_priv);
2196
2197         dev->dev_private = NULL;
2198         return 0;
2199 }
2200
2201 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2202 {
2203         int i;
2204         u32 *ring;
2205         int tail_aligned;
2206
2207         /* check if the ring is padded out to 16-dword alignment */
2208
2209         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2210         if (tail_aligned) {
2211                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2212
2213                 ring = dev_priv->ring.start;
2214                 /* pad with some CP_PACKET2 */
2215                 for (i = 0; i < num_p2; i++)
2216                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2217
2218                 dev_priv->ring.tail += i;
2219
2220                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2221         }
2222
2223         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2224
2225         mb();
2226         GET_RING_HEAD( dev_priv );
2227
2228         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2229                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2230                 /* read from PCI bus to ensure correct posting */
2231                 RADEON_READ(R600_CP_RB_RPTR);
2232         } else {
2233                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2234                 /* read from PCI bus to ensure correct posting */
2235                 RADEON_READ(RADEON_CP_RB_RPTR);
2236         }
2237 }