2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/acpi.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
33 #include <drm/drm_device.h>
37 #include "radeon_reg.h"
43 /* If you boot an IGP board with a discrete card as the primary,
44 * the IGP rom is not accessible via the rom bar as the IGP rom is
45 * part of the system bios. On boot, the system bios puts a
46 * copy of the igp rom at the start of vram if a discrete card is
49 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
51 uint8_t __iomem *bios;
52 resource_size_t vram_base;
53 resource_size_t size = 256 * 1024; /* ??? */
55 if (!(rdev->flags & RADEON_IS_IGP))
56 if (!radeon_card_posted(rdev))
60 vram_base = pci_resource_start(rdev->pdev, 0);
61 bios = ioremap(vram_base, size);
66 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
70 rdev->bios = kmalloc(size, GFP_KERNEL);
71 if (rdev->bios == NULL) {
75 memcpy_fromio(rdev->bios, bios, size);
80 static bool radeon_read_bios(struct radeon_device *rdev)
82 uint8_t __iomem *bios, val1, val2;
86 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
87 bios = pci_map_rom(rdev->pdev, &size);
92 val1 = readb(&bios[0]);
93 val2 = readb(&bios[1]);
95 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
96 pci_unmap_rom(rdev->pdev, bios);
99 rdev->bios = kzalloc(size, GFP_KERNEL);
100 if (rdev->bios == NULL) {
101 pci_unmap_rom(rdev->pdev, bios);
104 memcpy_fromio(rdev->bios, bios, size);
105 pci_unmap_rom(rdev->pdev, bios);
109 static bool radeon_read_platform_bios(struct radeon_device *rdev)
111 phys_addr_t rom = rdev->pdev->rom;
112 size_t romlen = rdev->pdev->romlen;
117 if (!rom || romlen == 0)
120 rdev->bios = kzalloc(romlen, GFP_KERNEL);
124 bios = ioremap(rom, romlen);
128 memcpy_fromio(rdev->bios, bios, romlen);
131 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
141 /* ATRM is used to get the BIOS on the discrete cards in
144 /* retrieve the ROM in 4k blocks */
145 #define ATRM_BIOS_PAGE 4096
147 * radeon_atrm_call - fetch a chunk of the vbios
149 * @atrm_handle: acpi ATRM handle
150 * @bios: vbios image pointer
151 * @offset: offset of vbios image data to fetch
152 * @len: length of vbios image data to fetch
154 * Executes ATRM to fetch a chunk of the discrete
155 * vbios image on PX systems (all asics).
156 * Returns the length of the buffer fetched.
158 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
162 union acpi_object atrm_arg_elements[2], *obj;
163 struct acpi_object_list atrm_arg;
164 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
167 atrm_arg.pointer = &atrm_arg_elements[0];
169 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
170 atrm_arg_elements[0].integer.value = offset;
172 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
173 atrm_arg_elements[1].integer.value = len;
175 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
176 if (ACPI_FAILURE(status)) {
177 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
181 obj = (union acpi_object *)buffer.pointer;
182 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
183 len = obj->buffer.length;
184 kfree(buffer.pointer);
188 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
191 int size = 256 * 1024;
193 struct pci_dev *pdev = NULL;
194 acpi_handle dhandle, atrm_handle;
198 /* ATRM is for the discrete card only */
199 if (rdev->flags & RADEON_IS_IGP)
202 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
203 dhandle = ACPI_HANDLE(&pdev->dev);
207 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
208 if (!ACPI_FAILURE(status)) {
215 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
216 dhandle = ACPI_HANDLE(&pdev->dev);
220 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
221 if (!ACPI_FAILURE(status)) {
231 rdev->bios = kmalloc(size, GFP_KERNEL);
233 DRM_ERROR("Unable to allocate bios\n");
237 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
238 ret = radeon_atrm_call(atrm_handle,
240 (i * ATRM_BIOS_PAGE),
242 if (ret < ATRM_BIOS_PAGE)
246 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
253 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
259 static bool ni_read_disabled_bios(struct radeon_device *rdev)
264 u32 vga_render_control;
268 bus_cntl = RREG32(R600_BUS_CNTL);
269 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
270 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
271 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
272 rom_cntl = RREG32(R600_ROM_CNTL);
275 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
276 if (!ASIC_IS_NODCE(rdev)) {
277 /* Disable VGA mode */
278 WREG32(AVIVO_D1VGA_CONTROL,
279 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
280 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
281 WREG32(AVIVO_D2VGA_CONTROL,
282 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
283 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
284 WREG32(AVIVO_VGA_RENDER_CONTROL,
285 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
287 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
289 r = radeon_read_bios(rdev);
292 WREG32(R600_BUS_CNTL, bus_cntl);
293 if (!ASIC_IS_NODCE(rdev)) {
294 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
295 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
296 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
298 WREG32(R600_ROM_CNTL, rom_cntl);
302 static bool r700_read_disabled_bios(struct radeon_device *rdev)
304 uint32_t viph_control;
306 uint32_t d1vga_control;
307 uint32_t d2vga_control;
308 uint32_t vga_render_control;
310 uint32_t cg_spll_func_cntl = 0;
311 uint32_t cg_spll_status;
314 viph_control = RREG32(RADEON_VIPH_CONTROL);
315 bus_cntl = RREG32(R600_BUS_CNTL);
316 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
317 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
318 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
319 rom_cntl = RREG32(R600_ROM_CNTL);
322 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
324 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
325 /* Disable VGA mode */
326 WREG32(AVIVO_D1VGA_CONTROL,
327 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
328 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
329 WREG32(AVIVO_D2VGA_CONTROL,
330 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
331 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
332 WREG32(AVIVO_VGA_RENDER_CONTROL,
333 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
335 if (rdev->family == CHIP_RV730) {
336 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
338 /* enable bypass mode */
339 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
340 R600_SPLL_BYPASS_EN));
342 /* wait for SPLL_CHG_STATUS to change to 1 */
344 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
345 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
347 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
349 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
351 r = radeon_read_bios(rdev);
354 if (rdev->family == CHIP_RV730) {
355 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
357 /* wait for SPLL_CHG_STATUS to change to 1 */
359 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
360 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
362 WREG32(RADEON_VIPH_CONTROL, viph_control);
363 WREG32(R600_BUS_CNTL, bus_cntl);
364 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
365 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
366 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
367 WREG32(R600_ROM_CNTL, rom_cntl);
371 static bool r600_read_disabled_bios(struct radeon_device *rdev)
373 uint32_t viph_control;
375 uint32_t d1vga_control;
376 uint32_t d2vga_control;
377 uint32_t vga_render_control;
379 uint32_t general_pwrmgt;
380 uint32_t low_vid_lower_gpio_cntl;
381 uint32_t medium_vid_lower_gpio_cntl;
382 uint32_t high_vid_lower_gpio_cntl;
383 uint32_t ctxsw_vid_lower_gpio_cntl;
384 uint32_t lower_gpio_enable;
387 viph_control = RREG32(RADEON_VIPH_CONTROL);
388 bus_cntl = RREG32(R600_BUS_CNTL);
389 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
390 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
391 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
392 rom_cntl = RREG32(R600_ROM_CNTL);
393 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
394 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
395 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
396 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
397 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
398 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
401 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
403 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
404 /* Disable VGA mode */
405 WREG32(AVIVO_D1VGA_CONTROL,
406 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
407 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
408 WREG32(AVIVO_D2VGA_CONTROL,
409 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
410 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
411 WREG32(AVIVO_VGA_RENDER_CONTROL,
412 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
414 WREG32(R600_ROM_CNTL,
415 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
416 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
417 R600_SCK_OVERWRITE));
419 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
420 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
421 (low_vid_lower_gpio_cntl & ~0x400));
422 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
423 (medium_vid_lower_gpio_cntl & ~0x400));
424 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
425 (high_vid_lower_gpio_cntl & ~0x400));
426 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
427 (ctxsw_vid_lower_gpio_cntl & ~0x400));
428 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
430 r = radeon_read_bios(rdev);
433 WREG32(RADEON_VIPH_CONTROL, viph_control);
434 WREG32(R600_BUS_CNTL, bus_cntl);
435 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
436 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
437 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
438 WREG32(R600_ROM_CNTL, rom_cntl);
439 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
440 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
441 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
442 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
443 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
444 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
448 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
450 uint32_t seprom_cntl1;
451 uint32_t viph_control;
453 uint32_t d1vga_control;
454 uint32_t d2vga_control;
455 uint32_t vga_render_control;
458 uint32_t gpiopad_mask;
461 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
462 viph_control = RREG32(RADEON_VIPH_CONTROL);
463 bus_cntl = RREG32(RV370_BUS_CNTL);
464 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
465 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
466 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
467 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
468 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
469 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
471 WREG32(RADEON_SEPROM_CNTL1,
472 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
473 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
474 WREG32(RADEON_GPIOPAD_A, 0);
475 WREG32(RADEON_GPIOPAD_EN, 0);
476 WREG32(RADEON_GPIOPAD_MASK, 0);
479 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
482 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
484 /* Disable VGA mode */
485 WREG32(AVIVO_D1VGA_CONTROL,
486 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
487 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
488 WREG32(AVIVO_D2VGA_CONTROL,
489 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
490 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
491 WREG32(AVIVO_VGA_RENDER_CONTROL,
492 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
494 r = radeon_read_bios(rdev);
497 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
498 WREG32(RADEON_VIPH_CONTROL, viph_control);
499 WREG32(RV370_BUS_CNTL, bus_cntl);
500 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
501 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
502 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
503 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
504 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
505 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
509 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
511 uint32_t seprom_cntl1;
512 uint32_t viph_control;
514 uint32_t crtc_gen_cntl;
515 uint32_t crtc2_gen_cntl;
516 uint32_t crtc_ext_cntl;
517 uint32_t fp2_gen_cntl;
520 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
521 viph_control = RREG32(RADEON_VIPH_CONTROL);
522 if (rdev->flags & RADEON_IS_PCIE)
523 bus_cntl = RREG32(RV370_BUS_CNTL);
525 bus_cntl = RREG32(RADEON_BUS_CNTL);
526 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
528 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
531 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
532 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
535 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
536 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
539 WREG32(RADEON_SEPROM_CNTL1,
540 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
541 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
544 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
547 if (rdev->flags & RADEON_IS_PCIE)
548 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
550 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
552 /* Turn off mem requests and CRTC for both controllers */
553 WREG32(RADEON_CRTC_GEN_CNTL,
554 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
555 (RADEON_CRTC_DISP_REQ_EN_B |
556 RADEON_CRTC_EXT_DISP_EN)));
557 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
558 WREG32(RADEON_CRTC2_GEN_CNTL,
559 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
560 RADEON_CRTC2_DISP_REQ_EN_B));
563 WREG32(RADEON_CRTC_EXT_CNTL,
564 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
565 (RADEON_CRTC_SYNC_TRISTAT |
566 RADEON_CRTC_DISPLAY_DIS)));
568 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
569 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
572 r = radeon_read_bios(rdev);
575 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
576 WREG32(RADEON_VIPH_CONTROL, viph_control);
577 if (rdev->flags & RADEON_IS_PCIE)
578 WREG32(RV370_BUS_CNTL, bus_cntl);
580 WREG32(RADEON_BUS_CNTL, bus_cntl);
581 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
582 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
583 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
585 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
586 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
587 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
592 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
594 if (rdev->flags & RADEON_IS_IGP)
595 return igp_read_bios_from_vram(rdev);
596 else if (rdev->family >= CHIP_BARTS)
597 return ni_read_disabled_bios(rdev);
598 else if (rdev->family >= CHIP_RV770)
599 return r700_read_disabled_bios(rdev);
600 else if (rdev->family >= CHIP_R600)
601 return r600_read_disabled_bios(rdev);
602 else if (rdev->family >= CHIP_RS600)
603 return avivo_read_disabled_bios(rdev);
605 return legacy_read_disabled_bios(rdev);
609 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
611 struct acpi_table_header *hdr;
613 UEFI_ACPI_VFCT *vfct;
616 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
618 tbl_size = hdr->length;
619 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
620 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
624 vfct = (UEFI_ACPI_VFCT *)hdr;
625 offset = vfct->VBIOSImageOffset;
627 while (offset < tbl_size) {
628 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
629 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
631 offset += sizeof(VFCT_IMAGE_HEADER);
632 if (offset > tbl_size) {
633 DRM_ERROR("ACPI VFCT image header truncated\n");
637 offset += vhdr->ImageLength;
638 if (offset > tbl_size) {
639 DRM_ERROR("ACPI VFCT image truncated\n");
643 if (vhdr->ImageLength &&
644 vhdr->PCIBus == rdev->pdev->bus->number &&
645 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
646 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
647 vhdr->VendorID == rdev->pdev->vendor &&
648 vhdr->DeviceID == rdev->pdev->device) {
649 rdev->bios = kmemdup(&vbios->VbiosContent,
659 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
663 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
669 bool radeon_get_bios(struct radeon_device *rdev)
674 r = radeon_atrm_get_bios(rdev);
676 r = radeon_acpi_vfct_bios(rdev);
678 r = igp_read_bios_from_vram(rdev);
680 r = radeon_read_bios(rdev);
682 r = radeon_read_disabled_bios(rdev);
684 r = radeon_read_platform_bios(rdev);
685 if (!r || rdev->bios == NULL) {
686 DRM_ERROR("Unable to locate a BIOS ROM\n");
690 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
691 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
696 if (RBIOS8(tmp + 0x14) != 0x0) {
697 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
701 rdev->bios_header_start = RBIOS16(0x48);
702 if (!rdev->bios_header_start) {
705 tmp = rdev->bios_header_start + 4;
706 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
707 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
708 rdev->is_atom_bios = true;
710 rdev->is_atom_bios = false;
713 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");