drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32 #include "radeon_asic.h"
  33
  34 extern void
  35 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  36                         uint32_t supported_device, u16 caps);
  37
  38 /* from radeon_legacy_encoder.c */
  39 extern void
  40 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  41                           uint32_t supported_device);
  42
  43 union atom_supported_devices {
  44         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  45         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  46         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  47 };
  48
  49 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  50                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  51                                           u8 index)
  52 {
  53         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  54         if ((rdev->family == CHIP_R420) ||
  55             (rdev->family == CHIP_R423) ||
  56             (rdev->family == CHIP_RV410)) {
  57                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  58                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  59                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  60                         gpio->ucClkMaskShift = 0x19;
  61                         gpio->ucDataMaskShift = 0x18;
  62                 }
  63         }
  64
  65         /* some evergreen boards have bad data for this entry */
  66         if (ASIC_IS_DCE4(rdev)) {
  67                 if ((index == 7) &&
  68                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  69                     (gpio->sucI2cId.ucAccess == 0)) {
  70                         gpio->sucI2cId.ucAccess = 0x97;
  71                         gpio->ucDataMaskShift = 8;
  72                         gpio->ucDataEnShift = 8;
  73                         gpio->ucDataY_Shift = 8;
  74                         gpio->ucDataA_Shift = 8;
  75                 }
  76         }
  77
  78         /* some DCE3 boards have bad data for this entry */
  79         if (ASIC_IS_DCE3(rdev)) {
  80                 if ((index == 4) &&
  81                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  82                     (gpio->sucI2cId.ucAccess == 0x94))
  83                         gpio->sucI2cId.ucAccess = 0x14;
  84         }
  85 }
  86
  87 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  88 {
  89         struct radeon_i2c_bus_rec i2c;
  90
  91         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  92
  93         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  94         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  95         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  96         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  97         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  98         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  99         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 100         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 101         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 102         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 103         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 104         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 105         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 106         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 107         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 108         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 109
 110         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 111                 i2c.hw_capable = true;
 112         else
 113                 i2c.hw_capable = false;
 114
 115         if (gpio->sucI2cId.ucAccess == 0xa0)
 116                 i2c.mm_i2c = true;
 117         else
 118                 i2c.mm_i2c = false;
 119
 120         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 121
 122         if (i2c.mask_clk_reg)
 123                 i2c.valid = true;
 124         else
 125                 i2c.valid = false;
 126
 127         return i2c;
 128 }
 129
 130 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 131                                                                uint8_t id)
 132 {
 133         struct atom_context *ctx = rdev->mode_info.atom_context;
 134         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 135         struct radeon_i2c_bus_rec i2c;
 136         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 137         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 138         uint16_t data_offset, size;
 139         int i, num_indices;
 140
 141         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 142         i2c.valid = false;
 143
 144         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 145                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 146
 147                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 148                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 149
 150                 gpio = &i2c_info->asGPIO_Info[0];
 151                 for (i = 0; i < num_indices; i++) {
 152
 153                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 154
 155                         if (gpio->sucI2cId.ucAccess == id) {
 156                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 157                                 break;
 158                         }
 159                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 160                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 161                 }
 162         }
 163
 164         return i2c;
 165 }
 166
 167 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 168 {
 169         struct atom_context *ctx = rdev->mode_info.atom_context;
 170         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 171         struct radeon_i2c_bus_rec i2c;
 172         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 173         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 174         uint16_t data_offset, size;
 175         int i, num_indices;
 176         char stmp[32];
 177
 178         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 179                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 180
 181                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 182                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 183
 184                 gpio = &i2c_info->asGPIO_Info[0];
 185                 for (i = 0; i < num_indices; i++) {
 186                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 187
 188                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 189
 190                         if (i2c.valid) {
 191                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 192                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 193                         }
 194                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 195                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 196                 }
 197         }
 198 }
 199
 200 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
 201                                                    u8 id)
 202 {
 203         struct atom_context *ctx = rdev->mode_info.atom_context;
 204         struct radeon_gpio_rec gpio;
 205         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 206         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 207         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 208         u16 data_offset, size;
 209         int i, num_indices;
 210
 211         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 212         gpio.valid = false;
 213
 214         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 215                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 216
 217                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 218                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 219
 220                 pin = gpio_info->asGPIO_Pin;
 221                 for (i = 0; i < num_indices; i++) {
 222                         if (id == pin->ucGPIO_ID) {
 223                                 gpio.id = pin->ucGPIO_ID;
 224                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 225                                 gpio.shift = pin->ucGpioPinBitShift;
 226                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 227                                 gpio.valid = true;
 228                                 break;
 229                         }
 230                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 231                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 232                 }
 233         }
 234
 235         return gpio;
 236 }
 237
 238 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 239                                                             struct radeon_gpio_rec *gpio)
 240 {
 241         struct radeon_hpd hpd;
 242         u32 reg;
 243
 244         memset(&hpd, 0, sizeof(struct radeon_hpd));
 245
 246         if (ASIC_IS_DCE6(rdev))
 247                 reg = SI_DC_GPIO_HPD_A;
 248         else if (ASIC_IS_DCE4(rdev))
 249                 reg = EVERGREEN_DC_GPIO_HPD_A;
 250         else
 251                 reg = AVIVO_DC_GPIO_HPD_A;
 252
 253         hpd.gpio = *gpio;
 254         if (gpio->reg == reg) {
 255                 switch(gpio->mask) {
 256                 case (1 << 0):
 257                         hpd.hpd = RADEON_HPD_1;
 258                         break;
 259                 case (1 << 8):
 260                         hpd.hpd = RADEON_HPD_2;
 261                         break;
 262                 case (1 << 16):
 263                         hpd.hpd = RADEON_HPD_3;
 264                         break;
 265                 case (1 << 24):
 266                         hpd.hpd = RADEON_HPD_4;
 267                         break;
 268                 case (1 << 26):
 269                         hpd.hpd = RADEON_HPD_5;
 270                         break;
 271                 case (1 << 28):
 272                         hpd.hpd = RADEON_HPD_6;
 273                         break;
 274                 default:
 275                         hpd.hpd = RADEON_HPD_NONE;
 276                         break;
 277                 }
 278         } else
 279                 hpd.hpd = RADEON_HPD_NONE;
 280         return hpd;
 281 }
 282
 283 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 284                                      uint32_t supported_device,
 285                                      int *connector_type,
 286                                      struct radeon_i2c_bus_rec *i2c_bus,
 287                                      uint16_t *line_mux,
 288                                      struct radeon_hpd *hpd)
 289 {
 290
 291         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 292         if ((dev->pdev->device == 0x791e) &&
 293             (dev->pdev->subsystem_vendor == 0x1043) &&
 294             (dev->pdev->subsystem_device == 0x826d)) {
 295                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 296                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 297                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 298         }
 299
 300         /* Asrock RS600 board lists the DVI port as HDMI */
 301         if ((dev->pdev->device == 0x7941) &&
 302             (dev->pdev->subsystem_vendor == 0x1849) &&
 303             (dev->pdev->subsystem_device == 0x7941)) {
 304                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 305                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 306                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 307         }
 308
 309         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 310         if ((dev->pdev->device == 0x796e) &&
 311             (dev->pdev->subsystem_vendor == 0x1462) &&
 312             (dev->pdev->subsystem_device == 0x7302)) {
 313                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 314                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 315                         return false;
 316         }
 317
 318         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 319         if ((dev->pdev->device == 0x7941) &&
 320             (dev->pdev->subsystem_vendor == 0x147b) &&
 321             (dev->pdev->subsystem_device == 0x2412)) {
 322                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 323                         return false;
 324         }
 325
 326         /* Falcon NW laptop lists vga ddc line for LVDS */
 327         if ((dev->pdev->device == 0x5653) &&
 328             (dev->pdev->subsystem_vendor == 0x1462) &&
 329             (dev->pdev->subsystem_device == 0x0291)) {
 330                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 331                         i2c_bus->valid = false;
 332                         *line_mux = 53;
 333                 }
 334         }
 335
 336         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 337         if ((dev->pdev->device == 0x7146) &&
 338             (dev->pdev->subsystem_vendor == 0x17af) &&
 339             (dev->pdev->subsystem_device == 0x2058)) {
 340                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 341                         return false;
 342         }
 343
 344         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 345         if ((dev->pdev->device == 0x7142) &&
 346             (dev->pdev->subsystem_vendor == 0x1458) &&
 347             (dev->pdev->subsystem_device == 0x2134)) {
 348                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 349                         return false;
 350         }
 351
 352
 353         /* Funky macbooks */
 354         if ((dev->pdev->device == 0x71C5) &&
 355             (dev->pdev->subsystem_vendor == 0x106b) &&
 356             (dev->pdev->subsystem_device == 0x0080)) {
 357                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 358                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 359                         return false;
 360                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 361                         *line_mux = 0x90;
 362         }
 363
 364         /* mac rv630, rv730, others */
 365         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 366             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 367                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 368                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 369         }
 370
 371         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 372         if ((dev->pdev->device == 0x9598) &&
 373             (dev->pdev->subsystem_vendor == 0x1043) &&
 374             (dev->pdev->subsystem_device == 0x01da)) {
 375                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 376                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 377                 }
 378         }
 379
 380         /* ASUS HD 3600 board lists the DVI port as HDMI */
 381         if ((dev->pdev->device == 0x9598) &&
 382             (dev->pdev->subsystem_vendor == 0x1043) &&
 383             (dev->pdev->subsystem_device == 0x01e4)) {
 384                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 385                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 386                 }
 387         }
 388
 389         /* ASUS HD 3450 board lists the DVI port as HDMI */
 390         if ((dev->pdev->device == 0x95C5) &&
 391             (dev->pdev->subsystem_vendor == 0x1043) &&
 392             (dev->pdev->subsystem_device == 0x01e2)) {
 393                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 394                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 395                 }
 396         }
 397
 398         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 399          * HDMI + VGA reporting as HDMI
 400          */
 401         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 402                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 403                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 404                         *line_mux = 0;
 405                 }
 406         }
 407
 408         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 409          * on the laptop and a DVI port on the docking station and
 410          * both share the same encoder, hpd pin, and ddc line.
 411          * So while the bios table is technically correct,
 412          * we drop the DVI port here since xrandr has no concept of
 413          * encoders and will try and drive both connectors
 414          * with different crtcs which isn't possible on the hardware
 415          * side and leaves no crtcs for LVDS or VGA.
 416          */
 417         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 418             (dev->pdev->subsystem_vendor == 0x1025) &&
 419             (dev->pdev->subsystem_device == 0x013c)) {
 420                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 421                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 422                         /* actually it's a DVI-D port not DVI-I */
 423                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 424                         return false;
 425                 }
 426         }
 427
 428         /* XFX Pine Group device rv730 reports no VGA DDC lines
 429          * even though they are wired up to record 0x93
 430          */
 431         if ((dev->pdev->device == 0x9498) &&
 432             (dev->pdev->subsystem_vendor == 0x1682) &&
 433             (dev->pdev->subsystem_device == 0x2452) &&
 434             (i2c_bus->valid == false) &&
 435             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 436                 struct radeon_device *rdev = dev->dev_private;
 437                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 438         }
 439
 440         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 441         if (((dev->pdev->device == 0x9802) ||
 442              (dev->pdev->device == 0x9805) ||
 443              (dev->pdev->device == 0x9806)) &&
 444             (dev->pdev->subsystem_vendor == 0x1734) &&
 445             (dev->pdev->subsystem_device == 0x11bd)) {
 446                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 447                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 448                         *line_mux = 0x3103;
 449                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 450                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 451                 }
 452         }
 453
 454         return true;
 455 }
 456
 457 static const int supported_devices_connector_convert[] = {
 458         DRM_MODE_CONNECTOR_Unknown,
 459         DRM_MODE_CONNECTOR_VGA,
 460         DRM_MODE_CONNECTOR_DVII,
 461         DRM_MODE_CONNECTOR_DVID,
 462         DRM_MODE_CONNECTOR_DVIA,
 463         DRM_MODE_CONNECTOR_SVIDEO,
 464         DRM_MODE_CONNECTOR_Composite,
 465         DRM_MODE_CONNECTOR_LVDS,
 466         DRM_MODE_CONNECTOR_Unknown,
 467         DRM_MODE_CONNECTOR_Unknown,
 468         DRM_MODE_CONNECTOR_HDMIA,
 469         DRM_MODE_CONNECTOR_HDMIB,
 470         DRM_MODE_CONNECTOR_Unknown,
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_9PinDIN,
 473         DRM_MODE_CONNECTOR_DisplayPort
 474 };
 475
 476 static const uint16_t supported_devices_connector_object_id_convert[] = {
 477         CONNECTOR_OBJECT_ID_NONE,
 478         CONNECTOR_OBJECT_ID_VGA,
 479         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 480         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 481         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 482         CONNECTOR_OBJECT_ID_COMPOSITE,
 483         CONNECTOR_OBJECT_ID_SVIDEO,
 484         CONNECTOR_OBJECT_ID_LVDS,
 485         CONNECTOR_OBJECT_ID_9PIN_DIN,
 486         CONNECTOR_OBJECT_ID_9PIN_DIN,
 487         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 488         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 489         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 490         CONNECTOR_OBJECT_ID_SVIDEO
 491 };
 492
 493 static const int object_connector_convert[] = {
 494         DRM_MODE_CONNECTOR_Unknown,
 495         DRM_MODE_CONNECTOR_DVII,
 496         DRM_MODE_CONNECTOR_DVII,
 497         DRM_MODE_CONNECTOR_DVID,
 498         DRM_MODE_CONNECTOR_DVID,
 499         DRM_MODE_CONNECTOR_VGA,
 500         DRM_MODE_CONNECTOR_Composite,
 501         DRM_MODE_CONNECTOR_SVIDEO,
 502         DRM_MODE_CONNECTOR_Unknown,
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_9PinDIN,
 505         DRM_MODE_CONNECTOR_Unknown,
 506         DRM_MODE_CONNECTOR_HDMIA,
 507         DRM_MODE_CONNECTOR_HDMIB,
 508         DRM_MODE_CONNECTOR_LVDS,
 509         DRM_MODE_CONNECTOR_9PinDIN,
 510         DRM_MODE_CONNECTOR_Unknown,
 511         DRM_MODE_CONNECTOR_Unknown,
 512         DRM_MODE_CONNECTOR_Unknown,
 513         DRM_MODE_CONNECTOR_DisplayPort,
 514         DRM_MODE_CONNECTOR_eDP,
 515         DRM_MODE_CONNECTOR_Unknown
 516 };
 517
 518 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 519 {
 520         struct radeon_device *rdev = dev->dev_private;
 521         struct radeon_mode_info *mode_info = &rdev->mode_info;
 522         struct atom_context *ctx = mode_info->atom_context;
 523         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 524         u16 size, data_offset;
 525         u8 frev, crev;
 526         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 527         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 528         ATOM_OBJECT_TABLE *router_obj;
 529         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 530         ATOM_OBJECT_HEADER *obj_header;
 531         int i, j, k, path_size, device_support;
 532         int connector_type;
 533         u16 igp_lane_info, conn_id, connector_object_id;
 534         struct radeon_i2c_bus_rec ddc_bus;
 535         struct radeon_router router;
 536         struct radeon_gpio_rec gpio;
 537         struct radeon_hpd hpd;
 538
 539         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 540                 return false;
 541
 542         if (crev < 2)
 543                 return false;
 544
 545         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 546         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 547             (ctx->bios + data_offset +
 548              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 549         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 550             (ctx->bios + data_offset +
 551              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 552         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 553             (ctx->bios + data_offset +
 554              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 555         router_obj = (ATOM_OBJECT_TABLE *)
 556                 (ctx->bios + data_offset +
 557                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 558         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 559
 560         path_size = 0;
 561         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 562                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 563                 ATOM_DISPLAY_OBJECT_PATH *path;
 564                 addr += path_size;
 565                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 566                 path_size += le16_to_cpu(path->usSize);
 567
 568                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 569                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 570
 571                         con_obj_id =
 572                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 573                             >> OBJECT_ID_SHIFT;
 574                         con_obj_num =
 575                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 576                             >> ENUM_ID_SHIFT;
 577                         con_obj_type =
 578                             (le16_to_cpu(path->usConnObjectId) &
 579                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 580
 581                         /* TODO CV support */
 582                         if (le16_to_cpu(path->usDeviceTag) ==
 583                                 ATOM_DEVICE_CV_SUPPORT)
 584                                 continue;
 585
 586                         /* IGP chips */
 587                         if ((rdev->flags & RADEON_IS_IGP) &&
 588                             (con_obj_id ==
 589                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 590                                 uint16_t igp_offset = 0;
 591                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 592
 593                                 index =
 594                                     GetIndexIntoMasterTable(DATA,
 595                                                             IntegratedSystemInfo);
 596
 597                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 598                                                            &crev, &igp_offset)) {
 599
 600                                         if (crev >= 2) {
 601                                                 igp_obj =
 602                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 603                                                          *) (ctx->bios + igp_offset);
 604
 605                                                 if (igp_obj) {
 606                                                         uint32_t slot_config, ct;
 607
 608                                                         if (con_obj_num == 1)
 609                                                                 slot_config =
 610                                                                         igp_obj->
 611                                                                         ulDDISlot1Config;
 612                                                         else
 613                                                                 slot_config =
 614                                                                         igp_obj->
 615                                                                         ulDDISlot2Config;
 616
 617                                                         ct = (slot_config >> 16) & 0xff;
 618                                                         connector_type =
 619                                                                 object_connector_convert
 620                                                                 [ct];
 621                                                         connector_object_id = ct;
 622                                                         igp_lane_info =
 623                                                                 slot_config & 0xffff;
 624                                                 } else
 625                                                         continue;
 626                                         } else
 627                                                 continue;
 628                                 } else {
 629                                         igp_lane_info = 0;
 630                                         connector_type =
 631                                                 object_connector_convert[con_obj_id];
 632                                         connector_object_id = con_obj_id;
 633                                 }
 634                         } else {
 635                                 igp_lane_info = 0;
 636                                 connector_type =
 637                                     object_connector_convert[con_obj_id];
 638                                 connector_object_id = con_obj_id;
 639                         }
 640
 641                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 642                                 continue;
 643
 644                         router.ddc_valid = false;
 645                         router.cd_valid = false;
 646                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 647                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 648
 649                                 grph_obj_id =
 650                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 651                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 652                                 grph_obj_num =
 653                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 654                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 655                                 grph_obj_type =
 656                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 657                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 658
 659                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 660                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 661                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 662                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 663                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 664                                                                 (ctx->bios + data_offset +
 665                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 666                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 667                                                         u16 caps = 0;
 668
 669                                                         while (record->ucRecordSize > 0 &&
 670                                                                record->ucRecordType > 0 &&
 671                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 672                                                                 switch (record->ucRecordType) {
 673                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 674                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 675                                                                                 record;
 676                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 677                                                                         break;
 678                                                                 }
 679                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 680                                                                         ((char *)record + record->ucRecordSize);
 681                                                         }
 682                                                         radeon_add_atom_encoder(dev,
 683                                                                                 encoder_obj,
 684                                                                                 le16_to_cpu
 685                                                                                 (path->
 686                                                                                  usDeviceTag),
 687                                                                                 caps);
 688                                                 }
 689                                         }
 690                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 691                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 692                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 693                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 694                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 695                                                                 (ctx->bios + data_offset +
 696                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 697                                                         ATOM_I2C_RECORD *i2c_record;
 698                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 699                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 700                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 701                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 702                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 703                                                                 (ctx->bios + data_offset +
 704                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 705                                                         u8 *num_dst_objs = (u8 *)
 706                                                                 ((u8 *)router_src_dst_table + 1 +
 707                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 708                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 709                                                         int enum_id;
 710
 711                                                         router.router_id = router_obj_id;
 712                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 713                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 714                                                                     le16_to_cpu(dst_objs[enum_id]))
 715                                                                         break;
 716                                                         }
 717
 718                                                         while (record->ucRecordSize > 0 &&
 719                                                                record->ucRecordType > 0 &&
 720                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 721                                                                 switch (record->ucRecordType) {
 722                                                                 case ATOM_I2C_RECORD_TYPE:
 723                                                                         i2c_record =
 724                                                                                 (ATOM_I2C_RECORD *)
 725                                                                                 record;
 726                                                                         i2c_config =
 727                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 728                                                                                 &i2c_record->sucI2cId;
 729                                                                         router.i2c_info =
 730                                                                                 radeon_lookup_i2c_gpio(rdev,
 731                                                                                                        i2c_config->
 732                                                                                                        ucAccess);
 733                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 734                                                                         break;
 735                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 736                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 737                                                                                 record;
 738                                                                         router.ddc_valid = true;
 739                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 740                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 741                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 742                                                                         break;
 743                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 744                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 745                                                                                 record;
 746                                                                         router.cd_valid = true;
 747                                                                         router.cd_mux_type = cd_path->ucMuxType;
 748                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 749                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 750                                                                         break;
 751                                                                 }
 752                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 753                                                                         ((char *)record + record->ucRecordSize);
 754                                                         }
 755                                                 }
 756                                         }
 757                                 }
 758                         }
 759
 760                         /* look up gpio for ddc, hpd */
 761                         ddc_bus.valid = false;
 762                         hpd.hpd = RADEON_HPD_NONE;
 763                         if ((le16_to_cpu(path->usDeviceTag) &
 764                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 765                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 766                                         if (le16_to_cpu(path->usConnObjectId) ==
 767                                             le16_to_cpu(con_obj->asObjects[j].
 768                                                         usObjectID)) {
 769                                                 ATOM_COMMON_RECORD_HEADER
 770                                                     *record =
 771                                                     (ATOM_COMMON_RECORD_HEADER
 772                                                      *)
 773                                                     (ctx->bios + data_offset +
 774                                                      le16_to_cpu(con_obj->
 775                                                                  asObjects[j].
 776                                                                  usRecordOffset));
 777                                                 ATOM_I2C_RECORD *i2c_record;
 778                                                 ATOM_HPD_INT_RECORD *hpd_record;
 779                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 780
 781                                                 while (record->ucRecordSize > 0 &&
 782                                                        record->ucRecordType > 0 &&
 783                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 784                                                         switch (record->ucRecordType) {
 785                                                         case ATOM_I2C_RECORD_TYPE:
 786                                                                 i2c_record =
 787                                                                     (ATOM_I2C_RECORD *)
 788                                                                         record;
 789                                                                 i2c_config =
 790                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 791                                                                         &i2c_record->sucI2cId;
 792                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 793                                                                                                  i2c_config->
 794                                                                                                  ucAccess);
 795                                                                 break;
 796                                                         case ATOM_HPD_INT_RECORD_TYPE:
 797                                                                 hpd_record =
 798                                                                         (ATOM_HPD_INT_RECORD *)
 799                                                                         record;
 800                                                                 gpio = radeon_atombios_lookup_gpio(rdev,
 801                                                                                           hpd_record->ucHPDIntGPIOID);
 802                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 803                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 804                                                                 break;
 805                                                         }
 806                                                         record =
 807                                                             (ATOM_COMMON_RECORD_HEADER
 808                                                              *) ((char *)record
 809                                                                  +
 810                                                                  record->
 811                                                                  ucRecordSize);
 812                                                 }
 813                                                 break;
 814                                         }
 815                                 }
 816                         }
 817
 818                         /* needed for aux chan transactions */
 819                         ddc_bus.hpd = hpd.hpd;
 820
 821                         conn_id = le16_to_cpu(path->usConnObjectId);
 822
 823                         if (!radeon_atom_apply_quirks
 824                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 825                              &ddc_bus, &conn_id, &hpd))
 826                                 continue;
 827
 828                         radeon_add_atom_connector(dev,
 829                                                   conn_id,
 830                                                   le16_to_cpu(path->
 831                                                               usDeviceTag),
 832                                                   connector_type, &ddc_bus,
 833                                                   igp_lane_info,
 834                                                   connector_object_id,
 835                                                   &hpd,
 836                                                   &router);
 837
 838                 }
 839         }
 840
 841         radeon_link_encoder_connector(dev);
 842
 843         radeon_setup_mst_connector(dev);
 844         return true;
 845 }
 846
 847 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 848                                                  int connector_type,
 849                                                  uint16_t devices)
 850 {
 851         struct radeon_device *rdev = dev->dev_private;
 852
 853         if (rdev->flags & RADEON_IS_IGP) {
 854                 return supported_devices_connector_object_id_convert
 855                         [connector_type];
 856         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 857                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 858                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 859                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 860                 struct atom_context *ctx = mode_info->atom_context;
 861                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 862                 uint16_t size, data_offset;
 863                 uint8_t frev, crev;
 864                 ATOM_XTMDS_INFO *xtmds;
 865
 866                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 867                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 868
 869                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 870                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 871                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 872                                 else
 873                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 874                         } else {
 875                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 876                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 877                                 else
 878                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 879                         }
 880                 } else
 881                         return supported_devices_connector_object_id_convert
 882                                 [connector_type];
 883         } else {
 884                 return supported_devices_connector_object_id_convert
 885                         [connector_type];
 886         }
 887 }
 888
 889 struct bios_connector {
 890         bool valid;
 891         uint16_t line_mux;
 892         uint16_t devices;
 893         int connector_type;
 894         struct radeon_i2c_bus_rec ddc_bus;
 895         struct radeon_hpd hpd;
 896 };
 897
 898 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 899                                                                  drm_device
 900                                                                  *dev)
 901 {
 902         struct radeon_device *rdev = dev->dev_private;
 903         struct radeon_mode_info *mode_info = &rdev->mode_info;
 904         struct atom_context *ctx = mode_info->atom_context;
 905         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 906         uint16_t size, data_offset;
 907         uint8_t frev, crev;
 908         uint16_t device_support;
 909         uint8_t dac;
 910         union atom_supported_devices *supported_devices;
 911         int i, j, max_device;
 912         struct bios_connector *bios_connectors;
 913         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 914         struct radeon_router router;
 915
 916         router.ddc_valid = false;
 917         router.cd_valid = false;
 918
 919         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 920         if (!bios_connectors)
 921                 return false;
 922
 923         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 924                                     &data_offset)) {
 925                 kfree(bios_connectors);
 926                 return false;
 927         }
 928
 929         supported_devices =
 930             (union atom_supported_devices *)(ctx->bios + data_offset);
 931
 932         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 933
 934         if (frev > 1)
 935                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 936         else
 937                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 938
 939         for (i = 0; i < max_device; i++) {
 940                 ATOM_CONNECTOR_INFO_I2C ci =
 941                     supported_devices->info.asConnInfo[i];
 942
 943                 bios_connectors[i].valid = false;
 944
 945                 if (!(device_support & (1 << i))) {
 946                         continue;
 947                 }
 948
 949                 if (i == ATOM_DEVICE_CV_INDEX) {
 950                         DRM_DEBUG_KMS("Skipping Component Video\n");
 951                         continue;
 952                 }
 953
 954                 bios_connectors[i].connector_type =
 955                     supported_devices_connector_convert[ci.sucConnectorInfo.
 956                                                         sbfAccess.
 957                                                         bfConnectorType];
 958
 959                 if (bios_connectors[i].connector_type ==
 960                     DRM_MODE_CONNECTOR_Unknown)
 961                         continue;
 962
 963                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 964
 965                 bios_connectors[i].line_mux =
 966                         ci.sucI2cId.ucAccess;
 967
 968                 /* give tv unique connector ids */
 969                 if (i == ATOM_DEVICE_TV1_INDEX) {
 970                         bios_connectors[i].ddc_bus.valid = false;
 971                         bios_connectors[i].line_mux = 50;
 972                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 973                         bios_connectors[i].ddc_bus.valid = false;
 974                         bios_connectors[i].line_mux = 51;
 975                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 976                         bios_connectors[i].ddc_bus.valid = false;
 977                         bios_connectors[i].line_mux = 52;
 978                 } else
 979                         bios_connectors[i].ddc_bus =
 980                             radeon_lookup_i2c_gpio(rdev,
 981                                                    bios_connectors[i].line_mux);
 982
 983                 if ((crev > 1) && (frev > 1)) {
 984                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 985                         switch (isb) {
 986                         case 0x4:
 987                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 988                                 break;
 989                         case 0xa:
 990                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 991                                 break;
 992                         default:
 993                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 994                                 break;
 995                         }
 996                 } else {
 997                         if (i == ATOM_DEVICE_DFP1_INDEX)
 998                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 999                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1000                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1001                         else
1002                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1003                 }
1004
1005                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1006                  * shared with a DVI port, we'll pick up the DVI connector when we
1007                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1008                  */
1009                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1010                         bios_connectors[i].connector_type =
1011                             DRM_MODE_CONNECTOR_VGA;
1012
1013                 if (!radeon_atom_apply_quirks
1014                     (dev, (1 << i), &bios_connectors[i].connector_type,
1015                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1016                      &bios_connectors[i].hpd))
1017                         continue;
1018
1019                 bios_connectors[i].valid = true;
1020                 bios_connectors[i].devices = (1 << i);
1021
1022                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1023                         radeon_add_atom_encoder(dev,
1024                                                 radeon_get_encoder_enum(dev,
1025                                                                       (1 << i),
1026                                                                       dac),
1027                                                 (1 << i),
1028                                                 0);
1029                 else
1030                         radeon_add_legacy_encoder(dev,
1031                                                   radeon_get_encoder_enum(dev,
1032                                                                         (1 << i),
1033                                                                         dac),
1034                                                   (1 << i));
1035         }
1036
1037         /* combine shared connectors */
1038         for (i = 0; i < max_device; i++) {
1039                 if (bios_connectors[i].valid) {
1040                         for (j = 0; j < max_device; j++) {
1041                                 if (bios_connectors[j].valid && (i != j)) {
1042                                         if (bios_connectors[i].line_mux ==
1043                                             bios_connectors[j].line_mux) {
1044                                                 /* make sure not to combine LVDS */
1045                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1046                                                         bios_connectors[i].line_mux = 53;
1047                                                         bios_connectors[i].ddc_bus.valid = false;
1048                                                         continue;
1049                                                 }
1050                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051                                                         bios_connectors[j].line_mux = 53;
1052                                                         bios_connectors[j].ddc_bus.valid = false;
1053                                                         continue;
1054                                                 }
1055                                                 /* combine analog and digital for DVI-I */
1056                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1057                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1058                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1059                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1060                                                         bios_connectors[i].devices |=
1061                                                                 bios_connectors[j].devices;
1062                                                         bios_connectors[i].connector_type =
1063                                                                 DRM_MODE_CONNECTOR_DVII;
1064                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1065                                                                 bios_connectors[i].hpd =
1066                                                                         bios_connectors[j].hpd;
1067                                                         bios_connectors[j].valid = false;
1068                                                 }
1069                                         }
1070                                 }
1071                         }
1072                 }
1073         }
1074
1075         /* add the connectors */
1076         for (i = 0; i < max_device; i++) {
1077                 if (bios_connectors[i].valid) {
1078                         uint16_t connector_object_id =
1079                                 atombios_get_connector_object_id(dev,
1080                                                       bios_connectors[i].connector_type,
1081                                                       bios_connectors[i].devices);
1082                         radeon_add_atom_connector(dev,
1083                                                   bios_connectors[i].line_mux,
1084                                                   bios_connectors[i].devices,
1085                                                   bios_connectors[i].
1086                                                   connector_type,
1087                                                   &bios_connectors[i].ddc_bus,
1088                                                   0,
1089                                                   connector_object_id,
1090                                                   &bios_connectors[i].hpd,
1091                                                   &router);
1092                 }
1093         }
1094
1095         radeon_link_encoder_connector(dev);
1096
1097         kfree(bios_connectors);
1098         return true;
1099 }
1100
1101 union firmware_info {
1102         ATOM_FIRMWARE_INFO info;
1103         ATOM_FIRMWARE_INFO_V1_2 info_12;
1104         ATOM_FIRMWARE_INFO_V1_3 info_13;
1105         ATOM_FIRMWARE_INFO_V1_4 info_14;
1106         ATOM_FIRMWARE_INFO_V2_1 info_21;
1107         ATOM_FIRMWARE_INFO_V2_2 info_22;
1108 };
1109
1110 union igp_info {
1111         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1112         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1113         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1114         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1115         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1116 };
1117
1118 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1119 {
1120         struct radeon_mode_info *mode_info = &rdev->mode_info;
1121         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1122         union igp_info *igp_info;
1123         u8 frev, crev;
1124         u16 data_offset;
1125
1126         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1127                         &frev, &crev, &data_offset)) {
1128                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1129                         data_offset);
1130                 rdev->clock.vco_freq =
1131                         le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1132         }
1133 }
1134
1135 bool radeon_atom_get_clock_info(struct drm_device *dev)
1136 {
1137         struct radeon_device *rdev = dev->dev_private;
1138         struct radeon_mode_info *mode_info = &rdev->mode_info;
1139         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1140         union firmware_info *firmware_info;
1141         uint8_t frev, crev;
1142         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1143         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1144         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1145         struct radeon_pll *spll = &rdev->clock.spll;
1146         struct radeon_pll *mpll = &rdev->clock.mpll;
1147         uint16_t data_offset;
1148
1149         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1150                                    &frev, &crev, &data_offset)) {
1151                 firmware_info =
1152                         (union firmware_info *)(mode_info->atom_context->bios +
1153                                                 data_offset);
1154                 /* pixel clocks */
1155                 p1pll->reference_freq =
1156                     le16_to_cpu(firmware_info->info.usReferenceClock);
1157                 p1pll->reference_div = 0;
1158
1159                 if ((frev < 2) && (crev < 2))
1160                         p1pll->pll_out_min =
1161                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1162                 else
1163                         p1pll->pll_out_min =
1164                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1165                 p1pll->pll_out_max =
1166                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1167
1168                 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1169                         p1pll->lcd_pll_out_min =
1170                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1171                         if (p1pll->lcd_pll_out_min == 0)
1172                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1173                         p1pll->lcd_pll_out_max =
1174                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1175                         if (p1pll->lcd_pll_out_max == 0)
1176                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1177                 } else {
1178                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1179                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1180                 }
1181
1182                 if (p1pll->pll_out_min == 0) {
1183                         if (ASIC_IS_AVIVO(rdev))
1184                                 p1pll->pll_out_min = 64800;
1185                         else
1186                                 p1pll->pll_out_min = 20000;
1187                 }
1188
1189                 p1pll->pll_in_min =
1190                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1191                 p1pll->pll_in_max =
1192                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1193
1194                 *p2pll = *p1pll;
1195
1196                 /* system clock */
1197                 if (ASIC_IS_DCE4(rdev))
1198                         spll->reference_freq =
1199                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1200                 else
1201                         spll->reference_freq =
1202                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1203                 spll->reference_div = 0;
1204
1205                 spll->pll_out_min =
1206                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1207                 spll->pll_out_max =
1208                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1209
1210                 /* ??? */
1211                 if (spll->pll_out_min == 0) {
1212                         if (ASIC_IS_AVIVO(rdev))
1213                                 spll->pll_out_min = 64800;
1214                         else
1215                                 spll->pll_out_min = 20000;
1216                 }
1217
1218                 spll->pll_in_min =
1219                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1220                 spll->pll_in_max =
1221                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1222
1223                 /* memory clock */
1224                 if (ASIC_IS_DCE4(rdev))
1225                         mpll->reference_freq =
1226                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1227                 else
1228                         mpll->reference_freq =
1229                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1230                 mpll->reference_div = 0;
1231
1232                 mpll->pll_out_min =
1233                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1234                 mpll->pll_out_max =
1235                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1236
1237                 /* ??? */
1238                 if (mpll->pll_out_min == 0) {
1239                         if (ASIC_IS_AVIVO(rdev))
1240                                 mpll->pll_out_min = 64800;
1241                         else
1242                                 mpll->pll_out_min = 20000;
1243                 }
1244
1245                 mpll->pll_in_min =
1246                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1247                 mpll->pll_in_max =
1248                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1249
1250                 rdev->clock.default_sclk =
1251                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1252                 rdev->clock.default_mclk =
1253                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1254
1255                 if (ASIC_IS_DCE4(rdev)) {
1256                         rdev->clock.default_dispclk =
1257                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1258                         if (rdev->clock.default_dispclk == 0) {
1259                                 if (ASIC_IS_DCE6(rdev))
1260                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1261                                 else if (ASIC_IS_DCE5(rdev))
1262                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1263                                 else
1264                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1265                         }
1266                         /* set a reasonable default for DP */
1267                         if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1268                                 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1269                                          rdev->clock.default_dispclk / 100);
1270                                 rdev->clock.default_dispclk = 60000;
1271                         }
1272                         rdev->clock.dp_extclk =
1273                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1274                         rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1275                 }
1276                 *dcpll = *p1pll;
1277
1278                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1279                 if (rdev->clock.max_pixel_clock == 0)
1280                         rdev->clock.max_pixel_clock = 40000;
1281
1282                 /* not technically a clock, but... */
1283                 rdev->mode_info.firmware_flags =
1284                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1285
1286                 if (ASIC_IS_DCE8(rdev))
1287                         rdev->clock.vco_freq =
1288                                 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1289                 else if (ASIC_IS_DCE5(rdev))
1290                         rdev->clock.vco_freq = rdev->clock.current_dispclk;
1291                 else if (ASIC_IS_DCE41(rdev))
1292                         radeon_atombios_get_dentist_vco_freq(rdev);
1293                 else
1294                         rdev->clock.vco_freq = rdev->clock.current_dispclk;
1295
1296                 if (rdev->clock.vco_freq == 0)
1297                         rdev->clock.vco_freq = 360000;  /* 3.6 GHz */
1298
1299                 return true;
1300         }
1301
1302         return false;
1303 }
1304
1305 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1306 {
1307         struct radeon_mode_info *mode_info = &rdev->mode_info;
1308         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1309         union igp_info *igp_info;
1310         u8 frev, crev;
1311         u16 data_offset;
1312
1313         /* sideport is AMD only */
1314         if (rdev->family == CHIP_RS600)
1315                 return false;
1316
1317         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1318                                    &frev, &crev, &data_offset)) {
1319                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1320                                       data_offset);
1321                 switch (crev) {
1322                 case 1:
1323                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1324                                 return true;
1325                         break;
1326                 case 2:
1327                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1328                                 return true;
1329                         break;
1330                 default:
1331                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1332                         break;
1333                 }
1334         }
1335         return false;
1336 }
1337
1338 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1339                                    struct radeon_encoder_int_tmds *tmds)
1340 {
1341         struct drm_device *dev = encoder->base.dev;
1342         struct radeon_device *rdev = dev->dev_private;
1343         struct radeon_mode_info *mode_info = &rdev->mode_info;
1344         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1345         uint16_t data_offset;
1346         struct _ATOM_TMDS_INFO *tmds_info;
1347         uint8_t frev, crev;
1348         uint16_t maxfreq;
1349         int i;
1350
1351         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1352                                    &frev, &crev, &data_offset)) {
1353                 tmds_info =
1354                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1355                                                    data_offset);
1356
1357                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1358                 for (i = 0; i < 4; i++) {
1359                         tmds->tmds_pll[i].freq =
1360                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1361                         tmds->tmds_pll[i].value =
1362                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1363                         tmds->tmds_pll[i].value |=
1364                             (tmds_info->asMiscInfo[i].
1365                              ucPLL_VCO_Gain & 0x3f) << 6;
1366                         tmds->tmds_pll[i].value |=
1367                             (tmds_info->asMiscInfo[i].
1368                              ucPLL_DutyCycle & 0xf) << 12;
1369                         tmds->tmds_pll[i].value |=
1370                             (tmds_info->asMiscInfo[i].
1371                              ucPLL_VoltageSwing & 0xf) << 16;
1372
1373                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1374                                   tmds->tmds_pll[i].freq,
1375                                   tmds->tmds_pll[i].value);
1376
1377                         if (maxfreq == tmds->tmds_pll[i].freq) {
1378                                 tmds->tmds_pll[i].freq = 0xffffffff;
1379                                 break;
1380                         }
1381                 }
1382                 return true;
1383         }
1384         return false;
1385 }
1386
1387 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1388                                       struct radeon_atom_ss *ss,
1389                                       int id)
1390 {
1391         struct radeon_mode_info *mode_info = &rdev->mode_info;
1392         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1393         uint16_t data_offset, size;
1394         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1395         struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1396         uint8_t frev, crev;
1397         int i, num_indices;
1398
1399         memset(ss, 0, sizeof(struct radeon_atom_ss));
1400         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1401                                    &frev, &crev, &data_offset)) {
1402                 ss_info =
1403                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1404
1405                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1406                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1407                 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1408                         ((u8 *)&ss_info->asSS_Info[0]);
1409                 for (i = 0; i < num_indices; i++) {
1410                         if (ss_assign->ucSS_Id == id) {
1411                                 ss->percentage =
1412                                         le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1413                                 ss->type = ss_assign->ucSpreadSpectrumType;
1414                                 ss->step = ss_assign->ucSS_Step;
1415                                 ss->delay = ss_assign->ucSS_Delay;
1416                                 ss->range = ss_assign->ucSS_Range;
1417                                 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1418                                 return true;
1419                         }
1420                         ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1421                                 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1422                 }
1423         }
1424         return false;
1425 }
1426
1427 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1428                                                  struct radeon_atom_ss *ss,
1429                                                  int id)
1430 {
1431         struct radeon_mode_info *mode_info = &rdev->mode_info;
1432         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1433         u16 data_offset, size;
1434         union igp_info *igp_info;
1435         u8 frev, crev;
1436         u16 percentage = 0, rate = 0;
1437
1438         /* get any igp specific overrides */
1439         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1440                                    &frev, &crev, &data_offset)) {
1441                 igp_info = (union igp_info *)
1442                         (mode_info->atom_context->bios + data_offset);
1443                 switch (crev) {
1444                 case 6:
1445                         switch (id) {
1446                         case ASIC_INTERNAL_SS_ON_TMDS:
1447                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1448                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1449                                 break;
1450                         case ASIC_INTERNAL_SS_ON_HDMI:
1451                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1452                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1453                                 break;
1454                         case ASIC_INTERNAL_SS_ON_LVDS:
1455                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1456                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1457                                 break;
1458                         }
1459                         break;
1460                 case 7:
1461                         switch (id) {
1462                         case ASIC_INTERNAL_SS_ON_TMDS:
1463                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1464                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1465                                 break;
1466                         case ASIC_INTERNAL_SS_ON_HDMI:
1467                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1468                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1469                                 break;
1470                         case ASIC_INTERNAL_SS_ON_LVDS:
1471                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1472                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1473                                 break;
1474                         }
1475                         break;
1476                 case 8:
1477                         switch (id) {
1478                         case ASIC_INTERNAL_SS_ON_TMDS:
1479                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1480                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1481                                 break;
1482                         case ASIC_INTERNAL_SS_ON_HDMI:
1483                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1484                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1485                                 break;
1486                         case ASIC_INTERNAL_SS_ON_LVDS:
1487                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1488                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1489                                 break;
1490                         }
1491                         break;
1492                 default:
1493                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1494                         break;
1495                 }
1496                 if (percentage)
1497                         ss->percentage = percentage;
1498                 if (rate)
1499                         ss->rate = rate;
1500         }
1501 }
1502
1503 union asic_ss_info {
1504         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1505         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1506         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1507 };
1508
1509 union asic_ss_assignment {
1510         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1511         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1512         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1513 };
1514
1515 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1516                                       struct radeon_atom_ss *ss,
1517                                       int id, u32 clock)
1518 {
1519         struct radeon_mode_info *mode_info = &rdev->mode_info;
1520         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1521         uint16_t data_offset, size;
1522         union asic_ss_info *ss_info;
1523         union asic_ss_assignment *ss_assign;
1524         uint8_t frev, crev;
1525         int i, num_indices;
1526
1527         if (id == ASIC_INTERNAL_MEMORY_SS) {
1528                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1529                         return false;
1530         }
1531         if (id == ASIC_INTERNAL_ENGINE_SS) {
1532                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1533                         return false;
1534         }
1535
1536         memset(ss, 0, sizeof(struct radeon_atom_ss));
1537         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1538                                    &frev, &crev, &data_offset)) {
1539
1540                 ss_info =
1541                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1542
1543                 switch (frev) {
1544                 case 1:
1545                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1546                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1547
1548                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1549                         for (i = 0; i < num_indices; i++) {
1550                                 if ((ss_assign->v1.ucClockIndication == id) &&
1551                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1552                                         ss->percentage =
1553                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1554                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1555                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1556                                         ss->percentage_divider = 100;
1557                                         return true;
1558                                 }
1559                                 ss_assign = (union asic_ss_assignment *)
1560                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1561                         }
1562                         break;
1563                 case 2:
1564                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1565                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1566                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1567                         for (i = 0; i < num_indices; i++) {
1568                                 if ((ss_assign->v2.ucClockIndication == id) &&
1569                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1570                                         ss->percentage =
1571                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1572                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1573                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1574                                         ss->percentage_divider = 100;
1575                                         if ((crev == 2) &&
1576                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
1577                                              (id == ASIC_INTERNAL_MEMORY_SS)))
1578                                                 ss->rate /= 100;
1579                                         return true;
1580                                 }
1581                                 ss_assign = (union asic_ss_assignment *)
1582                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1583                         }
1584                         break;
1585                 case 3:
1586                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1587                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1588                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1589                         for (i = 0; i < num_indices; i++) {
1590                                 if ((ss_assign->v3.ucClockIndication == id) &&
1591                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1592                                         ss->percentage =
1593                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1594                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1595                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1596                                         if (ss_assign->v3.ucSpreadSpectrumMode &
1597                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1598                                                 ss->percentage_divider = 1000;
1599                                         else
1600                                                 ss->percentage_divider = 100;
1601                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1602                                             (id == ASIC_INTERNAL_MEMORY_SS))
1603                                                 ss->rate /= 100;
1604                                         if (rdev->flags & RADEON_IS_IGP)
1605                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1606                                         return true;
1607                                 }
1608                                 ss_assign = (union asic_ss_assignment *)
1609                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1610                         }
1611                         break;
1612                 default:
1613                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1614                         break;
1615                 }
1616
1617         }
1618         return false;
1619 }
1620
1621 union lvds_info {
1622         struct _ATOM_LVDS_INFO info;
1623         struct _ATOM_LVDS_INFO_V12 info_12;
1624 };
1625
1626 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1627                                                               radeon_encoder
1628                                                               *encoder)
1629 {
1630         struct drm_device *dev = encoder->base.dev;
1631         struct radeon_device *rdev = dev->dev_private;
1632         struct radeon_mode_info *mode_info = &rdev->mode_info;
1633         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1634         uint16_t data_offset, misc;
1635         union lvds_info *lvds_info;
1636         uint8_t frev, crev;
1637         struct radeon_encoder_atom_dig *lvds = NULL;
1638         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1639
1640         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1641                                    &frev, &crev, &data_offset)) {
1642                 lvds_info =
1643                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1644                 lvds =
1645                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1646
1647                 if (!lvds)
1648                         return NULL;
1649
1650                 lvds->native_mode.clock =
1651                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1652                 lvds->native_mode.hdisplay =
1653                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1654                 lvds->native_mode.vdisplay =
1655                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1656                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1657                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1658                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1659                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1660                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1661                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1662                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1663                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1664                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1665                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1666                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1667                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1668                 lvds->panel_pwr_delay =
1669                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1670                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1671
1672                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1673                 if (misc & ATOM_VSYNC_POLARITY)
1674                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1675                 if (misc & ATOM_HSYNC_POLARITY)
1676                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1677                 if (misc & ATOM_COMPOSITESYNC)
1678                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1679                 if (misc & ATOM_INTERLACE)
1680                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1681                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1682                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1683
1684                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1685                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1686
1687                 /* set crtc values */
1688                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1689
1690                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1691
1692                 encoder->native_mode = lvds->native_mode;
1693
1694                 if (encoder_enum == 2)
1695                         lvds->linkb = true;
1696                 else
1697                         lvds->linkb = false;
1698
1699                 /* parse the lcd record table */
1700                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1701                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1702                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1703                         bool bad_record = false;
1704                         u8 *record;
1705
1706                         if ((frev == 1) && (crev < 2))
1707                                 /* absolute */
1708                                 record = (u8 *)(mode_info->atom_context->bios +
1709                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1710                         else
1711                                 /* relative */
1712                                 record = (u8 *)(mode_info->atom_context->bios +
1713                                                 data_offset +
1714                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1715                         while (*record != ATOM_RECORD_END_TYPE) {
1716                                 switch (*record) {
1717                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1718                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1719                                         break;
1720                                 case LCD_RTS_RECORD_TYPE:
1721                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1722                                         break;
1723                                 case LCD_CAP_RECORD_TYPE:
1724                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1725                                         break;
1726                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1727                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1728                                         if (fake_edid_record->ucFakeEDIDLength) {
1729                                                 struct edid *edid;
1730                                                 int edid_size =
1731                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1732                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1733                                                 if (edid) {
1734                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1735                                                                fake_edid_record->ucFakeEDIDLength);
1736
1737                                                         if (drm_edid_is_valid(edid)) {
1738                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1739                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1740                                                         } else
1741                                                                 kfree(edid);
1742                                                 }
1743                                         }
1744                                         record += fake_edid_record->ucFakeEDIDLength ?
1745                                                 fake_edid_record->ucFakeEDIDLength + 2 :
1746                                                 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1747                                         break;
1748                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1749                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1750                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1751                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1752                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1753                                         break;
1754                                 default:
1755                                         DRM_ERROR("Bad LCD record %d\n", *record);
1756                                         bad_record = true;
1757                                         break;
1758                                 }
1759                                 if (bad_record)
1760                                         break;
1761                         }
1762                 }
1763         }
1764         return lvds;
1765 }
1766
1767 struct radeon_encoder_primary_dac *
1768 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1769 {
1770         struct drm_device *dev = encoder->base.dev;
1771         struct radeon_device *rdev = dev->dev_private;
1772         struct radeon_mode_info *mode_info = &rdev->mode_info;
1773         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1774         uint16_t data_offset;
1775         struct _COMPASSIONATE_DATA *dac_info;
1776         uint8_t frev, crev;
1777         uint8_t bg, dac;
1778         struct radeon_encoder_primary_dac *p_dac = NULL;
1779
1780         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1781                                    &frev, &crev, &data_offset)) {
1782                 dac_info = (struct _COMPASSIONATE_DATA *)
1783                         (mode_info->atom_context->bios + data_offset);
1784
1785                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1786
1787                 if (!p_dac)
1788                         return NULL;
1789
1790                 bg = dac_info->ucDAC1_BG_Adjustment;
1791                 dac = dac_info->ucDAC1_DAC_Adjustment;
1792                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1793
1794         }
1795         return p_dac;
1796 }
1797
1798 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1799                                 struct drm_display_mode *mode)
1800 {
1801         struct radeon_mode_info *mode_info = &rdev->mode_info;
1802         ATOM_ANALOG_TV_INFO *tv_info;
1803         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1804         ATOM_DTD_FORMAT *dtd_timings;
1805         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1806         u8 frev, crev;
1807         u16 data_offset, misc;
1808
1809         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1810                                     &frev, &crev, &data_offset))
1811                 return false;
1812
1813         switch (crev) {
1814         case 1:
1815                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1816                 if (index >= MAX_SUPPORTED_TV_TIMING)
1817                         return false;
1818
1819                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1820                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1821                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1822                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1823                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1824
1825                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1826                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1827                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1828                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1829                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1830
1831                 mode->flags = 0;
1832                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1833                 if (misc & ATOM_VSYNC_POLARITY)
1834                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1835                 if (misc & ATOM_HSYNC_POLARITY)
1836                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1837                 if (misc & ATOM_COMPOSITESYNC)
1838                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1839                 if (misc & ATOM_INTERLACE)
1840                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1841                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1842                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1843
1844                 mode->crtc_clock = mode->clock =
1845                         le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1846
1847                 if (index == 1) {
1848                         /* PAL timings appear to have wrong values for totals */
1849                         mode->crtc_htotal -= 1;
1850                         mode->crtc_vtotal -= 1;
1851                 }
1852                 break;
1853         case 2:
1854                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1855                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1856                         return false;
1857
1858                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1859                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1860                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1861                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1862                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1863                         le16_to_cpu(dtd_timings->usHSyncOffset);
1864                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1865                         le16_to_cpu(dtd_timings->usHSyncWidth);
1866
1867                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1868                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1869                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1870                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1871                         le16_to_cpu(dtd_timings->usVSyncOffset);
1872                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1873                         le16_to_cpu(dtd_timings->usVSyncWidth);
1874
1875                 mode->flags = 0;
1876                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1877                 if (misc & ATOM_VSYNC_POLARITY)
1878                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1879                 if (misc & ATOM_HSYNC_POLARITY)
1880                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1881                 if (misc & ATOM_COMPOSITESYNC)
1882                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1883                 if (misc & ATOM_INTERLACE)
1884                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1885                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1886                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1887
1888                 mode->crtc_clock = mode->clock =
1889                         le16_to_cpu(dtd_timings->usPixClk) * 10;
1890                 break;
1891         }
1892         return true;
1893 }
1894
1895 enum radeon_tv_std
1896 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1897 {
1898         struct radeon_mode_info *mode_info = &rdev->mode_info;
1899         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1900         uint16_t data_offset;
1901         uint8_t frev, crev;
1902         struct _ATOM_ANALOG_TV_INFO *tv_info;
1903         enum radeon_tv_std tv_std = TV_STD_NTSC;
1904
1905         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1906                                    &frev, &crev, &data_offset)) {
1907
1908                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1909                         (mode_info->atom_context->bios + data_offset);
1910
1911                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1912                 case ATOM_TV_NTSC:
1913                         tv_std = TV_STD_NTSC;
1914                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1915                         break;
1916                 case ATOM_TV_NTSCJ:
1917                         tv_std = TV_STD_NTSC_J;
1918                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1919                         break;
1920                 case ATOM_TV_PAL:
1921                         tv_std = TV_STD_PAL;
1922                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1923                         break;
1924                 case ATOM_TV_PALM:
1925                         tv_std = TV_STD_PAL_M;
1926                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1927                         break;
1928                 case ATOM_TV_PALN:
1929                         tv_std = TV_STD_PAL_N;
1930                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1931                         break;
1932                 case ATOM_TV_PALCN:
1933                         tv_std = TV_STD_PAL_CN;
1934                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1935                         break;
1936                 case ATOM_TV_PAL60:
1937                         tv_std = TV_STD_PAL_60;
1938                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1939                         break;
1940                 case ATOM_TV_SECAM:
1941                         tv_std = TV_STD_SECAM;
1942                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1943                         break;
1944                 default:
1945                         tv_std = TV_STD_NTSC;
1946                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1947                         break;
1948                 }
1949         }
1950         return tv_std;
1951 }
1952
1953 struct radeon_encoder_tv_dac *
1954 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1955 {
1956         struct drm_device *dev = encoder->base.dev;
1957         struct radeon_device *rdev = dev->dev_private;
1958         struct radeon_mode_info *mode_info = &rdev->mode_info;
1959         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1960         uint16_t data_offset;
1961         struct _COMPASSIONATE_DATA *dac_info;
1962         uint8_t frev, crev;
1963         uint8_t bg, dac;
1964         struct radeon_encoder_tv_dac *tv_dac = NULL;
1965
1966         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1967                                    &frev, &crev, &data_offset)) {
1968
1969                 dac_info = (struct _COMPASSIONATE_DATA *)
1970                         (mode_info->atom_context->bios + data_offset);
1971
1972                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1973
1974                 if (!tv_dac)
1975                         return NULL;
1976
1977                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1978                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1979                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1980
1981                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1982                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1983                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1984
1985                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1986                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1987                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1988
1989                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1990         }
1991         return tv_dac;
1992 }
1993
1994 static const char *thermal_controller_names[] = {
1995         "NONE",
1996         "lm63",
1997         "adm1032",
1998         "adm1030",
1999         "max6649",
2000         "lm63", /* lm64 */
2001         "f75375",
2002         "asc7xxx",
2003 };
2004
2005 static const char *pp_lib_thermal_controller_names[] = {
2006         "NONE",
2007         "lm63",
2008         "adm1032",
2009         "adm1030",
2010         "max6649",
2011         "lm63", /* lm64 */
2012         "f75375",
2013         "RV6xx",
2014         "RV770",
2015         "adt7473",
2016         "NONE",
2017         "External GPIO",
2018         "Evergreen",
2019         "emc2103",
2020         "Sumo",
2021         "Northern Islands",
2022         "Southern Islands",
2023         "lm96163",
2024         "Sea Islands",
2025 };
2026
2027 union power_info {
2028         struct _ATOM_POWERPLAY_INFO info;
2029         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2030         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2031         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2032         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2033         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2034 };
2035
2036 union pplib_clock_info {
2037         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2038         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2039         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2040         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2041         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2042         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2043 };
2044
2045 union pplib_power_state {
2046         struct _ATOM_PPLIB_STATE v1;
2047         struct _ATOM_PPLIB_STATE_V2 v2;
2048 };
2049
2050 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2051                                                  int state_index,
2052                                                  u32 misc, u32 misc2)
2053 {
2054         rdev->pm.power_state[state_index].misc = misc;
2055         rdev->pm.power_state[state_index].misc2 = misc2;
2056         /* order matters! */
2057         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2058                 rdev->pm.power_state[state_index].type =
2059                         POWER_STATE_TYPE_POWERSAVE;
2060         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2061                 rdev->pm.power_state[state_index].type =
2062                         POWER_STATE_TYPE_BATTERY;
2063         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2064                 rdev->pm.power_state[state_index].type =
2065                         POWER_STATE_TYPE_BATTERY;
2066         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2067                 rdev->pm.power_state[state_index].type =
2068                         POWER_STATE_TYPE_BALANCED;
2069         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2070                 rdev->pm.power_state[state_index].type =
2071                         POWER_STATE_TYPE_PERFORMANCE;
2072                 rdev->pm.power_state[state_index].flags &=
2073                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2074         }
2075         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2076                 rdev->pm.power_state[state_index].type =
2077                         POWER_STATE_TYPE_BALANCED;
2078         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2079                 rdev->pm.power_state[state_index].type =
2080                         POWER_STATE_TYPE_DEFAULT;
2081                 rdev->pm.default_power_state_index = state_index;
2082                 rdev->pm.power_state[state_index].default_clock_mode =
2083                         &rdev->pm.power_state[state_index].clock_info[0];
2084         } else if (state_index == 0) {
2085                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2086                         RADEON_PM_MODE_NO_DISPLAY;
2087         }
2088 }
2089
2090 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2091 {
2092         struct radeon_mode_info *mode_info = &rdev->mode_info;
2093         u32 misc, misc2 = 0;
2094         int num_modes = 0, i;
2095         int state_index = 0;
2096         struct radeon_i2c_bus_rec i2c_bus;
2097         union power_info *power_info;
2098         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2099         u16 data_offset;
2100         u8 frev, crev;
2101
2102         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2103                                    &frev, &crev, &data_offset))
2104                 return state_index;
2105         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2106
2107         /* add the i2c bus for thermal/fan chip */
2108         if ((power_info->info.ucOverdriveThermalController > 0) &&
2109             (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2110                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2111                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2112                          power_info->info.ucOverdriveControllerAddress >> 1);
2113                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2114                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2115                 if (rdev->pm.i2c_bus) {
2116                         struct i2c_board_info info = { };
2117                         const char *name = thermal_controller_names[power_info->info.
2118                                                                     ucOverdriveThermalController];
2119                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2120                         strlcpy(info.type, name, sizeof(info.type));
2121                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2122                 }
2123         }
2124         num_modes = power_info->info.ucNumOfPowerModeEntries;
2125         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2126                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2127         if (num_modes == 0)
2128                 return state_index;
2129         rdev->pm.power_state = kcalloc(num_modes,
2130                                        sizeof(struct radeon_power_state),
2131                                        GFP_KERNEL);
2132         if (!rdev->pm.power_state)
2133                 return state_index;
2134         /* last mode is usually default, array is low to high */
2135         for (i = 0; i < num_modes; i++) {
2136                 /* avoid memory leaks from invalid modes or unknown frev. */
2137                 if (!rdev->pm.power_state[state_index].clock_info) {
2138                         rdev->pm.power_state[state_index].clock_info =
2139                                 kzalloc(sizeof(struct radeon_pm_clock_info),
2140                                         GFP_KERNEL);
2141                 }
2142                 if (!rdev->pm.power_state[state_index].clock_info)
2143                         goto out;
2144                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2145                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2146                 switch (frev) {
2147                 case 1:
2148                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2149                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2150                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2151                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2152                         /* skip invalid modes */
2153                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2154                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2155                                 continue;
2156                         rdev->pm.power_state[state_index].pcie_lanes =
2157                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2158                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2159                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2160                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2161                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2162                                         VOLTAGE_GPIO;
2163                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2164                                         radeon_atombios_lookup_gpio(rdev,
2165                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2166                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2167                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2168                                                 true;
2169                                 else
2170                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2171                                                 false;
2172                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2173                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2174                                         VOLTAGE_VDDC;
2175                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2176                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2177                         }
2178                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2179                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2180                         state_index++;
2181                         break;
2182                 case 2:
2183                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2184                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2185                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2186                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2187                         /* skip invalid modes */
2188                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2189                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2190                                 continue;
2191                         rdev->pm.power_state[state_index].pcie_lanes =
2192                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2193                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2194                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2195                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2196                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2197                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2198                                         VOLTAGE_GPIO;
2199                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2200                                         radeon_atombios_lookup_gpio(rdev,
2201                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2202                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2203                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2204                                                 true;
2205                                 else
2206                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2207                                                 false;
2208                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2209                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2210                                         VOLTAGE_VDDC;
2211                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2212                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2213                         }
2214                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2215                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2216                         state_index++;
2217                         break;
2218                 case 3:
2219                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2220                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2221                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2222                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2223                         /* skip invalid modes */
2224                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2225                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2226                                 continue;
2227                         rdev->pm.power_state[state_index].pcie_lanes =
2228                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2229                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2230                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2231                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2232                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2233                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2234                                         VOLTAGE_GPIO;
2235                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2236                                         radeon_atombios_lookup_gpio(rdev,
2237                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2238                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2239                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2240                                                 true;
2241                                 else
2242                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2243                                                 false;
2244                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2245                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2246                                         VOLTAGE_VDDC;
2247                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2248                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2249                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2250                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2251                                                 true;
2252                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2253                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2254                                 }
2255                         }
2256                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2257                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2258                         state_index++;
2259                         break;
2260                 }
2261         }
2262 out:
2263         /* free any unused clock_info allocation. */
2264         if (state_index && state_index < num_modes) {
2265                 kfree(rdev->pm.power_state[state_index].clock_info);
2266                 rdev->pm.power_state[state_index].clock_info = NULL;
2267         }
2268
2269         /* last mode is usually default */
2270         if (state_index && rdev->pm.default_power_state_index == -1) {
2271                 rdev->pm.power_state[state_index - 1].type =
2272                         POWER_STATE_TYPE_DEFAULT;
2273                 rdev->pm.default_power_state_index = state_index - 1;
2274                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2275                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2276                 rdev->pm.power_state[state_index - 1].flags &=
2277                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2278                 rdev->pm.power_state[state_index - 1].misc = 0;
2279                 rdev->pm.power_state[state_index - 1].misc2 = 0;
2280         }
2281         return state_index;
2282 }
2283
2284 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2285                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2286 {
2287         struct radeon_i2c_bus_rec i2c_bus;
2288
2289         /* add the i2c bus for thermal/fan chip */
2290         if (controller->ucType > 0) {
2291                 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2292                         rdev->pm.no_fan = true;
2293                 rdev->pm.fan_pulses_per_revolution =
2294                         controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2295                 if (rdev->pm.fan_pulses_per_revolution) {
2296                         rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2297                         rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2298                 }
2299                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2300                         DRM_INFO("Internal thermal controller %s fan control\n",
2301                                  (controller->ucFanParameters &
2302                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2303                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2304                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2305                         DRM_INFO("Internal thermal controller %s fan control\n",
2306                                  (controller->ucFanParameters &
2307                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2308                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2309                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2310                         DRM_INFO("Internal thermal controller %s fan control\n",
2311                                  (controller->ucFanParameters &
2312                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2313                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2314                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2315                         DRM_INFO("Internal thermal controller %s fan control\n",
2316                                  (controller->ucFanParameters &
2317                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2318                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2319                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2320                         DRM_INFO("Internal thermal controller %s fan control\n",
2321                                  (controller->ucFanParameters &
2322                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2323                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2324                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2325                         DRM_INFO("Internal thermal controller %s fan control\n",
2326                                  (controller->ucFanParameters &
2327                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2328                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2329                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2330                         DRM_INFO("Internal thermal controller %s fan control\n",
2331                                  (controller->ucFanParameters &
2332                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2333                         rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2334                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2335                         DRM_INFO("Internal thermal controller %s fan control\n",
2336                                  (controller->ucFanParameters &
2337                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2338                         rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2339                 } else if (controller->ucType ==
2340                            ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2341                         DRM_INFO("External GPIO thermal controller %s fan control\n",
2342                                  (controller->ucFanParameters &
2343                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2344                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2345                 } else if (controller->ucType ==
2346                            ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2347                         DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2348                                  (controller->ucFanParameters &
2349                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2350                         rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2351                 } else if (controller->ucType ==
2352                            ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2353                         DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2354                                  (controller->ucFanParameters &
2355                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2356                         rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2357                 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2358                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2359                                  pp_lib_thermal_controller_names[controller->ucType],
2360                                  controller->ucI2cAddress >> 1,
2361                                  (controller->ucFanParameters &
2362                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2363                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2364                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2365                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2366                         if (rdev->pm.i2c_bus) {
2367                                 struct i2c_board_info info = { };
2368                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2369                                 info.addr = controller->ucI2cAddress >> 1;
2370                                 strlcpy(info.type, name, sizeof(info.type));
2371                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2372                         }
2373                 } else {
2374                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2375                                  controller->ucType,
2376                                  controller->ucI2cAddress >> 1,
2377                                  (controller->ucFanParameters &
2378                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2379                 }
2380         }
2381 }
2382
2383 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2384                                           u16 *vddc, u16 *vddci, u16 *mvdd)
2385 {
2386         struct radeon_mode_info *mode_info = &rdev->mode_info;
2387         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2388         u8 frev, crev;
2389         u16 data_offset;
2390         union firmware_info *firmware_info;
2391
2392         *vddc = 0;
2393         *vddci = 0;
2394         *mvdd = 0;
2395
2396         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2397                                    &frev, &crev, &data_offset)) {
2398                 firmware_info =
2399                         (union firmware_info *)(mode_info->atom_context->bios +
2400                                                 data_offset);
2401                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2402                 if ((frev == 2) && (crev >= 2)) {
2403                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2404                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2405                 }
2406         }
2407 }
2408
2409 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2410                                                        int state_index, int mode_index,
2411                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2412 {
2413         int j;
2414         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2415         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2416         u16 vddc, vddci, mvdd;
2417
2418         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2419
2420         rdev->pm.power_state[state_index].misc = misc;
2421         rdev->pm.power_state[state_index].misc2 = misc2;
2422         rdev->pm.power_state[state_index].pcie_lanes =
2423                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2424                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2425         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2426         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2427                 rdev->pm.power_state[state_index].type =
2428                         POWER_STATE_TYPE_BATTERY;
2429                 break;
2430         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2431                 rdev->pm.power_state[state_index].type =
2432                         POWER_STATE_TYPE_BALANCED;
2433                 break;
2434         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2435                 rdev->pm.power_state[state_index].type =
2436                         POWER_STATE_TYPE_PERFORMANCE;
2437                 break;
2438         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2439                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2440                         rdev->pm.power_state[state_index].type =
2441                                 POWER_STATE_TYPE_PERFORMANCE;
2442                 break;
2443         }
2444         rdev->pm.power_state[state_index].flags = 0;
2445         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2446                 rdev->pm.power_state[state_index].flags |=
2447                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2448         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2449                 rdev->pm.power_state[state_index].type =
2450                         POWER_STATE_TYPE_DEFAULT;
2451                 rdev->pm.default_power_state_index = state_index;
2452                 rdev->pm.power_state[state_index].default_clock_mode =
2453                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2454                 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2455                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2456                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2457                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2458                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2459                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2460                 } else {
2461                         u16 max_vddci = 0;
2462
2463                         if (ASIC_IS_DCE4(rdev))
2464                                 radeon_atom_get_max_voltage(rdev,
2465                                                             SET_VOLTAGE_TYPE_ASIC_VDDCI,
2466                                                             &max_vddci);
2467                         /* patch the table values with the default sclk/mclk from firmware info */
2468                         for (j = 0; j < mode_index; j++) {
2469                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2470                                         rdev->clock.default_mclk;
2471                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2472                                         rdev->clock.default_sclk;
2473                                 if (vddc)
2474                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2475                                                 vddc;
2476                                 if (max_vddci)
2477                                         rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2478                                                 max_vddci;
2479                         }
2480                 }
2481         }
2482 }
2483
2484 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2485                                                    int state_index, int mode_index,
2486                                                    union pplib_clock_info *clock_info)
2487 {
2488         u32 sclk, mclk;
2489         u16 vddc;
2490
2491         if (rdev->flags & RADEON_IS_IGP) {
2492                 if (rdev->family >= CHIP_PALM) {
2493                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2494                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2495                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2496                 } else {
2497                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2498                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2499                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2500                 }
2501         } else if (rdev->family >= CHIP_BONAIRE) {
2502                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2503                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2504                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2505                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2506                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2507                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2508                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2509                         VOLTAGE_NONE;
2510         } else if (rdev->family >= CHIP_TAHITI) {
2511                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2512                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2513                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2514                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2515                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2516                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2517                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2518                         VOLTAGE_SW;
2519                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2520                         le16_to_cpu(clock_info->si.usVDDC);
2521                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2522                         le16_to_cpu(clock_info->si.usVDDCI);
2523         } else if (rdev->family >= CHIP_CEDAR) {
2524                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2525                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2526                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2527                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2528                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2529                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2530                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2531                         VOLTAGE_SW;
2532                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2533                         le16_to_cpu(clock_info->evergreen.usVDDC);
2534                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2535                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2536         } else {
2537                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2538                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2539                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2540                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2541                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2542                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2543                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2544                         VOLTAGE_SW;
2545                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2546                         le16_to_cpu(clock_info->r600.usVDDC);
2547         }
2548
2549         /* patch up vddc if necessary */
2550         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2551         case ATOM_VIRTUAL_VOLTAGE_ID0:
2552         case ATOM_VIRTUAL_VOLTAGE_ID1:
2553         case ATOM_VIRTUAL_VOLTAGE_ID2:
2554         case ATOM_VIRTUAL_VOLTAGE_ID3:
2555         case ATOM_VIRTUAL_VOLTAGE_ID4:
2556         case ATOM_VIRTUAL_VOLTAGE_ID5:
2557         case ATOM_VIRTUAL_VOLTAGE_ID6:
2558         case ATOM_VIRTUAL_VOLTAGE_ID7:
2559                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2560                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2561                                              &vddc) == 0)
2562                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2563                 break;
2564         default:
2565                 break;
2566         }
2567
2568         if (rdev->flags & RADEON_IS_IGP) {
2569                 /* skip invalid modes */
2570                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2571                         return false;
2572         } else {
2573                 /* skip invalid modes */
2574                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2575                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2576                         return false;
2577         }
2578         return true;
2579 }
2580
2581 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2582 {
2583         struct radeon_mode_info *mode_info = &rdev->mode_info;
2584         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2585         union pplib_power_state *power_state;
2586         int i, j;
2587         int state_index = 0, mode_index = 0;
2588         union pplib_clock_info *clock_info;
2589         bool valid;
2590         union power_info *power_info;
2591         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2592         u16 data_offset;
2593         u8 frev, crev;
2594
2595         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2596                                    &frev, &crev, &data_offset))
2597                 return state_index;
2598         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2599
2600         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2601         if (power_info->pplib.ucNumStates == 0)
2602                 return state_index;
2603         rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2604                                        sizeof(struct radeon_power_state),
2605                                        GFP_KERNEL);
2606         if (!rdev->pm.power_state)
2607                 return state_index;
2608         /* first mode is usually default, followed by low to high */
2609         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2610                 mode_index = 0;
2611                 power_state = (union pplib_power_state *)
2612                         (mode_info->atom_context->bios + data_offset +
2613                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2614                          i * power_info->pplib.ucStateEntrySize);
2615                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2616                         (mode_info->atom_context->bios + data_offset +
2617                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2618                          (power_state->v1.ucNonClockStateIndex *
2619                           power_info->pplib.ucNonClockSize));
2620                 rdev->pm.power_state[i].clock_info =
2621                         kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2622                                 (power_info->pplib.ucStateEntrySize - 1) : 1,
2623                                 sizeof(struct radeon_pm_clock_info),
2624                                 GFP_KERNEL);
2625                 if (!rdev->pm.power_state[i].clock_info)
2626                         return state_index;
2627                 if (power_info->pplib.ucStateEntrySize - 1) {
2628                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2629                                 clock_info = (union pplib_clock_info *)
2630                                         (mode_info->atom_context->bios + data_offset +
2631                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2632                                          (power_state->v1.ucClockStateIndices[j] *
2633                                           power_info->pplib.ucClockInfoSize));
2634                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2635                                                                                state_index, mode_index,
2636                                                                                clock_info);
2637                                 if (valid)
2638                                         mode_index++;
2639                         }
2640                 } else {
2641                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2642                                 rdev->clock.default_mclk;
2643                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2644                                 rdev->clock.default_sclk;
2645                         mode_index++;
2646                 }
2647                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2648                 if (mode_index) {
2649                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2650                                                                    non_clock_info);
2651                         state_index++;
2652                 }
2653         }
2654         /* if multiple clock modes, mark the lowest as no display */
2655         for (i = 0; i < state_index; i++) {
2656                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2657                         rdev->pm.power_state[i].clock_info[0].flags |=
2658                                 RADEON_PM_MODE_NO_DISPLAY;
2659         }
2660         /* first mode is usually default */
2661         if (rdev->pm.default_power_state_index == -1) {
2662                 rdev->pm.power_state[0].type =
2663                         POWER_STATE_TYPE_DEFAULT;
2664                 rdev->pm.default_power_state_index = 0;
2665                 rdev->pm.power_state[0].default_clock_mode =
2666                         &rdev->pm.power_state[0].clock_info[0];
2667         }
2668         return state_index;
2669 }
2670
2671 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2672 {
2673         struct radeon_mode_info *mode_info = &rdev->mode_info;
2674         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2675         union pplib_power_state *power_state;
2676         int i, j, non_clock_array_index, clock_array_index;
2677         int state_index = 0, mode_index = 0;
2678         union pplib_clock_info *clock_info;
2679         struct _StateArray *state_array;
2680         struct _ClockInfoArray *clock_info_array;
2681         struct _NonClockInfoArray *non_clock_info_array;
2682         bool valid;
2683         union power_info *power_info;
2684         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2685         u16 data_offset;
2686         u8 frev, crev;
2687         u8 *power_state_offset;
2688
2689         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2690                                    &frev, &crev, &data_offset))
2691                 return state_index;
2692         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2693
2694         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2695         state_array = (struct _StateArray *)
2696                 (mode_info->atom_context->bios + data_offset +
2697                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2698         clock_info_array = (struct _ClockInfoArray *)
2699                 (mode_info->atom_context->bios + data_offset +
2700                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2701         non_clock_info_array = (struct _NonClockInfoArray *)
2702                 (mode_info->atom_context->bios + data_offset +
2703                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2704         if (state_array->ucNumEntries == 0)
2705                 return state_index;
2706         rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2707                                        sizeof(struct radeon_power_state),
2708                                        GFP_KERNEL);
2709         if (!rdev->pm.power_state)
2710                 return state_index;
2711         power_state_offset = (u8 *)state_array->states;
2712         for (i = 0; i < state_array->ucNumEntries; i++) {
2713                 mode_index = 0;
2714                 power_state = (union pplib_power_state *)power_state_offset;
2715                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2716                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2717                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2718                 rdev->pm.power_state[i].clock_info =
2719                         kcalloc(power_state->v2.ucNumDPMLevels ?
2720                                 power_state->v2.ucNumDPMLevels : 1,
2721                                 sizeof(struct radeon_pm_clock_info),
2722                                 GFP_KERNEL);
2723                 if (!rdev->pm.power_state[i].clock_info)
2724                         return state_index;
2725                 if (power_state->v2.ucNumDPMLevels) {
2726                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2727                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2728                                 clock_info = (union pplib_clock_info *)
2729                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2730                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2731                                                                                state_index, mode_index,
2732                                                                                clock_info);
2733                                 if (valid)
2734                                         mode_index++;
2735                         }
2736                 } else {
2737                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2738                                 rdev->clock.default_mclk;
2739                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2740                                 rdev->clock.default_sclk;
2741                         mode_index++;
2742                 }
2743                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2744                 if (mode_index) {
2745                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2746                                                                    non_clock_info);
2747                         state_index++;
2748                 }
2749                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2750         }
2751         /* if multiple clock modes, mark the lowest as no display */
2752         for (i = 0; i < state_index; i++) {
2753                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2754                         rdev->pm.power_state[i].clock_info[0].flags |=
2755                                 RADEON_PM_MODE_NO_DISPLAY;
2756         }
2757         /* first mode is usually default */
2758         if (rdev->pm.default_power_state_index == -1) {
2759                 rdev->pm.power_state[0].type =
2760                         POWER_STATE_TYPE_DEFAULT;
2761                 rdev->pm.default_power_state_index = 0;
2762                 rdev->pm.power_state[0].default_clock_mode =
2763                         &rdev->pm.power_state[0].clock_info[0];
2764         }
2765         return state_index;
2766 }
2767
2768 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2769 {
2770         struct radeon_mode_info *mode_info = &rdev->mode_info;
2771         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2772         u16 data_offset;
2773         u8 frev, crev;
2774         int state_index = 0;
2775
2776         rdev->pm.default_power_state_index = -1;
2777
2778         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2779                                    &frev, &crev, &data_offset)) {
2780                 switch (frev) {
2781                 case 1:
2782                 case 2:
2783                 case 3:
2784                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2785                         break;
2786                 case 4:
2787                 case 5:
2788                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2789                         break;
2790                 case 6:
2791                         state_index = radeon_atombios_parse_power_table_6(rdev);
2792                         break;
2793                 default:
2794                         break;
2795                 }
2796         }
2797
2798         if (state_index == 0) {
2799                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2800                 if (rdev->pm.power_state) {
2801                         rdev->pm.power_state[0].clock_info =
2802                                 kcalloc(1,
2803                                         sizeof(struct radeon_pm_clock_info),
2804                                         GFP_KERNEL);
2805                         if (rdev->pm.power_state[0].clock_info) {
2806                                 /* add the default mode */
2807                                 rdev->pm.power_state[state_index].type =
2808                                         POWER_STATE_TYPE_DEFAULT;
2809                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2810                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2811                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2812                                 rdev->pm.power_state[state_index].default_clock_mode =
2813                                         &rdev->pm.power_state[state_index].clock_info[0];
2814                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2815                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2816                                 rdev->pm.default_power_state_index = state_index;
2817                                 rdev->pm.power_state[state_index].flags = 0;
2818                                 state_index++;
2819                         }
2820                 }
2821         }
2822
2823         rdev->pm.num_power_states = state_index;
2824
2825         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2826         rdev->pm.current_clock_mode_index = 0;
2827         if (rdev->pm.default_power_state_index >= 0)
2828                 rdev->pm.current_vddc =
2829                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2830         else
2831                 rdev->pm.current_vddc = 0;
2832 }
2833
2834 union get_clock_dividers {
2835         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2836         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2837         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2838         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2839         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2840         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2841         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2842 };
2843
2844 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2845                                    u8 clock_type,
2846                                    u32 clock,
2847                                    bool strobe_mode,
2848                                    struct atom_clock_dividers *dividers)
2849 {
2850         union get_clock_dividers args;
2851         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2852         u8 frev, crev;
2853
2854         memset(&args, 0, sizeof(args));
2855         memset(dividers, 0, sizeof(struct atom_clock_dividers));
2856
2857         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2858                 return -EINVAL;
2859
2860         switch (crev) {
2861         case 1:
2862                 /* r4xx, r5xx */
2863                 args.v1.ucAction = clock_type;
2864                 args.v1.ulClock = cpu_to_le32(clock);   /* 10 khz */
2865
2866                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2867
2868                 dividers->post_div = args.v1.ucPostDiv;
2869                 dividers->fb_div = args.v1.ucFbDiv;
2870                 dividers->enable_post_div = true;
2871                 break;
2872         case 2:
2873         case 3:
2874         case 5:
2875                 /* r6xx, r7xx, evergreen, ni, si */
2876                 if (rdev->family <= CHIP_RV770) {
2877                         args.v2.ucAction = clock_type;
2878                         args.v2.ulClock = cpu_to_le32(clock);   /* 10 khz */
2879
2880                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2881
2882                         dividers->post_div = args.v2.ucPostDiv;
2883                         dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2884                         dividers->ref_div = args.v2.ucAction;
2885                         if (rdev->family == CHIP_RV770) {
2886                                 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2887                                         true : false;
2888                                 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2889                         } else
2890                                 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2891                 } else {
2892                         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2893                                 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2894
2895                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2896
2897                                 dividers->post_div = args.v3.ucPostDiv;
2898                                 dividers->enable_post_div = (args.v3.ucCntlFlag &
2899                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2900                                 dividers->enable_dithen = (args.v3.ucCntlFlag &
2901                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2902                                 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2903                                 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2904                                 dividers->ref_div = args.v3.ucRefDiv;
2905                                 dividers->vco_mode = (args.v3.ucCntlFlag &
2906                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2907                         } else {
2908                                 /* for SI we use ComputeMemoryClockParam for memory plls */
2909                                 if (rdev->family >= CHIP_TAHITI)
2910                                         return -EINVAL;
2911                                 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2912                                 if (strobe_mode)
2913                                         args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2914
2915                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2916
2917                                 dividers->post_div = args.v5.ucPostDiv;
2918                                 dividers->enable_post_div = (args.v5.ucCntlFlag &
2919                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2920                                 dividers->enable_dithen = (args.v5.ucCntlFlag &
2921                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2922                                 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2923                                 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2924                                 dividers->ref_div = args.v5.ucRefDiv;
2925                                 dividers->vco_mode = (args.v5.ucCntlFlag &
2926                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2927                         }
2928                 }
2929                 break;
2930         case 4:
2931                 /* fusion */
2932                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
2933
2934                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2935
2936                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2937                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2938                 break;
2939         case 6:
2940                 /* CI */
2941                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2942                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2943                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
2944
2945                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2946
2947                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2948                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2949                 dividers->ref_div = args.v6_out.ucPllRefDiv;
2950                 dividers->post_div = args.v6_out.ucPllPostDiv;
2951                 dividers->flags = args.v6_out.ucPllCntlFlag;
2952                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2953                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2954                 break;
2955         default:
2956                 return -EINVAL;
2957         }
2958         return 0;
2959 }
2960
2961 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2962                                         u32 clock,
2963                                         bool strobe_mode,
2964                                         struct atom_mpll_param *mpll_param)
2965 {
2966         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2967         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2968         u8 frev, crev;
2969
2970         memset(&args, 0, sizeof(args));
2971         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2972
2973         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2974                 return -EINVAL;
2975
2976         switch (frev) {
2977         case 2:
2978                 switch (crev) {
2979                 case 1:
2980                         /* SI */
2981                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
2982                         args.ucInputFlag = 0;
2983                         if (strobe_mode)
2984                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2985
2986                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2987
2988                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2989                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2990                         mpll_param->post_div = args.ucPostDiv;
2991                         mpll_param->dll_speed = args.ucDllSpeed;
2992                         mpll_param->bwcntl = args.ucBWCntl;
2993                         mpll_param->vco_mode =
2994                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2995                         mpll_param->yclk_sel =
2996                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2997                         mpll_param->qdr =
2998                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2999                         mpll_param->half_rate =
3000                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
3001                         break;
3002                 default:
3003                         return -EINVAL;
3004                 }
3005                 break;
3006         default:
3007                 return -EINVAL;
3008         }
3009         return 0;
3010 }
3011
3012 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3013 {
3014         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3015         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3016
3017         args.ucEnable = enable;
3018
3019         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3020 }
3021
3022 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3023 {
3024         GET_ENGINE_CLOCK_PS_ALLOCATION args;
3025         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3026
3027         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3028         return le32_to_cpu(args.ulReturnEngineClock);
3029 }
3030
3031 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3032 {
3033         GET_MEMORY_CLOCK_PS_ALLOCATION args;
3034         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3035
3036         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3037         return le32_to_cpu(args.ulReturnMemoryClock);
3038 }
3039
3040 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3041                                   uint32_t eng_clock)
3042 {
3043         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3044         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3045
3046         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
3047
3048         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3049 }
3050
3051 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3052                                   uint32_t mem_clock)
3053 {
3054         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3055         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3056
3057         if (rdev->flags & RADEON_IS_IGP)
3058                 return;
3059
3060         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
3061
3062         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3063 }
3064
3065 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3066                                          u32 eng_clock, u32 mem_clock)
3067 {
3068         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3069         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3070         u32 tmp;
3071
3072         memset(&args, 0, sizeof(args));
3073
3074         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3075         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3076
3077         args.ulTargetEngineClock = cpu_to_le32(tmp);
3078         if (mem_clock)
3079                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3080
3081         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3082 }
3083
3084 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3085                                    u32 mem_clock)
3086 {
3087         u32 args;
3088         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3089
3090         args = cpu_to_le32(mem_clock);  /* 10 khz */
3091
3092         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3093 }
3094
3095 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3096                                u32 mem_clock)
3097 {
3098         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3099         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3100         u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3101
3102         args.ulTargetMemoryClock = cpu_to_le32(tmp);    /* 10 khz */
3103
3104         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3105 }
3106
3107 union set_voltage {
3108         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3109         struct _SET_VOLTAGE_PARAMETERS v1;
3110         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3111         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3112 };
3113
3114 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3115 {
3116         union set_voltage args;
3117         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3118         u8 frev, crev, volt_index = voltage_level;
3119
3120         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3121                 return;
3122
3123         /* 0xff01 is a flag rather then an actual voltage */
3124         if (voltage_level == 0xff01)
3125                 return;
3126
3127         switch (crev) {
3128         case 1:
3129                 args.v1.ucVoltageType = voltage_type;
3130                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3131                 args.v1.ucVoltageIndex = volt_index;
3132                 break;
3133         case 2:
3134                 args.v2.ucVoltageType = voltage_type;
3135                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3136                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3137                 break;
3138         case 3:
3139                 args.v3.ucVoltageType = voltage_type;
3140                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3141                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3142                 break;
3143         default:
3144                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3145                 return;
3146         }
3147
3148         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3149 }
3150
3151 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3152                              u16 voltage_id, u16 *voltage)
3153 {
3154         union set_voltage args;
3155         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3156         u8 frev, crev;
3157
3158         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3159                 return -EINVAL;
3160
3161         switch (crev) {
3162         case 1:
3163                 return -EINVAL;
3164         case 2:
3165                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3166                 args.v2.ucVoltageMode = 0;
3167                 args.v2.usVoltageLevel = 0;
3168
3169                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3170
3171                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3172                 break;
3173         case 3:
3174                 args.v3.ucVoltageType = voltage_type;
3175                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3176                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3177
3178                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3179
3180                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3181                 break;
3182         default:
3183                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3184                 return -EINVAL;
3185         }
3186
3187         return 0;
3188 }
3189
3190 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3191                                                       u16 *voltage,
3192                                                       u16 leakage_idx)
3193 {
3194         return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3195 }
3196
3197 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3198                                           u16 *leakage_id)
3199 {
3200         union set_voltage args;
3201         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3202         u8 frev, crev;
3203
3204         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3205                 return -EINVAL;
3206
3207         switch (crev) {
3208         case 3:
3209         case 4:
3210                 args.v3.ucVoltageType = 0;
3211                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3212                 args.v3.usVoltageLevel = 0;
3213
3214                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3215
3216                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3217                 break;
3218         default:
3219                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3220                 return -EINVAL;
3221         }
3222
3223         return 0;
3224 }
3225
3226 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3227                                                          u16 *vddc, u16 *vddci,
3228                                                          u16 virtual_voltage_id,
3229                                                          u16 vbios_voltage_id)
3230 {
3231         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3232         u8 frev, crev;
3233         u16 data_offset, size;
3234         int i, j;
3235         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3236         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3237
3238         *vddc = 0;
3239         *vddci = 0;
3240
3241         if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3242                                     &frev, &crev, &data_offset))
3243                 return -EINVAL;
3244
3245         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3246                 (rdev->mode_info.atom_context->bios + data_offset);
3247
3248         switch (frev) {
3249         case 1:
3250                 return -EINVAL;
3251         case 2:
3252                 switch (crev) {
3253                 case 1:
3254                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3255                                 return -EINVAL;
3256                         leakage_bin = (u16 *)
3257                                 (rdev->mode_info.atom_context->bios + data_offset +
3258                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
3259                         vddc_id_buf = (u16 *)
3260                                 (rdev->mode_info.atom_context->bios + data_offset +
3261                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3262                         vddc_buf = (u16 *)
3263                                 (rdev->mode_info.atom_context->bios + data_offset +
3264                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3265                         vddci_id_buf = (u16 *)
3266                                 (rdev->mode_info.atom_context->bios + data_offset +
3267                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3268                         vddci_buf = (u16 *)
3269                                 (rdev->mode_info.atom_context->bios + data_offset +
3270                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3271
3272                         if (profile->ucElbVDDC_Num > 0) {
3273                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3274                                         if (vddc_id_buf[i] == virtual_voltage_id) {
3275                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3276                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3277                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3278                                                                 break;
3279                                                         }
3280                                                 }
3281                                                 break;
3282                                         }
3283                                 }
3284                         }
3285                         if (profile->ucElbVDDCI_Num > 0) {
3286                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3287                                         if (vddci_id_buf[i] == virtual_voltage_id) {
3288                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3289                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3290                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3291                                                                 break;
3292                                                         }
3293                                                 }
3294                                                 break;
3295                                         }
3296                                 }
3297                         }
3298                         break;
3299                 default:
3300                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3301                         return -EINVAL;
3302                 }
3303                 break;
3304         default:
3305                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3306                 return -EINVAL;
3307         }
3308
3309         return 0;
3310 }
3311
3312 union get_voltage_info {
3313         struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3314         struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3315 };
3316
3317 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3318                                 u16 virtual_voltage_id,
3319                                 u16 *voltage)
3320 {
3321         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3322         u32 entry_id;
3323         u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3324         union get_voltage_info args;
3325
3326         for (entry_id = 0; entry_id < count; entry_id++) {
3327                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3328                     virtual_voltage_id)
3329                         break;
3330         }
3331
3332         if (entry_id >= count)
3333                 return -EINVAL;
3334
3335         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3336         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3337         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3338         args.in.ulSCLKFreq =
3339                 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3340
3341         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3342
3343         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3344
3345         return 0;
3346 }
3347
3348 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3349                                           u16 voltage_level, u8 voltage_type,
3350                                           u32 *gpio_value, u32 *gpio_mask)
3351 {
3352         union set_voltage args;
3353         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3354         u8 frev, crev;
3355
3356         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3357                 return -EINVAL;
3358
3359         switch (crev) {
3360         case 1:
3361                 return -EINVAL;
3362         case 2:
3363                 args.v2.ucVoltageType = voltage_type;
3364                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3365                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3366
3367                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3368
3369                 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3370
3371                 args.v2.ucVoltageType = voltage_type;
3372                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3373                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3374
3375                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3376
3377                 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3378                 break;
3379         default:
3380                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3381                 return -EINVAL;
3382         }
3383
3384         return 0;
3385 }
3386
3387 union voltage_object_info {
3388         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3389         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3390         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3391 };
3392
3393 union voltage_object {
3394         struct _ATOM_VOLTAGE_OBJECT v1;
3395         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3396         union _ATOM_VOLTAGE_OBJECT_V3 v3;
3397 };
3398
3399 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3400                                                           u8 voltage_type)
3401 {
3402         u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3403         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3404         u8 *start = (u8 *)v1;
3405
3406         while (offset < size) {
3407                 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3408                 if (vo->ucVoltageType == voltage_type)
3409                         return vo;
3410                 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3411                         vo->asFormula.ucNumOfVoltageEntries;
3412         }
3413         return NULL;
3414 }
3415
3416 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3417                                                              u8 voltage_type)
3418 {
3419         u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3420         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3421         u8 *start = (u8*)v2;
3422
3423         while (offset < size) {
3424                 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3425                 if (vo->ucVoltageType == voltage_type)
3426                         return vo;
3427                 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3428                         (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3429         }
3430         return NULL;
3431 }
3432
3433 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3434                                                              u8 voltage_type, u8 voltage_mode)
3435 {
3436         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3437         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3438         u8 *start = (u8*)v3;
3439
3440         while (offset < size) {
3441                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3442                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3443                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3444                         return vo;
3445                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3446         }
3447         return NULL;
3448 }
3449
3450 bool
3451 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3452                             u8 voltage_type, u8 voltage_mode)
3453 {
3454         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3455         u8 frev, crev;
3456         u16 data_offset, size;
3457         union voltage_object_info *voltage_info;
3458         union voltage_object *voltage_object = NULL;
3459
3460         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3461                                    &frev, &crev, &data_offset)) {
3462                 voltage_info = (union voltage_object_info *)
3463                         (rdev->mode_info.atom_context->bios + data_offset);
3464
3465                 switch (frev) {
3466                 case 1:
3467                 case 2:
3468                         switch (crev) {
3469                         case 1:
3470                                 voltage_object = (union voltage_object *)
3471                                         atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3472                                 if (voltage_object &&
3473                                     (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3474                                         return true;
3475                                 break;
3476                         case 2:
3477                                 voltage_object = (union voltage_object *)
3478                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3479                                 if (voltage_object &&
3480                                     (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3481                                         return true;
3482                                 break;
3483                         default:
3484                                 DRM_ERROR("unknown voltage object table\n");
3485                                 return false;
3486                         }
3487                         break;
3488                 case 3:
3489                         switch (crev) {
3490                         case 1:
3491                                 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3492                                                                   voltage_type, voltage_mode))
3493                                         return true;
3494                                 break;
3495                         default:
3496                                 DRM_ERROR("unknown voltage object table\n");
3497                                 return false;
3498                         }
3499                         break;
3500                 default:
3501                         DRM_ERROR("unknown voltage object table\n");
3502                         return false;
3503                 }
3504
3505         }
3506         return false;
3507 }
3508
3509 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3510                               u8 voltage_type,
3511                               u8 *svd_gpio_id, u8 *svc_gpio_id)
3512 {
3513         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3514         u8 frev, crev;
3515         u16 data_offset, size;
3516         union voltage_object_info *voltage_info;
3517         union voltage_object *voltage_object = NULL;
3518
3519         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3520                                    &frev, &crev, &data_offset)) {
3521                 voltage_info = (union voltage_object_info *)
3522                         (rdev->mode_info.atom_context->bios + data_offset);
3523
3524                 switch (frev) {
3525                 case 3:
3526                         switch (crev) {
3527                         case 1:
3528                                 voltage_object = (union voltage_object *)
3529                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3530                                                                       voltage_type,
3531                                                                       VOLTAGE_OBJ_SVID2);
3532                                 if (voltage_object) {
3533                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3534                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3535                                 } else {
3536                                         return -EINVAL;
3537                                 }
3538                                 break;
3539                         default:
3540                                 DRM_ERROR("unknown voltage object table\n");
3541                                 return -EINVAL;
3542                         }
3543                         break;
3544                 default:
3545                         DRM_ERROR("unknown voltage object table\n");
3546                         return -EINVAL;
3547                 }
3548
3549         }
3550         return 0;
3551 }
3552
3553 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3554                                 u8 voltage_type, u16 *max_voltage)
3555 {
3556         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3557         u8 frev, crev;
3558         u16 data_offset, size;
3559         union voltage_object_info *voltage_info;
3560         union voltage_object *voltage_object = NULL;
3561
3562         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3563                                    &frev, &crev, &data_offset)) {
3564                 voltage_info = (union voltage_object_info *)
3565                         (rdev->mode_info.atom_context->bios + data_offset);
3566
3567                 switch (crev) {
3568                 case 1:
3569                         voltage_object = (union voltage_object *)
3570                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3571                         if (voltage_object) {
3572                                 ATOM_VOLTAGE_FORMULA *formula =
3573                                         &voltage_object->v1.asFormula;
3574                                 if (formula->ucFlag & 1)
3575                                         *max_voltage =
3576                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3577                                                 formula->ucNumOfVoltageEntries / 2 *
3578                                                 le16_to_cpu(formula->usVoltageStep);
3579                                 else
3580                                         *max_voltage =
3581                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3582                                                 (formula->ucNumOfVoltageEntries - 1) *
3583                                                 le16_to_cpu(formula->usVoltageStep);
3584                                 return 0;
3585                         }
3586                         break;
3587                 case 2:
3588                         voltage_object = (union voltage_object *)
3589                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3590                         if (voltage_object) {
3591                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3592                                         &voltage_object->v2.asFormula;
3593                                 if (formula->ucNumOfVoltageEntries) {
3594                                         VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3595                                                 ((u8 *)&formula->asVIDAdjustEntries[0] +
3596                                                  (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3597                                         *max_voltage =
3598                                                 le16_to_cpu(lut->usVoltageValue);
3599                                         return 0;
3600                                 }
3601                         }
3602                         break;
3603                 default:
3604                         DRM_ERROR("unknown voltage object table\n");
3605                         return -EINVAL;
3606                 }
3607
3608         }
3609         return -EINVAL;
3610 }
3611
3612 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3613                                 u8 voltage_type, u16 *min_voltage)
3614 {
3615         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3616         u8 frev, crev;
3617         u16 data_offset, size;
3618         union voltage_object_info *voltage_info;
3619         union voltage_object *voltage_object = NULL;
3620
3621         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3622                                    &frev, &crev, &data_offset)) {
3623                 voltage_info = (union voltage_object_info *)
3624                         (rdev->mode_info.atom_context->bios + data_offset);
3625
3626                 switch (crev) {
3627                 case 1:
3628                         voltage_object = (union voltage_object *)
3629                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3630                         if (voltage_object) {
3631                                 ATOM_VOLTAGE_FORMULA *formula =
3632                                         &voltage_object->v1.asFormula;
3633                                 *min_voltage =
3634                                         le16_to_cpu(formula->usVoltageBaseLevel);
3635                                 return 0;
3636                         }
3637                         break;
3638                 case 2:
3639                         voltage_object = (union voltage_object *)
3640                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3641                         if (voltage_object) {
3642                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3643                                         &voltage_object->v2.asFormula;
3644                                 if (formula->ucNumOfVoltageEntries) {
3645                                         *min_voltage =
3646                                                 le16_to_cpu(formula->asVIDAdjustEntries[
3647                                                                     0
3648                                                                     ].usVoltageValue);
3649                                         return 0;
3650                                 }
3651                         }
3652                         break;
3653                 default:
3654                         DRM_ERROR("unknown voltage object table\n");
3655                         return -EINVAL;
3656                 }
3657
3658         }
3659         return -EINVAL;
3660 }
3661
3662 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3663                                  u8 voltage_type, u16 *voltage_step)
3664 {
3665         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3666         u8 frev, crev;
3667         u16 data_offset, size;
3668         union voltage_object_info *voltage_info;
3669         union voltage_object *voltage_object = NULL;
3670
3671         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3672                                    &frev, &crev, &data_offset)) {
3673                 voltage_info = (union voltage_object_info *)
3674                         (rdev->mode_info.atom_context->bios + data_offset);
3675
3676                 switch (crev) {
3677                 case 1:
3678                         voltage_object = (union voltage_object *)
3679                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3680                         if (voltage_object) {
3681                                 ATOM_VOLTAGE_FORMULA *formula =
3682                                         &voltage_object->v1.asFormula;
3683                                 if (formula->ucFlag & 1)
3684                                         *voltage_step =
3685                                                 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3686                                 else
3687                                         *voltage_step =
3688                                                 le16_to_cpu(formula->usVoltageStep);
3689                                 return 0;
3690                         }
3691                         break;
3692                 case 2:
3693                         return -EINVAL;
3694                 default:
3695                         DRM_ERROR("unknown voltage object table\n");
3696                         return -EINVAL;
3697                 }
3698
3699         }
3700         return -EINVAL;
3701 }
3702
3703 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3704                                       u8 voltage_type,
3705                                       u16 nominal_voltage,
3706                                       u16 *true_voltage)
3707 {
3708         u16 min_voltage, max_voltage, voltage_step;
3709
3710         if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3711                 return -EINVAL;
3712         if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3713                 return -EINVAL;
3714         if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3715                 return -EINVAL;
3716
3717         if (nominal_voltage <= min_voltage)
3718                 *true_voltage = min_voltage;
3719         else if (nominal_voltage >= max_voltage)
3720                 *true_voltage = max_voltage;
3721         else
3722                 *true_voltage = min_voltage +
3723                         ((nominal_voltage - min_voltage) / voltage_step) *
3724                         voltage_step;
3725
3726         return 0;
3727 }
3728
3729 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3730                                   u8 voltage_type, u8 voltage_mode,
3731                                   struct atom_voltage_table *voltage_table)
3732 {
3733         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3734         u8 frev, crev;
3735         u16 data_offset, size;
3736         int i, ret;
3737         union voltage_object_info *voltage_info;
3738         union voltage_object *voltage_object = NULL;
3739
3740         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3741                                    &frev, &crev, &data_offset)) {
3742                 voltage_info = (union voltage_object_info *)
3743                         (rdev->mode_info.atom_context->bios + data_offset);
3744
3745                 switch (frev) {
3746                 case 1:
3747                 case 2:
3748                         switch (crev) {
3749                         case 1:
3750                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3751                                 return -EINVAL;
3752                         case 2:
3753                                 voltage_object = (union voltage_object *)
3754                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3755                                 if (voltage_object) {
3756                                         ATOM_VOLTAGE_FORMULA_V2 *formula =
3757                                                 &voltage_object->v2.asFormula;
3758                                         VOLTAGE_LUT_ENTRY *lut;
3759                                         if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3760                                                 return -EINVAL;
3761                                         lut = &formula->asVIDAdjustEntries[0];
3762                                         for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3763                                                 voltage_table->entries[i].value =
3764                                                         le16_to_cpu(lut->usVoltageValue);
3765                                                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3766                                                                                             voltage_table->entries[i].value,
3767                                                                                             voltage_type,
3768                                                                                             &voltage_table->entries[i].smio_low,
3769                                                                                             &voltage_table->mask_low);
3770                                                 if (ret)
3771                                                         return ret;
3772                                                 lut = (VOLTAGE_LUT_ENTRY *)
3773                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3774                                         }
3775                                         voltage_table->count = formula->ucNumOfVoltageEntries;
3776                                         return 0;
3777                                 }
3778                                 break;
3779                         default:
3780                                 DRM_ERROR("unknown voltage object table\n");
3781                                 return -EINVAL;
3782                         }
3783                         break;
3784                 case 3:
3785                         switch (crev) {
3786                         case 1:
3787                                 voltage_object = (union voltage_object *)
3788                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3789                                                                       voltage_type, voltage_mode);
3790                                 if (voltage_object) {
3791                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3792                                                 &voltage_object->v3.asGpioVoltageObj;
3793                                         VOLTAGE_LUT_ENTRY_V2 *lut;
3794                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3795                                                 return -EINVAL;
3796                                         lut = &gpio->asVolGpioLut[0];
3797                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3798                                                 voltage_table->entries[i].value =
3799                                                         le16_to_cpu(lut->usVoltageValue);
3800                                                 voltage_table->entries[i].smio_low =
3801                                                         le32_to_cpu(lut->ulVoltageId);
3802                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3803                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3804                                         }
3805                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3806                                         voltage_table->count = gpio->ucGpioEntryNum;
3807                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
3808                                         return 0;
3809                                 }
3810                                 break;
3811                         default:
3812                                 DRM_ERROR("unknown voltage object table\n");
3813                                 return -EINVAL;
3814                         }
3815                         break;
3816                 default:
3817                         DRM_ERROR("unknown voltage object table\n");
3818                         return -EINVAL;
3819                 }
3820         }
3821         return -EINVAL;
3822 }
3823
3824 union vram_info {
3825         struct _ATOM_VRAM_INFO_V3 v1_3;
3826         struct _ATOM_VRAM_INFO_V4 v1_4;
3827         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3828 };
3829
3830 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3831                                 u8 module_index, struct atom_memory_info *mem_info)
3832 {
3833         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3834         u8 frev, crev, i;
3835         u16 data_offset, size;
3836         union vram_info *vram_info;
3837
3838         memset(mem_info, 0, sizeof(struct atom_memory_info));
3839
3840         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3841                                    &frev, &crev, &data_offset)) {
3842                 vram_info = (union vram_info *)
3843                         (rdev->mode_info.atom_context->bios + data_offset);
3844                 switch (frev) {
3845                 case 1:
3846                         switch (crev) {
3847                         case 3:
3848                                 /* r6xx */
3849                                 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3850                                         ATOM_VRAM_MODULE_V3 *vram_module =
3851                                                 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3852
3853                                         for (i = 0; i < module_index; i++) {
3854                                                 if (le16_to_cpu(vram_module->usSize) == 0)
3855                                                         return -EINVAL;
3856                                                 vram_module = (ATOM_VRAM_MODULE_V3 *)
3857                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3858                                         }
3859                                         mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3860                                         mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3861                                 } else
3862                                         return -EINVAL;
3863                                 break;
3864                         case 4:
3865                                 /* r7xx, evergreen */
3866                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3867                                         ATOM_VRAM_MODULE_V4 *vram_module =
3868                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3869
3870                                         for (i = 0; i < module_index; i++) {
3871                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3872                                                         return -EINVAL;
3873                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3874                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3875                                         }
3876                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3877                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3878                                 } else
3879                                         return -EINVAL;
3880                                 break;
3881                         default:
3882                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3883                                 return -EINVAL;
3884                         }
3885                         break;
3886                 case 2:
3887                         switch (crev) {
3888                         case 1:
3889                                 /* ni */
3890                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3891                                         ATOM_VRAM_MODULE_V7 *vram_module =
3892                                                 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3893
3894                                         for (i = 0; i < module_index; i++) {
3895                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3896                                                         return -EINVAL;
3897                                                 vram_module = (ATOM_VRAM_MODULE_V7 *)
3898                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3899                                         }
3900                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3901                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3902                                 } else
3903                                         return -EINVAL;
3904                                 break;
3905                         default:
3906                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3907                                 return -EINVAL;
3908                         }
3909                         break;
3910                 default:
3911                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3912                         return -EINVAL;
3913                 }
3914                 return 0;
3915         }
3916         return -EINVAL;
3917 }
3918
3919 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3920                                      bool gddr5, u8 module_index,
3921                                      struct atom_memory_clock_range_table *mclk_range_table)
3922 {
3923         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3924         u8 frev, crev, i;
3925         u16 data_offset, size;
3926         union vram_info *vram_info;
3927         u32 mem_timing_size = gddr5 ?
3928                 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3929
3930         memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3931
3932         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3933                                    &frev, &crev, &data_offset)) {
3934                 vram_info = (union vram_info *)
3935                         (rdev->mode_info.atom_context->bios + data_offset);
3936                 switch (frev) {
3937                 case 1:
3938                         switch (crev) {
3939                         case 3:
3940                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3941                                 return -EINVAL;
3942                         case 4:
3943                                 /* r7xx, evergreen */
3944                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3945                                         ATOM_VRAM_MODULE_V4 *vram_module =
3946                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3947                                         ATOM_MEMORY_TIMING_FORMAT *format;
3948
3949                                         for (i = 0; i < module_index; i++) {
3950                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3951                                                         return -EINVAL;
3952                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3953                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3954                                         }
3955                                         mclk_range_table->num_entries = (u8)
3956                                                 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3957                                                  mem_timing_size);
3958                                         format = &vram_module->asMemTiming[0];
3959                                         for (i = 0; i < mclk_range_table->num_entries; i++) {
3960                                                 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3961                                                 format = (ATOM_MEMORY_TIMING_FORMAT *)
3962                                                         ((u8 *)format + mem_timing_size);
3963                                         }
3964                                 } else
3965                                         return -EINVAL;
3966                                 break;
3967                         default:
3968                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3969                                 return -EINVAL;
3970                         }
3971                         break;
3972                 case 2:
3973                         DRM_ERROR("new table version %d, %d\n", frev, crev);
3974                         return -EINVAL;
3975                 default:
3976                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3977                         return -EINVAL;
3978                 }
3979                 return 0;
3980         }
3981         return -EINVAL;
3982 }
3983
3984 #define MEM_ID_MASK           0xff000000
3985 #define MEM_ID_SHIFT          24
3986 #define CLOCK_RANGE_MASK      0x00ffffff
3987 #define CLOCK_RANGE_SHIFT     0
3988 #define LOW_NIBBLE_MASK       0xf
3989 #define DATA_EQU_PREV         0
3990 #define DATA_FROM_TABLE       4
3991
3992 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3993                                   u8 module_index,
3994                                   struct atom_mc_reg_table *reg_table)
3995 {
3996         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3997         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3998         u32 i = 0, j;
3999         u16 data_offset, size;
4000         union vram_info *vram_info;
4001
4002         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
4003
4004         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
4005                                    &frev, &crev, &data_offset)) {
4006                 vram_info = (union vram_info *)
4007                         (rdev->mode_info.atom_context->bios + data_offset);
4008                 switch (frev) {
4009                 case 1:
4010                         DRM_ERROR("old table version %d, %d\n", frev, crev);
4011                         return -EINVAL;
4012                 case 2:
4013                         switch (crev) {
4014                         case 1:
4015                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4016                                         ATOM_INIT_REG_BLOCK *reg_block =
4017                                                 (ATOM_INIT_REG_BLOCK *)
4018                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4019                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4020                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4021                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
4022                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
4023                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
4024                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4025                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4026                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4027                                                 return -EINVAL;
4028                                         while (i < num_entries) {
4029                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4030                                                         break;
4031                                                 reg_table->mc_reg_address[i].s1 =
4032                                                         (u16)(le16_to_cpu(format->usRegIndex));
4033                                                 reg_table->mc_reg_address[i].pre_reg_data =
4034                                                         (u8)(format->ucPreRegDataLength);
4035                                                 i++;
4036                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4037                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4038                                         }
4039                                         reg_table->last = i;
4040                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4041                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4042                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4043                                                                 >> MEM_ID_SHIFT);
4044                                                 if (module_index == t_mem_id) {
4045                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4046                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4047                                                                       >> CLOCK_RANGE_SHIFT);
4048                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
4049                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4050                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4051                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4052                                                                         j++;
4053                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4054                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4055                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4056                                                                 }
4057                                                         }
4058                                                         num_ranges++;
4059                                                 }
4060                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4061                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4062                                         }
4063                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4064                                                 return -EINVAL;
4065                                         reg_table->num_entries = num_ranges;
4066                                 } else
4067                                         return -EINVAL;
4068                                 break;
4069                         default:
4070                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4071                                 return -EINVAL;
4072                         }
4073                         break;
4074                 default:
4075                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4076                         return -EINVAL;
4077                 }
4078                 return 0;
4079         }
4080         return -EINVAL;
4081 }
4082
4083 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4084 {
4085         struct radeon_device *rdev = dev->dev_private;
4086         uint32_t bios_2_scratch, bios_6_scratch;
4087
4088         if (rdev->family >= CHIP_R600) {
4089                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4090                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4091         } else {
4092                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4093                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4094         }
4095
4096         /* let the bios control the backlight */
4097         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4098
4099         /* tell the bios not to handle mode switching */
4100         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4101
4102         /* clear the vbios dpms state */
4103         if (ASIC_IS_DCE4(rdev))
4104                 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4105
4106         if (rdev->family >= CHIP_R600) {
4107                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4108                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4109         } else {
4110                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4111                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4112         }
4113
4114 }
4115
4116 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4117 {
4118         uint32_t scratch_reg;
4119         int i;
4120
4121         if (rdev->family >= CHIP_R600)
4122                 scratch_reg = R600_BIOS_0_SCRATCH;
4123         else
4124                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4125
4126         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4127                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4128 }
4129
4130 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4131 {
4132         uint32_t scratch_reg;
4133         int i;
4134
4135         if (rdev->family >= CHIP_R600)
4136                 scratch_reg = R600_BIOS_0_SCRATCH;
4137         else
4138                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4139
4140         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4141                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4142 }
4143
4144 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4145 {
4146         struct drm_device *dev = encoder->dev;
4147         struct radeon_device *rdev = dev->dev_private;
4148         uint32_t bios_6_scratch;
4149
4150         if (rdev->family >= CHIP_R600)
4151                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4152         else
4153                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4154
4155         if (lock) {
4156                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4157                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4158         } else {
4159                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4160                 bios_6_scratch |= ATOM_S6_ACC_MODE;
4161         }
4162
4163         if (rdev->family >= CHIP_R600)
4164                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4165         else
4166                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4167 }
4168
4169 /* at some point we may want to break this out into individual functions */
4170 void
4171 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4172                                        struct drm_encoder *encoder,
4173                                        bool connected)
4174 {
4175         struct drm_device *dev = connector->dev;
4176         struct radeon_device *rdev = dev->dev_private;
4177         struct radeon_connector *radeon_connector =
4178             to_radeon_connector(connector);
4179         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4180         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4181
4182         if (rdev->family >= CHIP_R600) {
4183                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4184                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4185                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4186         } else {
4187                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4188                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4189                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4190         }
4191
4192         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4193             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4194                 if (connected) {
4195                         DRM_DEBUG_KMS("TV1 connected\n");
4196                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4197                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4198                 } else {
4199                         DRM_DEBUG_KMS("TV1 disconnected\n");
4200                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4201                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4202                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4203                 }
4204         }
4205         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4206             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4207                 if (connected) {
4208                         DRM_DEBUG_KMS("CV connected\n");
4209                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4210                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4211                 } else {
4212                         DRM_DEBUG_KMS("CV disconnected\n");
4213                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
4214                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4215                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4216                 }
4217         }
4218         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4219             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4220                 if (connected) {
4221                         DRM_DEBUG_KMS("LCD1 connected\n");
4222                         bios_0_scratch |= ATOM_S0_LCD1;
4223                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4224                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4225                 } else {
4226                         DRM_DEBUG_KMS("LCD1 disconnected\n");
4227                         bios_0_scratch &= ~ATOM_S0_LCD1;
4228                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4229                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4230                 }
4231         }
4232         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4233             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4234                 if (connected) {
4235                         DRM_DEBUG_KMS("CRT1 connected\n");
4236                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4237                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4238                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4239                 } else {
4240                         DRM_DEBUG_KMS("CRT1 disconnected\n");
4241                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4242                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4243                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4244                 }
4245         }
4246         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4247             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4248                 if (connected) {
4249                         DRM_DEBUG_KMS("CRT2 connected\n");
4250                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4251                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4252                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4253                 } else {
4254                         DRM_DEBUG_KMS("CRT2 disconnected\n");
4255                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4256                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4257                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4258                 }
4259         }
4260         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4261             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4262                 if (connected) {
4263                         DRM_DEBUG_KMS("DFP1 connected\n");
4264                         bios_0_scratch |= ATOM_S0_DFP1;
4265                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4266                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4267                 } else {
4268                         DRM_DEBUG_KMS("DFP1 disconnected\n");
4269                         bios_0_scratch &= ~ATOM_S0_DFP1;
4270                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4271                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4272                 }
4273         }
4274         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4275             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4276                 if (connected) {
4277                         DRM_DEBUG_KMS("DFP2 connected\n");
4278                         bios_0_scratch |= ATOM_S0_DFP2;
4279                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4280                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4281                 } else {
4282                         DRM_DEBUG_KMS("DFP2 disconnected\n");
4283                         bios_0_scratch &= ~ATOM_S0_DFP2;
4284                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4285                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4286                 }
4287         }
4288         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4289             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4290                 if (connected) {
4291                         DRM_DEBUG_KMS("DFP3 connected\n");
4292                         bios_0_scratch |= ATOM_S0_DFP3;
4293                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4294                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4295                 } else {
4296                         DRM_DEBUG_KMS("DFP3 disconnected\n");
4297                         bios_0_scratch &= ~ATOM_S0_DFP3;
4298                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4299                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4300                 }
4301         }
4302         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4303             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4304                 if (connected) {
4305                         DRM_DEBUG_KMS("DFP4 connected\n");
4306                         bios_0_scratch |= ATOM_S0_DFP4;
4307                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4308                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4309                 } else {
4310                         DRM_DEBUG_KMS("DFP4 disconnected\n");
4311                         bios_0_scratch &= ~ATOM_S0_DFP4;
4312                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4313                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4314                 }
4315         }
4316         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4317             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4318                 if (connected) {
4319                         DRM_DEBUG_KMS("DFP5 connected\n");
4320                         bios_0_scratch |= ATOM_S0_DFP5;
4321                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4322                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4323                 } else {
4324                         DRM_DEBUG_KMS("DFP5 disconnected\n");
4325                         bios_0_scratch &= ~ATOM_S0_DFP5;
4326                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4327                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4328                 }
4329         }
4330         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4331             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4332                 if (connected) {
4333                         DRM_DEBUG_KMS("DFP6 connected\n");
4334                         bios_0_scratch |= ATOM_S0_DFP6;
4335                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4336                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4337                 } else {
4338                         DRM_DEBUG_KMS("DFP6 disconnected\n");
4339                         bios_0_scratch &= ~ATOM_S0_DFP6;
4340                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4341                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4342                 }
4343         }
4344
4345         if (rdev->family >= CHIP_R600) {
4346                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4347                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4348                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4349         } else {
4350                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4351                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4352                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4353         }
4354 }
4355
4356 void
4357 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4358 {
4359         struct drm_device *dev = encoder->dev;
4360         struct radeon_device *rdev = dev->dev_private;
4361         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4362         uint32_t bios_3_scratch;
4363
4364         if (ASIC_IS_DCE4(rdev))
4365                 return;
4366
4367         if (rdev->family >= CHIP_R600)
4368                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4369         else
4370                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4371
4372         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4373                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4374                 bios_3_scratch |= (crtc << 18);
4375         }
4376         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4377                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4378                 bios_3_scratch |= (crtc << 24);
4379         }
4380         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4381                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4382                 bios_3_scratch |= (crtc << 16);
4383         }
4384         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4385                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4386                 bios_3_scratch |= (crtc << 20);
4387         }
4388         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4389                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4390                 bios_3_scratch |= (crtc << 17);
4391         }
4392         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4393                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4394                 bios_3_scratch |= (crtc << 19);
4395         }
4396         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4397                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4398                 bios_3_scratch |= (crtc << 23);
4399         }
4400         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4401                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4402                 bios_3_scratch |= (crtc << 25);
4403         }
4404
4405         if (rdev->family >= CHIP_R600)
4406                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4407         else
4408                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4409 }
4410
4411 void
4412 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4413 {
4414         struct drm_device *dev = encoder->dev;
4415         struct radeon_device *rdev = dev->dev_private;
4416         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4417         uint32_t bios_2_scratch;
4418
4419         if (ASIC_IS_DCE4(rdev))
4420                 return;
4421
4422         if (rdev->family >= CHIP_R600)
4423                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4424         else
4425                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4426
4427         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4428                 if (on)
4429                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4430                 else
4431                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4432         }
4433         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4434                 if (on)
4435                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4436                 else
4437                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4438         }
4439         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4440                 if (on)
4441                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4442                 else
4443                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4444         }
4445         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4446                 if (on)
4447                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4448                 else
4449                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4450         }
4451         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4452                 if (on)
4453                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4454                 else
4455                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4456         }
4457         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4458                 if (on)
4459                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4460                 else
4461                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4462         }
4463         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4464                 if (on)
4465                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4466                 else
4467                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4468         }
4469         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4470                 if (on)
4471                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4472                 else
4473                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4474         }
4475         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4476                 if (on)
4477                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4478                 else
4479                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4480         }
4481         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4482                 if (on)
4483                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4484                 else
4485                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4486         }
4487
4488         if (rdev->family >= CHIP_R600)
4489                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4490         else
4491                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4492 }