drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/pci.h>
  28
  29 #include <drm/drm_device.h>
  30 #include <drm/radeon_drm.h>
  31
  32 #include "radeon.h"
  33
  34 #include "atom.h"
  35 #include "atom-bits.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_atombios.h"
  38 #include "radeon_legacy_encoders.h"
  39
  40 union atom_supported_devices {
  41         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  42         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  43         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  44 };
  45
  46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  47                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  48                                           u8 index)
  49 {
  50         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  51         if ((rdev->family == CHIP_R420) ||
  52             (rdev->family == CHIP_R423) ||
  53             (rdev->family == CHIP_RV410)) {
  54                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  55                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  56                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  57                         gpio->ucClkMaskShift = 0x19;
  58                         gpio->ucDataMaskShift = 0x18;
  59                 }
  60         }
  61
  62         /* some evergreen boards have bad data for this entry */
  63         if (ASIC_IS_DCE4(rdev)) {
  64                 if ((index == 7) &&
  65                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  66                     (gpio->sucI2cId.ucAccess == 0)) {
  67                         gpio->sucI2cId.ucAccess = 0x97;
  68                         gpio->ucDataMaskShift = 8;
  69                         gpio->ucDataEnShift = 8;
  70                         gpio->ucDataY_Shift = 8;
  71                         gpio->ucDataA_Shift = 8;
  72                 }
  73         }
  74
  75         /* some DCE3 boards have bad data for this entry */
  76         if (ASIC_IS_DCE3(rdev)) {
  77                 if ((index == 4) &&
  78                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  79                     (gpio->sucI2cId.ucAccess == 0x94))
  80                         gpio->sucI2cId.ucAccess = 0x14;
  81         }
  82 }
  83
  84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  85 {
  86         struct radeon_i2c_bus_rec i2c;
  87
  88         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  89
  90         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  91         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  92         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  93         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  94         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  95         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  96         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  97         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  98         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  99         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 100         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 101         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 102         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 103         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 104         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 105         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 106
 107         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 108                 i2c.hw_capable = true;
 109         else
 110                 i2c.hw_capable = false;
 111
 112         if (gpio->sucI2cId.ucAccess == 0xa0)
 113                 i2c.mm_i2c = true;
 114         else
 115                 i2c.mm_i2c = false;
 116
 117         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 118
 119         if (i2c.mask_clk_reg)
 120                 i2c.valid = true;
 121         else
 122                 i2c.valid = false;
 123
 124         return i2c;
 125 }
 126
 127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 128                                                                uint8_t id)
 129 {
 130         struct atom_context *ctx = rdev->mode_info.atom_context;
 131         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 132         struct radeon_i2c_bus_rec i2c;
 133         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 134         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 135         uint16_t data_offset, size;
 136         int i, num_indices;
 137
 138         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 139         i2c.valid = false;
 140
 141         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 142                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 143
 144                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 145                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 146
 147                 gpio = &i2c_info->asGPIO_Info[0];
 148                 for (i = 0; i < num_indices; i++) {
 149
 150                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 151
 152                         if (gpio->sucI2cId.ucAccess == id) {
 153                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 154                                 break;
 155                         }
 156                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 157                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 158                 }
 159         }
 160
 161         return i2c;
 162 }
 163
 164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 165 {
 166         struct atom_context *ctx = rdev->mode_info.atom_context;
 167         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 168         struct radeon_i2c_bus_rec i2c;
 169         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 170         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 171         uint16_t data_offset, size;
 172         int i, num_indices;
 173         char stmp[32];
 174
 175         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 176                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 177
 178                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 179                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 180
 181                 gpio = &i2c_info->asGPIO_Info[0];
 182                 for (i = 0; i < num_indices; i++) {
 183                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 184
 185                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 186
 187                         if (i2c.valid) {
 188                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 189                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 190                         }
 191                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 192                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 193                 }
 194         }
 195 }
 196
 197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
 198                                                    u8 id)
 199 {
 200         struct atom_context *ctx = rdev->mode_info.atom_context;
 201         struct radeon_gpio_rec gpio;
 202         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 203         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 204         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 205         u16 data_offset, size;
 206         int i, num_indices;
 207
 208         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 209         gpio.valid = false;
 210
 211         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 212                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 213
 214                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 215                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 216
 217                 pin = gpio_info->asGPIO_Pin;
 218                 for (i = 0; i < num_indices; i++) {
 219                         if (id == pin->ucGPIO_ID) {
 220                                 gpio.id = pin->ucGPIO_ID;
 221                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 222                                 gpio.shift = pin->ucGpioPinBitShift;
 223                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 224                                 gpio.valid = true;
 225                                 break;
 226                         }
 227                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 228                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 229                 }
 230         }
 231
 232         return gpio;
 233 }
 234
 235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 236                                                             struct radeon_gpio_rec *gpio)
 237 {
 238         struct radeon_hpd hpd;
 239         u32 reg;
 240
 241         memset(&hpd, 0, sizeof(struct radeon_hpd));
 242
 243         if (ASIC_IS_DCE6(rdev))
 244                 reg = SI_DC_GPIO_HPD_A;
 245         else if (ASIC_IS_DCE4(rdev))
 246                 reg = EVERGREEN_DC_GPIO_HPD_A;
 247         else
 248                 reg = AVIVO_DC_GPIO_HPD_A;
 249
 250         hpd.gpio = *gpio;
 251         if (gpio->reg == reg) {
 252                 switch(gpio->mask) {
 253                 case (1 << 0):
 254                         hpd.hpd = RADEON_HPD_1;
 255                         break;
 256                 case (1 << 8):
 257                         hpd.hpd = RADEON_HPD_2;
 258                         break;
 259                 case (1 << 16):
 260                         hpd.hpd = RADEON_HPD_3;
 261                         break;
 262                 case (1 << 24):
 263                         hpd.hpd = RADEON_HPD_4;
 264                         break;
 265                 case (1 << 26):
 266                         hpd.hpd = RADEON_HPD_5;
 267                         break;
 268                 case (1 << 28):
 269                         hpd.hpd = RADEON_HPD_6;
 270                         break;
 271                 default:
 272                         hpd.hpd = RADEON_HPD_NONE;
 273                         break;
 274                 }
 275         } else
 276                 hpd.hpd = RADEON_HPD_NONE;
 277         return hpd;
 278 }
 279
 280 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 281                                      uint32_t supported_device,
 282                                      int *connector_type,
 283                                      struct radeon_i2c_bus_rec *i2c_bus,
 284                                      uint16_t *line_mux,
 285                                      struct radeon_hpd *hpd)
 286 {
 287         struct pci_dev *pdev = to_pci_dev(dev->dev);
 288
 289         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 290         if ((pdev->device == 0x791e) &&
 291             (pdev->subsystem_vendor == 0x1043) &&
 292             (pdev->subsystem_device == 0x826d)) {
 293                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 294                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 295                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 296         }
 297
 298         /* Asrock RS600 board lists the DVI port as HDMI */
 299         if ((pdev->device == 0x7941) &&
 300             (pdev->subsystem_vendor == 0x1849) &&
 301             (pdev->subsystem_device == 0x7941)) {
 302                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 303                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 304                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 305         }
 306
 307         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 308         if ((pdev->device == 0x796e) &&
 309             (pdev->subsystem_vendor == 0x1462) &&
 310             (pdev->subsystem_device == 0x7302)) {
 311                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 312                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 313                         return false;
 314         }
 315
 316         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 317         if ((pdev->device == 0x7941) &&
 318             (pdev->subsystem_vendor == 0x147b) &&
 319             (pdev->subsystem_device == 0x2412)) {
 320                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 321                         return false;
 322         }
 323
 324         /* Falcon NW laptop lists vga ddc line for LVDS */
 325         if ((pdev->device == 0x5653) &&
 326             (pdev->subsystem_vendor == 0x1462) &&
 327             (pdev->subsystem_device == 0x0291)) {
 328                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 329                         i2c_bus->valid = false;
 330                         *line_mux = 53;
 331                 }
 332         }
 333
 334         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 335         if ((pdev->device == 0x7146) &&
 336             (pdev->subsystem_vendor == 0x17af) &&
 337             (pdev->subsystem_device == 0x2058)) {
 338                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 339                         return false;
 340         }
 341
 342         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 343         if ((pdev->device == 0x7142) &&
 344             (pdev->subsystem_vendor == 0x1458) &&
 345             (pdev->subsystem_device == 0x2134)) {
 346                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 347                         return false;
 348         }
 349
 350
 351         /* Funky macbooks */
 352         if ((pdev->device == 0x71C5) &&
 353             (pdev->subsystem_vendor == 0x106b) &&
 354             (pdev->subsystem_device == 0x0080)) {
 355                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 356                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 357                         return false;
 358                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 359                         *line_mux = 0x90;
 360         }
 361
 362         /* mac rv630, rv730, others */
 363         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 364             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 365                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 366                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 367         }
 368
 369         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 370         if ((pdev->device == 0x9598) &&
 371             (pdev->subsystem_vendor == 0x1043) &&
 372             (pdev->subsystem_device == 0x01da)) {
 373                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 374                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 375                 }
 376         }
 377
 378         /* ASUS HD 3600 board lists the DVI port as HDMI */
 379         if ((pdev->device == 0x9598) &&
 380             (pdev->subsystem_vendor == 0x1043) &&
 381             (pdev->subsystem_device == 0x01e4)) {
 382                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 383                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 384                 }
 385         }
 386
 387         /* ASUS HD 3450 board lists the DVI port as HDMI */
 388         if ((pdev->device == 0x95C5) &&
 389             (pdev->subsystem_vendor == 0x1043) &&
 390             (pdev->subsystem_device == 0x01e2)) {
 391                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 392                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 393                 }
 394         }
 395
 396         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 397          * HDMI + VGA reporting as HDMI
 398          */
 399         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 400                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 401                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 402                         *line_mux = 0;
 403                 }
 404         }
 405
 406         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 407          * on the laptop and a DVI port on the docking station and
 408          * both share the same encoder, hpd pin, and ddc line.
 409          * So while the bios table is technically correct,
 410          * we drop the DVI port here since xrandr has no concept of
 411          * encoders and will try and drive both connectors
 412          * with different crtcs which isn't possible on the hardware
 413          * side and leaves no crtcs for LVDS or VGA.
 414          */
 415         if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
 416             (pdev->subsystem_vendor == 0x1025) &&
 417             (pdev->subsystem_device == 0x013c)) {
 418                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 419                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 420                         /* actually it's a DVI-D port not DVI-I */
 421                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 422                         return false;
 423                 }
 424         }
 425
 426         /* XFX Pine Group device rv730 reports no VGA DDC lines
 427          * even though they are wired up to record 0x93
 428          */
 429         if ((pdev->device == 0x9498) &&
 430             (pdev->subsystem_vendor == 0x1682) &&
 431             (pdev->subsystem_device == 0x2452) &&
 432             (i2c_bus->valid == false) &&
 433             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 434                 struct radeon_device *rdev = dev->dev_private;
 435                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 436         }
 437
 438         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 439         if (((pdev->device == 0x9802) ||
 440              (pdev->device == 0x9805) ||
 441              (pdev->device == 0x9806)) &&
 442             (pdev->subsystem_vendor == 0x1734) &&
 443             (pdev->subsystem_device == 0x11bd)) {
 444                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 445                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 446                         *line_mux = 0x3103;
 447                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 448                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 449                 }
 450         }
 451
 452         return true;
 453 }
 454
 455 static const int supported_devices_connector_convert[] = {
 456         DRM_MODE_CONNECTOR_Unknown,
 457         DRM_MODE_CONNECTOR_VGA,
 458         DRM_MODE_CONNECTOR_DVII,
 459         DRM_MODE_CONNECTOR_DVID,
 460         DRM_MODE_CONNECTOR_DVIA,
 461         DRM_MODE_CONNECTOR_SVIDEO,
 462         DRM_MODE_CONNECTOR_Composite,
 463         DRM_MODE_CONNECTOR_LVDS,
 464         DRM_MODE_CONNECTOR_Unknown,
 465         DRM_MODE_CONNECTOR_Unknown,
 466         DRM_MODE_CONNECTOR_HDMIA,
 467         DRM_MODE_CONNECTOR_HDMIB,
 468         DRM_MODE_CONNECTOR_Unknown,
 469         DRM_MODE_CONNECTOR_Unknown,
 470         DRM_MODE_CONNECTOR_9PinDIN,
 471         DRM_MODE_CONNECTOR_DisplayPort
 472 };
 473
 474 static const uint16_t supported_devices_connector_object_id_convert[] = {
 475         CONNECTOR_OBJECT_ID_NONE,
 476         CONNECTOR_OBJECT_ID_VGA,
 477         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 478         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 479         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 480         CONNECTOR_OBJECT_ID_COMPOSITE,
 481         CONNECTOR_OBJECT_ID_SVIDEO,
 482         CONNECTOR_OBJECT_ID_LVDS,
 483         CONNECTOR_OBJECT_ID_9PIN_DIN,
 484         CONNECTOR_OBJECT_ID_9PIN_DIN,
 485         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 486         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 487         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 488         CONNECTOR_OBJECT_ID_SVIDEO
 489 };
 490
 491 static const int object_connector_convert[] = {
 492         DRM_MODE_CONNECTOR_Unknown,
 493         DRM_MODE_CONNECTOR_DVII,
 494         DRM_MODE_CONNECTOR_DVII,
 495         DRM_MODE_CONNECTOR_DVID,
 496         DRM_MODE_CONNECTOR_DVID,
 497         DRM_MODE_CONNECTOR_VGA,
 498         DRM_MODE_CONNECTOR_Composite,
 499         DRM_MODE_CONNECTOR_SVIDEO,
 500         DRM_MODE_CONNECTOR_Unknown,
 501         DRM_MODE_CONNECTOR_Unknown,
 502         DRM_MODE_CONNECTOR_9PinDIN,
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_HDMIA,
 505         DRM_MODE_CONNECTOR_HDMIB,
 506         DRM_MODE_CONNECTOR_LVDS,
 507         DRM_MODE_CONNECTOR_9PinDIN,
 508         DRM_MODE_CONNECTOR_Unknown,
 509         DRM_MODE_CONNECTOR_Unknown,
 510         DRM_MODE_CONNECTOR_Unknown,
 511         DRM_MODE_CONNECTOR_DisplayPort,
 512         DRM_MODE_CONNECTOR_eDP,
 513         DRM_MODE_CONNECTOR_Unknown
 514 };
 515
 516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 517 {
 518         struct radeon_device *rdev = dev->dev_private;
 519         struct radeon_mode_info *mode_info = &rdev->mode_info;
 520         struct atom_context *ctx = mode_info->atom_context;
 521         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 522         u16 size, data_offset;
 523         u8 frev, crev;
 524         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 525         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 526         ATOM_OBJECT_TABLE *router_obj;
 527         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 528         ATOM_OBJECT_HEADER *obj_header;
 529         int i, j, k, path_size, device_support;
 530         int connector_type;
 531         u16 igp_lane_info, conn_id, connector_object_id;
 532         struct radeon_i2c_bus_rec ddc_bus;
 533         struct radeon_router router;
 534         struct radeon_gpio_rec gpio;
 535         struct radeon_hpd hpd;
 536
 537         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 538                 return false;
 539
 540         if (crev < 2)
 541                 return false;
 542
 543         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 544         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 545             (ctx->bios + data_offset +
 546              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 547         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 548             (ctx->bios + data_offset +
 549              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 550         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 551             (ctx->bios + data_offset +
 552              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 553         router_obj = (ATOM_OBJECT_TABLE *)
 554                 (ctx->bios + data_offset +
 555                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 556         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 557
 558         path_size = 0;
 559         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 560                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 561                 ATOM_DISPLAY_OBJECT_PATH *path;
 562                 addr += path_size;
 563                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 564                 path_size += le16_to_cpu(path->usSize);
 565
 566                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 567                         uint8_t con_obj_id, con_obj_num;
 568
 569                         con_obj_id =
 570                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 571                             >> OBJECT_ID_SHIFT;
 572                         con_obj_num =
 573                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 574                             >> ENUM_ID_SHIFT;
 575
 576                         /* TODO CV support */
 577                         if (le16_to_cpu(path->usDeviceTag) ==
 578                                 ATOM_DEVICE_CV_SUPPORT)
 579                                 continue;
 580
 581                         /* IGP chips */
 582                         if ((rdev->flags & RADEON_IS_IGP) &&
 583                             (con_obj_id ==
 584                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 585                                 uint16_t igp_offset = 0;
 586                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 587
 588                                 index =
 589                                     GetIndexIntoMasterTable(DATA,
 590                                                             IntegratedSystemInfo);
 591
 592                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 593                                                            &crev, &igp_offset)) {
 594
 595                                         if (crev >= 2) {
 596                                                 igp_obj =
 597                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 598                                                          *) (ctx->bios + igp_offset);
 599
 600                                                 if (igp_obj) {
 601                                                         uint32_t slot_config, ct;
 602
 603                                                         if (con_obj_num == 1)
 604                                                                 slot_config =
 605                                                                         igp_obj->
 606                                                                         ulDDISlot1Config;
 607                                                         else
 608                                                                 slot_config =
 609                                                                         igp_obj->
 610                                                                         ulDDISlot2Config;
 611
 612                                                         ct = (slot_config >> 16) & 0xff;
 613                                                         connector_type =
 614                                                                 object_connector_convert
 615                                                                 [ct];
 616                                                         connector_object_id = ct;
 617                                                         igp_lane_info =
 618                                                                 slot_config & 0xffff;
 619                                                 } else
 620                                                         continue;
 621                                         } else
 622                                                 continue;
 623                                 } else {
 624                                         igp_lane_info = 0;
 625                                         connector_type =
 626                                                 object_connector_convert[con_obj_id];
 627                                         connector_object_id = con_obj_id;
 628                                 }
 629                         } else {
 630                                 igp_lane_info = 0;
 631                                 connector_type =
 632                                     object_connector_convert[con_obj_id];
 633                                 connector_object_id = con_obj_id;
 634                         }
 635
 636                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 637                                 continue;
 638
 639                         router.ddc_valid = false;
 640                         router.cd_valid = false;
 641                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 642                                 uint8_t grph_obj_type =
 643                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 644                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 645
 646                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 647                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 648                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 649                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 650                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 651                                                                 (ctx->bios + data_offset +
 652                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 653                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 654                                                         u16 caps = 0;
 655
 656                                                         while (record->ucRecordSize > 0 &&
 657                                                                record->ucRecordType > 0 &&
 658                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 659                                                                 switch (record->ucRecordType) {
 660                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 661                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 662                                                                                 record;
 663                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 664                                                                         break;
 665                                                                 }
 666                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 667                                                                         ((char *)record + record->ucRecordSize);
 668                                                         }
 669                                                         radeon_add_atom_encoder(dev,
 670                                                                                 encoder_obj,
 671                                                                                 le16_to_cpu
 672                                                                                 (path->
 673                                                                                  usDeviceTag),
 674                                                                                 caps);
 675                                                 }
 676                                         }
 677                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 678                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 679                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 680                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 681                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 682                                                                 (ctx->bios + data_offset +
 683                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 684                                                         ATOM_I2C_RECORD *i2c_record;
 685                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 686                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 687                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 688                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 689                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 690                                                                 (ctx->bios + data_offset +
 691                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 692                                                         u8 *num_dst_objs = (u8 *)
 693                                                                 ((u8 *)router_src_dst_table + 1 +
 694                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 695                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 696                                                         int enum_id;
 697
 698                                                         router.router_id = router_obj_id;
 699                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 700                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 701                                                                     le16_to_cpu(dst_objs[enum_id]))
 702                                                                         break;
 703                                                         }
 704
 705                                                         while (record->ucRecordSize > 0 &&
 706                                                                record->ucRecordType > 0 &&
 707                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 708                                                                 switch (record->ucRecordType) {
 709                                                                 case ATOM_I2C_RECORD_TYPE:
 710                                                                         i2c_record =
 711                                                                                 (ATOM_I2C_RECORD *)
 712                                                                                 record;
 713                                                                         i2c_config =
 714                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 715                                                                                 &i2c_record->sucI2cId;
 716                                                                         router.i2c_info =
 717                                                                                 radeon_lookup_i2c_gpio(rdev,
 718                                                                                                        i2c_config->
 719                                                                                                        ucAccess);
 720                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 721                                                                         break;
 722                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 723                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 724                                                                                 record;
 725                                                                         router.ddc_valid = true;
 726                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 727                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 728                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 729                                                                         break;
 730                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 731                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 732                                                                                 record;
 733                                                                         router.cd_valid = true;
 734                                                                         router.cd_mux_type = cd_path->ucMuxType;
 735                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 736                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 737                                                                         break;
 738                                                                 }
 739                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 740                                                                         ((char *)record + record->ucRecordSize);
 741                                                         }
 742                                                 }
 743                                         }
 744                                 }
 745                         }
 746
 747                         /* look up gpio for ddc, hpd */
 748                         ddc_bus.valid = false;
 749                         hpd.hpd = RADEON_HPD_NONE;
 750                         if ((le16_to_cpu(path->usDeviceTag) &
 751                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 752                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 753                                         if (le16_to_cpu(path->usConnObjectId) ==
 754                                             le16_to_cpu(con_obj->asObjects[j].
 755                                                         usObjectID)) {
 756                                                 ATOM_COMMON_RECORD_HEADER
 757                                                     *record =
 758                                                     (ATOM_COMMON_RECORD_HEADER
 759                                                      *)
 760                                                     (ctx->bios + data_offset +
 761                                                      le16_to_cpu(con_obj->
 762                                                                  asObjects[j].
 763                                                                  usRecordOffset));
 764                                                 ATOM_I2C_RECORD *i2c_record;
 765                                                 ATOM_HPD_INT_RECORD *hpd_record;
 766                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 767
 768                                                 while (record->ucRecordSize > 0 &&
 769                                                        record->ucRecordType > 0 &&
 770                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 771                                                         switch (record->ucRecordType) {
 772                                                         case ATOM_I2C_RECORD_TYPE:
 773                                                                 i2c_record =
 774                                                                     (ATOM_I2C_RECORD *)
 775                                                                         record;
 776                                                                 i2c_config =
 777                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 778                                                                         &i2c_record->sucI2cId;
 779                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 780                                                                                                  i2c_config->
 781                                                                                                  ucAccess);
 782                                                                 break;
 783                                                         case ATOM_HPD_INT_RECORD_TYPE:
 784                                                                 hpd_record =
 785                                                                         (ATOM_HPD_INT_RECORD *)
 786                                                                         record;
 787                                                                 gpio = radeon_atombios_lookup_gpio(rdev,
 788                                                                                           hpd_record->ucHPDIntGPIOID);
 789                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 790                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 791                                                                 break;
 792                                                         }
 793                                                         record =
 794                                                             (ATOM_COMMON_RECORD_HEADER
 795                                                              *) ((char *)record
 796                                                                  +
 797                                                                  record->
 798                                                                  ucRecordSize);
 799                                                 }
 800                                                 break;
 801                                         }
 802                                 }
 803                         }
 804
 805                         /* needed for aux chan transactions */
 806                         ddc_bus.hpd = hpd.hpd;
 807
 808                         conn_id = le16_to_cpu(path->usConnObjectId);
 809
 810                         if (!radeon_atom_apply_quirks
 811                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 812                              &ddc_bus, &conn_id, &hpd))
 813                                 continue;
 814
 815                         radeon_add_atom_connector(dev,
 816                                                   conn_id,
 817                                                   le16_to_cpu(path->
 818                                                               usDeviceTag),
 819                                                   connector_type, &ddc_bus,
 820                                                   igp_lane_info,
 821                                                   connector_object_id,
 822                                                   &hpd,
 823                                                   &router);
 824
 825                 }
 826         }
 827
 828         radeon_link_encoder_connector(dev);
 829
 830         radeon_setup_mst_connector(dev);
 831         return true;
 832 }
 833
 834 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 835                                                  int connector_type,
 836                                                  uint16_t devices)
 837 {
 838         struct radeon_device *rdev = dev->dev_private;
 839
 840         if (rdev->flags & RADEON_IS_IGP) {
 841                 return supported_devices_connector_object_id_convert
 842                         [connector_type];
 843         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 844                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 845                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 846                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 847                 struct atom_context *ctx = mode_info->atom_context;
 848                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 849                 uint16_t size, data_offset;
 850                 uint8_t frev, crev;
 851                 ATOM_XTMDS_INFO *xtmds;
 852
 853                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 854                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 855
 856                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 857                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 858                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 859                                 else
 860                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 861                         } else {
 862                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 863                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 864                                 else
 865                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 866                         }
 867                 } else
 868                         return supported_devices_connector_object_id_convert
 869                                 [connector_type];
 870         } else {
 871                 return supported_devices_connector_object_id_convert
 872                         [connector_type];
 873         }
 874 }
 875
 876 struct bios_connector {
 877         bool valid;
 878         uint16_t line_mux;
 879         uint16_t devices;
 880         int connector_type;
 881         struct radeon_i2c_bus_rec ddc_bus;
 882         struct radeon_hpd hpd;
 883 };
 884
 885 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 886                                                                  drm_device
 887                                                                  *dev)
 888 {
 889         struct radeon_device *rdev = dev->dev_private;
 890         struct radeon_mode_info *mode_info = &rdev->mode_info;
 891         struct atom_context *ctx = mode_info->atom_context;
 892         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 893         uint16_t size, data_offset;
 894         uint8_t frev, crev;
 895         uint16_t device_support;
 896         uint8_t dac;
 897         union atom_supported_devices *supported_devices;
 898         int i, j, max_device;
 899         struct bios_connector *bios_connectors;
 900         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 901         struct radeon_router router;
 902
 903         router.ddc_valid = false;
 904         router.cd_valid = false;
 905
 906         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 907         if (!bios_connectors)
 908                 return false;
 909
 910         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 911                                     &data_offset)) {
 912                 kfree(bios_connectors);
 913                 return false;
 914         }
 915
 916         supported_devices =
 917             (union atom_supported_devices *)(ctx->bios + data_offset);
 918
 919         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 920
 921         if (frev > 1)
 922                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 923         else
 924                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 925
 926         for (i = 0; i < max_device; i++) {
 927                 ATOM_CONNECTOR_INFO_I2C ci =
 928                     supported_devices->info.asConnInfo[i];
 929
 930                 bios_connectors[i].valid = false;
 931
 932                 if (!(device_support & (1 << i))) {
 933                         continue;
 934                 }
 935
 936                 if (i == ATOM_DEVICE_CV_INDEX) {
 937                         DRM_DEBUG_KMS("Skipping Component Video\n");
 938                         continue;
 939                 }
 940
 941                 bios_connectors[i].connector_type =
 942                     supported_devices_connector_convert[ci.sucConnectorInfo.
 943                                                         sbfAccess.
 944                                                         bfConnectorType];
 945
 946                 if (bios_connectors[i].connector_type ==
 947                     DRM_MODE_CONNECTOR_Unknown)
 948                         continue;
 949
 950                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 951
 952                 bios_connectors[i].line_mux =
 953                         ci.sucI2cId.ucAccess;
 954
 955                 /* give tv unique connector ids */
 956                 if (i == ATOM_DEVICE_TV1_INDEX) {
 957                         bios_connectors[i].ddc_bus.valid = false;
 958                         bios_connectors[i].line_mux = 50;
 959                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 960                         bios_connectors[i].ddc_bus.valid = false;
 961                         bios_connectors[i].line_mux = 51;
 962                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 963                         bios_connectors[i].ddc_bus.valid = false;
 964                         bios_connectors[i].line_mux = 52;
 965                 } else
 966                         bios_connectors[i].ddc_bus =
 967                             radeon_lookup_i2c_gpio(rdev,
 968                                                    bios_connectors[i].line_mux);
 969
 970                 if ((crev > 1) && (frev > 1)) {
 971                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 972                         switch (isb) {
 973                         case 0x4:
 974                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 975                                 break;
 976                         case 0xa:
 977                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 978                                 break;
 979                         default:
 980                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 981                                 break;
 982                         }
 983                 } else {
 984                         if (i == ATOM_DEVICE_DFP1_INDEX)
 985                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 986                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 987                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 988                         else
 989                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 990                 }
 991
 992                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 993                  * shared with a DVI port, we'll pick up the DVI connector when we
 994                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 995                  */
 996                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 997                         bios_connectors[i].connector_type =
 998                             DRM_MODE_CONNECTOR_VGA;
 999
1000                 if (!radeon_atom_apply_quirks
1001                     (dev, (1 << i), &bios_connectors[i].connector_type,
1002                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1003                      &bios_connectors[i].hpd))
1004                         continue;
1005
1006                 bios_connectors[i].valid = true;
1007                 bios_connectors[i].devices = (1 << i);
1008
1009                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1010                         radeon_add_atom_encoder(dev,
1011                                                 radeon_get_encoder_enum(dev,
1012                                                                       (1 << i),
1013                                                                       dac),
1014                                                 (1 << i),
1015                                                 0);
1016                 else
1017                         radeon_add_legacy_encoder(dev,
1018                                                   radeon_get_encoder_enum(dev,
1019                                                                         (1 << i),
1020                                                                         dac),
1021                                                   (1 << i));
1022         }
1023
1024         /* combine shared connectors */
1025         for (i = 0; i < max_device; i++) {
1026                 if (bios_connectors[i].valid) {
1027                         for (j = 0; j < max_device; j++) {
1028                                 if (bios_connectors[j].valid && (i != j)) {
1029                                         if (bios_connectors[i].line_mux ==
1030                                             bios_connectors[j].line_mux) {
1031                                                 /* make sure not to combine LVDS */
1032                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1033                                                         bios_connectors[i].line_mux = 53;
1034                                                         bios_connectors[i].ddc_bus.valid = false;
1035                                                         continue;
1036                                                 }
1037                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1038                                                         bios_connectors[j].line_mux = 53;
1039                                                         bios_connectors[j].ddc_bus.valid = false;
1040                                                         continue;
1041                                                 }
1042                                                 /* combine analog and digital for DVI-I */
1043                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1044                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1045                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1046                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1047                                                         bios_connectors[i].devices |=
1048                                                                 bios_connectors[j].devices;
1049                                                         bios_connectors[i].connector_type =
1050                                                                 DRM_MODE_CONNECTOR_DVII;
1051                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1052                                                                 bios_connectors[i].hpd =
1053                                                                         bios_connectors[j].hpd;
1054                                                         bios_connectors[j].valid = false;
1055                                                 }
1056                                         }
1057                                 }
1058                         }
1059                 }
1060         }
1061
1062         /* add the connectors */
1063         for (i = 0; i < max_device; i++) {
1064                 if (bios_connectors[i].valid) {
1065                         uint16_t connector_object_id =
1066                                 atombios_get_connector_object_id(dev,
1067                                                       bios_connectors[i].connector_type,
1068                                                       bios_connectors[i].devices);
1069                         radeon_add_atom_connector(dev,
1070                                                   bios_connectors[i].line_mux,
1071                                                   bios_connectors[i].devices,
1072                                                   bios_connectors[i].
1073                                                   connector_type,
1074                                                   &bios_connectors[i].ddc_bus,
1075                                                   0,
1076                                                   connector_object_id,
1077                                                   &bios_connectors[i].hpd,
1078                                                   &router);
1079                 }
1080         }
1081
1082         radeon_link_encoder_connector(dev);
1083
1084         kfree(bios_connectors);
1085         return true;
1086 }
1087
1088 union firmware_info {
1089         ATOM_FIRMWARE_INFO info;
1090         ATOM_FIRMWARE_INFO_V1_2 info_12;
1091         ATOM_FIRMWARE_INFO_V1_3 info_13;
1092         ATOM_FIRMWARE_INFO_V1_4 info_14;
1093         ATOM_FIRMWARE_INFO_V2_1 info_21;
1094         ATOM_FIRMWARE_INFO_V2_2 info_22;
1095 };
1096
1097 union igp_info {
1098         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1099         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1100         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1101         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1102         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1103 };
1104
1105 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1106 {
1107         struct radeon_mode_info *mode_info = &rdev->mode_info;
1108         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1109         union igp_info *igp_info;
1110         u8 frev, crev;
1111         u16 data_offset;
1112
1113         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1114                         &frev, &crev, &data_offset)) {
1115                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1116                         data_offset);
1117                 rdev->clock.vco_freq =
1118                         le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1119         }
1120 }
1121
1122 bool radeon_atom_get_clock_info(struct drm_device *dev)
1123 {
1124         struct radeon_device *rdev = dev->dev_private;
1125         struct radeon_mode_info *mode_info = &rdev->mode_info;
1126         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1127         union firmware_info *firmware_info;
1128         uint8_t frev, crev;
1129         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1130         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1131         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1132         struct radeon_pll *spll = &rdev->clock.spll;
1133         struct radeon_pll *mpll = &rdev->clock.mpll;
1134         uint16_t data_offset;
1135
1136         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1137                                    &frev, &crev, &data_offset)) {
1138                 firmware_info =
1139                         (union firmware_info *)(mode_info->atom_context->bios +
1140                                                 data_offset);
1141                 /* pixel clocks */
1142                 p1pll->reference_freq =
1143                     le16_to_cpu(firmware_info->info.usReferenceClock);
1144                 p1pll->reference_div = 0;
1145
1146                 if ((frev < 2) && (crev < 2))
1147                         p1pll->pll_out_min =
1148                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1149                 else
1150                         p1pll->pll_out_min =
1151                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1152                 p1pll->pll_out_max =
1153                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1154
1155                 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1156                         p1pll->lcd_pll_out_min =
1157                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1158                         if (p1pll->lcd_pll_out_min == 0)
1159                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1160                         p1pll->lcd_pll_out_max =
1161                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1162                         if (p1pll->lcd_pll_out_max == 0)
1163                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1164                 } else {
1165                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1166                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167                 }
1168
1169                 if (p1pll->pll_out_min == 0) {
1170                         if (ASIC_IS_AVIVO(rdev))
1171                                 p1pll->pll_out_min = 64800;
1172                         else
1173                                 p1pll->pll_out_min = 20000;
1174                 }
1175
1176                 p1pll->pll_in_min =
1177                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1178                 p1pll->pll_in_max =
1179                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1180
1181                 *p2pll = *p1pll;
1182
1183                 /* system clock */
1184                 if (ASIC_IS_DCE4(rdev))
1185                         spll->reference_freq =
1186                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1187                 else
1188                         spll->reference_freq =
1189                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1190                 spll->reference_div = 0;
1191
1192                 spll->pll_out_min =
1193                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1194                 spll->pll_out_max =
1195                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1196
1197                 /* ??? */
1198                 if (spll->pll_out_min == 0) {
1199                         if (ASIC_IS_AVIVO(rdev))
1200                                 spll->pll_out_min = 64800;
1201                         else
1202                                 spll->pll_out_min = 20000;
1203                 }
1204
1205                 spll->pll_in_min =
1206                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1207                 spll->pll_in_max =
1208                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1209
1210                 /* memory clock */
1211                 if (ASIC_IS_DCE4(rdev))
1212                         mpll->reference_freq =
1213                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1214                 else
1215                         mpll->reference_freq =
1216                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1217                 mpll->reference_div = 0;
1218
1219                 mpll->pll_out_min =
1220                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1221                 mpll->pll_out_max =
1222                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1223
1224                 /* ??? */
1225                 if (mpll->pll_out_min == 0) {
1226                         if (ASIC_IS_AVIVO(rdev))
1227                                 mpll->pll_out_min = 64800;
1228                         else
1229                                 mpll->pll_out_min = 20000;
1230                 }
1231
1232                 mpll->pll_in_min =
1233                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1234                 mpll->pll_in_max =
1235                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1236
1237                 rdev->clock.default_sclk =
1238                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1239                 rdev->clock.default_mclk =
1240                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1241
1242                 if (ASIC_IS_DCE4(rdev)) {
1243                         rdev->clock.default_dispclk =
1244                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1245                         if (rdev->clock.default_dispclk == 0) {
1246                                 if (ASIC_IS_DCE6(rdev))
1247                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1248                                 else if (ASIC_IS_DCE5(rdev))
1249                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1250                                 else
1251                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1252                         }
1253                         /* set a reasonable default for DP */
1254                         if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1255                                 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1256                                          rdev->clock.default_dispclk / 100);
1257                                 rdev->clock.default_dispclk = 60000;
1258                         }
1259                         rdev->clock.dp_extclk =
1260                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1261                         rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1262                 }
1263                 *dcpll = *p1pll;
1264
1265                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1266                 if (rdev->clock.max_pixel_clock == 0)
1267                         rdev->clock.max_pixel_clock = 40000;
1268
1269                 /* not technically a clock, but... */
1270                 rdev->mode_info.firmware_flags =
1271                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1272
1273                 if (ASIC_IS_DCE8(rdev))
1274                         rdev->clock.vco_freq =
1275                                 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1276                 else if (ASIC_IS_DCE5(rdev))
1277                         rdev->clock.vco_freq = rdev->clock.current_dispclk;
1278                 else if (ASIC_IS_DCE41(rdev))
1279                         radeon_atombios_get_dentist_vco_freq(rdev);
1280                 else
1281                         rdev->clock.vco_freq = rdev->clock.current_dispclk;
1282
1283                 if (rdev->clock.vco_freq == 0)
1284                         rdev->clock.vco_freq = 360000;  /* 3.6 GHz */
1285
1286                 return true;
1287         }
1288
1289         return false;
1290 }
1291
1292 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1293 {
1294         struct radeon_mode_info *mode_info = &rdev->mode_info;
1295         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1296         union igp_info *igp_info;
1297         u8 frev, crev;
1298         u16 data_offset;
1299
1300         /* sideport is AMD only */
1301         if (rdev->family == CHIP_RS600)
1302                 return false;
1303
1304         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1305                                    &frev, &crev, &data_offset)) {
1306                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1307                                       data_offset);
1308                 switch (crev) {
1309                 case 1:
1310                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1311                                 return true;
1312                         break;
1313                 case 2:
1314                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1315                                 return true;
1316                         break;
1317                 default:
1318                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1319                         break;
1320                 }
1321         }
1322         return false;
1323 }
1324
1325 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1326                                    struct radeon_encoder_int_tmds *tmds)
1327 {
1328         struct drm_device *dev = encoder->base.dev;
1329         struct radeon_device *rdev = dev->dev_private;
1330         struct radeon_mode_info *mode_info = &rdev->mode_info;
1331         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1332         uint16_t data_offset;
1333         struct _ATOM_TMDS_INFO *tmds_info;
1334         uint8_t frev, crev;
1335         uint16_t maxfreq;
1336         int i;
1337
1338         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1339                                    &frev, &crev, &data_offset)) {
1340                 tmds_info =
1341                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1342                                                    data_offset);
1343
1344                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1345                 for (i = 0; i < 4; i++) {
1346                         tmds->tmds_pll[i].freq =
1347                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1348                         tmds->tmds_pll[i].value =
1349                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1350                         tmds->tmds_pll[i].value |=
1351                             (tmds_info->asMiscInfo[i].
1352                              ucPLL_VCO_Gain & 0x3f) << 6;
1353                         tmds->tmds_pll[i].value |=
1354                             (tmds_info->asMiscInfo[i].
1355                              ucPLL_DutyCycle & 0xf) << 12;
1356                         tmds->tmds_pll[i].value |=
1357                             (tmds_info->asMiscInfo[i].
1358                              ucPLL_VoltageSwing & 0xf) << 16;
1359
1360                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1361                                   tmds->tmds_pll[i].freq,
1362                                   tmds->tmds_pll[i].value);
1363
1364                         if (maxfreq == tmds->tmds_pll[i].freq) {
1365                                 tmds->tmds_pll[i].freq = 0xffffffff;
1366                                 break;
1367                         }
1368                 }
1369                 return true;
1370         }
1371         return false;
1372 }
1373
1374 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1375                                       struct radeon_atom_ss *ss,
1376                                       int id)
1377 {
1378         struct radeon_mode_info *mode_info = &rdev->mode_info;
1379         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1380         uint16_t data_offset, size;
1381         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1382         struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1383         uint8_t frev, crev;
1384         int i, num_indices;
1385
1386         memset(ss, 0, sizeof(struct radeon_atom_ss));
1387         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1388                                    &frev, &crev, &data_offset)) {
1389                 ss_info =
1390                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1391
1392                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1393                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1394                 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1395                         ((u8 *)&ss_info->asSS_Info[0]);
1396                 for (i = 0; i < num_indices; i++) {
1397                         if (ss_assign->ucSS_Id == id) {
1398                                 ss->percentage =
1399                                         le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1400                                 ss->type = ss_assign->ucSpreadSpectrumType;
1401                                 ss->step = ss_assign->ucSS_Step;
1402                                 ss->delay = ss_assign->ucSS_Delay;
1403                                 ss->range = ss_assign->ucSS_Range;
1404                                 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1405                                 return true;
1406                         }
1407                         ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1408                                 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1409                 }
1410         }
1411         return false;
1412 }
1413
1414 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1415                                                  struct radeon_atom_ss *ss,
1416                                                  int id)
1417 {
1418         struct radeon_mode_info *mode_info = &rdev->mode_info;
1419         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1420         u16 data_offset, size;
1421         union igp_info *igp_info;
1422         u8 frev, crev;
1423         u16 percentage = 0, rate = 0;
1424
1425         /* get any igp specific overrides */
1426         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1427                                    &frev, &crev, &data_offset)) {
1428                 igp_info = (union igp_info *)
1429                         (mode_info->atom_context->bios + data_offset);
1430                 switch (crev) {
1431                 case 6:
1432                         switch (id) {
1433                         case ASIC_INTERNAL_SS_ON_TMDS:
1434                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1435                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1436                                 break;
1437                         case ASIC_INTERNAL_SS_ON_HDMI:
1438                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1439                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1440                                 break;
1441                         case ASIC_INTERNAL_SS_ON_LVDS:
1442                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1443                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1444                                 break;
1445                         }
1446                         break;
1447                 case 7:
1448                         switch (id) {
1449                         case ASIC_INTERNAL_SS_ON_TMDS:
1450                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1451                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1452                                 break;
1453                         case ASIC_INTERNAL_SS_ON_HDMI:
1454                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1455                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1456                                 break;
1457                         case ASIC_INTERNAL_SS_ON_LVDS:
1458                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1459                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1460                                 break;
1461                         }
1462                         break;
1463                 case 8:
1464                         switch (id) {
1465                         case ASIC_INTERNAL_SS_ON_TMDS:
1466                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1467                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1468                                 break;
1469                         case ASIC_INTERNAL_SS_ON_HDMI:
1470                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1471                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1472                                 break;
1473                         case ASIC_INTERNAL_SS_ON_LVDS:
1474                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1475                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1476                                 break;
1477                         }
1478                         break;
1479                 default:
1480                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1481                         break;
1482                 }
1483                 if (percentage)
1484                         ss->percentage = percentage;
1485                 if (rate)
1486                         ss->rate = rate;
1487         }
1488 }
1489
1490 union asic_ss_info {
1491         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1492         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1493         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1494 };
1495
1496 union asic_ss_assignment {
1497         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1498         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1499         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1500 };
1501
1502 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1503                                       struct radeon_atom_ss *ss,
1504                                       int id, u32 clock)
1505 {
1506         struct radeon_mode_info *mode_info = &rdev->mode_info;
1507         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1508         uint16_t data_offset, size;
1509         union asic_ss_info *ss_info;
1510         union asic_ss_assignment *ss_assign;
1511         uint8_t frev, crev;
1512         int i, num_indices;
1513
1514         if (id == ASIC_INTERNAL_MEMORY_SS) {
1515                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1516                         return false;
1517         }
1518         if (id == ASIC_INTERNAL_ENGINE_SS) {
1519                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1520                         return false;
1521         }
1522
1523         memset(ss, 0, sizeof(struct radeon_atom_ss));
1524         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1525                                    &frev, &crev, &data_offset)) {
1526
1527                 ss_info =
1528                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1529
1530                 switch (frev) {
1531                 case 1:
1532                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1533                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1534
1535                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1536                         for (i = 0; i < num_indices; i++) {
1537                                 if ((ss_assign->v1.ucClockIndication == id) &&
1538                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1539                                         ss->percentage =
1540                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1541                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1542                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1543                                         ss->percentage_divider = 100;
1544                                         return true;
1545                                 }
1546                                 ss_assign = (union asic_ss_assignment *)
1547                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1548                         }
1549                         break;
1550                 case 2:
1551                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1552                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1553                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1554                         for (i = 0; i < num_indices; i++) {
1555                                 if ((ss_assign->v2.ucClockIndication == id) &&
1556                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1557                                         ss->percentage =
1558                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1559                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1560                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1561                                         ss->percentage_divider = 100;
1562                                         if ((crev == 2) &&
1563                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
1564                                              (id == ASIC_INTERNAL_MEMORY_SS)))
1565                                                 ss->rate /= 100;
1566                                         return true;
1567                                 }
1568                                 ss_assign = (union asic_ss_assignment *)
1569                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1570                         }
1571                         break;
1572                 case 3:
1573                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1574                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1575                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1576                         for (i = 0; i < num_indices; i++) {
1577                                 if ((ss_assign->v3.ucClockIndication == id) &&
1578                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1579                                         ss->percentage =
1580                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1581                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1582                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1583                                         if (ss_assign->v3.ucSpreadSpectrumMode &
1584                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1585                                                 ss->percentage_divider = 1000;
1586                                         else
1587                                                 ss->percentage_divider = 100;
1588                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1589                                             (id == ASIC_INTERNAL_MEMORY_SS))
1590                                                 ss->rate /= 100;
1591                                         if (rdev->flags & RADEON_IS_IGP)
1592                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1593                                         return true;
1594                                 }
1595                                 ss_assign = (union asic_ss_assignment *)
1596                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1597                         }
1598                         break;
1599                 default:
1600                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1601                         break;
1602                 }
1603
1604         }
1605         return false;
1606 }
1607
1608 union lvds_info {
1609         struct _ATOM_LVDS_INFO info;
1610         struct _ATOM_LVDS_INFO_V12 info_12;
1611 };
1612
1613 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1614                                                               radeon_encoder
1615                                                               *encoder)
1616 {
1617         struct drm_device *dev = encoder->base.dev;
1618         struct radeon_device *rdev = dev->dev_private;
1619         struct radeon_mode_info *mode_info = &rdev->mode_info;
1620         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1621         uint16_t data_offset, misc;
1622         union lvds_info *lvds_info;
1623         uint8_t frev, crev;
1624         struct radeon_encoder_atom_dig *lvds = NULL;
1625         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1626
1627         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1628                                    &frev, &crev, &data_offset)) {
1629                 lvds_info =
1630                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1631                 lvds =
1632                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1633
1634                 if (!lvds)
1635                         return NULL;
1636
1637                 lvds->native_mode.clock =
1638                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1639                 lvds->native_mode.hdisplay =
1640                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1641                 lvds->native_mode.vdisplay =
1642                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1643                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1644                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1645                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1646                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1647                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1648                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1649                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1650                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1651                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1652                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1653                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1654                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1655                 lvds->panel_pwr_delay =
1656                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1657                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1658
1659                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1660                 if (misc & ATOM_VSYNC_POLARITY)
1661                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1662                 if (misc & ATOM_HSYNC_POLARITY)
1663                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1664                 if (misc & ATOM_COMPOSITESYNC)
1665                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1666                 if (misc & ATOM_INTERLACE)
1667                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1668                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1669                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1670
1671                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1672                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1673
1674                 /* set crtc values */
1675                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1676
1677                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1678
1679                 encoder->native_mode = lvds->native_mode;
1680
1681                 if (encoder_enum == 2)
1682                         lvds->linkb = true;
1683                 else
1684                         lvds->linkb = false;
1685
1686                 /* parse the lcd record table */
1687                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1688                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1689                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1690                         bool bad_record = false;
1691                         u8 *record;
1692
1693                         if ((frev == 1) && (crev < 2))
1694                                 /* absolute */
1695                                 record = (u8 *)(mode_info->atom_context->bios +
1696                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1697                         else
1698                                 /* relative */
1699                                 record = (u8 *)(mode_info->atom_context->bios +
1700                                                 data_offset +
1701                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1702                         while (*record != ATOM_RECORD_END_TYPE) {
1703                                 switch (*record) {
1704                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1705                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1706                                         break;
1707                                 case LCD_RTS_RECORD_TYPE:
1708                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1709                                         break;
1710                                 case LCD_CAP_RECORD_TYPE:
1711                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1712                                         break;
1713                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1714                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1715                                         if (fake_edid_record->ucFakeEDIDLength) {
1716                                                 struct edid *edid;
1717                                                 int edid_size =
1718                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1719                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1720                                                 if (edid) {
1721                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1722                                                                fake_edid_record->ucFakeEDIDLength);
1723
1724                                                         if (drm_edid_is_valid(edid)) {
1725                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1726                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1727                                                         } else
1728                                                                 kfree(edid);
1729                                                 }
1730                                         }
1731                                         record += fake_edid_record->ucFakeEDIDLength ?
1732                                                 fake_edid_record->ucFakeEDIDLength + 2 :
1733                                                 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1734                                         break;
1735                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1736                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1737                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1738                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1739                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1740                                         break;
1741                                 default:
1742                                         DRM_ERROR("Bad LCD record %d\n", *record);
1743                                         bad_record = true;
1744                                         break;
1745                                 }
1746                                 if (bad_record)
1747                                         break;
1748                         }
1749                 }
1750         }
1751         return lvds;
1752 }
1753
1754 struct radeon_encoder_primary_dac *
1755 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1756 {
1757         struct drm_device *dev = encoder->base.dev;
1758         struct radeon_device *rdev = dev->dev_private;
1759         struct radeon_mode_info *mode_info = &rdev->mode_info;
1760         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1761         uint16_t data_offset;
1762         struct _COMPASSIONATE_DATA *dac_info;
1763         uint8_t frev, crev;
1764         uint8_t bg, dac;
1765         struct radeon_encoder_primary_dac *p_dac = NULL;
1766
1767         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1768                                    &frev, &crev, &data_offset)) {
1769                 dac_info = (struct _COMPASSIONATE_DATA *)
1770                         (mode_info->atom_context->bios + data_offset);
1771
1772                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1773
1774                 if (!p_dac)
1775                         return NULL;
1776
1777                 bg = dac_info->ucDAC1_BG_Adjustment;
1778                 dac = dac_info->ucDAC1_DAC_Adjustment;
1779                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1780
1781         }
1782         return p_dac;
1783 }
1784
1785 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1786                                 struct drm_display_mode *mode)
1787 {
1788         struct radeon_mode_info *mode_info = &rdev->mode_info;
1789         ATOM_ANALOG_TV_INFO *tv_info;
1790         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1791         ATOM_DTD_FORMAT *dtd_timings;
1792         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1793         u8 frev, crev;
1794         u16 data_offset, misc;
1795
1796         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1797                                     &frev, &crev, &data_offset))
1798                 return false;
1799
1800         switch (crev) {
1801         case 1:
1802                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1803                 if (index >= MAX_SUPPORTED_TV_TIMING)
1804                         return false;
1805
1806                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1807                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1808                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1809                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1810                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1811
1812                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1813                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1814                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1815                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1816                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1817
1818                 mode->flags = 0;
1819                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1820                 if (misc & ATOM_VSYNC_POLARITY)
1821                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1822                 if (misc & ATOM_HSYNC_POLARITY)
1823                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1824                 if (misc & ATOM_COMPOSITESYNC)
1825                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1826                 if (misc & ATOM_INTERLACE)
1827                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1828                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1829                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1830
1831                 mode->crtc_clock = mode->clock =
1832                         le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1833
1834                 if (index == 1) {
1835                         /* PAL timings appear to have wrong values for totals */
1836                         mode->crtc_htotal -= 1;
1837                         mode->crtc_vtotal -= 1;
1838                 }
1839                 break;
1840         case 2:
1841                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1842                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1843                         return false;
1844
1845                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1846                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1847                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1848                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1849                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1850                         le16_to_cpu(dtd_timings->usHSyncOffset);
1851                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1852                         le16_to_cpu(dtd_timings->usHSyncWidth);
1853
1854                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1855                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1856                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1857                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1858                         le16_to_cpu(dtd_timings->usVSyncOffset);
1859                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1860                         le16_to_cpu(dtd_timings->usVSyncWidth);
1861
1862                 mode->flags = 0;
1863                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1864                 if (misc & ATOM_VSYNC_POLARITY)
1865                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1866                 if (misc & ATOM_HSYNC_POLARITY)
1867                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1868                 if (misc & ATOM_COMPOSITESYNC)
1869                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1870                 if (misc & ATOM_INTERLACE)
1871                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1872                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1873                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1874
1875                 mode->crtc_clock = mode->clock =
1876                         le16_to_cpu(dtd_timings->usPixClk) * 10;
1877                 break;
1878         }
1879         return true;
1880 }
1881
1882 enum radeon_tv_std
1883 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1884 {
1885         struct radeon_mode_info *mode_info = &rdev->mode_info;
1886         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1887         uint16_t data_offset;
1888         uint8_t frev, crev;
1889         struct _ATOM_ANALOG_TV_INFO *tv_info;
1890         enum radeon_tv_std tv_std = TV_STD_NTSC;
1891
1892         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1893                                    &frev, &crev, &data_offset)) {
1894
1895                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1896                         (mode_info->atom_context->bios + data_offset);
1897
1898                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1899                 case ATOM_TV_NTSC:
1900                         tv_std = TV_STD_NTSC;
1901                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1902                         break;
1903                 case ATOM_TV_NTSCJ:
1904                         tv_std = TV_STD_NTSC_J;
1905                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1906                         break;
1907                 case ATOM_TV_PAL:
1908                         tv_std = TV_STD_PAL;
1909                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1910                         break;
1911                 case ATOM_TV_PALM:
1912                         tv_std = TV_STD_PAL_M;
1913                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1914                         break;
1915                 case ATOM_TV_PALN:
1916                         tv_std = TV_STD_PAL_N;
1917                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1918                         break;
1919                 case ATOM_TV_PALCN:
1920                         tv_std = TV_STD_PAL_CN;
1921                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1922                         break;
1923                 case ATOM_TV_PAL60:
1924                         tv_std = TV_STD_PAL_60;
1925                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1926                         break;
1927                 case ATOM_TV_SECAM:
1928                         tv_std = TV_STD_SECAM;
1929                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1930                         break;
1931                 default:
1932                         tv_std = TV_STD_NTSC;
1933                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1934                         break;
1935                 }
1936         }
1937         return tv_std;
1938 }
1939
1940 struct radeon_encoder_tv_dac *
1941 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1942 {
1943         struct drm_device *dev = encoder->base.dev;
1944         struct radeon_device *rdev = dev->dev_private;
1945         struct radeon_mode_info *mode_info = &rdev->mode_info;
1946         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1947         uint16_t data_offset;
1948         struct _COMPASSIONATE_DATA *dac_info;
1949         uint8_t frev, crev;
1950         uint8_t bg, dac;
1951         struct radeon_encoder_tv_dac *tv_dac = NULL;
1952
1953         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1954                                    &frev, &crev, &data_offset)) {
1955
1956                 dac_info = (struct _COMPASSIONATE_DATA *)
1957                         (mode_info->atom_context->bios + data_offset);
1958
1959                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1960
1961                 if (!tv_dac)
1962                         return NULL;
1963
1964                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1965                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1966                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1967
1968                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1969                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1970                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1971
1972                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1973                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1974                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1977         }
1978         return tv_dac;
1979 }
1980
1981 static const char *thermal_controller_names[] = {
1982         "NONE",
1983         "lm63",
1984         "adm1032",
1985         "adm1030",
1986         "max6649",
1987         "lm63", /* lm64 */
1988         "f75375",
1989         "asc7xxx",
1990 };
1991
1992 static const char *pp_lib_thermal_controller_names[] = {
1993         "NONE",
1994         "lm63",
1995         "adm1032",
1996         "adm1030",
1997         "max6649",
1998         "lm63", /* lm64 */
1999         "f75375",
2000         "RV6xx",
2001         "RV770",
2002         "adt7473",
2003         "NONE",
2004         "External GPIO",
2005         "Evergreen",
2006         "emc2103",
2007         "Sumo",
2008         "Northern Islands",
2009         "Southern Islands",
2010         "lm96163",
2011         "Sea Islands",
2012 };
2013
2014 union power_info {
2015         struct _ATOM_POWERPLAY_INFO info;
2016         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2017         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2018         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2019         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2020         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2021 };
2022
2023 union pplib_clock_info {
2024         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2025         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2026         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2027         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2028         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2029         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2030 };
2031
2032 union pplib_power_state {
2033         struct _ATOM_PPLIB_STATE v1;
2034         struct _ATOM_PPLIB_STATE_V2 v2;
2035 };
2036
2037 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2038                                                  int state_index,
2039                                                  u32 misc, u32 misc2)
2040 {
2041         rdev->pm.power_state[state_index].misc = misc;
2042         rdev->pm.power_state[state_index].misc2 = misc2;
2043         /* order matters! */
2044         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2045                 rdev->pm.power_state[state_index].type =
2046                         POWER_STATE_TYPE_POWERSAVE;
2047         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2048                 rdev->pm.power_state[state_index].type =
2049                         POWER_STATE_TYPE_BATTERY;
2050         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2051                 rdev->pm.power_state[state_index].type =
2052                         POWER_STATE_TYPE_BATTERY;
2053         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2054                 rdev->pm.power_state[state_index].type =
2055                         POWER_STATE_TYPE_BALANCED;
2056         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2057                 rdev->pm.power_state[state_index].type =
2058                         POWER_STATE_TYPE_PERFORMANCE;
2059                 rdev->pm.power_state[state_index].flags &=
2060                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2061         }
2062         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2063                 rdev->pm.power_state[state_index].type =
2064                         POWER_STATE_TYPE_BALANCED;
2065         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2066                 rdev->pm.power_state[state_index].type =
2067                         POWER_STATE_TYPE_DEFAULT;
2068                 rdev->pm.default_power_state_index = state_index;
2069                 rdev->pm.power_state[state_index].default_clock_mode =
2070                         &rdev->pm.power_state[state_index].clock_info[0];
2071         } else if (state_index == 0) {
2072                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2073                         RADEON_PM_MODE_NO_DISPLAY;
2074         }
2075 }
2076
2077 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2078 {
2079         struct radeon_mode_info *mode_info = &rdev->mode_info;
2080         u32 misc, misc2 = 0;
2081         int num_modes = 0, i;
2082         int state_index = 0;
2083         struct radeon_i2c_bus_rec i2c_bus;
2084         union power_info *power_info;
2085         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2086         u16 data_offset;
2087         u8 frev, crev;
2088
2089         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2090                                    &frev, &crev, &data_offset))
2091                 return state_index;
2092         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2093
2094         /* add the i2c bus for thermal/fan chip */
2095         if ((power_info->info.ucOverdriveThermalController > 0) &&
2096             (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2097                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2098                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2099                          power_info->info.ucOverdriveControllerAddress >> 1);
2100                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2101                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2102                 if (rdev->pm.i2c_bus) {
2103                         struct i2c_board_info info = { };
2104                         const char *name = thermal_controller_names[power_info->info.
2105                                                                     ucOverdriveThermalController];
2106                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2107                         strlcpy(info.type, name, sizeof(info.type));
2108                         i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2109                 }
2110         }
2111         num_modes = power_info->info.ucNumOfPowerModeEntries;
2112         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2113                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2114         if (num_modes == 0)
2115                 return state_index;
2116         rdev->pm.power_state = kcalloc(num_modes,
2117                                        sizeof(struct radeon_power_state),
2118                                        GFP_KERNEL);
2119         if (!rdev->pm.power_state)
2120                 return state_index;
2121         /* last mode is usually default, array is low to high */
2122         for (i = 0; i < num_modes; i++) {
2123                 /* avoid memory leaks from invalid modes or unknown frev. */
2124                 if (!rdev->pm.power_state[state_index].clock_info) {
2125                         rdev->pm.power_state[state_index].clock_info =
2126                                 kzalloc(sizeof(struct radeon_pm_clock_info),
2127                                         GFP_KERNEL);
2128                 }
2129                 if (!rdev->pm.power_state[state_index].clock_info)
2130                         goto out;
2131                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2132                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2133                 switch (frev) {
2134                 case 1:
2135                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2136                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2137                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2138                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2139                         /* skip invalid modes */
2140                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2141                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2142                                 continue;
2143                         rdev->pm.power_state[state_index].pcie_lanes =
2144                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2145                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2146                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2147                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2148                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2149                                         VOLTAGE_GPIO;
2150                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2151                                         radeon_atombios_lookup_gpio(rdev,
2152                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2153                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2154                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2155                                                 true;
2156                                 else
2157                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2158                                                 false;
2159                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2160                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2161                                         VOLTAGE_VDDC;
2162                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2163                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2164                         }
2165                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2166                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2167                         state_index++;
2168                         break;
2169                 case 2:
2170                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2171                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2172                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2173                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2174                         /* skip invalid modes */
2175                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2176                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2177                                 continue;
2178                         rdev->pm.power_state[state_index].pcie_lanes =
2179                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2180                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2181                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2182                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2183                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2184                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2185                                         VOLTAGE_GPIO;
2186                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2187                                         radeon_atombios_lookup_gpio(rdev,
2188                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2189                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2190                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2191                                                 true;
2192                                 else
2193                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2194                                                 false;
2195                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2196                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2197                                         VOLTAGE_VDDC;
2198                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2199                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2200                         }
2201                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2202                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2203                         state_index++;
2204                         break;
2205                 case 3:
2206                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2207                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2208                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2209                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2210                         /* skip invalid modes */
2211                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2212                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2213                                 continue;
2214                         rdev->pm.power_state[state_index].pcie_lanes =
2215                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2216                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2217                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2218                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2219                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2220                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2221                                         VOLTAGE_GPIO;
2222                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2223                                         radeon_atombios_lookup_gpio(rdev,
2224                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2225                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2226                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2227                                                 true;
2228                                 else
2229                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2230                                                 false;
2231                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2232                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2233                                         VOLTAGE_VDDC;
2234                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2235                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2236                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2237                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2238                                                 true;
2239                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2240                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2241                                 }
2242                         }
2243                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2244                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2245                         state_index++;
2246                         break;
2247                 }
2248         }
2249 out:
2250         /* free any unused clock_info allocation. */
2251         if (state_index && state_index < num_modes) {
2252                 kfree(rdev->pm.power_state[state_index].clock_info);
2253                 rdev->pm.power_state[state_index].clock_info = NULL;
2254         }
2255
2256         /* last mode is usually default */
2257         if (state_index && rdev->pm.default_power_state_index == -1) {
2258                 rdev->pm.power_state[state_index - 1].type =
2259                         POWER_STATE_TYPE_DEFAULT;
2260                 rdev->pm.default_power_state_index = state_index - 1;
2261                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2262                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2263                 rdev->pm.power_state[state_index - 1].flags &=
2264                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2265                 rdev->pm.power_state[state_index - 1].misc = 0;
2266                 rdev->pm.power_state[state_index - 1].misc2 = 0;
2267         }
2268         return state_index;
2269 }
2270
2271 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2272                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2273 {
2274         struct radeon_i2c_bus_rec i2c_bus;
2275
2276         /* add the i2c bus for thermal/fan chip */
2277         if (controller->ucType > 0) {
2278                 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2279                         rdev->pm.no_fan = true;
2280                 rdev->pm.fan_pulses_per_revolution =
2281                         controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2282                 if (rdev->pm.fan_pulses_per_revolution) {
2283                         rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2284                         rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2285                 }
2286                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2287                         DRM_INFO("Internal thermal controller %s fan control\n",
2288                                  (controller->ucFanParameters &
2289                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2290                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2291                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2292                         DRM_INFO("Internal thermal controller %s fan control\n",
2293                                  (controller->ucFanParameters &
2294                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2295                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2296                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2297                         DRM_INFO("Internal thermal controller %s fan control\n",
2298                                  (controller->ucFanParameters &
2299                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2301                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2302                         DRM_INFO("Internal thermal controller %s fan control\n",
2303                                  (controller->ucFanParameters &
2304                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2305                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2306                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2307                         DRM_INFO("Internal thermal controller %s fan control\n",
2308                                  (controller->ucFanParameters &
2309                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2310                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2311                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2312                         DRM_INFO("Internal thermal controller %s fan control\n",
2313                                  (controller->ucFanParameters &
2314                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2315                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2316                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2317                         DRM_INFO("Internal thermal controller %s fan control\n",
2318                                  (controller->ucFanParameters &
2319                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2320                         rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2321                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2322                         DRM_INFO("Internal thermal controller %s fan control\n",
2323                                  (controller->ucFanParameters &
2324                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325                         rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2326                 } else if (controller->ucType ==
2327                            ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2328                         DRM_INFO("External GPIO thermal controller %s fan control\n",
2329                                  (controller->ucFanParameters &
2330                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2331                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2332                 } else if (controller->ucType ==
2333                            ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2334                         DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2335                                  (controller->ucFanParameters &
2336                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2337                         rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2338                 } else if (controller->ucType ==
2339                            ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2340                         DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2341                                  (controller->ucFanParameters &
2342                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2343                         rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2344                 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2345                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2346                                  pp_lib_thermal_controller_names[controller->ucType],
2347                                  controller->ucI2cAddress >> 1,
2348                                  (controller->ucFanParameters &
2349                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2350                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2351                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2352                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2353                         if (rdev->pm.i2c_bus) {
2354                                 struct i2c_board_info info = { };
2355                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2356                                 info.addr = controller->ucI2cAddress >> 1;
2357                                 strlcpy(info.type, name, sizeof(info.type));
2358                                 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2359                         }
2360                 } else {
2361                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2362                                  controller->ucType,
2363                                  controller->ucI2cAddress >> 1,
2364                                  (controller->ucFanParameters &
2365                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2366                 }
2367         }
2368 }
2369
2370 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2371                                           u16 *vddc, u16 *vddci, u16 *mvdd)
2372 {
2373         struct radeon_mode_info *mode_info = &rdev->mode_info;
2374         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2375         u8 frev, crev;
2376         u16 data_offset;
2377         union firmware_info *firmware_info;
2378
2379         *vddc = 0;
2380         *vddci = 0;
2381         *mvdd = 0;
2382
2383         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2384                                    &frev, &crev, &data_offset)) {
2385                 firmware_info =
2386                         (union firmware_info *)(mode_info->atom_context->bios +
2387                                                 data_offset);
2388                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2389                 if ((frev == 2) && (crev >= 2)) {
2390                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2391                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2392                 }
2393         }
2394 }
2395
2396 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2397                                                        int state_index, int mode_index,
2398                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2399 {
2400         int j;
2401         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2402         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2403         u16 vddc, vddci, mvdd;
2404
2405         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2406
2407         rdev->pm.power_state[state_index].misc = misc;
2408         rdev->pm.power_state[state_index].misc2 = misc2;
2409         rdev->pm.power_state[state_index].pcie_lanes =
2410                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2411                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2412         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2413         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2414                 rdev->pm.power_state[state_index].type =
2415                         POWER_STATE_TYPE_BATTERY;
2416                 break;
2417         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2418                 rdev->pm.power_state[state_index].type =
2419                         POWER_STATE_TYPE_BALANCED;
2420                 break;
2421         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2422                 rdev->pm.power_state[state_index].type =
2423                         POWER_STATE_TYPE_PERFORMANCE;
2424                 break;
2425         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2426                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2427                         rdev->pm.power_state[state_index].type =
2428                                 POWER_STATE_TYPE_PERFORMANCE;
2429                 break;
2430         }
2431         rdev->pm.power_state[state_index].flags = 0;
2432         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2433                 rdev->pm.power_state[state_index].flags |=
2434                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2435         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2436                 rdev->pm.power_state[state_index].type =
2437                         POWER_STATE_TYPE_DEFAULT;
2438                 rdev->pm.default_power_state_index = state_index;
2439                 rdev->pm.power_state[state_index].default_clock_mode =
2440                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2441                 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2442                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2443                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2444                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2445                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2446                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2447                 } else {
2448                         u16 max_vddci = 0;
2449
2450                         if (ASIC_IS_DCE4(rdev))
2451                                 radeon_atom_get_max_voltage(rdev,
2452                                                             SET_VOLTAGE_TYPE_ASIC_VDDCI,
2453                                                             &max_vddci);
2454                         /* patch the table values with the default sclk/mclk from firmware info */
2455                         for (j = 0; j < mode_index; j++) {
2456                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2457                                         rdev->clock.default_mclk;
2458                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2459                                         rdev->clock.default_sclk;
2460                                 if (vddc)
2461                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2462                                                 vddc;
2463                                 if (max_vddci)
2464                                         rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2465                                                 max_vddci;
2466                         }
2467                 }
2468         }
2469 }
2470
2471 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2472                                                    int state_index, int mode_index,
2473                                                    union pplib_clock_info *clock_info)
2474 {
2475         u32 sclk, mclk;
2476         u16 vddc;
2477
2478         if (rdev->flags & RADEON_IS_IGP) {
2479                 if (rdev->family >= CHIP_PALM) {
2480                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2481                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2482                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2483                 } else {
2484                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2485                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2486                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2487                 }
2488         } else if (rdev->family >= CHIP_BONAIRE) {
2489                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2490                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2491                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2492                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2493                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2494                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2495                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2496                         VOLTAGE_NONE;
2497         } else if (rdev->family >= CHIP_TAHITI) {
2498                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2499                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2500                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2501                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2502                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2503                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2504                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2505                         VOLTAGE_SW;
2506                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2507                         le16_to_cpu(clock_info->si.usVDDC);
2508                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2509                         le16_to_cpu(clock_info->si.usVDDCI);
2510         } else if (rdev->family >= CHIP_CEDAR) {
2511                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2512                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2513                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2514                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2515                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2516                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2517                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2518                         VOLTAGE_SW;
2519                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2520                         le16_to_cpu(clock_info->evergreen.usVDDC);
2521                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2522                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2523         } else {
2524                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2525                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2526                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2527                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2528                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2529                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2530                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2531                         VOLTAGE_SW;
2532                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2533                         le16_to_cpu(clock_info->r600.usVDDC);
2534         }
2535
2536         /* patch up vddc if necessary */
2537         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2538         case ATOM_VIRTUAL_VOLTAGE_ID0:
2539         case ATOM_VIRTUAL_VOLTAGE_ID1:
2540         case ATOM_VIRTUAL_VOLTAGE_ID2:
2541         case ATOM_VIRTUAL_VOLTAGE_ID3:
2542         case ATOM_VIRTUAL_VOLTAGE_ID4:
2543         case ATOM_VIRTUAL_VOLTAGE_ID5:
2544         case ATOM_VIRTUAL_VOLTAGE_ID6:
2545         case ATOM_VIRTUAL_VOLTAGE_ID7:
2546                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2547                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2548                                              &vddc) == 0)
2549                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2550                 break;
2551         default:
2552                 break;
2553         }
2554
2555         if (rdev->flags & RADEON_IS_IGP) {
2556                 /* skip invalid modes */
2557                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2558                         return false;
2559         } else {
2560                 /* skip invalid modes */
2561                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2562                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2563                         return false;
2564         }
2565         return true;
2566 }
2567
2568 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2569 {
2570         struct radeon_mode_info *mode_info = &rdev->mode_info;
2571         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2572         union pplib_power_state *power_state;
2573         int i, j;
2574         int state_index = 0, mode_index = 0;
2575         union pplib_clock_info *clock_info;
2576         bool valid;
2577         union power_info *power_info;
2578         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2579         u16 data_offset;
2580         u8 frev, crev;
2581
2582         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2583                                    &frev, &crev, &data_offset))
2584                 return state_index;
2585         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2586
2587         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2588         if (power_info->pplib.ucNumStates == 0)
2589                 return state_index;
2590         rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2591                                        sizeof(struct radeon_power_state),
2592                                        GFP_KERNEL);
2593         if (!rdev->pm.power_state)
2594                 return state_index;
2595         /* first mode is usually default, followed by low to high */
2596         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2597                 mode_index = 0;
2598                 power_state = (union pplib_power_state *)
2599                         (mode_info->atom_context->bios + data_offset +
2600                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2601                          i * power_info->pplib.ucStateEntrySize);
2602                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2603                         (mode_info->atom_context->bios + data_offset +
2604                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2605                          (power_state->v1.ucNonClockStateIndex *
2606                           power_info->pplib.ucNonClockSize));
2607                 rdev->pm.power_state[i].clock_info =
2608                         kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2609                                 (power_info->pplib.ucStateEntrySize - 1) : 1,
2610                                 sizeof(struct radeon_pm_clock_info),
2611                                 GFP_KERNEL);
2612                 if (!rdev->pm.power_state[i].clock_info)
2613                         return state_index;
2614                 if (power_info->pplib.ucStateEntrySize - 1) {
2615                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2616                                 clock_info = (union pplib_clock_info *)
2617                                         (mode_info->atom_context->bios + data_offset +
2618                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2619                                          (power_state->v1.ucClockStateIndices[j] *
2620                                           power_info->pplib.ucClockInfoSize));
2621                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2622                                                                                state_index, mode_index,
2623                                                                                clock_info);
2624                                 if (valid)
2625                                         mode_index++;
2626                         }
2627                 } else {
2628                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2629                                 rdev->clock.default_mclk;
2630                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2631                                 rdev->clock.default_sclk;
2632                         mode_index++;
2633                 }
2634                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2635                 if (mode_index) {
2636                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2637                                                                    non_clock_info);
2638                         state_index++;
2639                 }
2640         }
2641         /* if multiple clock modes, mark the lowest as no display */
2642         for (i = 0; i < state_index; i++) {
2643                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2644                         rdev->pm.power_state[i].clock_info[0].flags |=
2645                                 RADEON_PM_MODE_NO_DISPLAY;
2646         }
2647         /* first mode is usually default */
2648         if (rdev->pm.default_power_state_index == -1) {
2649                 rdev->pm.power_state[0].type =
2650                         POWER_STATE_TYPE_DEFAULT;
2651                 rdev->pm.default_power_state_index = 0;
2652                 rdev->pm.power_state[0].default_clock_mode =
2653                         &rdev->pm.power_state[0].clock_info[0];
2654         }
2655         return state_index;
2656 }
2657
2658 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2659 {
2660         struct radeon_mode_info *mode_info = &rdev->mode_info;
2661         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2662         union pplib_power_state *power_state;
2663         int i, j, non_clock_array_index, clock_array_index;
2664         int state_index = 0, mode_index = 0;
2665         union pplib_clock_info *clock_info;
2666         struct _StateArray *state_array;
2667         struct _ClockInfoArray *clock_info_array;
2668         struct _NonClockInfoArray *non_clock_info_array;
2669         bool valid;
2670         union power_info *power_info;
2671         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2672         u16 data_offset;
2673         u8 frev, crev;
2674         u8 *power_state_offset;
2675
2676         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2677                                    &frev, &crev, &data_offset))
2678                 return state_index;
2679         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2680
2681         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2682         state_array = (struct _StateArray *)
2683                 (mode_info->atom_context->bios + data_offset +
2684                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2685         clock_info_array = (struct _ClockInfoArray *)
2686                 (mode_info->atom_context->bios + data_offset +
2687                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2688         non_clock_info_array = (struct _NonClockInfoArray *)
2689                 (mode_info->atom_context->bios + data_offset +
2690                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2691         if (state_array->ucNumEntries == 0)
2692                 return state_index;
2693         rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2694                                        sizeof(struct radeon_power_state),
2695                                        GFP_KERNEL);
2696         if (!rdev->pm.power_state)
2697                 return state_index;
2698         power_state_offset = (u8 *)state_array->states;
2699         for (i = 0; i < state_array->ucNumEntries; i++) {
2700                 mode_index = 0;
2701                 power_state = (union pplib_power_state *)power_state_offset;
2702                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2703                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2704                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2705                 rdev->pm.power_state[i].clock_info =
2706                         kcalloc(power_state->v2.ucNumDPMLevels ?
2707                                 power_state->v2.ucNumDPMLevels : 1,
2708                                 sizeof(struct radeon_pm_clock_info),
2709                                 GFP_KERNEL);
2710                 if (!rdev->pm.power_state[i].clock_info)
2711                         return state_index;
2712                 if (power_state->v2.ucNumDPMLevels) {
2713                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2714                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2715                                 clock_info = (union pplib_clock_info *)
2716                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2717                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2718                                                                                state_index, mode_index,
2719                                                                                clock_info);
2720                                 if (valid)
2721                                         mode_index++;
2722                         }
2723                 } else {
2724                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2725                                 rdev->clock.default_mclk;
2726                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2727                                 rdev->clock.default_sclk;
2728                         mode_index++;
2729                 }
2730                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2731                 if (mode_index) {
2732                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2733                                                                    non_clock_info);
2734                         state_index++;
2735                 }
2736                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2737         }
2738         /* if multiple clock modes, mark the lowest as no display */
2739         for (i = 0; i < state_index; i++) {
2740                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2741                         rdev->pm.power_state[i].clock_info[0].flags |=
2742                                 RADEON_PM_MODE_NO_DISPLAY;
2743         }
2744         /* first mode is usually default */
2745         if (rdev->pm.default_power_state_index == -1) {
2746                 rdev->pm.power_state[0].type =
2747                         POWER_STATE_TYPE_DEFAULT;
2748                 rdev->pm.default_power_state_index = 0;
2749                 rdev->pm.power_state[0].default_clock_mode =
2750                         &rdev->pm.power_state[0].clock_info[0];
2751         }
2752         return state_index;
2753 }
2754
2755 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2756 {
2757         struct radeon_mode_info *mode_info = &rdev->mode_info;
2758         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2759         u16 data_offset;
2760         u8 frev, crev;
2761         int state_index = 0;
2762
2763         rdev->pm.default_power_state_index = -1;
2764
2765         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2766                                    &frev, &crev, &data_offset)) {
2767                 switch (frev) {
2768                 case 1:
2769                 case 2:
2770                 case 3:
2771                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2772                         break;
2773                 case 4:
2774                 case 5:
2775                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2776                         break;
2777                 case 6:
2778                         state_index = radeon_atombios_parse_power_table_6(rdev);
2779                         break;
2780                 default:
2781                         break;
2782                 }
2783         }
2784
2785         if (state_index == 0) {
2786                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2787                 if (rdev->pm.power_state) {
2788                         rdev->pm.power_state[0].clock_info =
2789                                 kcalloc(1,
2790                                         sizeof(struct radeon_pm_clock_info),
2791                                         GFP_KERNEL);
2792                         if (rdev->pm.power_state[0].clock_info) {
2793                                 /* add the default mode */
2794                                 rdev->pm.power_state[state_index].type =
2795                                         POWER_STATE_TYPE_DEFAULT;
2796                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2797                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2798                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2799                                 rdev->pm.power_state[state_index].default_clock_mode =
2800                                         &rdev->pm.power_state[state_index].clock_info[0];
2801                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2802                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2803                                 rdev->pm.default_power_state_index = state_index;
2804                                 rdev->pm.power_state[state_index].flags = 0;
2805                                 state_index++;
2806                         }
2807                 }
2808         }
2809
2810         rdev->pm.num_power_states = state_index;
2811
2812         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2813         rdev->pm.current_clock_mode_index = 0;
2814         if (rdev->pm.default_power_state_index >= 0)
2815                 rdev->pm.current_vddc =
2816                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2817         else
2818                 rdev->pm.current_vddc = 0;
2819 }
2820
2821 union get_clock_dividers {
2822         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2823         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2824         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2825         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2826         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2827         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2828         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2829 };
2830
2831 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2832                                    u8 clock_type,
2833                                    u32 clock,
2834                                    bool strobe_mode,
2835                                    struct atom_clock_dividers *dividers)
2836 {
2837         union get_clock_dividers args;
2838         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2839         u8 frev, crev;
2840
2841         memset(&args, 0, sizeof(args));
2842         memset(dividers, 0, sizeof(struct atom_clock_dividers));
2843
2844         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2845                 return -EINVAL;
2846
2847         switch (crev) {
2848         case 1:
2849                 /* r4xx, r5xx */
2850                 args.v1.ucAction = clock_type;
2851                 args.v1.ulClock = cpu_to_le32(clock);   /* 10 khz */
2852
2853                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2854
2855                 dividers->post_div = args.v1.ucPostDiv;
2856                 dividers->fb_div = args.v1.ucFbDiv;
2857                 dividers->enable_post_div = true;
2858                 break;
2859         case 2:
2860         case 3:
2861         case 5:
2862                 /* r6xx, r7xx, evergreen, ni, si */
2863                 if (rdev->family <= CHIP_RV770) {
2864                         args.v2.ucAction = clock_type;
2865                         args.v2.ulClock = cpu_to_le32(clock);   /* 10 khz */
2866
2867                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2868
2869                         dividers->post_div = args.v2.ucPostDiv;
2870                         dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2871                         dividers->ref_div = args.v2.ucAction;
2872                         if (rdev->family == CHIP_RV770) {
2873                                 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2874                                         true : false;
2875                                 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2876                         } else
2877                                 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2878                 } else {
2879                         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2880                                 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2881
2882                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2883
2884                                 dividers->post_div = args.v3.ucPostDiv;
2885                                 dividers->enable_post_div = (args.v3.ucCntlFlag &
2886                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2887                                 dividers->enable_dithen = (args.v3.ucCntlFlag &
2888                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2889                                 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2890                                 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2891                                 dividers->ref_div = args.v3.ucRefDiv;
2892                                 dividers->vco_mode = (args.v3.ucCntlFlag &
2893                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2894                         } else {
2895                                 /* for SI we use ComputeMemoryClockParam for memory plls */
2896                                 if (rdev->family >= CHIP_TAHITI)
2897                                         return -EINVAL;
2898                                 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2899                                 if (strobe_mode)
2900                                         args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2901
2902                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2903
2904                                 dividers->post_div = args.v5.ucPostDiv;
2905                                 dividers->enable_post_div = (args.v5.ucCntlFlag &
2906                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2907                                 dividers->enable_dithen = (args.v5.ucCntlFlag &
2908                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2909                                 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2910                                 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2911                                 dividers->ref_div = args.v5.ucRefDiv;
2912                                 dividers->vco_mode = (args.v5.ucCntlFlag &
2913                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2914                         }
2915                 }
2916                 break;
2917         case 4:
2918                 /* fusion */
2919                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
2920
2921                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2922
2923                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2924                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2925                 break;
2926         case 6:
2927                 /* CI */
2928                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2929                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2930                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
2931
2932                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2933
2934                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2935                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2936                 dividers->ref_div = args.v6_out.ucPllRefDiv;
2937                 dividers->post_div = args.v6_out.ucPllPostDiv;
2938                 dividers->flags = args.v6_out.ucPllCntlFlag;
2939                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2940                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2941                 break;
2942         default:
2943                 return -EINVAL;
2944         }
2945         return 0;
2946 }
2947
2948 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2949                                         u32 clock,
2950                                         bool strobe_mode,
2951                                         struct atom_mpll_param *mpll_param)
2952 {
2953         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2954         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2955         u8 frev, crev;
2956
2957         memset(&args, 0, sizeof(args));
2958         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2959
2960         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2961                 return -EINVAL;
2962
2963         switch (frev) {
2964         case 2:
2965                 switch (crev) {
2966                 case 1:
2967                         /* SI */
2968                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
2969                         args.ucInputFlag = 0;
2970                         if (strobe_mode)
2971                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2972
2973                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2974
2975                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2976                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2977                         mpll_param->post_div = args.ucPostDiv;
2978                         mpll_param->dll_speed = args.ucDllSpeed;
2979                         mpll_param->bwcntl = args.ucBWCntl;
2980                         mpll_param->vco_mode =
2981                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2982                         mpll_param->yclk_sel =
2983                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2984                         mpll_param->qdr =
2985                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2986                         mpll_param->half_rate =
2987                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2988                         break;
2989                 default:
2990                         return -EINVAL;
2991                 }
2992                 break;
2993         default:
2994                 return -EINVAL;
2995         }
2996         return 0;
2997 }
2998
2999 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3000 {
3001         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3002         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3003
3004         args.ucEnable = enable;
3005
3006         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3007 }
3008
3009 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3010 {
3011         GET_ENGINE_CLOCK_PS_ALLOCATION args;
3012         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3013
3014         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3015         return le32_to_cpu(args.ulReturnEngineClock);
3016 }
3017
3018 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3019 {
3020         GET_MEMORY_CLOCK_PS_ALLOCATION args;
3021         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3022
3023         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3024         return le32_to_cpu(args.ulReturnMemoryClock);
3025 }
3026
3027 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3028                                   uint32_t eng_clock)
3029 {
3030         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3031         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3032
3033         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
3034
3035         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3036 }
3037
3038 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3039                                   uint32_t mem_clock)
3040 {
3041         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3042         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3043
3044         if (rdev->flags & RADEON_IS_IGP)
3045                 return;
3046
3047         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
3048
3049         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3050 }
3051
3052 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3053                                          u32 eng_clock, u32 mem_clock)
3054 {
3055         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3056         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3057         u32 tmp;
3058
3059         memset(&args, 0, sizeof(args));
3060
3061         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3062         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3063
3064         args.ulTargetEngineClock = cpu_to_le32(tmp);
3065         if (mem_clock)
3066                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3067
3068         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3069 }
3070
3071 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3072                                    u32 mem_clock)
3073 {
3074         u32 args;
3075         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3076
3077         args = cpu_to_le32(mem_clock);  /* 10 khz */
3078
3079         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3080 }
3081
3082 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3083                                u32 mem_clock)
3084 {
3085         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3086         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3087         u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3088
3089         args.ulTargetMemoryClock = cpu_to_le32(tmp);    /* 10 khz */
3090
3091         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3092 }
3093
3094 union set_voltage {
3095         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3096         struct _SET_VOLTAGE_PARAMETERS v1;
3097         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3098         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3099 };
3100
3101 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3102 {
3103         union set_voltage args;
3104         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3105         u8 frev, crev, volt_index = voltage_level;
3106
3107         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3108                 return;
3109
3110         /* 0xff01 is a flag rather then an actual voltage */
3111         if (voltage_level == 0xff01)
3112                 return;
3113
3114         switch (crev) {
3115         case 1:
3116                 args.v1.ucVoltageType = voltage_type;
3117                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3118                 args.v1.ucVoltageIndex = volt_index;
3119                 break;
3120         case 2:
3121                 args.v2.ucVoltageType = voltage_type;
3122                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3123                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3124                 break;
3125         case 3:
3126                 args.v3.ucVoltageType = voltage_type;
3127                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3128                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3129                 break;
3130         default:
3131                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3132                 return;
3133         }
3134
3135         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3136 }
3137
3138 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3139                              u16 voltage_id, u16 *voltage)
3140 {
3141         union set_voltage args;
3142         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3143         u8 frev, crev;
3144
3145         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3146                 return -EINVAL;
3147
3148         switch (crev) {
3149         case 1:
3150                 return -EINVAL;
3151         case 2:
3152                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3153                 args.v2.ucVoltageMode = 0;
3154                 args.v2.usVoltageLevel = 0;
3155
3156                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3157
3158                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3159                 break;
3160         case 3:
3161                 args.v3.ucVoltageType = voltage_type;
3162                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3163                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3164
3165                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3166
3167                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3168                 break;
3169         default:
3170                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3171                 return -EINVAL;
3172         }
3173
3174         return 0;
3175 }
3176
3177 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3178                                                       u16 *voltage,
3179                                                       u16 leakage_idx)
3180 {
3181         return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3182 }
3183
3184 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3185                                           u16 *leakage_id)
3186 {
3187         union set_voltage args;
3188         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3189         u8 frev, crev;
3190
3191         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3192                 return -EINVAL;
3193
3194         switch (crev) {
3195         case 3:
3196         case 4:
3197                 args.v3.ucVoltageType = 0;
3198                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3199                 args.v3.usVoltageLevel = 0;
3200
3201                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3202
3203                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3204                 break;
3205         default:
3206                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3207                 return -EINVAL;
3208         }
3209
3210         return 0;
3211 }
3212
3213 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3214                                                          u16 *vddc, u16 *vddci,
3215                                                          u16 virtual_voltage_id,
3216                                                          u16 vbios_voltage_id)
3217 {
3218         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3219         u8 frev, crev;
3220         u16 data_offset, size;
3221         int i, j;
3222         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3223         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3224
3225         *vddc = 0;
3226         *vddci = 0;
3227
3228         if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3229                                     &frev, &crev, &data_offset))
3230                 return -EINVAL;
3231
3232         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3233                 (rdev->mode_info.atom_context->bios + data_offset);
3234
3235         switch (frev) {
3236         case 1:
3237                 return -EINVAL;
3238         case 2:
3239                 switch (crev) {
3240                 case 1:
3241                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3242                                 return -EINVAL;
3243                         leakage_bin = (u16 *)
3244                                 (rdev->mode_info.atom_context->bios + data_offset +
3245                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
3246                         vddc_id_buf = (u16 *)
3247                                 (rdev->mode_info.atom_context->bios + data_offset +
3248                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3249                         vddc_buf = (u16 *)
3250                                 (rdev->mode_info.atom_context->bios + data_offset +
3251                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3252                         vddci_id_buf = (u16 *)
3253                                 (rdev->mode_info.atom_context->bios + data_offset +
3254                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3255                         vddci_buf = (u16 *)
3256                                 (rdev->mode_info.atom_context->bios + data_offset +
3257                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3258
3259                         if (profile->ucElbVDDC_Num > 0) {
3260                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3261                                         if (vddc_id_buf[i] == virtual_voltage_id) {
3262                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3263                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3264                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3265                                                                 break;
3266                                                         }
3267                                                 }
3268                                                 break;
3269                                         }
3270                                 }
3271                         }
3272                         if (profile->ucElbVDDCI_Num > 0) {
3273                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3274                                         if (vddci_id_buf[i] == virtual_voltage_id) {
3275                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3276                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3277                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3278                                                                 break;
3279                                                         }
3280                                                 }
3281                                                 break;
3282                                         }
3283                                 }
3284                         }
3285                         break;
3286                 default:
3287                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3288                         return -EINVAL;
3289                 }
3290                 break;
3291         default:
3292                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3293                 return -EINVAL;
3294         }
3295
3296         return 0;
3297 }
3298
3299 union get_voltage_info {
3300         struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3301         struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3302 };
3303
3304 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3305                                 u16 virtual_voltage_id,
3306                                 u16 *voltage)
3307 {
3308         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3309         u32 entry_id;
3310         u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3311         union get_voltage_info args;
3312
3313         for (entry_id = 0; entry_id < count; entry_id++) {
3314                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3315                     virtual_voltage_id)
3316                         break;
3317         }
3318
3319         if (entry_id >= count)
3320                 return -EINVAL;
3321
3322         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3323         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3324         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3325         args.in.ulSCLKFreq =
3326                 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3327
3328         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3329
3330         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3331
3332         return 0;
3333 }
3334
3335 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3336                                           u16 voltage_level, u8 voltage_type,
3337                                           u32 *gpio_value, u32 *gpio_mask)
3338 {
3339         union set_voltage args;
3340         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3341         u8 frev, crev;
3342
3343         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3344                 return -EINVAL;
3345
3346         switch (crev) {
3347         case 1:
3348                 return -EINVAL;
3349         case 2:
3350                 args.v2.ucVoltageType = voltage_type;
3351                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3352                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3353
3354                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3355
3356                 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3357
3358                 args.v2.ucVoltageType = voltage_type;
3359                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3360                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3361
3362                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3363
3364                 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3365                 break;
3366         default:
3367                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3368                 return -EINVAL;
3369         }
3370
3371         return 0;
3372 }
3373
3374 union voltage_object_info {
3375         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3376         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3377         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3378 };
3379
3380 union voltage_object {
3381         struct _ATOM_VOLTAGE_OBJECT v1;
3382         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3383         union _ATOM_VOLTAGE_OBJECT_V3 v3;
3384 };
3385
3386 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3387                                                           u8 voltage_type)
3388 {
3389         u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3390         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3391         u8 *start = (u8 *)v1;
3392
3393         while (offset < size) {
3394                 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3395                 if (vo->ucVoltageType == voltage_type)
3396                         return vo;
3397                 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3398                         vo->asFormula.ucNumOfVoltageEntries;
3399         }
3400         return NULL;
3401 }
3402
3403 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3404                                                              u8 voltage_type)
3405 {
3406         u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3407         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3408         u8 *start = (u8*)v2;
3409
3410         while (offset < size) {
3411                 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3412                 if (vo->ucVoltageType == voltage_type)
3413                         return vo;
3414                 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3415                         (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3416         }
3417         return NULL;
3418 }
3419
3420 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3421                                                              u8 voltage_type, u8 voltage_mode)
3422 {
3423         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3424         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3425         u8 *start = (u8*)v3;
3426
3427         while (offset < size) {
3428                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3429                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3430                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3431                         return vo;
3432                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3433         }
3434         return NULL;
3435 }
3436
3437 bool
3438 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3439                             u8 voltage_type, u8 voltage_mode)
3440 {
3441         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3442         u8 frev, crev;
3443         u16 data_offset, size;
3444         union voltage_object_info *voltage_info;
3445         union voltage_object *voltage_object = NULL;
3446
3447         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3448                                    &frev, &crev, &data_offset)) {
3449                 voltage_info = (union voltage_object_info *)
3450                         (rdev->mode_info.atom_context->bios + data_offset);
3451
3452                 switch (frev) {
3453                 case 1:
3454                 case 2:
3455                         switch (crev) {
3456                         case 1:
3457                                 voltage_object = (union voltage_object *)
3458                                         atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3459                                 if (voltage_object &&
3460                                     (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3461                                         return true;
3462                                 break;
3463                         case 2:
3464                                 voltage_object = (union voltage_object *)
3465                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3466                                 if (voltage_object &&
3467                                     (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3468                                         return true;
3469                                 break;
3470                         default:
3471                                 DRM_ERROR("unknown voltage object table\n");
3472                                 return false;
3473                         }
3474                         break;
3475                 case 3:
3476                         switch (crev) {
3477                         case 1:
3478                                 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3479                                                                   voltage_type, voltage_mode))
3480                                         return true;
3481                                 break;
3482                         default:
3483                                 DRM_ERROR("unknown voltage object table\n");
3484                                 return false;
3485                         }
3486                         break;
3487                 default:
3488                         DRM_ERROR("unknown voltage object table\n");
3489                         return false;
3490                 }
3491
3492         }
3493         return false;
3494 }
3495
3496 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3497                               u8 voltage_type,
3498                               u8 *svd_gpio_id, u8 *svc_gpio_id)
3499 {
3500         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3501         u8 frev, crev;
3502         u16 data_offset, size;
3503         union voltage_object_info *voltage_info;
3504         union voltage_object *voltage_object = NULL;
3505
3506         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3507                                    &frev, &crev, &data_offset)) {
3508                 voltage_info = (union voltage_object_info *)
3509                         (rdev->mode_info.atom_context->bios + data_offset);
3510
3511                 switch (frev) {
3512                 case 3:
3513                         switch (crev) {
3514                         case 1:
3515                                 voltage_object = (union voltage_object *)
3516                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3517                                                                       voltage_type,
3518                                                                       VOLTAGE_OBJ_SVID2);
3519                                 if (voltage_object) {
3520                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3521                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3522                                 } else {
3523                                         return -EINVAL;
3524                                 }
3525                                 break;
3526                         default:
3527                                 DRM_ERROR("unknown voltage object table\n");
3528                                 return -EINVAL;
3529                         }
3530                         break;
3531                 default:
3532                         DRM_ERROR("unknown voltage object table\n");
3533                         return -EINVAL;
3534                 }
3535
3536         }
3537         return 0;
3538 }
3539
3540 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3541                                 u8 voltage_type, u16 *max_voltage)
3542 {
3543         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3544         u8 frev, crev;
3545         u16 data_offset, size;
3546         union voltage_object_info *voltage_info;
3547         union voltage_object *voltage_object = NULL;
3548
3549         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3550                                    &frev, &crev, &data_offset)) {
3551                 voltage_info = (union voltage_object_info *)
3552                         (rdev->mode_info.atom_context->bios + data_offset);
3553
3554                 switch (crev) {
3555                 case 1:
3556                         voltage_object = (union voltage_object *)
3557                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3558                         if (voltage_object) {
3559                                 ATOM_VOLTAGE_FORMULA *formula =
3560                                         &voltage_object->v1.asFormula;
3561                                 if (formula->ucFlag & 1)
3562                                         *max_voltage =
3563                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3564                                                 formula->ucNumOfVoltageEntries / 2 *
3565                                                 le16_to_cpu(formula->usVoltageStep);
3566                                 else
3567                                         *max_voltage =
3568                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3569                                                 (formula->ucNumOfVoltageEntries - 1) *
3570                                                 le16_to_cpu(formula->usVoltageStep);
3571                                 return 0;
3572                         }
3573                         break;
3574                 case 2:
3575                         voltage_object = (union voltage_object *)
3576                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3577                         if (voltage_object) {
3578                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3579                                         &voltage_object->v2.asFormula;
3580                                 if (formula->ucNumOfVoltageEntries) {
3581                                         VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3582                                                 ((u8 *)&formula->asVIDAdjustEntries[0] +
3583                                                  (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3584                                         *max_voltage =
3585                                                 le16_to_cpu(lut->usVoltageValue);
3586                                         return 0;
3587                                 }
3588                         }
3589                         break;
3590                 default:
3591                         DRM_ERROR("unknown voltage object table\n");
3592                         return -EINVAL;
3593                 }
3594
3595         }
3596         return -EINVAL;
3597 }
3598
3599 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3600                                 u8 voltage_type, u16 *min_voltage)
3601 {
3602         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3603         u8 frev, crev;
3604         u16 data_offset, size;
3605         union voltage_object_info *voltage_info;
3606         union voltage_object *voltage_object = NULL;
3607
3608         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3609                                    &frev, &crev, &data_offset)) {
3610                 voltage_info = (union voltage_object_info *)
3611                         (rdev->mode_info.atom_context->bios + data_offset);
3612
3613                 switch (crev) {
3614                 case 1:
3615                         voltage_object = (union voltage_object *)
3616                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3617                         if (voltage_object) {
3618                                 ATOM_VOLTAGE_FORMULA *formula =
3619                                         &voltage_object->v1.asFormula;
3620                                 *min_voltage =
3621                                         le16_to_cpu(formula->usVoltageBaseLevel);
3622                                 return 0;
3623                         }
3624                         break;
3625                 case 2:
3626                         voltage_object = (union voltage_object *)
3627                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3628                         if (voltage_object) {
3629                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3630                                         &voltage_object->v2.asFormula;
3631                                 if (formula->ucNumOfVoltageEntries) {
3632                                         *min_voltage =
3633                                                 le16_to_cpu(formula->asVIDAdjustEntries[
3634                                                                     0
3635                                                                     ].usVoltageValue);
3636                                         return 0;
3637                                 }
3638                         }
3639                         break;
3640                 default:
3641                         DRM_ERROR("unknown voltage object table\n");
3642                         return -EINVAL;
3643                 }
3644
3645         }
3646         return -EINVAL;
3647 }
3648
3649 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3650                                  u8 voltage_type, u16 *voltage_step)
3651 {
3652         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3653         u8 frev, crev;
3654         u16 data_offset, size;
3655         union voltage_object_info *voltage_info;
3656         union voltage_object *voltage_object = NULL;
3657
3658         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3659                                    &frev, &crev, &data_offset)) {
3660                 voltage_info = (union voltage_object_info *)
3661                         (rdev->mode_info.atom_context->bios + data_offset);
3662
3663                 switch (crev) {
3664                 case 1:
3665                         voltage_object = (union voltage_object *)
3666                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3667                         if (voltage_object) {
3668                                 ATOM_VOLTAGE_FORMULA *formula =
3669                                         &voltage_object->v1.asFormula;
3670                                 if (formula->ucFlag & 1)
3671                                         *voltage_step =
3672                                                 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3673                                 else
3674                                         *voltage_step =
3675                                                 le16_to_cpu(formula->usVoltageStep);
3676                                 return 0;
3677                         }
3678                         break;
3679                 case 2:
3680                         return -EINVAL;
3681                 default:
3682                         DRM_ERROR("unknown voltage object table\n");
3683                         return -EINVAL;
3684                 }
3685
3686         }
3687         return -EINVAL;
3688 }
3689
3690 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3691                                       u8 voltage_type,
3692                                       u16 nominal_voltage,
3693                                       u16 *true_voltage)
3694 {
3695         u16 min_voltage, max_voltage, voltage_step;
3696
3697         if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3698                 return -EINVAL;
3699         if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3700                 return -EINVAL;
3701         if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3702                 return -EINVAL;
3703
3704         if (nominal_voltage <= min_voltage)
3705                 *true_voltage = min_voltage;
3706         else if (nominal_voltage >= max_voltage)
3707                 *true_voltage = max_voltage;
3708         else
3709                 *true_voltage = min_voltage +
3710                         ((nominal_voltage - min_voltage) / voltage_step) *
3711                         voltage_step;
3712
3713         return 0;
3714 }
3715
3716 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3717                                   u8 voltage_type, u8 voltage_mode,
3718                                   struct atom_voltage_table *voltage_table)
3719 {
3720         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3721         u8 frev, crev;
3722         u16 data_offset, size;
3723         int i, ret;
3724         union voltage_object_info *voltage_info;
3725         union voltage_object *voltage_object = NULL;
3726
3727         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3728                                    &frev, &crev, &data_offset)) {
3729                 voltage_info = (union voltage_object_info *)
3730                         (rdev->mode_info.atom_context->bios + data_offset);
3731
3732                 switch (frev) {
3733                 case 1:
3734                 case 2:
3735                         switch (crev) {
3736                         case 1:
3737                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3738                                 return -EINVAL;
3739                         case 2:
3740                                 voltage_object = (union voltage_object *)
3741                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3742                                 if (voltage_object) {
3743                                         ATOM_VOLTAGE_FORMULA_V2 *formula =
3744                                                 &voltage_object->v2.asFormula;
3745                                         VOLTAGE_LUT_ENTRY *lut;
3746                                         if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3747                                                 return -EINVAL;
3748                                         lut = &formula->asVIDAdjustEntries[0];
3749                                         for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3750                                                 voltage_table->entries[i].value =
3751                                                         le16_to_cpu(lut->usVoltageValue);
3752                                                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3753                                                                                             voltage_table->entries[i].value,
3754                                                                                             voltage_type,
3755                                                                                             &voltage_table->entries[i].smio_low,
3756                                                                                             &voltage_table->mask_low);
3757                                                 if (ret)
3758                                                         return ret;
3759                                                 lut = (VOLTAGE_LUT_ENTRY *)
3760                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3761                                         }
3762                                         voltage_table->count = formula->ucNumOfVoltageEntries;
3763                                         return 0;
3764                                 }
3765                                 break;
3766                         default:
3767                                 DRM_ERROR("unknown voltage object table\n");
3768                                 return -EINVAL;
3769                         }
3770                         break;
3771                 case 3:
3772                         switch (crev) {
3773                         case 1:
3774                                 voltage_object = (union voltage_object *)
3775                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3776                                                                       voltage_type, voltage_mode);
3777                                 if (voltage_object) {
3778                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3779                                                 &voltage_object->v3.asGpioVoltageObj;
3780                                         VOLTAGE_LUT_ENTRY_V2 *lut;
3781                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3782                                                 return -EINVAL;
3783                                         lut = &gpio->asVolGpioLut[0];
3784                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3785                                                 voltage_table->entries[i].value =
3786                                                         le16_to_cpu(lut->usVoltageValue);
3787                                                 voltage_table->entries[i].smio_low =
3788                                                         le32_to_cpu(lut->ulVoltageId);
3789                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3790                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3791                                         }
3792                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3793                                         voltage_table->count = gpio->ucGpioEntryNum;
3794                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
3795                                         return 0;
3796                                 }
3797                                 break;
3798                         default:
3799                                 DRM_ERROR("unknown voltage object table\n");
3800                                 return -EINVAL;
3801                         }
3802                         break;
3803                 default:
3804                         DRM_ERROR("unknown voltage object table\n");
3805                         return -EINVAL;
3806                 }
3807         }
3808         return -EINVAL;
3809 }
3810
3811 union vram_info {
3812         struct _ATOM_VRAM_INFO_V3 v1_3;
3813         struct _ATOM_VRAM_INFO_V4 v1_4;
3814         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3815 };
3816
3817 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3818                                 u8 module_index, struct atom_memory_info *mem_info)
3819 {
3820         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3821         u8 frev, crev, i;
3822         u16 data_offset, size;
3823         union vram_info *vram_info;
3824
3825         memset(mem_info, 0, sizeof(struct atom_memory_info));
3826
3827         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3828                                    &frev, &crev, &data_offset)) {
3829                 vram_info = (union vram_info *)
3830                         (rdev->mode_info.atom_context->bios + data_offset);
3831                 switch (frev) {
3832                 case 1:
3833                         switch (crev) {
3834                         case 3:
3835                                 /* r6xx */
3836                                 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3837                                         ATOM_VRAM_MODULE_V3 *vram_module =
3838                                                 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3839
3840                                         for (i = 0; i < module_index; i++) {
3841                                                 if (le16_to_cpu(vram_module->usSize) == 0)
3842                                                         return -EINVAL;
3843                                                 vram_module = (ATOM_VRAM_MODULE_V3 *)
3844                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3845                                         }
3846                                         mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3847                                         mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3848                                 } else
3849                                         return -EINVAL;
3850                                 break;
3851                         case 4:
3852                                 /* r7xx, evergreen */
3853                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3854                                         ATOM_VRAM_MODULE_V4 *vram_module =
3855                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3856
3857                                         for (i = 0; i < module_index; i++) {
3858                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3859                                                         return -EINVAL;
3860                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3861                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3862                                         }
3863                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3864                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3865                                 } else
3866                                         return -EINVAL;
3867                                 break;
3868                         default:
3869                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3870                                 return -EINVAL;
3871                         }
3872                         break;
3873                 case 2:
3874                         switch (crev) {
3875                         case 1:
3876                                 /* ni */
3877                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3878                                         ATOM_VRAM_MODULE_V7 *vram_module =
3879                                                 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3880
3881                                         for (i = 0; i < module_index; i++) {
3882                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3883                                                         return -EINVAL;
3884                                                 vram_module = (ATOM_VRAM_MODULE_V7 *)
3885                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3886                                         }
3887                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3888                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3889                                 } else
3890                                         return -EINVAL;
3891                                 break;
3892                         default:
3893                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3894                                 return -EINVAL;
3895                         }
3896                         break;
3897                 default:
3898                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3899                         return -EINVAL;
3900                 }
3901                 return 0;
3902         }
3903         return -EINVAL;
3904 }
3905
3906 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3907                                      bool gddr5, u8 module_index,
3908                                      struct atom_memory_clock_range_table *mclk_range_table)
3909 {
3910         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3911         u8 frev, crev, i;
3912         u16 data_offset, size;
3913         union vram_info *vram_info;
3914         u32 mem_timing_size = gddr5 ?
3915                 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3916
3917         memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3918
3919         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3920                                    &frev, &crev, &data_offset)) {
3921                 vram_info = (union vram_info *)
3922                         (rdev->mode_info.atom_context->bios + data_offset);
3923                 switch (frev) {
3924                 case 1:
3925                         switch (crev) {
3926                         case 3:
3927                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3928                                 return -EINVAL;
3929                         case 4:
3930                                 /* r7xx, evergreen */
3931                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3932                                         ATOM_VRAM_MODULE_V4 *vram_module =
3933                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3934                                         ATOM_MEMORY_TIMING_FORMAT *format;
3935
3936                                         for (i = 0; i < module_index; i++) {
3937                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3938                                                         return -EINVAL;
3939                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3940                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3941                                         }
3942                                         mclk_range_table->num_entries = (u8)
3943                                                 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3944                                                  mem_timing_size);
3945                                         format = &vram_module->asMemTiming[0];
3946                                         for (i = 0; i < mclk_range_table->num_entries; i++) {
3947                                                 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3948                                                 format = (ATOM_MEMORY_TIMING_FORMAT *)
3949                                                         ((u8 *)format + mem_timing_size);
3950                                         }
3951                                 } else
3952                                         return -EINVAL;
3953                                 break;
3954                         default:
3955                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3956                                 return -EINVAL;
3957                         }
3958                         break;
3959                 case 2:
3960                         DRM_ERROR("new table version %d, %d\n", frev, crev);
3961                         return -EINVAL;
3962                 default:
3963                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3964                         return -EINVAL;
3965                 }
3966                 return 0;
3967         }
3968         return -EINVAL;
3969 }
3970
3971 #define MEM_ID_MASK           0xff000000
3972 #define MEM_ID_SHIFT          24
3973 #define CLOCK_RANGE_MASK      0x00ffffff
3974 #define CLOCK_RANGE_SHIFT     0
3975 #define LOW_NIBBLE_MASK       0xf
3976 #define DATA_EQU_PREV         0
3977 #define DATA_FROM_TABLE       4
3978
3979 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3980                                   u8 module_index,
3981                                   struct atom_mc_reg_table *reg_table)
3982 {
3983         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3984         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3985         u32 i = 0, j;
3986         u16 data_offset, size;
3987         union vram_info *vram_info;
3988
3989         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3990
3991         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3992                                    &frev, &crev, &data_offset)) {
3993                 vram_info = (union vram_info *)
3994                         (rdev->mode_info.atom_context->bios + data_offset);
3995                 switch (frev) {
3996                 case 1:
3997                         DRM_ERROR("old table version %d, %d\n", frev, crev);
3998                         return -EINVAL;
3999                 case 2:
4000                         switch (crev) {
4001                         case 1:
4002                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4003                                         ATOM_INIT_REG_BLOCK *reg_block =
4004                                                 (ATOM_INIT_REG_BLOCK *)
4005                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4006                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4007                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4008                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
4009                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
4010                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
4011                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4012                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4013                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4014                                                 return -EINVAL;
4015                                         while (i < num_entries) {
4016                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4017                                                         break;
4018                                                 reg_table->mc_reg_address[i].s1 =
4019                                                         (u16)(le16_to_cpu(format->usRegIndex));
4020                                                 reg_table->mc_reg_address[i].pre_reg_data =
4021                                                         (u8)(format->ucPreRegDataLength);
4022                                                 i++;
4023                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4024                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4025                                         }
4026                                         reg_table->last = i;
4027                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4028                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4029                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4030                                                                 >> MEM_ID_SHIFT);
4031                                                 if (module_index == t_mem_id) {
4032                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4033                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4034                                                                       >> CLOCK_RANGE_SHIFT);
4035                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
4036                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4037                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4038                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4039                                                                         j++;
4040                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4041                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4042                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4043                                                                 }
4044                                                         }
4045                                                         num_ranges++;
4046                                                 }
4047                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4048                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4049                                         }
4050                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4051                                                 return -EINVAL;
4052                                         reg_table->num_entries = num_ranges;
4053                                 } else
4054                                         return -EINVAL;
4055                                 break;
4056                         default:
4057                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4058                                 return -EINVAL;
4059                         }
4060                         break;
4061                 default:
4062                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4063                         return -EINVAL;
4064                 }
4065                 return 0;
4066         }
4067         return -EINVAL;
4068 }
4069
4070 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4071 {
4072         struct radeon_device *rdev = dev->dev_private;
4073         uint32_t bios_2_scratch, bios_6_scratch;
4074
4075         if (rdev->family >= CHIP_R600) {
4076                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4077                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4078         } else {
4079                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4080                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4081         }
4082
4083         /* let the bios control the backlight */
4084         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4085
4086         /* tell the bios not to handle mode switching */
4087         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4088
4089         /* clear the vbios dpms state */
4090         if (ASIC_IS_DCE4(rdev))
4091                 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4092
4093         if (rdev->family >= CHIP_R600) {
4094                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4095                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4096         } else {
4097                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4098                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4099         }
4100
4101 }
4102
4103 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4104 {
4105         uint32_t scratch_reg;
4106         int i;
4107
4108         if (rdev->family >= CHIP_R600)
4109                 scratch_reg = R600_BIOS_0_SCRATCH;
4110         else
4111                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4112
4113         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4114                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4115 }
4116
4117 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4118 {
4119         uint32_t scratch_reg;
4120         int i;
4121
4122         if (rdev->family >= CHIP_R600)
4123                 scratch_reg = R600_BIOS_0_SCRATCH;
4124         else
4125                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4126
4127         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4128                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4129 }
4130
4131 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4132 {
4133         struct drm_device *dev = encoder->dev;
4134         struct radeon_device *rdev = dev->dev_private;
4135         uint32_t bios_6_scratch;
4136
4137         if (rdev->family >= CHIP_R600)
4138                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4139         else
4140                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4141
4142         if (lock) {
4143                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4144                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4145         } else {
4146                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4147                 bios_6_scratch |= ATOM_S6_ACC_MODE;
4148         }
4149
4150         if (rdev->family >= CHIP_R600)
4151                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4152         else
4153                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4154 }
4155
4156 /* at some point we may want to break this out into individual functions */
4157 void
4158 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4159                                        struct drm_encoder *encoder,
4160                                        bool connected)
4161 {
4162         struct drm_device *dev = connector->dev;
4163         struct radeon_device *rdev = dev->dev_private;
4164         struct radeon_connector *radeon_connector =
4165             to_radeon_connector(connector);
4166         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4167         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4168
4169         if (rdev->family >= CHIP_R600) {
4170                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4171                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4172                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4173         } else {
4174                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4175                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4176                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4177         }
4178
4179         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4180             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4181                 if (connected) {
4182                         DRM_DEBUG_KMS("TV1 connected\n");
4183                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4184                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4185                 } else {
4186                         DRM_DEBUG_KMS("TV1 disconnected\n");
4187                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4188                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4189                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4190                 }
4191         }
4192         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4193             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4194                 if (connected) {
4195                         DRM_DEBUG_KMS("CV connected\n");
4196                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4197                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4198                 } else {
4199                         DRM_DEBUG_KMS("CV disconnected\n");
4200                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
4201                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4202                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4203                 }
4204         }
4205         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4206             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4207                 if (connected) {
4208                         DRM_DEBUG_KMS("LCD1 connected\n");
4209                         bios_0_scratch |= ATOM_S0_LCD1;
4210                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4211                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4212                 } else {
4213                         DRM_DEBUG_KMS("LCD1 disconnected\n");
4214                         bios_0_scratch &= ~ATOM_S0_LCD1;
4215                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4216                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4217                 }
4218         }
4219         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4220             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4221                 if (connected) {
4222                         DRM_DEBUG_KMS("CRT1 connected\n");
4223                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4224                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4225                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4226                 } else {
4227                         DRM_DEBUG_KMS("CRT1 disconnected\n");
4228                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4229                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4230                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4231                 }
4232         }
4233         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4234             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4235                 if (connected) {
4236                         DRM_DEBUG_KMS("CRT2 connected\n");
4237                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4238                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4239                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4240                 } else {
4241                         DRM_DEBUG_KMS("CRT2 disconnected\n");
4242                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4243                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4244                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4245                 }
4246         }
4247         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4248             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4249                 if (connected) {
4250                         DRM_DEBUG_KMS("DFP1 connected\n");
4251                         bios_0_scratch |= ATOM_S0_DFP1;
4252                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4253                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4254                 } else {
4255                         DRM_DEBUG_KMS("DFP1 disconnected\n");
4256                         bios_0_scratch &= ~ATOM_S0_DFP1;
4257                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4258                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4259                 }
4260         }
4261         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4262             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4263                 if (connected) {
4264                         DRM_DEBUG_KMS("DFP2 connected\n");
4265                         bios_0_scratch |= ATOM_S0_DFP2;
4266                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4267                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4268                 } else {
4269                         DRM_DEBUG_KMS("DFP2 disconnected\n");
4270                         bios_0_scratch &= ~ATOM_S0_DFP2;
4271                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4272                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4273                 }
4274         }
4275         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4276             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4277                 if (connected) {
4278                         DRM_DEBUG_KMS("DFP3 connected\n");
4279                         bios_0_scratch |= ATOM_S0_DFP3;
4280                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4281                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4282                 } else {
4283                         DRM_DEBUG_KMS("DFP3 disconnected\n");
4284                         bios_0_scratch &= ~ATOM_S0_DFP3;
4285                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4286                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4287                 }
4288         }
4289         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4290             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4291                 if (connected) {
4292                         DRM_DEBUG_KMS("DFP4 connected\n");
4293                         bios_0_scratch |= ATOM_S0_DFP4;
4294                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4295                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4296                 } else {
4297                         DRM_DEBUG_KMS("DFP4 disconnected\n");
4298                         bios_0_scratch &= ~ATOM_S0_DFP4;
4299                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4300                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4301                 }
4302         }
4303         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4304             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4305                 if (connected) {
4306                         DRM_DEBUG_KMS("DFP5 connected\n");
4307                         bios_0_scratch |= ATOM_S0_DFP5;
4308                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4309                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4310                 } else {
4311                         DRM_DEBUG_KMS("DFP5 disconnected\n");
4312                         bios_0_scratch &= ~ATOM_S0_DFP5;
4313                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4314                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4315                 }
4316         }
4317         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4318             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4319                 if (connected) {
4320                         DRM_DEBUG_KMS("DFP6 connected\n");
4321                         bios_0_scratch |= ATOM_S0_DFP6;
4322                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4323                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4324                 } else {
4325                         DRM_DEBUG_KMS("DFP6 disconnected\n");
4326                         bios_0_scratch &= ~ATOM_S0_DFP6;
4327                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4328                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4329                 }
4330         }
4331
4332         if (rdev->family >= CHIP_R600) {
4333                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4334                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4335                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4336         } else {
4337                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4338                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4339                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4340         }
4341 }
4342
4343 void
4344 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4345 {
4346         struct drm_device *dev = encoder->dev;
4347         struct radeon_device *rdev = dev->dev_private;
4348         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4349         uint32_t bios_3_scratch;
4350
4351         if (ASIC_IS_DCE4(rdev))
4352                 return;
4353
4354         if (rdev->family >= CHIP_R600)
4355                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4356         else
4357                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4358
4359         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4360                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4361                 bios_3_scratch |= (crtc << 18);
4362         }
4363         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4364                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4365                 bios_3_scratch |= (crtc << 24);
4366         }
4367         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4368                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4369                 bios_3_scratch |= (crtc << 16);
4370         }
4371         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4372                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4373                 bios_3_scratch |= (crtc << 20);
4374         }
4375         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4376                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4377                 bios_3_scratch |= (crtc << 17);
4378         }
4379         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4380                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4381                 bios_3_scratch |= (crtc << 19);
4382         }
4383         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4384                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4385                 bios_3_scratch |= (crtc << 23);
4386         }
4387         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4388                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4389                 bios_3_scratch |= (crtc << 25);
4390         }
4391
4392         if (rdev->family >= CHIP_R600)
4393                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4394         else
4395                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4396 }
4397
4398 void
4399 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4400 {
4401         struct drm_device *dev = encoder->dev;
4402         struct radeon_device *rdev = dev->dev_private;
4403         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4404         uint32_t bios_2_scratch;
4405
4406         if (ASIC_IS_DCE4(rdev))
4407                 return;
4408
4409         if (rdev->family >= CHIP_R600)
4410                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4411         else
4412                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4413
4414         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4415                 if (on)
4416                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4417                 else
4418                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4419         }
4420         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4421                 if (on)
4422                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4423                 else
4424                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4425         }
4426         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4427                 if (on)
4428                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4429                 else
4430                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4431         }
4432         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4433                 if (on)
4434                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4435                 else
4436                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4437         }
4438         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4439                 if (on)
4440                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4441                 else
4442                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4443         }
4444         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4445                 if (on)
4446                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4447                 else
4448                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4449         }
4450         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4451                 if (on)
4452                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4453                 else
4454                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4455         }
4456         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4457                 if (on)
4458                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4459                 else
4460                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4461         }
4462         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4463                 if (on)
4464                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4465                 else
4466                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4467         }
4468         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4469                 if (on)
4470                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4471                 else
4472                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4473         }
4474
4475         if (rdev->family >= CHIP_R600)
4476                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4477         else
4478                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4479 }