drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_audio.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41 #include "radeon_ucode.h"
  42
  43 /* Firmware Names */
  44 /*(DEBLOBBED)*/
  45
  46 static const u32 crtc_offsets[2] =
  47 {
  48         0,
  49         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  50 };
  51
  52 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  53
  54 /* r600,rv610,rv630,rv620,rv635,rv670 */
  55 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  56 static void r600_gpu_init(struct radeon_device *rdev);
  57 void r600_fini(struct radeon_device *rdev);
  58 void r600_irq_disable(struct radeon_device *rdev);
  59 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  60 extern int evergreen_rlc_resume(struct radeon_device *rdev);
  61 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
  62
  63 /*
  64  * Indirect registers accessor
  65  */
  66 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
  67 {
  68         unsigned long flags;
  69         u32 r;
  70
  71         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  72         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  73         r = RREG32(R600_RCU_DATA);
  74         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  75         return r;
  76 }
  77
  78 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  79 {
  80         unsigned long flags;
  81
  82         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  83         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  84         WREG32(R600_RCU_DATA, (v));
  85         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  86 }
  87
  88 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
  89 {
  90         unsigned long flags;
  91         u32 r;
  92
  93         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
  94         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
  95         r = RREG32(R600_UVD_CTX_DATA);
  96         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
  97         return r;
  98 }
  99
 100 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 101 {
 102         unsigned long flags;
 103
 104         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 105         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 106         WREG32(R600_UVD_CTX_DATA, (v));
 107         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 108 }
 109
 110 /**
 111  * r600_get_allowed_info_register - fetch the register for the info ioctl
 112  *
 113  * @rdev: radeon_device pointer
 114  * @reg: register offset in bytes
 115  * @val: register value
 116  *
 117  * Returns 0 for success or -EINVAL for an invalid register
 118  *
 119  */
 120 int r600_get_allowed_info_register(struct radeon_device *rdev,
 121                                    u32 reg, u32 *val)
 122 {
 123         switch (reg) {
 124         case GRBM_STATUS:
 125         case GRBM_STATUS2:
 126         case R_000E50_SRBM_STATUS:
 127         case DMA_STATUS_REG:
 128         case UVD_STATUS:
 129                 *val = RREG32(reg);
 130                 return 0;
 131         default:
 132                 return -EINVAL;
 133         }
 134 }
 135
 136 /**
 137  * r600_get_xclk - get the xclk
 138  *
 139  * @rdev: radeon_device pointer
 140  *
 141  * Returns the reference clock used by the gfx engine
 142  * (r6xx, IGPs, APUs).
 143  */
 144 u32 r600_get_xclk(struct radeon_device *rdev)
 145 {
 146         return rdev->clock.spll.reference_freq;
 147 }
 148
 149 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 150 {
 151         unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
 152         int r;
 153
 154         /* bypass vclk and dclk with bclk */
 155         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 156                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
 157                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 158
 159         /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
 160         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
 161                  UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
 162
 163         if (rdev->family >= CHIP_RS780)
 164                 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
 165                          ~UPLL_BYPASS_CNTL);
 166
 167         if (!vclk || !dclk) {
 168                 /* keep the Bypass mode, put PLL to sleep */
 169                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
 170                 return 0;
 171         }
 172
 173         if (rdev->clock.spll.reference_freq == 10000)
 174                 ref_div = 34;
 175         else
 176                 ref_div = 4;
 177
 178         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
 179                                           ref_div + 1, 0xFFF, 2, 30, ~0,
 180                                           &fb_div, &vclk_div, &dclk_div);
 181         if (r)
 182                 return r;
 183
 184         if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
 185                 fb_div >>= 1;
 186         else
 187                 fb_div |= 1;
 188
 189         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 190         if (r)
 191                 return r;
 192
 193         /* assert PLL_RESET */
 194         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
 195
 196         /* For RS780 we have to choose ref clk */
 197         if (rdev->family >= CHIP_RS780)
 198                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
 199                          ~UPLL_REFCLK_SRC_SEL_MASK);
 200
 201         /* set the required fb, ref and post divder values */
 202         WREG32_P(CG_UPLL_FUNC_CNTL,
 203                  UPLL_FB_DIV(fb_div) |
 204                  UPLL_REF_DIV(ref_div),
 205                  ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
 206         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 207                  UPLL_SW_HILEN(vclk_div >> 1) |
 208                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
 209                  UPLL_SW_HILEN2(dclk_div >> 1) |
 210                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
 211                  UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
 212                  ~UPLL_SW_MASK);
 213
 214         /* give the PLL some time to settle */
 215         mdelay(15);
 216
 217         /* deassert PLL_RESET */
 218         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 219
 220         mdelay(15);
 221
 222         /* deassert BYPASS EN */
 223         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 224
 225         if (rdev->family >= CHIP_RS780)
 226                 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
 227
 228         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 229         if (r)
 230                 return r;
 231
 232         /* switch VCLK and DCLK selection */
 233         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 234                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 235                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 236
 237         mdelay(100);
 238
 239         return 0;
 240 }
 241
 242 void dce3_program_fmt(struct drm_encoder *encoder)
 243 {
 244         struct drm_device *dev = encoder->dev;
 245         struct radeon_device *rdev = dev->dev_private;
 246         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 247         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 248         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 249         int bpc = 0;
 250         u32 tmp = 0;
 251         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 252
 253         if (connector) {
 254                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 255                 bpc = radeon_get_monitor_bpc(connector);
 256                 dither = radeon_connector->dither;
 257         }
 258
 259         /* LVDS FMT is set up by atom */
 260         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 261                 return;
 262
 263         /* not needed for analog */
 264         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 265             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 266                 return;
 267
 268         if (bpc == 0)
 269                 return;
 270
 271         switch (bpc) {
 272         case 6:
 273                 if (dither == RADEON_FMT_DITHER_ENABLE)
 274                         /* XXX sort out optimal dither settings */
 275                         tmp |= FMT_SPATIAL_DITHER_EN;
 276                 else
 277                         tmp |= FMT_TRUNCATE_EN;
 278                 break;
 279         case 8:
 280                 if (dither == RADEON_FMT_DITHER_ENABLE)
 281                         /* XXX sort out optimal dither settings */
 282                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 283                 else
 284                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 285                 break;
 286         case 10:
 287         default:
 288                 /* not needed */
 289                 break;
 290         }
 291
 292         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 293 }
 294
 295 /* get temperature in millidegrees */
 296 int rv6xx_get_temp(struct radeon_device *rdev)
 297 {
 298         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 299                 ASIC_T_SHIFT;
 300         int actual_temp = temp & 0xff;
 301
 302         if (temp & 0x100)
 303                 actual_temp -= 256;
 304
 305         return actual_temp * 1000;
 306 }
 307
 308 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 309 {
 310         int i;
 311
 312         rdev->pm.dynpm_can_upclock = true;
 313         rdev->pm.dynpm_can_downclock = true;
 314
 315         /* power state array is low to high, default is first */
 316         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 317                 int min_power_state_index = 0;
 318
 319                 if (rdev->pm.num_power_states > 2)
 320                         min_power_state_index = 1;
 321
 322                 switch (rdev->pm.dynpm_planned_action) {
 323                 case DYNPM_ACTION_MINIMUM:
 324                         rdev->pm.requested_power_state_index = min_power_state_index;
 325                         rdev->pm.requested_clock_mode_index = 0;
 326                         rdev->pm.dynpm_can_downclock = false;
 327                         break;
 328                 case DYNPM_ACTION_DOWNCLOCK:
 329                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 330                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 331                                 rdev->pm.dynpm_can_downclock = false;
 332                         } else {
 333                                 if (rdev->pm.active_crtc_count > 1) {
 334                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 335                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 336                                                         continue;
 337                                                 else if (i >= rdev->pm.current_power_state_index) {
 338                                                         rdev->pm.requested_power_state_index =
 339                                                                 rdev->pm.current_power_state_index;
 340                                                         break;
 341                                                 } else {
 342                                                         rdev->pm.requested_power_state_index = i;
 343                                                         break;
 344                                                 }
 345                                         }
 346                                 } else {
 347                                         if (rdev->pm.current_power_state_index == 0)
 348                                                 rdev->pm.requested_power_state_index =
 349                                                         rdev->pm.num_power_states - 1;
 350                                         else
 351                                                 rdev->pm.requested_power_state_index =
 352                                                         rdev->pm.current_power_state_index - 1;
 353                                 }
 354                         }
 355                         rdev->pm.requested_clock_mode_index = 0;
 356                         /* don't use the power state if crtcs are active and no display flag is set */
 357                         if ((rdev->pm.active_crtc_count > 0) &&
 358                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 359                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 360                              RADEON_PM_MODE_NO_DISPLAY)) {
 361                                 rdev->pm.requested_power_state_index++;
 362                         }
 363                         break;
 364                 case DYNPM_ACTION_UPCLOCK:
 365                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 366                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 367                                 rdev->pm.dynpm_can_upclock = false;
 368                         } else {
 369                                 if (rdev->pm.active_crtc_count > 1) {
 370                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 371                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 372                                                         continue;
 373                                                 else if (i <= rdev->pm.current_power_state_index) {
 374                                                         rdev->pm.requested_power_state_index =
 375                                                                 rdev->pm.current_power_state_index;
 376                                                         break;
 377                                                 } else {
 378                                                         rdev->pm.requested_power_state_index = i;
 379                                                         break;
 380                                                 }
 381                                         }
 382                                 } else
 383                                         rdev->pm.requested_power_state_index =
 384                                                 rdev->pm.current_power_state_index + 1;
 385                         }
 386                         rdev->pm.requested_clock_mode_index = 0;
 387                         break;
 388                 case DYNPM_ACTION_DEFAULT:
 389                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 390                         rdev->pm.requested_clock_mode_index = 0;
 391                         rdev->pm.dynpm_can_upclock = false;
 392                         break;
 393                 case DYNPM_ACTION_NONE:
 394                 default:
 395                         DRM_ERROR("Requested mode for not defined action\n");
 396                         return;
 397                 }
 398         } else {
 399                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 400                 /* for now just select the first power state and switch between clock modes */
 401                 /* power state array is low to high, default is first (0) */
 402                 if (rdev->pm.active_crtc_count > 1) {
 403                         rdev->pm.requested_power_state_index = -1;
 404                         /* start at 1 as we don't want the default mode */
 405                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 406                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 407                                         continue;
 408                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 409                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 410                                         rdev->pm.requested_power_state_index = i;
 411                                         break;
 412                                 }
 413                         }
 414                         /* if nothing selected, grab the default state. */
 415                         if (rdev->pm.requested_power_state_index == -1)
 416                                 rdev->pm.requested_power_state_index = 0;
 417                 } else
 418                         rdev->pm.requested_power_state_index = 1;
 419
 420                 switch (rdev->pm.dynpm_planned_action) {
 421                 case DYNPM_ACTION_MINIMUM:
 422                         rdev->pm.requested_clock_mode_index = 0;
 423                         rdev->pm.dynpm_can_downclock = false;
 424                         break;
 425                 case DYNPM_ACTION_DOWNCLOCK:
 426                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 427                                 if (rdev->pm.current_clock_mode_index == 0) {
 428                                         rdev->pm.requested_clock_mode_index = 0;
 429                                         rdev->pm.dynpm_can_downclock = false;
 430                                 } else
 431                                         rdev->pm.requested_clock_mode_index =
 432                                                 rdev->pm.current_clock_mode_index - 1;
 433                         } else {
 434                                 rdev->pm.requested_clock_mode_index = 0;
 435                                 rdev->pm.dynpm_can_downclock = false;
 436                         }
 437                         /* don't use the power state if crtcs are active and no display flag is set */
 438                         if ((rdev->pm.active_crtc_count > 0) &&
 439                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 440                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 441                              RADEON_PM_MODE_NO_DISPLAY)) {
 442                                 rdev->pm.requested_clock_mode_index++;
 443                         }
 444                         break;
 445                 case DYNPM_ACTION_UPCLOCK:
 446                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 447                                 if (rdev->pm.current_clock_mode_index ==
 448                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 449                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 450                                         rdev->pm.dynpm_can_upclock = false;
 451                                 } else
 452                                         rdev->pm.requested_clock_mode_index =
 453                                                 rdev->pm.current_clock_mode_index + 1;
 454                         } else {
 455                                 rdev->pm.requested_clock_mode_index =
 456                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 457                                 rdev->pm.dynpm_can_upclock = false;
 458                         }
 459                         break;
 460                 case DYNPM_ACTION_DEFAULT:
 461                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 462                         rdev->pm.requested_clock_mode_index = 0;
 463                         rdev->pm.dynpm_can_upclock = false;
 464                         break;
 465                 case DYNPM_ACTION_NONE:
 466                 default:
 467                         DRM_ERROR("Requested mode for not defined action\n");
 468                         return;
 469                 }
 470         }
 471
 472         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 473                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 474                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 475                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 476                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 477                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 478                   pcie_lanes);
 479 }
 480
 481 void rs780_pm_init_profile(struct radeon_device *rdev)
 482 {
 483         if (rdev->pm.num_power_states == 2) {
 484                 /* default */
 485                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 486                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 487                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 488                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 489                 /* low sh */
 490                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 491                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 492                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 493                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 494                 /* mid sh */
 495                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 496                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 497                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 498                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 499                 /* high sh */
 500                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 501                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 502                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 503                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 504                 /* low mh */
 505                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 506                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 507                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 508                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 509                 /* mid mh */
 510                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 511                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 512                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 513                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 514                 /* high mh */
 515                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 516                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 517                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 518                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 519         } else if (rdev->pm.num_power_states == 3) {
 520                 /* default */
 521                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 522                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 523                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 524                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 525                 /* low sh */
 526                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 527                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 528                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 529                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 530                 /* mid sh */
 531                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 532                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 533                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 534                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 535                 /* high sh */
 536                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 537                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 538                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 539                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 540                 /* low mh */
 541                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 542                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 543                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 544                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 545                 /* mid mh */
 546                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 547                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 548                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 549                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 550                 /* high mh */
 551                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 552                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 553                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 554                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 555         } else {
 556                 /* default */
 557                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 558                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 559                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 560                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 561                 /* low sh */
 562                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 563                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 564                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 565                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 566                 /* mid sh */
 567                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 568                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 569                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 570                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 571                 /* high sh */
 572                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 573                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 574                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 575                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 576                 /* low mh */
 577                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 578                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 579                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 580                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 581                 /* mid mh */
 582                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 583                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 584                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 585                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 586                 /* high mh */
 587                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 588                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 589                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 590                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 591         }
 592 }
 593
 594 void r600_pm_init_profile(struct radeon_device *rdev)
 595 {
 596         int idx;
 597
 598         if (rdev->family == CHIP_R600) {
 599                 /* XXX */
 600                 /* default */
 601                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 602                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 603                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 604                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 605                 /* low sh */
 606                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 607                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 608                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 609                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 610                 /* mid sh */
 611                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 612                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 613                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 614                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 615                 /* high sh */
 616                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 617                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 618                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 619                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 620                 /* low mh */
 621                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 622                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 623                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 624                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 625                 /* mid mh */
 626                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 627                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 628                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 629                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 630                 /* high mh */
 631                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 632                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 633                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 634                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 635         } else {
 636                 if (rdev->pm.num_power_states < 4) {
 637                         /* default */
 638                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 639                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 640                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 641                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 642                         /* low sh */
 643                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 644                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 645                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 646                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 647                         /* mid sh */
 648                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 649                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 650                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 651                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 652                         /* high sh */
 653                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 654                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 655                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 656                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 657                         /* low mh */
 658                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 659                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 660                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 661                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 662                         /* low mh */
 663                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 664                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 665                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 666                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 667                         /* high mh */
 668                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 669                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 670                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 671                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 672                 } else {
 673                         /* default */
 674                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 675                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 676                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 677                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 678                         /* low sh */
 679                         if (rdev->flags & RADEON_IS_MOBILITY)
 680                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 681                         else
 682                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 683                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 684                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 685                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 686                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 687                         /* mid sh */
 688                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 689                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 690                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 691                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 692                         /* high sh */
 693                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 694                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 695                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 696                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 697                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 698                         /* low mh */
 699                         if (rdev->flags & RADEON_IS_MOBILITY)
 700                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 701                         else
 702                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 703                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 704                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 705                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 706                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 707                         /* mid mh */
 708                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 709                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 710                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 711                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 712                         /* high mh */
 713                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 714                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 715                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 716                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 717                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 718                 }
 719         }
 720 }
 721
 722 void r600_pm_misc(struct radeon_device *rdev)
 723 {
 724         int req_ps_idx = rdev->pm.requested_power_state_index;
 725         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 726         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 727         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 728
 729         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 730                 /* 0xff01 is a flag rather then an actual voltage */
 731                 if (voltage->voltage == 0xff01)
 732                         return;
 733                 if (voltage->voltage != rdev->pm.current_vddc) {
 734                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 735                         rdev->pm.current_vddc = voltage->voltage;
 736                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 737                 }
 738         }
 739 }
 740
 741 bool r600_gui_idle(struct radeon_device *rdev)
 742 {
 743         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 744                 return false;
 745         else
 746                 return true;
 747 }
 748
 749 /* hpd for digital panel detect/disconnect */
 750 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 751 {
 752         bool connected = false;
 753
 754         if (ASIC_IS_DCE3(rdev)) {
 755                 switch (hpd) {
 756                 case RADEON_HPD_1:
 757                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 758                                 connected = true;
 759                         break;
 760                 case RADEON_HPD_2:
 761                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 762                                 connected = true;
 763                         break;
 764                 case RADEON_HPD_3:
 765                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 766                                 connected = true;
 767                         break;
 768                 case RADEON_HPD_4:
 769                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 770                                 connected = true;
 771                         break;
 772                         /* DCE 3.2 */
 773                 case RADEON_HPD_5:
 774                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 775                                 connected = true;
 776                         break;
 777                 case RADEON_HPD_6:
 778                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 779                                 connected = true;
 780                         break;
 781                 default:
 782                         break;
 783                 }
 784         } else {
 785                 switch (hpd) {
 786                 case RADEON_HPD_1:
 787                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 788                                 connected = true;
 789                         break;
 790                 case RADEON_HPD_2:
 791                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 792                                 connected = true;
 793                         break;
 794                 case RADEON_HPD_3:
 795                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 796                                 connected = true;
 797                         break;
 798                 default:
 799                         break;
 800                 }
 801         }
 802         return connected;
 803 }
 804
 805 void r600_hpd_set_polarity(struct radeon_device *rdev,
 806                            enum radeon_hpd_id hpd)
 807 {
 808         u32 tmp;
 809         bool connected = r600_hpd_sense(rdev, hpd);
 810
 811         if (ASIC_IS_DCE3(rdev)) {
 812                 switch (hpd) {
 813                 case RADEON_HPD_1:
 814                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 815                         if (connected)
 816                                 tmp &= ~DC_HPDx_INT_POLARITY;
 817                         else
 818                                 tmp |= DC_HPDx_INT_POLARITY;
 819                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 820                         break;
 821                 case RADEON_HPD_2:
 822                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 823                         if (connected)
 824                                 tmp &= ~DC_HPDx_INT_POLARITY;
 825                         else
 826                                 tmp |= DC_HPDx_INT_POLARITY;
 827                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 828                         break;
 829                 case RADEON_HPD_3:
 830                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 831                         if (connected)
 832                                 tmp &= ~DC_HPDx_INT_POLARITY;
 833                         else
 834                                 tmp |= DC_HPDx_INT_POLARITY;
 835                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 836                         break;
 837                 case RADEON_HPD_4:
 838                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 839                         if (connected)
 840                                 tmp &= ~DC_HPDx_INT_POLARITY;
 841                         else
 842                                 tmp |= DC_HPDx_INT_POLARITY;
 843                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 844                         break;
 845                 case RADEON_HPD_5:
 846                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 847                         if (connected)
 848                                 tmp &= ~DC_HPDx_INT_POLARITY;
 849                         else
 850                                 tmp |= DC_HPDx_INT_POLARITY;
 851                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 852                         break;
 853                         /* DCE 3.2 */
 854                 case RADEON_HPD_6:
 855                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 856                         if (connected)
 857                                 tmp &= ~DC_HPDx_INT_POLARITY;
 858                         else
 859                                 tmp |= DC_HPDx_INT_POLARITY;
 860                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 861                         break;
 862                 default:
 863                         break;
 864                 }
 865         } else {
 866                 switch (hpd) {
 867                 case RADEON_HPD_1:
 868                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 869                         if (connected)
 870                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 871                         else
 872                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 873                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 874                         break;
 875                 case RADEON_HPD_2:
 876                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 877                         if (connected)
 878                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 879                         else
 880                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 881                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 882                         break;
 883                 case RADEON_HPD_3:
 884                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 885                         if (connected)
 886                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 887                         else
 888                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 889                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 890                         break;
 891                 default:
 892                         break;
 893                 }
 894         }
 895 }
 896
 897 void r600_hpd_init(struct radeon_device *rdev)
 898 {
 899         struct drm_device *dev = rdev->ddev;
 900         struct drm_connector *connector;
 901         unsigned enable = 0;
 902
 903         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 904                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 905
 906                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 907                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 908                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 909                          * aux dp channel on imac and help (but not completely fix)
 910                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 911                          */
 912                         continue;
 913                 }
 914                 if (ASIC_IS_DCE3(rdev)) {
 915                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 916                         if (ASIC_IS_DCE32(rdev))
 917                                 tmp |= DC_HPDx_EN;
 918
 919                         switch (radeon_connector->hpd.hpd) {
 920                         case RADEON_HPD_1:
 921                                 WREG32(DC_HPD1_CONTROL, tmp);
 922                                 break;
 923                         case RADEON_HPD_2:
 924                                 WREG32(DC_HPD2_CONTROL, tmp);
 925                                 break;
 926                         case RADEON_HPD_3:
 927                                 WREG32(DC_HPD3_CONTROL, tmp);
 928                                 break;
 929                         case RADEON_HPD_4:
 930                                 WREG32(DC_HPD4_CONTROL, tmp);
 931                                 break;
 932                                 /* DCE 3.2 */
 933                         case RADEON_HPD_5:
 934                                 WREG32(DC_HPD5_CONTROL, tmp);
 935                                 break;
 936                         case RADEON_HPD_6:
 937                                 WREG32(DC_HPD6_CONTROL, tmp);
 938                                 break;
 939                         default:
 940                                 break;
 941                         }
 942                 } else {
 943                         switch (radeon_connector->hpd.hpd) {
 944                         case RADEON_HPD_1:
 945                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 946                                 break;
 947                         case RADEON_HPD_2:
 948                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 949                                 break;
 950                         case RADEON_HPD_3:
 951                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 952                                 break;
 953                         default:
 954                                 break;
 955                         }
 956                 }
 957                 enable |= 1 << radeon_connector->hpd.hpd;
 958                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 959         }
 960         radeon_irq_kms_enable_hpd(rdev, enable);
 961 }
 962
 963 void r600_hpd_fini(struct radeon_device *rdev)
 964 {
 965         struct drm_device *dev = rdev->ddev;
 966         struct drm_connector *connector;
 967         unsigned disable = 0;
 968
 969         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 970                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 971                 if (ASIC_IS_DCE3(rdev)) {
 972                         switch (radeon_connector->hpd.hpd) {
 973                         case RADEON_HPD_1:
 974                                 WREG32(DC_HPD1_CONTROL, 0);
 975                                 break;
 976                         case RADEON_HPD_2:
 977                                 WREG32(DC_HPD2_CONTROL, 0);
 978                                 break;
 979                         case RADEON_HPD_3:
 980                                 WREG32(DC_HPD3_CONTROL, 0);
 981                                 break;
 982                         case RADEON_HPD_4:
 983                                 WREG32(DC_HPD4_CONTROL, 0);
 984                                 break;
 985                                 /* DCE 3.2 */
 986                         case RADEON_HPD_5:
 987                                 WREG32(DC_HPD5_CONTROL, 0);
 988                                 break;
 989                         case RADEON_HPD_6:
 990                                 WREG32(DC_HPD6_CONTROL, 0);
 991                                 break;
 992                         default:
 993                                 break;
 994                         }
 995                 } else {
 996                         switch (radeon_connector->hpd.hpd) {
 997                         case RADEON_HPD_1:
 998                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 999                                 break;
1000                         case RADEON_HPD_2:
1001                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1002                                 break;
1003                         case RADEON_HPD_3:
1004                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1005                                 break;
1006                         default:
1007                                 break;
1008                         }
1009                 }
1010                 disable |= 1 << radeon_connector->hpd.hpd;
1011         }
1012         radeon_irq_kms_disable_hpd(rdev, disable);
1013 }
1014
1015 /*
1016  * R600 PCIE GART
1017  */
1018 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1019 {
1020         unsigned i;
1021         u32 tmp;
1022
1023         /* flush hdp cache so updates hit vram */
1024         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1025             !(rdev->flags & RADEON_IS_AGP)) {
1026                 void __iomem *ptr = (void *)rdev->gart.ptr;
1027                 u32 tmp;
1028
1029                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
1030                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1031                  * This seems to cause problems on some AGP cards. Just use the old
1032                  * method for them.
1033                  */
1034                 WREG32(HDP_DEBUG1, 0);
1035                 tmp = readl((void __iomem *)ptr);
1036         } else
1037                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1038
1039         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1040         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1041         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1042         for (i = 0; i < rdev->usec_timeout; i++) {
1043                 /* read MC_STATUS */
1044                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1045                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1046                 if (tmp == 2) {
1047                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1048                         return;
1049                 }
1050                 if (tmp) {
1051                         return;
1052                 }
1053                 udelay(1);
1054         }
1055 }
1056
1057 int r600_pcie_gart_init(struct radeon_device *rdev)
1058 {
1059         int r;
1060
1061         if (rdev->gart.robj) {
1062                 WARN(1, "R600 PCIE GART already initialized\n");
1063                 return 0;
1064         }
1065         /* Initialize common gart structure */
1066         r = radeon_gart_init(rdev);
1067         if (r)
1068                 return r;
1069         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1070         return radeon_gart_table_vram_alloc(rdev);
1071 }
1072
1073 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1074 {
1075         u32 tmp;
1076         int r, i;
1077
1078         if (rdev->gart.robj == NULL) {
1079                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1080                 return -EINVAL;
1081         }
1082         r = radeon_gart_table_vram_pin(rdev);
1083         if (r)
1084                 return r;
1085
1086         /* Setup L2 cache */
1087         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1088                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1089                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1090         WREG32(VM_L2_CNTL2, 0);
1091         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1092         /* Setup TLB control */
1093         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1094                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1095                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1096                 ENABLE_WAIT_L2_QUERY;
1097         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1098         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1099         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1100         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1101         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1102         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1103         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1104         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1105         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1106         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1107         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1108         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1109         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1110         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1111         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1112         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1113         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1114         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1115         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1116         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1117                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1118         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1119                         (u32)(rdev->dummy_page.addr >> 12));
1120         for (i = 1; i < 7; i++)
1121                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1122
1123         r600_pcie_gart_tlb_flush(rdev);
1124         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1125                  (unsigned)(rdev->mc.gtt_size >> 20),
1126                  (unsigned long long)rdev->gart.table_addr);
1127         rdev->gart.ready = true;
1128         return 0;
1129 }
1130
1131 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1132 {
1133         u32 tmp;
1134         int i;
1135
1136         /* Disable all tables */
1137         for (i = 0; i < 7; i++)
1138                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1139
1140         /* Disable L2 cache */
1141         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1142                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1143         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1144         /* Setup L1 TLB control */
1145         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1146                 ENABLE_WAIT_L2_QUERY;
1147         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1148         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1149         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1150         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1151         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1152         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1153         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1154         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1155         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1156         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1157         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1158         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1159         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1160         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1161         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1162         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1163         radeon_gart_table_vram_unpin(rdev);
1164 }
1165
1166 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1167 {
1168         radeon_gart_fini(rdev);
1169         r600_pcie_gart_disable(rdev);
1170         radeon_gart_table_vram_free(rdev);
1171 }
1172
1173 static void r600_agp_enable(struct radeon_device *rdev)
1174 {
1175         u32 tmp;
1176         int i;
1177
1178         /* Setup L2 cache */
1179         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1180                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1181                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1182         WREG32(VM_L2_CNTL2, 0);
1183         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1184         /* Setup TLB control */
1185         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1186                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1187                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1188                 ENABLE_WAIT_L2_QUERY;
1189         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1190         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1191         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1192         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1193         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1194         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1195         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1196         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1197         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1198         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1199         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1200         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1201         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1202         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1203         for (i = 0; i < 7; i++)
1204                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1205 }
1206
1207 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1208 {
1209         unsigned i;
1210         u32 tmp;
1211
1212         for (i = 0; i < rdev->usec_timeout; i++) {
1213                 /* read MC_STATUS */
1214                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1215                 if (!tmp)
1216                         return 0;
1217                 udelay(1);
1218         }
1219         return -1;
1220 }
1221
1222 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1223 {
1224         unsigned long flags;
1225         uint32_t r;
1226
1227         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1228         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1229         r = RREG32(R_0028FC_MC_DATA);
1230         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1231         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1232         return r;
1233 }
1234
1235 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1236 {
1237         unsigned long flags;
1238
1239         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1240         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1241                 S_0028F8_MC_IND_WR_EN(1));
1242         WREG32(R_0028FC_MC_DATA, v);
1243         WREG32(R_0028F8_MC_INDEX, 0x7F);
1244         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1245 }
1246
1247 static void r600_mc_program(struct radeon_device *rdev)
1248 {
1249         struct rv515_mc_save save;
1250         u32 tmp;
1251         int i, j;
1252
1253         /* Initialize HDP */
1254         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1255                 WREG32((0x2c14 + j), 0x00000000);
1256                 WREG32((0x2c18 + j), 0x00000000);
1257                 WREG32((0x2c1c + j), 0x00000000);
1258                 WREG32((0x2c20 + j), 0x00000000);
1259                 WREG32((0x2c24 + j), 0x00000000);
1260         }
1261         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1262
1263         rv515_mc_stop(rdev, &save);
1264         if (r600_mc_wait_for_idle(rdev)) {
1265                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1266         }
1267         /* Lockout access through VGA aperture (doesn't exist before R600) */
1268         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1269         /* Update configuration */
1270         if (rdev->flags & RADEON_IS_AGP) {
1271                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1272                         /* VRAM before AGP */
1273                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1274                                 rdev->mc.vram_start >> 12);
1275                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1276                                 rdev->mc.gtt_end >> 12);
1277                 } else {
1278                         /* VRAM after AGP */
1279                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1280                                 rdev->mc.gtt_start >> 12);
1281                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1282                                 rdev->mc.vram_end >> 12);
1283                 }
1284         } else {
1285                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1286                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1287         }
1288         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1289         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1290         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1291         WREG32(MC_VM_FB_LOCATION, tmp);
1292         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1293         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1294         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1295         if (rdev->flags & RADEON_IS_AGP) {
1296                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1297                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1298                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1299         } else {
1300                 WREG32(MC_VM_AGP_BASE, 0);
1301                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1302                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1303         }
1304         if (r600_mc_wait_for_idle(rdev)) {
1305                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1306         }
1307         rv515_mc_resume(rdev, &save);
1308         /* we need to own VRAM, so turn off the VGA renderer here
1309          * to stop it overwriting our objects */
1310         rv515_vga_render_disable(rdev);
1311 }
1312
1313 /**
1314  * r600_vram_gtt_location - try to find VRAM & GTT location
1315  * @rdev: radeon device structure holding all necessary informations
1316  * @mc: memory controller structure holding memory informations
1317  *
1318  * Function will place try to place VRAM at same place as in CPU (PCI)
1319  * address space as some GPU seems to have issue when we reprogram at
1320  * different address space.
1321  *
1322  * If there is not enough space to fit the unvisible VRAM after the
1323  * aperture then we limit the VRAM size to the aperture.
1324  *
1325  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1326  * them to be in one from GPU point of view so that we can program GPU to
1327  * catch access outside them (weird GPU policy see ??).
1328  *
1329  * This function will never fails, worst case are limiting VRAM or GTT.
1330  *
1331  * Note: GTT start, end, size should be initialized before calling this
1332  * function on AGP platform.
1333  */
1334 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1335 {
1336         u64 size_bf, size_af;
1337
1338         if (mc->mc_vram_size > 0xE0000000) {
1339                 /* leave room for at least 512M GTT */
1340                 dev_warn(rdev->dev, "limiting VRAM\n");
1341                 mc->real_vram_size = 0xE0000000;
1342                 mc->mc_vram_size = 0xE0000000;
1343         }
1344         if (rdev->flags & RADEON_IS_AGP) {
1345                 size_bf = mc->gtt_start;
1346                 size_af = mc->mc_mask - mc->gtt_end;
1347                 if (size_bf > size_af) {
1348                         if (mc->mc_vram_size > size_bf) {
1349                                 dev_warn(rdev->dev, "limiting VRAM\n");
1350                                 mc->real_vram_size = size_bf;
1351                                 mc->mc_vram_size = size_bf;
1352                         }
1353                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1354                 } else {
1355                         if (mc->mc_vram_size > size_af) {
1356                                 dev_warn(rdev->dev, "limiting VRAM\n");
1357                                 mc->real_vram_size = size_af;
1358                                 mc->mc_vram_size = size_af;
1359                         }
1360                         mc->vram_start = mc->gtt_end + 1;
1361                 }
1362                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1363                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1364                                 mc->mc_vram_size >> 20, mc->vram_start,
1365                                 mc->vram_end, mc->real_vram_size >> 20);
1366         } else {
1367                 u64 base = 0;
1368                 if (rdev->flags & RADEON_IS_IGP) {
1369                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1370                         base <<= 24;
1371                 }
1372                 radeon_vram_location(rdev, &rdev->mc, base);
1373                 rdev->mc.gtt_base_align = 0;
1374                 radeon_gtt_location(rdev, mc);
1375         }
1376 }
1377
1378 static int r600_mc_init(struct radeon_device *rdev)
1379 {
1380         u32 tmp;
1381         int chansize, numchan;
1382         uint32_t h_addr, l_addr;
1383         unsigned long long k8_addr;
1384
1385         /* Get VRAM informations */
1386         rdev->mc.vram_is_ddr = true;
1387         tmp = RREG32(RAMCFG);
1388         if (tmp & CHANSIZE_OVERRIDE) {
1389                 chansize = 16;
1390         } else if (tmp & CHANSIZE_MASK) {
1391                 chansize = 64;
1392         } else {
1393                 chansize = 32;
1394         }
1395         tmp = RREG32(CHMAP);
1396         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1397         case 0:
1398         default:
1399                 numchan = 1;
1400                 break;
1401         case 1:
1402                 numchan = 2;
1403                 break;
1404         case 2:
1405                 numchan = 4;
1406                 break;
1407         case 3:
1408                 numchan = 8;
1409                 break;
1410         }
1411         rdev->mc.vram_width = numchan * chansize;
1412         /* Could aper size report 0 ? */
1413         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1414         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1415         /* Setup GPU memory space */
1416         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1417         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1418         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1419         r600_vram_gtt_location(rdev, &rdev->mc);
1420
1421         if (rdev->flags & RADEON_IS_IGP) {
1422                 rs690_pm_info(rdev);
1423                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1424
1425                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1426                         /* Use K8 direct mapping for fast fb access. */
1427                         rdev->fastfb_working = false;
1428                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1429                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1430                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1431 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1432                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1433 #endif
1434                         {
1435                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1436                                 * memory is present.
1437                                 */
1438                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1439                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1440                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1441                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1442                                         rdev->fastfb_working = true;
1443                                 }
1444                         }
1445                 }
1446         }
1447
1448         radeon_update_bandwidth_info(rdev);
1449         return 0;
1450 }
1451
1452 int r600_vram_scratch_init(struct radeon_device *rdev)
1453 {
1454         int r;
1455
1456         if (rdev->vram_scratch.robj == NULL) {
1457                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1458                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1459                                      0, NULL, NULL, &rdev->vram_scratch.robj);
1460                 if (r) {
1461                         return r;
1462                 }
1463         }
1464
1465         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1466         if (unlikely(r != 0))
1467                 return r;
1468         r = radeon_bo_pin(rdev->vram_scratch.robj,
1469                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1470         if (r) {
1471                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1472                 return r;
1473         }
1474         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1475                                 (void **)&rdev->vram_scratch.ptr);
1476         if (r)
1477                 radeon_bo_unpin(rdev->vram_scratch.robj);
1478         radeon_bo_unreserve(rdev->vram_scratch.robj);
1479
1480         return r;
1481 }
1482
1483 void r600_vram_scratch_fini(struct radeon_device *rdev)
1484 {
1485         int r;
1486
1487         if (rdev->vram_scratch.robj == NULL) {
1488                 return;
1489         }
1490         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1491         if (likely(r == 0)) {
1492                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1493                 radeon_bo_unpin(rdev->vram_scratch.robj);
1494                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1495         }
1496         radeon_bo_unref(&rdev->vram_scratch.robj);
1497 }
1498
1499 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1500 {
1501         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1502
1503         if (hung)
1504                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1505         else
1506                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1507
1508         WREG32(R600_BIOS_3_SCRATCH, tmp);
1509 }
1510
1511 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1512 {
1513         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1514                  RREG32(R_008010_GRBM_STATUS));
1515         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1516                  RREG32(R_008014_GRBM_STATUS2));
1517         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1518                  RREG32(R_000E50_SRBM_STATUS));
1519         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1520                  RREG32(CP_STALLED_STAT1));
1521         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1522                  RREG32(CP_STALLED_STAT2));
1523         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1524                  RREG32(CP_BUSY_STAT));
1525         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1526                  RREG32(CP_STAT));
1527         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1528                 RREG32(DMA_STATUS_REG));
1529 }
1530
1531 static bool r600_is_display_hung(struct radeon_device *rdev)
1532 {
1533         u32 crtc_hung = 0;
1534         u32 crtc_status[2];
1535         u32 i, j, tmp;
1536
1537         for (i = 0; i < rdev->num_crtc; i++) {
1538                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1539                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1540                         crtc_hung |= (1 << i);
1541                 }
1542         }
1543
1544         for (j = 0; j < 10; j++) {
1545                 for (i = 0; i < rdev->num_crtc; i++) {
1546                         if (crtc_hung & (1 << i)) {
1547                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1548                                 if (tmp != crtc_status[i])
1549                                         crtc_hung &= ~(1 << i);
1550                         }
1551                 }
1552                 if (crtc_hung == 0)
1553                         return false;
1554                 udelay(100);
1555         }
1556
1557         return true;
1558 }
1559
1560 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1561 {
1562         u32 reset_mask = 0;
1563         u32 tmp;
1564
1565         /* GRBM_STATUS */
1566         tmp = RREG32(R_008010_GRBM_STATUS);
1567         if (rdev->family >= CHIP_RV770) {
1568                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1569                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1570                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1571                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1572                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1573                         reset_mask |= RADEON_RESET_GFX;
1574         } else {
1575                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1576                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1577                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1578                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1579                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1580                         reset_mask |= RADEON_RESET_GFX;
1581         }
1582
1583         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1584             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1585                 reset_mask |= RADEON_RESET_CP;
1586
1587         if (G_008010_GRBM_EE_BUSY(tmp))
1588                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1589
1590         /* DMA_STATUS_REG */
1591         tmp = RREG32(DMA_STATUS_REG);
1592         if (!(tmp & DMA_IDLE))
1593                 reset_mask |= RADEON_RESET_DMA;
1594
1595         /* SRBM_STATUS */
1596         tmp = RREG32(R_000E50_SRBM_STATUS);
1597         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1598                 reset_mask |= RADEON_RESET_RLC;
1599
1600         if (G_000E50_IH_BUSY(tmp))
1601                 reset_mask |= RADEON_RESET_IH;
1602
1603         if (G_000E50_SEM_BUSY(tmp))
1604                 reset_mask |= RADEON_RESET_SEM;
1605
1606         if (G_000E50_GRBM_RQ_PENDING(tmp))
1607                 reset_mask |= RADEON_RESET_GRBM;
1608
1609         if (G_000E50_VMC_BUSY(tmp))
1610                 reset_mask |= RADEON_RESET_VMC;
1611
1612         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1613             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1614             G_000E50_MCDW_BUSY(tmp))
1615                 reset_mask |= RADEON_RESET_MC;
1616
1617         if (r600_is_display_hung(rdev))
1618                 reset_mask |= RADEON_RESET_DISPLAY;
1619
1620         /* Skip MC reset as it's mostly likely not hung, just busy */
1621         if (reset_mask & RADEON_RESET_MC) {
1622                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1623                 reset_mask &= ~RADEON_RESET_MC;
1624         }
1625
1626         return reset_mask;
1627 }
1628
1629 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1630 {
1631         struct rv515_mc_save save;
1632         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1633         u32 tmp;
1634
1635         if (reset_mask == 0)
1636                 return;
1637
1638         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1639
1640         r600_print_gpu_status_regs(rdev);
1641
1642         /* Disable CP parsing/prefetching */
1643         if (rdev->family >= CHIP_RV770)
1644                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1645         else
1646                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1647
1648         /* disable the RLC */
1649         WREG32(RLC_CNTL, 0);
1650
1651         if (reset_mask & RADEON_RESET_DMA) {
1652                 /* Disable DMA */
1653                 tmp = RREG32(DMA_RB_CNTL);
1654                 tmp &= ~DMA_RB_ENABLE;
1655                 WREG32(DMA_RB_CNTL, tmp);
1656         }
1657
1658         mdelay(50);
1659
1660         rv515_mc_stop(rdev, &save);
1661         if (r600_mc_wait_for_idle(rdev)) {
1662                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1663         }
1664
1665         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1666                 if (rdev->family >= CHIP_RV770)
1667                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1668                                 S_008020_SOFT_RESET_CB(1) |
1669                                 S_008020_SOFT_RESET_PA(1) |
1670                                 S_008020_SOFT_RESET_SC(1) |
1671                                 S_008020_SOFT_RESET_SPI(1) |
1672                                 S_008020_SOFT_RESET_SX(1) |
1673                                 S_008020_SOFT_RESET_SH(1) |
1674                                 S_008020_SOFT_RESET_TC(1) |
1675                                 S_008020_SOFT_RESET_TA(1) |
1676                                 S_008020_SOFT_RESET_VC(1) |
1677                                 S_008020_SOFT_RESET_VGT(1);
1678                 else
1679                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1680                                 S_008020_SOFT_RESET_DB(1) |
1681                                 S_008020_SOFT_RESET_CB(1) |
1682                                 S_008020_SOFT_RESET_PA(1) |
1683                                 S_008020_SOFT_RESET_SC(1) |
1684                                 S_008020_SOFT_RESET_SMX(1) |
1685                                 S_008020_SOFT_RESET_SPI(1) |
1686                                 S_008020_SOFT_RESET_SX(1) |
1687                                 S_008020_SOFT_RESET_SH(1) |
1688                                 S_008020_SOFT_RESET_TC(1) |
1689                                 S_008020_SOFT_RESET_TA(1) |
1690                                 S_008020_SOFT_RESET_VC(1) |
1691                                 S_008020_SOFT_RESET_VGT(1);
1692         }
1693
1694         if (reset_mask & RADEON_RESET_CP) {
1695                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1696                         S_008020_SOFT_RESET_VGT(1);
1697
1698                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1699         }
1700
1701         if (reset_mask & RADEON_RESET_DMA) {
1702                 if (rdev->family >= CHIP_RV770)
1703                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1704                 else
1705                         srbm_soft_reset |= SOFT_RESET_DMA;
1706         }
1707
1708         if (reset_mask & RADEON_RESET_RLC)
1709                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1710
1711         if (reset_mask & RADEON_RESET_SEM)
1712                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1713
1714         if (reset_mask & RADEON_RESET_IH)
1715                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1716
1717         if (reset_mask & RADEON_RESET_GRBM)
1718                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1719
1720         if (!(rdev->flags & RADEON_IS_IGP)) {
1721                 if (reset_mask & RADEON_RESET_MC)
1722                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1723         }
1724
1725         if (reset_mask & RADEON_RESET_VMC)
1726                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1727
1728         if (grbm_soft_reset) {
1729                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1730                 tmp |= grbm_soft_reset;
1731                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1732                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1733                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1734
1735                 udelay(50);
1736
1737                 tmp &= ~grbm_soft_reset;
1738                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1739                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1740         }
1741
1742         if (srbm_soft_reset) {
1743                 tmp = RREG32(SRBM_SOFT_RESET);
1744                 tmp |= srbm_soft_reset;
1745                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1746                 WREG32(SRBM_SOFT_RESET, tmp);
1747                 tmp = RREG32(SRBM_SOFT_RESET);
1748
1749                 udelay(50);
1750
1751                 tmp &= ~srbm_soft_reset;
1752                 WREG32(SRBM_SOFT_RESET, tmp);
1753                 tmp = RREG32(SRBM_SOFT_RESET);
1754         }
1755
1756         /* Wait a little for things to settle down */
1757         mdelay(1);
1758
1759         rv515_mc_resume(rdev, &save);
1760         udelay(50);
1761
1762         r600_print_gpu_status_regs(rdev);
1763 }
1764
1765 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1766 {
1767         struct rv515_mc_save save;
1768         u32 tmp, i;
1769
1770         dev_info(rdev->dev, "GPU pci config reset\n");
1771
1772         /* disable dpm? */
1773
1774         /* Disable CP parsing/prefetching */
1775         if (rdev->family >= CHIP_RV770)
1776                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1777         else
1778                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1779
1780         /* disable the RLC */
1781         WREG32(RLC_CNTL, 0);
1782
1783         /* Disable DMA */
1784         tmp = RREG32(DMA_RB_CNTL);
1785         tmp &= ~DMA_RB_ENABLE;
1786         WREG32(DMA_RB_CNTL, tmp);
1787
1788         mdelay(50);
1789
1790         /* set mclk/sclk to bypass */
1791         if (rdev->family >= CHIP_RV770)
1792                 rv770_set_clk_bypass_mode(rdev);
1793         /* disable BM */
1794         pci_clear_master(rdev->pdev);
1795         /* disable mem access */
1796         rv515_mc_stop(rdev, &save);
1797         if (r600_mc_wait_for_idle(rdev)) {
1798                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1799         }
1800
1801         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1802         tmp = RREG32(BUS_CNTL);
1803         tmp |= VGA_COHE_SPEC_TIMER_DIS;
1804         WREG32(BUS_CNTL, tmp);
1805
1806         tmp = RREG32(BIF_SCRATCH0);
1807
1808         /* reset */
1809         radeon_pci_config_reset(rdev);
1810         mdelay(1);
1811
1812         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1813         tmp = SOFT_RESET_BIF;
1814         WREG32(SRBM_SOFT_RESET, tmp);
1815         mdelay(1);
1816         WREG32(SRBM_SOFT_RESET, 0);
1817
1818         /* wait for asic to come out of reset */
1819         for (i = 0; i < rdev->usec_timeout; i++) {
1820                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1821                         break;
1822                 udelay(1);
1823         }
1824 }
1825
1826 int r600_asic_reset(struct radeon_device *rdev)
1827 {
1828         u32 reset_mask;
1829
1830         reset_mask = r600_gpu_check_soft_reset(rdev);
1831
1832         if (reset_mask)
1833                 r600_set_bios_scratch_engine_hung(rdev, true);
1834
1835         /* try soft reset */
1836         r600_gpu_soft_reset(rdev, reset_mask);
1837
1838         reset_mask = r600_gpu_check_soft_reset(rdev);
1839
1840         /* try pci config reset */
1841         if (reset_mask && radeon_hard_reset)
1842                 r600_gpu_pci_config_reset(rdev);
1843
1844         reset_mask = r600_gpu_check_soft_reset(rdev);
1845
1846         if (!reset_mask)
1847                 r600_set_bios_scratch_engine_hung(rdev, false);
1848
1849         return 0;
1850 }
1851
1852 /**
1853  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1854  *
1855  * @rdev: radeon_device pointer
1856  * @ring: radeon_ring structure holding ring information
1857  *
1858  * Check if the GFX engine is locked up.
1859  * Returns true if the engine appears to be locked up, false if not.
1860  */
1861 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1862 {
1863         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1864
1865         if (!(reset_mask & (RADEON_RESET_GFX |
1866                             RADEON_RESET_COMPUTE |
1867                             RADEON_RESET_CP))) {
1868                 radeon_ring_lockup_update(rdev, ring);
1869                 return false;
1870         }
1871         return radeon_ring_test_lockup(rdev, ring);
1872 }
1873
1874 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1875                               u32 tiling_pipe_num,
1876                               u32 max_rb_num,
1877                               u32 total_max_rb_num,
1878                               u32 disabled_rb_mask)
1879 {
1880         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1881         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1882         u32 data = 0, mask = 1 << (max_rb_num - 1);
1883         unsigned i, j;
1884
1885         /* mask out the RBs that don't exist on that asic */
1886         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1887         /* make sure at least one RB is available */
1888         if ((tmp & 0xff) != 0xff)
1889                 disabled_rb_mask = tmp;
1890
1891         rendering_pipe_num = 1 << tiling_pipe_num;
1892         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1893         BUG_ON(rendering_pipe_num < req_rb_num);
1894
1895         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1896         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1897
1898         if (rdev->family <= CHIP_RV740) {
1899                 /* r6xx/r7xx */
1900                 rb_num_width = 2;
1901         } else {
1902                 /* eg+ */
1903                 rb_num_width = 4;
1904         }
1905
1906         for (i = 0; i < max_rb_num; i++) {
1907                 if (!(mask & disabled_rb_mask)) {
1908                         for (j = 0; j < pipe_rb_ratio; j++) {
1909                                 data <<= rb_num_width;
1910                                 data |= max_rb_num - i - 1;
1911                         }
1912                         if (pipe_rb_remain) {
1913                                 data <<= rb_num_width;
1914                                 data |= max_rb_num - i - 1;
1915                                 pipe_rb_remain--;
1916                         }
1917                 }
1918                 mask >>= 1;
1919         }
1920
1921         return data;
1922 }
1923
1924 int r600_count_pipe_bits(uint32_t val)
1925 {
1926         return hweight32(val);
1927 }
1928
1929 static void r600_gpu_init(struct radeon_device *rdev)
1930 {
1931         u32 tiling_config;
1932         u32 ramcfg;
1933         u32 cc_gc_shader_pipe_config;
1934         u32 tmp;
1935         int i, j;
1936         u32 sq_config;
1937         u32 sq_gpr_resource_mgmt_1 = 0;
1938         u32 sq_gpr_resource_mgmt_2 = 0;
1939         u32 sq_thread_resource_mgmt = 0;
1940         u32 sq_stack_resource_mgmt_1 = 0;
1941         u32 sq_stack_resource_mgmt_2 = 0;
1942         u32 disabled_rb_mask;
1943
1944         rdev->config.r600.tiling_group_size = 256;
1945         switch (rdev->family) {
1946         case CHIP_R600:
1947                 rdev->config.r600.max_pipes = 4;
1948                 rdev->config.r600.max_tile_pipes = 8;
1949                 rdev->config.r600.max_simds = 4;
1950                 rdev->config.r600.max_backends = 4;
1951                 rdev->config.r600.max_gprs = 256;
1952                 rdev->config.r600.max_threads = 192;
1953                 rdev->config.r600.max_stack_entries = 256;
1954                 rdev->config.r600.max_hw_contexts = 8;
1955                 rdev->config.r600.max_gs_threads = 16;
1956                 rdev->config.r600.sx_max_export_size = 128;
1957                 rdev->config.r600.sx_max_export_pos_size = 16;
1958                 rdev->config.r600.sx_max_export_smx_size = 128;
1959                 rdev->config.r600.sq_num_cf_insts = 2;
1960                 break;
1961         case CHIP_RV630:
1962         case CHIP_RV635:
1963                 rdev->config.r600.max_pipes = 2;
1964                 rdev->config.r600.max_tile_pipes = 2;
1965                 rdev->config.r600.max_simds = 3;
1966                 rdev->config.r600.max_backends = 1;
1967                 rdev->config.r600.max_gprs = 128;
1968                 rdev->config.r600.max_threads = 192;
1969                 rdev->config.r600.max_stack_entries = 128;
1970                 rdev->config.r600.max_hw_contexts = 8;
1971                 rdev->config.r600.max_gs_threads = 4;
1972                 rdev->config.r600.sx_max_export_size = 128;
1973                 rdev->config.r600.sx_max_export_pos_size = 16;
1974                 rdev->config.r600.sx_max_export_smx_size = 128;
1975                 rdev->config.r600.sq_num_cf_insts = 2;
1976                 break;
1977         case CHIP_RV610:
1978         case CHIP_RV620:
1979         case CHIP_RS780:
1980         case CHIP_RS880:
1981                 rdev->config.r600.max_pipes = 1;
1982                 rdev->config.r600.max_tile_pipes = 1;
1983                 rdev->config.r600.max_simds = 2;
1984                 rdev->config.r600.max_backends = 1;
1985                 rdev->config.r600.max_gprs = 128;
1986                 rdev->config.r600.max_threads = 192;
1987                 rdev->config.r600.max_stack_entries = 128;
1988                 rdev->config.r600.max_hw_contexts = 4;
1989                 rdev->config.r600.max_gs_threads = 4;
1990                 rdev->config.r600.sx_max_export_size = 128;
1991                 rdev->config.r600.sx_max_export_pos_size = 16;
1992                 rdev->config.r600.sx_max_export_smx_size = 128;
1993                 rdev->config.r600.sq_num_cf_insts = 1;
1994                 break;
1995         case CHIP_RV670:
1996                 rdev->config.r600.max_pipes = 4;
1997                 rdev->config.r600.max_tile_pipes = 4;
1998                 rdev->config.r600.max_simds = 4;
1999                 rdev->config.r600.max_backends = 4;
2000                 rdev->config.r600.max_gprs = 192;
2001                 rdev->config.r600.max_threads = 192;
2002                 rdev->config.r600.max_stack_entries = 256;
2003                 rdev->config.r600.max_hw_contexts = 8;
2004                 rdev->config.r600.max_gs_threads = 16;
2005                 rdev->config.r600.sx_max_export_size = 128;
2006                 rdev->config.r600.sx_max_export_pos_size = 16;
2007                 rdev->config.r600.sx_max_export_smx_size = 128;
2008                 rdev->config.r600.sq_num_cf_insts = 2;
2009                 break;
2010         default:
2011                 break;
2012         }
2013
2014         /* Initialize HDP */
2015         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2016                 WREG32((0x2c14 + j), 0x00000000);
2017                 WREG32((0x2c18 + j), 0x00000000);
2018                 WREG32((0x2c1c + j), 0x00000000);
2019                 WREG32((0x2c20 + j), 0x00000000);
2020                 WREG32((0x2c24 + j), 0x00000000);
2021         }
2022
2023         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2024
2025         /* Setup tiling */
2026         tiling_config = 0;
2027         ramcfg = RREG32(RAMCFG);
2028         switch (rdev->config.r600.max_tile_pipes) {
2029         case 1:
2030                 tiling_config |= PIPE_TILING(0);
2031                 break;
2032         case 2:
2033                 tiling_config |= PIPE_TILING(1);
2034                 break;
2035         case 4:
2036                 tiling_config |= PIPE_TILING(2);
2037                 break;
2038         case 8:
2039                 tiling_config |= PIPE_TILING(3);
2040                 break;
2041         default:
2042                 break;
2043         }
2044         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2045         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2046         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2047         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2048
2049         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2050         if (tmp > 3) {
2051                 tiling_config |= ROW_TILING(3);
2052                 tiling_config |= SAMPLE_SPLIT(3);
2053         } else {
2054                 tiling_config |= ROW_TILING(tmp);
2055                 tiling_config |= SAMPLE_SPLIT(tmp);
2056         }
2057         tiling_config |= BANK_SWAPS(1);
2058
2059         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2060         tmp = rdev->config.r600.max_simds -
2061                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2062         rdev->config.r600.active_simds = tmp;
2063
2064         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2065         tmp = 0;
2066         for (i = 0; i < rdev->config.r600.max_backends; i++)
2067                 tmp |= (1 << i);
2068         /* if all the backends are disabled, fix it up here */
2069         if ((disabled_rb_mask & tmp) == tmp) {
2070                 for (i = 0; i < rdev->config.r600.max_backends; i++)
2071                         disabled_rb_mask &= ~(1 << i);
2072         }
2073         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2074         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2075                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
2076         tiling_config |= tmp << 16;
2077         rdev->config.r600.backend_map = tmp;
2078
2079         rdev->config.r600.tile_config = tiling_config;
2080         WREG32(GB_TILING_CONFIG, tiling_config);
2081         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2082         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2083         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2084
2085         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2086         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2087         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2088
2089         /* Setup some CP states */
2090         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2091         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2092
2093         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2094                              SYNC_WALKER | SYNC_ALIGNER));
2095         /* Setup various GPU states */
2096         if (rdev->family == CHIP_RV670)
2097                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2098
2099         tmp = RREG32(SX_DEBUG_1);
2100         tmp |= SMX_EVENT_RELEASE;
2101         if ((rdev->family > CHIP_R600))
2102                 tmp |= ENABLE_NEW_SMX_ADDRESS;
2103         WREG32(SX_DEBUG_1, tmp);
2104
2105         if (((rdev->family) == CHIP_R600) ||
2106             ((rdev->family) == CHIP_RV630) ||
2107             ((rdev->family) == CHIP_RV610) ||
2108             ((rdev->family) == CHIP_RV620) ||
2109             ((rdev->family) == CHIP_RS780) ||
2110             ((rdev->family) == CHIP_RS880)) {
2111                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2112         } else {
2113                 WREG32(DB_DEBUG, 0);
2114         }
2115         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2116                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2117
2118         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2119         WREG32(VGT_NUM_INSTANCES, 0);
2120
2121         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2122         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2123
2124         tmp = RREG32(SQ_MS_FIFO_SIZES);
2125         if (((rdev->family) == CHIP_RV610) ||
2126             ((rdev->family) == CHIP_RV620) ||
2127             ((rdev->family) == CHIP_RS780) ||
2128             ((rdev->family) == CHIP_RS880)) {
2129                 tmp = (CACHE_FIFO_SIZE(0xa) |
2130                        FETCH_FIFO_HIWATER(0xa) |
2131                        DONE_FIFO_HIWATER(0xe0) |
2132                        ALU_UPDATE_FIFO_HIWATER(0x8));
2133         } else if (((rdev->family) == CHIP_R600) ||
2134                    ((rdev->family) == CHIP_RV630)) {
2135                 tmp &= ~DONE_FIFO_HIWATER(0xff);
2136                 tmp |= DONE_FIFO_HIWATER(0x4);
2137         }
2138         WREG32(SQ_MS_FIFO_SIZES, tmp);
2139
2140         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2141          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
2142          */
2143         sq_config = RREG32(SQ_CONFIG);
2144         sq_config &= ~(PS_PRIO(3) |
2145                        VS_PRIO(3) |
2146                        GS_PRIO(3) |
2147                        ES_PRIO(3));
2148         sq_config |= (DX9_CONSTS |
2149                       VC_ENABLE |
2150                       PS_PRIO(0) |
2151                       VS_PRIO(1) |
2152                       GS_PRIO(2) |
2153                       ES_PRIO(3));
2154
2155         if ((rdev->family) == CHIP_R600) {
2156                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2157                                           NUM_VS_GPRS(124) |
2158                                           NUM_CLAUSE_TEMP_GPRS(4));
2159                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2160                                           NUM_ES_GPRS(0));
2161                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2162                                            NUM_VS_THREADS(48) |
2163                                            NUM_GS_THREADS(4) |
2164                                            NUM_ES_THREADS(4));
2165                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2166                                             NUM_VS_STACK_ENTRIES(128));
2167                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2168                                             NUM_ES_STACK_ENTRIES(0));
2169         } else if (((rdev->family) == CHIP_RV610) ||
2170                    ((rdev->family) == CHIP_RV620) ||
2171                    ((rdev->family) == CHIP_RS780) ||
2172                    ((rdev->family) == CHIP_RS880)) {
2173                 /* no vertex cache */
2174                 sq_config &= ~VC_ENABLE;
2175
2176                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2177                                           NUM_VS_GPRS(44) |
2178                                           NUM_CLAUSE_TEMP_GPRS(2));
2179                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2180                                           NUM_ES_GPRS(17));
2181                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2182                                            NUM_VS_THREADS(78) |
2183                                            NUM_GS_THREADS(4) |
2184                                            NUM_ES_THREADS(31));
2185                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2186                                             NUM_VS_STACK_ENTRIES(40));
2187                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2188                                             NUM_ES_STACK_ENTRIES(16));
2189         } else if (((rdev->family) == CHIP_RV630) ||
2190                    ((rdev->family) == CHIP_RV635)) {
2191                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2192                                           NUM_VS_GPRS(44) |
2193                                           NUM_CLAUSE_TEMP_GPRS(2));
2194                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2195                                           NUM_ES_GPRS(18));
2196                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2197                                            NUM_VS_THREADS(78) |
2198                                            NUM_GS_THREADS(4) |
2199                                            NUM_ES_THREADS(31));
2200                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2201                                             NUM_VS_STACK_ENTRIES(40));
2202                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2203                                             NUM_ES_STACK_ENTRIES(16));
2204         } else if ((rdev->family) == CHIP_RV670) {
2205                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2206                                           NUM_VS_GPRS(44) |
2207                                           NUM_CLAUSE_TEMP_GPRS(2));
2208                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2209                                           NUM_ES_GPRS(17));
2210                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2211                                            NUM_VS_THREADS(78) |
2212                                            NUM_GS_THREADS(4) |
2213                                            NUM_ES_THREADS(31));
2214                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2215                                             NUM_VS_STACK_ENTRIES(64));
2216                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2217                                             NUM_ES_STACK_ENTRIES(64));
2218         }
2219
2220         WREG32(SQ_CONFIG, sq_config);
2221         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2222         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2223         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2224         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2225         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2226
2227         if (((rdev->family) == CHIP_RV610) ||
2228             ((rdev->family) == CHIP_RV620) ||
2229             ((rdev->family) == CHIP_RS780) ||
2230             ((rdev->family) == CHIP_RS880)) {
2231                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2232         } else {
2233                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2234         }
2235
2236         /* More default values. 2D/3D driver should adjust as needed */
2237         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2238                                          S1_X(0x4) | S1_Y(0xc)));
2239         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2240                                          S1_X(0x2) | S1_Y(0x2) |
2241                                          S2_X(0xa) | S2_Y(0x6) |
2242                                          S3_X(0x6) | S3_Y(0xa)));
2243         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2244                                              S1_X(0x4) | S1_Y(0xc) |
2245                                              S2_X(0x1) | S2_Y(0x6) |
2246                                              S3_X(0xa) | S3_Y(0xe)));
2247         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2248                                              S5_X(0x0) | S5_Y(0x0) |
2249                                              S6_X(0xb) | S6_Y(0x4) |
2250                                              S7_X(0x7) | S7_Y(0x8)));
2251
2252         WREG32(VGT_STRMOUT_EN, 0);
2253         tmp = rdev->config.r600.max_pipes * 16;
2254         switch (rdev->family) {
2255         case CHIP_RV610:
2256         case CHIP_RV620:
2257         case CHIP_RS780:
2258         case CHIP_RS880:
2259                 tmp += 32;
2260                 break;
2261         case CHIP_RV670:
2262                 tmp += 128;
2263                 break;
2264         default:
2265                 break;
2266         }
2267         if (tmp > 256) {
2268                 tmp = 256;
2269         }
2270         WREG32(VGT_ES_PER_GS, 128);
2271         WREG32(VGT_GS_PER_ES, tmp);
2272         WREG32(VGT_GS_PER_VS, 2);
2273         WREG32(VGT_GS_VERTEX_REUSE, 16);
2274
2275         /* more default values. 2D/3D driver should adjust as needed */
2276         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2277         WREG32(VGT_STRMOUT_EN, 0);
2278         WREG32(SX_MISC, 0);
2279         WREG32(PA_SC_MODE_CNTL, 0);
2280         WREG32(PA_SC_AA_CONFIG, 0);
2281         WREG32(PA_SC_LINE_STIPPLE, 0);
2282         WREG32(SPI_INPUT_Z, 0);
2283         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2284         WREG32(CB_COLOR7_FRAG, 0);
2285
2286         /* Clear render buffer base addresses */
2287         WREG32(CB_COLOR0_BASE, 0);
2288         WREG32(CB_COLOR1_BASE, 0);
2289         WREG32(CB_COLOR2_BASE, 0);
2290         WREG32(CB_COLOR3_BASE, 0);
2291         WREG32(CB_COLOR4_BASE, 0);
2292         WREG32(CB_COLOR5_BASE, 0);
2293         WREG32(CB_COLOR6_BASE, 0);
2294         WREG32(CB_COLOR7_BASE, 0);
2295         WREG32(CB_COLOR7_FRAG, 0);
2296
2297         switch (rdev->family) {
2298         case CHIP_RV610:
2299         case CHIP_RV620:
2300         case CHIP_RS780:
2301         case CHIP_RS880:
2302                 tmp = TC_L2_SIZE(8);
2303                 break;
2304         case CHIP_RV630:
2305         case CHIP_RV635:
2306                 tmp = TC_L2_SIZE(4);
2307                 break;
2308         case CHIP_R600:
2309                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2310                 break;
2311         default:
2312                 tmp = TC_L2_SIZE(0);
2313                 break;
2314         }
2315         WREG32(TC_CNTL, tmp);
2316
2317         tmp = RREG32(HDP_HOST_PATH_CNTL);
2318         WREG32(HDP_HOST_PATH_CNTL, tmp);
2319
2320         tmp = RREG32(ARB_POP);
2321         tmp |= ENABLE_TC128;
2322         WREG32(ARB_POP, tmp);
2323
2324         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2325         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2326                                NUM_CLIP_SEQ(3)));
2327         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2328         WREG32(VC_ENHANCE, 0);
2329 }
2330
2331
2332 /*
2333  * Indirect registers accessor
2334  */
2335 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2336 {
2337         unsigned long flags;
2338         u32 r;
2339
2340         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2341         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2342         (void)RREG32(PCIE_PORT_INDEX);
2343         r = RREG32(PCIE_PORT_DATA);
2344         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2345         return r;
2346 }
2347
2348 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2349 {
2350         unsigned long flags;
2351
2352         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2353         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2354         (void)RREG32(PCIE_PORT_INDEX);
2355         WREG32(PCIE_PORT_DATA, (v));
2356         (void)RREG32(PCIE_PORT_DATA);
2357         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2358 }
2359
2360 /*
2361  * CP & Ring
2362  */
2363 void r600_cp_stop(struct radeon_device *rdev)
2364 {
2365         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2366                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2367         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2368         WREG32(SCRATCH_UMSK, 0);
2369         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2370 }
2371
2372 int r600_init_microcode(struct radeon_device *rdev)
2373 {
2374         const char *chip_name;
2375         const char *rlc_chip_name;
2376         const char *smc_chip_name = "RV770";
2377         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2378         char fw_name[30];
2379         int err;
2380
2381         DRM_DEBUG("\n");
2382
2383         switch (rdev->family) {
2384         case CHIP_R600:
2385                 chip_name = "R600";
2386                 rlc_chip_name = "R600";
2387                 break;
2388         case CHIP_RV610:
2389                 chip_name = "RV610";
2390                 rlc_chip_name = "R600";
2391                 break;
2392         case CHIP_RV630:
2393                 chip_name = "RV630";
2394                 rlc_chip_name = "R600";
2395                 break;
2396         case CHIP_RV620:
2397                 chip_name = "RV620";
2398                 rlc_chip_name = "R600";
2399                 break;
2400         case CHIP_RV635:
2401                 chip_name = "RV635";
2402                 rlc_chip_name = "R600";
2403                 break;
2404         case CHIP_RV670:
2405                 chip_name = "RV670";
2406                 rlc_chip_name = "R600";
2407                 break;
2408         case CHIP_RS780:
2409         case CHIP_RS880:
2410                 chip_name = "RS780";
2411                 rlc_chip_name = "R600";
2412                 break;
2413         case CHIP_RV770:
2414                 chip_name = "RV770";
2415                 rlc_chip_name = "R700";
2416                 smc_chip_name = "RV770";
2417                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2418                 break;
2419         case CHIP_RV730:
2420                 chip_name = "RV730";
2421                 rlc_chip_name = "R700";
2422                 smc_chip_name = "RV730";
2423                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2424                 break;
2425         case CHIP_RV710:
2426                 chip_name = "RV710";
2427                 rlc_chip_name = "R700";
2428                 smc_chip_name = "RV710";
2429                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2430                 break;
2431         case CHIP_RV740:
2432                 chip_name = "RV730";
2433                 rlc_chip_name = "R700";
2434                 smc_chip_name = "RV740";
2435                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2436                 break;
2437         case CHIP_CEDAR:
2438                 chip_name = "CEDAR";
2439                 rlc_chip_name = "CEDAR";
2440                 smc_chip_name = "CEDAR";
2441                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2442                 break;
2443         case CHIP_REDWOOD:
2444                 chip_name = "REDWOOD";
2445                 rlc_chip_name = "REDWOOD";
2446                 smc_chip_name = "REDWOOD";
2447                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2448                 break;
2449         case CHIP_JUNIPER:
2450                 chip_name = "JUNIPER";
2451                 rlc_chip_name = "JUNIPER";
2452                 smc_chip_name = "JUNIPER";
2453                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2454                 break;
2455         case CHIP_CYPRESS:
2456         case CHIP_HEMLOCK:
2457                 chip_name = "CYPRESS";
2458                 rlc_chip_name = "CYPRESS";
2459                 smc_chip_name = "CYPRESS";
2460                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2461                 break;
2462         case CHIP_PALM:
2463                 chip_name = "PALM";
2464                 rlc_chip_name = "SUMO";
2465                 break;
2466         case CHIP_SUMO:
2467                 chip_name = "SUMO";
2468                 rlc_chip_name = "SUMO";
2469                 break;
2470         case CHIP_SUMO2:
2471                 chip_name = "SUMO2";
2472                 rlc_chip_name = "SUMO";
2473                 break;
2474         default: BUG();
2475         }
2476
2477         if (rdev->family >= CHIP_CEDAR) {
2478                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2479                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2480                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2481         } else if (rdev->family >= CHIP_RV770) {
2482                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2483                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2484                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2485         } else {
2486                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2487                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2488                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2489         }
2490
2491         DRM_INFO("Loading %s Microcode\n", chip_name);
2492
2493         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
2494         err = reject_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2495         if (err)
2496                 goto out;
2497         if (rdev->pfp_fw->size != pfp_req_size) {
2498                 printk(KERN_ERR
2499                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2500                        rdev->pfp_fw->size, fw_name);
2501                 err = -EINVAL;
2502                 goto out;
2503         }
2504
2505         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
2506         err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
2507         if (err)
2508                 goto out;
2509         if (rdev->me_fw->size != me_req_size) {
2510                 printk(KERN_ERR
2511                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2512                        rdev->me_fw->size, fw_name);
2513                 err = -EINVAL;
2514         }
2515
2516         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", rlc_chip_name);
2517         err = reject_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2518         if (err)
2519                 goto out;
2520         if (rdev->rlc_fw->size != rlc_req_size) {
2521                 printk(KERN_ERR
2522                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2523                        rdev->rlc_fw->size, fw_name);
2524                 err = -EINVAL;
2525         }
2526
2527         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2528                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", smc_chip_name);
2529                 err = reject_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2530                 if (err) {
2531                         printk(KERN_ERR
2532                                "smc: error loading firmware \"%s\"\n",
2533                                fw_name);
2534                         release_firmware(rdev->smc_fw);
2535                         rdev->smc_fw = NULL;
2536                         err = 0;
2537                 } else if (rdev->smc_fw->size != smc_req_size) {
2538                         printk(KERN_ERR
2539                                "smc: Bogus length %zu in firmware \"%s\"\n",
2540                                rdev->smc_fw->size, fw_name);
2541                         err = -EINVAL;
2542                 }
2543         }
2544
2545 out:
2546         if (err) {
2547                 if (err != -EINVAL)
2548                         printk(KERN_ERR
2549                                "r600_cp: Failed to load firmware \"%s\"\n",
2550                                fw_name);
2551                 release_firmware(rdev->pfp_fw);
2552                 rdev->pfp_fw = NULL;
2553                 release_firmware(rdev->me_fw);
2554                 rdev->me_fw = NULL;
2555                 release_firmware(rdev->rlc_fw);
2556                 rdev->rlc_fw = NULL;
2557                 release_firmware(rdev->smc_fw);
2558                 rdev->smc_fw = NULL;
2559         }
2560         return err;
2561 }
2562
2563 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2564                       struct radeon_ring *ring)
2565 {
2566         u32 rptr;
2567
2568         if (rdev->wb.enabled)
2569                 rptr = rdev->wb.wb[ring->rptr_offs/4];
2570         else
2571                 rptr = RREG32(R600_CP_RB_RPTR);
2572
2573         return rptr;
2574 }
2575
2576 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2577                       struct radeon_ring *ring)
2578 {
2579         u32 wptr;
2580
2581         wptr = RREG32(R600_CP_RB_WPTR);
2582
2583         return wptr;
2584 }
2585
2586 void r600_gfx_set_wptr(struct radeon_device *rdev,
2587                        struct radeon_ring *ring)
2588 {
2589         WREG32(R600_CP_RB_WPTR, ring->wptr);
2590         (void)RREG32(R600_CP_RB_WPTR);
2591 }
2592
2593 static int r600_cp_load_microcode(struct radeon_device *rdev)
2594 {
2595         const __be32 *fw_data;
2596         int i;
2597
2598         if (!rdev->me_fw || !rdev->pfp_fw)
2599                 return -EINVAL;
2600
2601         r600_cp_stop(rdev);
2602
2603         WREG32(CP_RB_CNTL,
2604 #ifdef __BIG_ENDIAN
2605                BUF_SWAP_32BIT |
2606 #endif
2607                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2608
2609         /* Reset cp */
2610         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2611         RREG32(GRBM_SOFT_RESET);
2612         mdelay(15);
2613         WREG32(GRBM_SOFT_RESET, 0);
2614
2615         WREG32(CP_ME_RAM_WADDR, 0);
2616
2617         fw_data = (const __be32 *)rdev->me_fw->data;
2618         WREG32(CP_ME_RAM_WADDR, 0);
2619         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2620                 WREG32(CP_ME_RAM_DATA,
2621                        be32_to_cpup(fw_data++));
2622
2623         fw_data = (const __be32 *)rdev->pfp_fw->data;
2624         WREG32(CP_PFP_UCODE_ADDR, 0);
2625         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2626                 WREG32(CP_PFP_UCODE_DATA,
2627                        be32_to_cpup(fw_data++));
2628
2629         WREG32(CP_PFP_UCODE_ADDR, 0);
2630         WREG32(CP_ME_RAM_WADDR, 0);
2631         WREG32(CP_ME_RAM_RADDR, 0);
2632         return 0;
2633 }
2634
2635 int r600_cp_start(struct radeon_device *rdev)
2636 {
2637         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2638         int r;
2639         uint32_t cp_me;
2640
2641         r = radeon_ring_lock(rdev, ring, 7);
2642         if (r) {
2643                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2644                 return r;
2645         }
2646         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2647         radeon_ring_write(ring, 0x1);
2648         if (rdev->family >= CHIP_RV770) {
2649                 radeon_ring_write(ring, 0x0);
2650                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2651         } else {
2652                 radeon_ring_write(ring, 0x3);
2653                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2654         }
2655         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2656         radeon_ring_write(ring, 0);
2657         radeon_ring_write(ring, 0);
2658         radeon_ring_unlock_commit(rdev, ring, false);
2659
2660         cp_me = 0xff;
2661         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2662         return 0;
2663 }
2664
2665 int r600_cp_resume(struct radeon_device *rdev)
2666 {
2667         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2668         u32 tmp;
2669         u32 rb_bufsz;
2670         int r;
2671
2672         /* Reset cp */
2673         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2674         RREG32(GRBM_SOFT_RESET);
2675         mdelay(15);
2676         WREG32(GRBM_SOFT_RESET, 0);
2677
2678         /* Set ring buffer size */
2679         rb_bufsz = order_base_2(ring->ring_size / 8);
2680         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2681 #ifdef __BIG_ENDIAN
2682         tmp |= BUF_SWAP_32BIT;
2683 #endif
2684         WREG32(CP_RB_CNTL, tmp);
2685         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2686
2687         /* Set the write pointer delay */
2688         WREG32(CP_RB_WPTR_DELAY, 0);
2689
2690         /* Initialize the ring buffer's read and write pointers */
2691         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2692         WREG32(CP_RB_RPTR_WR, 0);
2693         ring->wptr = 0;
2694         WREG32(CP_RB_WPTR, ring->wptr);
2695
2696         /* set the wb address whether it's enabled or not */
2697         WREG32(CP_RB_RPTR_ADDR,
2698                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2699         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2700         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2701
2702         if (rdev->wb.enabled)
2703                 WREG32(SCRATCH_UMSK, 0xff);
2704         else {
2705                 tmp |= RB_NO_UPDATE;
2706                 WREG32(SCRATCH_UMSK, 0);
2707         }
2708
2709         mdelay(1);
2710         WREG32(CP_RB_CNTL, tmp);
2711
2712         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2713         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2714
2715         r600_cp_start(rdev);
2716         ring->ready = true;
2717         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2718         if (r) {
2719                 ring->ready = false;
2720                 return r;
2721         }
2722
2723         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2724                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2725
2726         return 0;
2727 }
2728
2729 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2730 {
2731         u32 rb_bufsz;
2732         int r;
2733
2734         /* Align ring size */
2735         rb_bufsz = order_base_2(ring_size / 8);
2736         ring_size = (1 << (rb_bufsz + 1)) * 4;
2737         ring->ring_size = ring_size;
2738         ring->align_mask = 16 - 1;
2739
2740         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2741                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2742                 if (r) {
2743                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2744                         ring->rptr_save_reg = 0;
2745                 }
2746         }
2747 }
2748
2749 void r600_cp_fini(struct radeon_device *rdev)
2750 {
2751         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2752         r600_cp_stop(rdev);
2753         radeon_ring_fini(rdev, ring);
2754         radeon_scratch_free(rdev, ring->rptr_save_reg);
2755 }
2756
2757 /*
2758  * GPU scratch registers helpers function.
2759  */
2760 void r600_scratch_init(struct radeon_device *rdev)
2761 {
2762         int i;
2763
2764         rdev->scratch.num_reg = 7;
2765         rdev->scratch.reg_base = SCRATCH_REG0;
2766         for (i = 0; i < rdev->scratch.num_reg; i++) {
2767                 rdev->scratch.free[i] = true;
2768                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2769         }
2770 }
2771
2772 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2773 {
2774         uint32_t scratch;
2775         uint32_t tmp = 0;
2776         unsigned i;
2777         int r;
2778
2779         r = radeon_scratch_get(rdev, &scratch);
2780         if (r) {
2781                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2782                 return r;
2783         }
2784         WREG32(scratch, 0xCAFEDEAD);
2785         r = radeon_ring_lock(rdev, ring, 3);
2786         if (r) {
2787                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2788                 radeon_scratch_free(rdev, scratch);
2789                 return r;
2790         }
2791         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2792         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2793         radeon_ring_write(ring, 0xDEADBEEF);
2794         radeon_ring_unlock_commit(rdev, ring, false);
2795         for (i = 0; i < rdev->usec_timeout; i++) {
2796                 tmp = RREG32(scratch);
2797                 if (tmp == 0xDEADBEEF)
2798                         break;
2799                 DRM_UDELAY(1);
2800         }
2801         if (i < rdev->usec_timeout) {
2802                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2803         } else {
2804                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2805                           ring->idx, scratch, tmp);
2806                 r = -EINVAL;
2807         }
2808         radeon_scratch_free(rdev, scratch);
2809         return r;
2810 }
2811
2812 /*
2813  * CP fences/semaphores
2814  */
2815
2816 void r600_fence_ring_emit(struct radeon_device *rdev,
2817                           struct radeon_fence *fence)
2818 {
2819         struct radeon_ring *ring = &rdev->ring[fence->ring];
2820         u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2821                 PACKET3_SH_ACTION_ENA;
2822
2823         if (rdev->family >= CHIP_RV770)
2824                 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2825
2826         if (rdev->wb.use_event) {
2827                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2828                 /* flush read cache over gart */
2829                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2830                 radeon_ring_write(ring, cp_coher_cntl);
2831                 radeon_ring_write(ring, 0xFFFFFFFF);
2832                 radeon_ring_write(ring, 0);
2833                 radeon_ring_write(ring, 10); /* poll interval */
2834                 /* EVENT_WRITE_EOP - flush caches, send int */
2835                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2836                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2837                 radeon_ring_write(ring, lower_32_bits(addr));
2838                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2839                 radeon_ring_write(ring, fence->seq);
2840                 radeon_ring_write(ring, 0);
2841         } else {
2842                 /* flush read cache over gart */
2843                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2844                 radeon_ring_write(ring, cp_coher_cntl);
2845                 radeon_ring_write(ring, 0xFFFFFFFF);
2846                 radeon_ring_write(ring, 0);
2847                 radeon_ring_write(ring, 10); /* poll interval */
2848                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2849                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2850                 /* wait for 3D idle clean */
2851                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2852                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2853                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2854                 /* Emit fence sequence & fire IRQ */
2855                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2856                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2857                 radeon_ring_write(ring, fence->seq);
2858                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2859                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2860                 radeon_ring_write(ring, RB_INT_STAT);
2861         }
2862 }
2863
2864 /**
2865  * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2866  *
2867  * @rdev: radeon_device pointer
2868  * @ring: radeon ring buffer object
2869  * @semaphore: radeon semaphore object
2870  * @emit_wait: Is this a sempahore wait?
2871  *
2872  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2873  * from running ahead of semaphore waits.
2874  */
2875 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2876                               struct radeon_ring *ring,
2877                               struct radeon_semaphore *semaphore,
2878                               bool emit_wait)
2879 {
2880         uint64_t addr = semaphore->gpu_addr;
2881         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2882
2883         if (rdev->family < CHIP_CAYMAN)
2884                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2885
2886         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2887         radeon_ring_write(ring, lower_32_bits(addr));
2888         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2889
2890         /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2891         if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2892                 /* Prevent the PFP from running ahead of the semaphore wait */
2893                 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2894                 radeon_ring_write(ring, 0x0);
2895         }
2896
2897         return true;
2898 }
2899
2900 /**
2901  * r600_copy_cpdma - copy pages using the CP DMA engine
2902  *
2903  * @rdev: radeon_device pointer
2904  * @src_offset: src GPU address
2905  * @dst_offset: dst GPU address
2906  * @num_gpu_pages: number of GPU pages to xfer
2907  * @fence: radeon fence object
2908  *
2909  * Copy GPU paging using the CP DMA engine (r6xx+).
2910  * Used by the radeon ttm implementation to move pages if
2911  * registered as the asic copy callback.
2912  */
2913 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2914                                      uint64_t src_offset, uint64_t dst_offset,
2915                                      unsigned num_gpu_pages,
2916                                      struct reservation_object *resv)
2917 {
2918         struct radeon_fence *fence;
2919         struct radeon_sync sync;
2920         int ring_index = rdev->asic->copy.blit_ring_index;
2921         struct radeon_ring *ring = &rdev->ring[ring_index];
2922         u32 size_in_bytes, cur_size_in_bytes, tmp;
2923         int i, num_loops;
2924         int r = 0;
2925
2926         radeon_sync_create(&sync);
2927
2928         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2929         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2930         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2931         if (r) {
2932                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2933                 radeon_sync_free(rdev, &sync, NULL);
2934                 return ERR_PTR(r);
2935         }
2936
2937         radeon_sync_resv(rdev, &sync, resv, false);
2938         radeon_sync_rings(rdev, &sync, ring->idx);
2939
2940         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2941         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2942         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2943         for (i = 0; i < num_loops; i++) {
2944                 cur_size_in_bytes = size_in_bytes;
2945                 if (cur_size_in_bytes > 0x1fffff)
2946                         cur_size_in_bytes = 0x1fffff;
2947                 size_in_bytes -= cur_size_in_bytes;
2948                 tmp = upper_32_bits(src_offset) & 0xff;
2949                 if (size_in_bytes == 0)
2950                         tmp |= PACKET3_CP_DMA_CP_SYNC;
2951                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2952                 radeon_ring_write(ring, lower_32_bits(src_offset));
2953                 radeon_ring_write(ring, tmp);
2954                 radeon_ring_write(ring, lower_32_bits(dst_offset));
2955                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2956                 radeon_ring_write(ring, cur_size_in_bytes);
2957                 src_offset += cur_size_in_bytes;
2958                 dst_offset += cur_size_in_bytes;
2959         }
2960         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2961         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2962         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2963
2964         r = radeon_fence_emit(rdev, &fence, ring->idx);
2965         if (r) {
2966                 radeon_ring_unlock_undo(rdev, ring);
2967                 radeon_sync_free(rdev, &sync, NULL);
2968                 return ERR_PTR(r);
2969         }
2970
2971         radeon_ring_unlock_commit(rdev, ring, false);
2972         radeon_sync_free(rdev, &sync, fence);
2973
2974         return fence;
2975 }
2976
2977 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2978                          uint32_t tiling_flags, uint32_t pitch,
2979                          uint32_t offset, uint32_t obj_size)
2980 {
2981         /* FIXME: implement */
2982         return 0;
2983 }
2984
2985 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2986 {
2987         /* FIXME: implement */
2988 }
2989
2990 static int r600_startup(struct radeon_device *rdev)
2991 {
2992         struct radeon_ring *ring;
2993         int r;
2994
2995         /* enable pcie gen2 link */
2996         r600_pcie_gen2_enable(rdev);
2997
2998         /* scratch needs to be initialized before MC */
2999         r = r600_vram_scratch_init(rdev);
3000         if (r)
3001                 return r;
3002
3003         r600_mc_program(rdev);
3004
3005         if (rdev->flags & RADEON_IS_AGP) {
3006                 r600_agp_enable(rdev);
3007         } else {
3008                 r = r600_pcie_gart_enable(rdev);
3009                 if (r)
3010                         return r;
3011         }
3012         r600_gpu_init(rdev);
3013
3014         /* allocate wb buffer */
3015         r = radeon_wb_init(rdev);
3016         if (r)
3017                 return r;
3018
3019         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3020         if (r) {
3021                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3022                 return r;
3023         }
3024
3025         if (rdev->has_uvd) {
3026                 r = uvd_v1_0_resume(rdev);
3027                 if (!r) {
3028                         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3029                         if (r) {
3030                                 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3031                         }
3032                 }
3033                 if (r)
3034                         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3035         }
3036
3037         /* Enable IRQ */
3038         if (!rdev->irq.installed) {
3039                 r = radeon_irq_kms_init(rdev);
3040                 if (r)
3041                         return r;
3042         }
3043
3044         r = r600_irq_init(rdev);
3045         if (r) {
3046                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3047                 radeon_irq_kms_fini(rdev);
3048                 return r;
3049         }
3050         r600_irq_set(rdev);
3051
3052         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3053         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3054                              RADEON_CP_PACKET2);
3055         if (r)
3056                 return r;
3057
3058         r = r600_cp_load_microcode(rdev);
3059         if (r)
3060                 return r;
3061         r = r600_cp_resume(rdev);
3062         if (r)
3063                 return r;
3064
3065         if (rdev->has_uvd) {
3066                 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3067                 if (ring->ring_size) {
3068                         r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
3069                                              RADEON_CP_PACKET2);
3070                         if (!r)
3071                                 r = uvd_v1_0_init(rdev);
3072                         if (r)
3073                                 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
3074                 }
3075         }
3076
3077         r = radeon_ib_pool_init(rdev);
3078         if (r) {
3079                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3080                 return r;
3081         }
3082
3083         r = radeon_audio_init(rdev);
3084         if (r) {
3085                 DRM_ERROR("radeon: audio init failed\n");
3086                 return r;
3087         }
3088
3089         return 0;
3090 }
3091
3092 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3093 {
3094         uint32_t temp;
3095
3096         temp = RREG32(CONFIG_CNTL);
3097         if (state == false) {
3098                 temp &= ~(1<<0);
3099                 temp |= (1<<1);
3100         } else {
3101                 temp &= ~(1<<1);
3102         }
3103         WREG32(CONFIG_CNTL, temp);
3104 }
3105
3106 int r600_resume(struct radeon_device *rdev)
3107 {
3108         int r;
3109
3110         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3111          * posting will perform necessary task to bring back GPU into good
3112          * shape.
3113          */
3114         /* post card */
3115         atom_asic_init(rdev->mode_info.atom_context);
3116
3117         if (rdev->pm.pm_method == PM_METHOD_DPM)
3118                 radeon_pm_resume(rdev);
3119
3120         rdev->accel_working = true;
3121         r = r600_startup(rdev);
3122         if (r) {
3123                 DRM_ERROR("r600 startup failed on resume\n");
3124                 rdev->accel_working = false;
3125                 return r;
3126         }
3127
3128         return r;
3129 }
3130
3131 int r600_suspend(struct radeon_device *rdev)
3132 {
3133         radeon_pm_suspend(rdev);
3134         radeon_audio_fini(rdev);
3135         r600_cp_stop(rdev);
3136         if (rdev->has_uvd) {
3137                 uvd_v1_0_fini(rdev);
3138                 radeon_uvd_suspend(rdev);
3139         }
3140         r600_irq_suspend(rdev);
3141         radeon_wb_disable(rdev);
3142         r600_pcie_gart_disable(rdev);
3143
3144         return 0;
3145 }
3146
3147 /* Plan is to move initialization in that function and use
3148  * helper function so that radeon_device_init pretty much
3149  * do nothing more than calling asic specific function. This
3150  * should also allow to remove a bunch of callback function
3151  * like vram_info.
3152  */
3153 int r600_init(struct radeon_device *rdev)
3154 {
3155         int r;
3156
3157         if (r600_debugfs_mc_info_init(rdev)) {
3158                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3159         }
3160         /* Read BIOS */
3161         if (!radeon_get_bios(rdev)) {
3162                 if (ASIC_IS_AVIVO(rdev))
3163                         return -EINVAL;
3164         }
3165         /* Must be an ATOMBIOS */
3166         if (!rdev->is_atom_bios) {
3167                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3168                 return -EINVAL;
3169         }
3170         r = radeon_atombios_init(rdev);
3171         if (r)
3172                 return r;
3173         /* Post card if necessary */
3174         if (!radeon_card_posted(rdev)) {
3175                 if (!rdev->bios) {
3176                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3177                         return -EINVAL;
3178                 }
3179                 DRM_INFO("GPU not posted. posting now...\n");
3180                 atom_asic_init(rdev->mode_info.atom_context);
3181         }
3182         /* Initialize scratch registers */
3183         r600_scratch_init(rdev);
3184         /* Initialize surface registers */
3185         radeon_surface_init(rdev);
3186         /* Initialize clocks */
3187         radeon_get_clock_info(rdev->ddev);
3188         /* Fence driver */
3189         r = radeon_fence_driver_init(rdev);
3190         if (r)
3191                 return r;
3192         if (rdev->flags & RADEON_IS_AGP) {
3193                 r = radeon_agp_init(rdev);
3194                 if (r)
3195                         radeon_agp_disable(rdev);
3196         }
3197         r = r600_mc_init(rdev);
3198         if (r)
3199                 return r;
3200         /* Memory manager */
3201         r = radeon_bo_init(rdev);
3202         if (r)
3203                 return r;
3204
3205         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3206                 r = r600_init_microcode(rdev);
3207                 if (r) {
3208                         DRM_ERROR("Failed to load firmware!\n");
3209                         return r;
3210                 }
3211         }
3212
3213         /* Initialize power management */
3214         radeon_pm_init(rdev);
3215
3216         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3217         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3218
3219         if (rdev->has_uvd) {
3220                 r = radeon_uvd_init(rdev);
3221                 if (!r) {
3222                         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3223                         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3224                 }
3225         }
3226
3227         rdev->ih.ring_obj = NULL;
3228         r600_ih_ring_init(rdev, 64 * 1024);
3229
3230         r = r600_pcie_gart_init(rdev);
3231         if (r)
3232                 return r;
3233
3234         rdev->accel_working = true;
3235         r = r600_startup(rdev);
3236         if (r) {
3237                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3238                 r600_cp_fini(rdev);
3239                 r600_irq_fini(rdev);
3240                 radeon_wb_fini(rdev);
3241                 radeon_ib_pool_fini(rdev);
3242                 radeon_irq_kms_fini(rdev);
3243                 r600_pcie_gart_fini(rdev);
3244                 rdev->accel_working = false;
3245         }
3246
3247         return 0;
3248 }
3249
3250 void r600_fini(struct radeon_device *rdev)
3251 {
3252         radeon_pm_fini(rdev);
3253         radeon_audio_fini(rdev);
3254         r600_cp_fini(rdev);
3255         r600_irq_fini(rdev);
3256         if (rdev->has_uvd) {
3257                 uvd_v1_0_fini(rdev);
3258                 radeon_uvd_fini(rdev);
3259         }
3260         radeon_wb_fini(rdev);
3261         radeon_ib_pool_fini(rdev);
3262         radeon_irq_kms_fini(rdev);
3263         r600_pcie_gart_fini(rdev);
3264         r600_vram_scratch_fini(rdev);
3265         radeon_agp_fini(rdev);
3266         radeon_gem_fini(rdev);
3267         radeon_fence_driver_fini(rdev);
3268         radeon_bo_fini(rdev);
3269         radeon_atombios_fini(rdev);
3270         kfree(rdev->bios);
3271         rdev->bios = NULL;
3272 }
3273
3274
3275 /*
3276  * CS stuff
3277  */
3278 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3279 {
3280         struct radeon_ring *ring = &rdev->ring[ib->ring];
3281         u32 next_rptr;
3282
3283         if (ring->rptr_save_reg) {
3284                 next_rptr = ring->wptr + 3 + 4;
3285                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3286                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3287                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3288                 radeon_ring_write(ring, next_rptr);
3289         } else if (rdev->wb.enabled) {
3290                 next_rptr = ring->wptr + 5 + 4;
3291                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3292                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3293                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3294                 radeon_ring_write(ring, next_rptr);
3295                 radeon_ring_write(ring, 0);
3296         }
3297
3298         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3299         radeon_ring_write(ring,
3300 #ifdef __BIG_ENDIAN
3301                           (2 << 0) |
3302 #endif
3303                           (ib->gpu_addr & 0xFFFFFFFC));
3304         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3305         radeon_ring_write(ring, ib->length_dw);
3306 }
3307
3308 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3309 {
3310         struct radeon_ib ib;
3311         uint32_t scratch;
3312         uint32_t tmp = 0;
3313         unsigned i;
3314         int r;
3315
3316         r = radeon_scratch_get(rdev, &scratch);
3317         if (r) {
3318                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3319                 return r;
3320         }
3321         WREG32(scratch, 0xCAFEDEAD);
3322         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3323         if (r) {
3324                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3325                 goto free_scratch;
3326         }
3327         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3328         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3329         ib.ptr[2] = 0xDEADBEEF;
3330         ib.length_dw = 3;
3331         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3332         if (r) {
3333                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3334                 goto free_ib;
3335         }
3336         r = radeon_fence_wait(ib.fence, false);
3337         if (r) {
3338                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3339                 goto free_ib;
3340         }
3341         for (i = 0; i < rdev->usec_timeout; i++) {
3342                 tmp = RREG32(scratch);
3343                 if (tmp == 0xDEADBEEF)
3344                         break;
3345                 DRM_UDELAY(1);
3346         }
3347         if (i < rdev->usec_timeout) {
3348                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3349         } else {
3350                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3351                           scratch, tmp);
3352                 r = -EINVAL;
3353         }
3354 free_ib:
3355         radeon_ib_free(rdev, &ib);
3356 free_scratch:
3357         radeon_scratch_free(rdev, scratch);
3358         return r;
3359 }
3360
3361 /*
3362  * Interrupts
3363  *
3364  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3365  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3366  * writing to the ring and the GPU consuming, the GPU writes to the ring
3367  * and host consumes.  As the host irq handler processes interrupts, it
3368  * increments the rptr.  When the rptr catches up with the wptr, all the
3369  * current interrupts have been processed.
3370  */
3371
3372 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3373 {
3374         u32 rb_bufsz;
3375
3376         /* Align ring size */
3377         rb_bufsz = order_base_2(ring_size / 4);
3378         ring_size = (1 << rb_bufsz) * 4;
3379         rdev->ih.ring_size = ring_size;
3380         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3381         rdev->ih.rptr = 0;
3382 }
3383
3384 int r600_ih_ring_alloc(struct radeon_device *rdev)
3385 {
3386         int r;
3387
3388         /* Allocate ring buffer */
3389         if (rdev->ih.ring_obj == NULL) {
3390                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3391                                      PAGE_SIZE, true,
3392                                      RADEON_GEM_DOMAIN_GTT, 0,
3393                                      NULL, NULL, &rdev->ih.ring_obj);
3394                 if (r) {
3395                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3396                         return r;
3397                 }
3398                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3399                 if (unlikely(r != 0))
3400                         return r;
3401                 r = radeon_bo_pin(rdev->ih.ring_obj,
3402                                   RADEON_GEM_DOMAIN_GTT,
3403                                   &rdev->ih.gpu_addr);
3404                 if (r) {
3405                         radeon_bo_unreserve(rdev->ih.ring_obj);
3406                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3407                         return r;
3408                 }
3409                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3410                                    (void **)&rdev->ih.ring);
3411                 radeon_bo_unreserve(rdev->ih.ring_obj);
3412                 if (r) {
3413                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3414                         return r;
3415                 }
3416         }
3417         return 0;
3418 }
3419
3420 void r600_ih_ring_fini(struct radeon_device *rdev)
3421 {
3422         int r;
3423         if (rdev->ih.ring_obj) {
3424                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3425                 if (likely(r == 0)) {
3426                         radeon_bo_kunmap(rdev->ih.ring_obj);
3427                         radeon_bo_unpin(rdev->ih.ring_obj);
3428                         radeon_bo_unreserve(rdev->ih.ring_obj);
3429                 }
3430                 radeon_bo_unref(&rdev->ih.ring_obj);
3431                 rdev->ih.ring = NULL;
3432                 rdev->ih.ring_obj = NULL;
3433         }
3434 }
3435
3436 void r600_rlc_stop(struct radeon_device *rdev)
3437 {
3438
3439         if ((rdev->family >= CHIP_RV770) &&
3440             (rdev->family <= CHIP_RV740)) {
3441                 /* r7xx asics need to soft reset RLC before halting */
3442                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3443                 RREG32(SRBM_SOFT_RESET);
3444                 mdelay(15);
3445                 WREG32(SRBM_SOFT_RESET, 0);
3446                 RREG32(SRBM_SOFT_RESET);
3447         }
3448
3449         WREG32(RLC_CNTL, 0);
3450 }
3451
3452 static void r600_rlc_start(struct radeon_device *rdev)
3453 {
3454         WREG32(RLC_CNTL, RLC_ENABLE);
3455 }
3456
3457 static int r600_rlc_resume(struct radeon_device *rdev)
3458 {
3459         u32 i;
3460         const __be32 *fw_data;
3461
3462         if (!rdev->rlc_fw)
3463                 return -EINVAL;
3464
3465         r600_rlc_stop(rdev);
3466
3467         WREG32(RLC_HB_CNTL, 0);
3468
3469         WREG32(RLC_HB_BASE, 0);
3470         WREG32(RLC_HB_RPTR, 0);
3471         WREG32(RLC_HB_WPTR, 0);
3472         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3473         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3474         WREG32(RLC_MC_CNTL, 0);
3475         WREG32(RLC_UCODE_CNTL, 0);
3476
3477         fw_data = (const __be32 *)rdev->rlc_fw->data;
3478         if (rdev->family >= CHIP_RV770) {
3479                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3480                         WREG32(RLC_UCODE_ADDR, i);
3481                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3482                 }
3483         } else {
3484                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3485                         WREG32(RLC_UCODE_ADDR, i);
3486                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3487                 }
3488         }
3489         WREG32(RLC_UCODE_ADDR, 0);
3490
3491         r600_rlc_start(rdev);
3492
3493         return 0;
3494 }
3495
3496 static void r600_enable_interrupts(struct radeon_device *rdev)
3497 {
3498         u32 ih_cntl = RREG32(IH_CNTL);
3499         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3500
3501         ih_cntl |= ENABLE_INTR;
3502         ih_rb_cntl |= IH_RB_ENABLE;
3503         WREG32(IH_CNTL, ih_cntl);
3504         WREG32(IH_RB_CNTL, ih_rb_cntl);
3505         rdev->ih.enabled = true;
3506 }
3507
3508 void r600_disable_interrupts(struct radeon_device *rdev)
3509 {
3510         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3511         u32 ih_cntl = RREG32(IH_CNTL);
3512
3513         ih_rb_cntl &= ~IH_RB_ENABLE;
3514         ih_cntl &= ~ENABLE_INTR;
3515         WREG32(IH_RB_CNTL, ih_rb_cntl);
3516         WREG32(IH_CNTL, ih_cntl);
3517         /* set rptr, wptr to 0 */
3518         WREG32(IH_RB_RPTR, 0);
3519         WREG32(IH_RB_WPTR, 0);
3520         rdev->ih.enabled = false;
3521         rdev->ih.rptr = 0;
3522 }
3523
3524 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3525 {
3526         u32 tmp;
3527
3528         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3529         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3530         WREG32(DMA_CNTL, tmp);
3531         WREG32(GRBM_INT_CNTL, 0);
3532         WREG32(DxMODE_INT_MASK, 0);
3533         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3534         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3535         if (ASIC_IS_DCE3(rdev)) {
3536                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3537                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3538                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3539                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3540                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3541                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3542                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3543                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3544                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3545                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3546                 if (ASIC_IS_DCE32(rdev)) {
3547                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3548                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3549                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3550                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3551                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3552                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3553                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3554                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3555                 } else {
3556                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3557                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3558                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3559                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3560                 }
3561         } else {
3562                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3563                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3564                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3565                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3566                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3567                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3568                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3569                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3570                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3571                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3572                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3573                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3574         }
3575 }
3576
3577 int r600_irq_init(struct radeon_device *rdev)
3578 {
3579         int ret = 0;
3580         int rb_bufsz;
3581         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3582
3583         /* allocate ring */
3584         ret = r600_ih_ring_alloc(rdev);
3585         if (ret)
3586                 return ret;
3587
3588         /* disable irqs */
3589         r600_disable_interrupts(rdev);
3590
3591         /* init rlc */
3592         if (rdev->family >= CHIP_CEDAR)
3593                 ret = evergreen_rlc_resume(rdev);
3594         else
3595                 ret = r600_rlc_resume(rdev);
3596         if (ret) {
3597                 r600_ih_ring_fini(rdev);
3598                 return ret;
3599         }
3600
3601         /* setup interrupt control */
3602         /* set dummy read address to dummy page address */
3603         WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3604         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3605         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3606          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3607          */
3608         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3609         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3610         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3611         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3612
3613         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3614         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3615
3616         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3617                       IH_WPTR_OVERFLOW_CLEAR |
3618                       (rb_bufsz << 1));
3619
3620         if (rdev->wb.enabled)
3621                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3622
3623         /* set the writeback address whether it's enabled or not */
3624         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3625         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3626
3627         WREG32(IH_RB_CNTL, ih_rb_cntl);
3628
3629         /* set rptr, wptr to 0 */
3630         WREG32(IH_RB_RPTR, 0);
3631         WREG32(IH_RB_WPTR, 0);
3632
3633         /* Default settings for IH_CNTL (disabled at first) */
3634         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3635         /* RPTR_REARM only works if msi's are enabled */
3636         if (rdev->msi_enabled)
3637                 ih_cntl |= RPTR_REARM;
3638         WREG32(IH_CNTL, ih_cntl);
3639
3640         /* force the active interrupt state to all disabled */
3641         if (rdev->family >= CHIP_CEDAR)
3642                 evergreen_disable_interrupt_state(rdev);
3643         else
3644                 r600_disable_interrupt_state(rdev);
3645
3646         /* at this point everything should be setup correctly to enable master */
3647         pci_set_master(rdev->pdev);
3648
3649         /* enable irqs */
3650         r600_enable_interrupts(rdev);
3651
3652         return ret;
3653 }
3654
3655 void r600_irq_suspend(struct radeon_device *rdev)
3656 {
3657         r600_irq_disable(rdev);
3658         r600_rlc_stop(rdev);
3659 }
3660
3661 void r600_irq_fini(struct radeon_device *rdev)
3662 {
3663         r600_irq_suspend(rdev);
3664         r600_ih_ring_fini(rdev);
3665 }
3666
3667 int r600_irq_set(struct radeon_device *rdev)
3668 {
3669         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3670         u32 mode_int = 0;
3671         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3672         u32 grbm_int_cntl = 0;
3673         u32 hdmi0, hdmi1;
3674         u32 dma_cntl;
3675         u32 thermal_int = 0;
3676
3677         if (!rdev->irq.installed) {
3678                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3679                 return -EINVAL;
3680         }
3681         /* don't enable anything if the ih is disabled */
3682         if (!rdev->ih.enabled) {
3683                 r600_disable_interrupts(rdev);
3684                 /* force the active interrupt state to all disabled */
3685                 r600_disable_interrupt_state(rdev);
3686                 return 0;
3687         }
3688
3689         if (ASIC_IS_DCE3(rdev)) {
3690                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3691                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3692                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3693                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3694                 if (ASIC_IS_DCE32(rdev)) {
3695                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3696                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3697                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3698                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3699                 } else {
3700                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3701                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3702                 }
3703         } else {
3704                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3705                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3706                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3707                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3708                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3709         }
3710
3711         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3712
3713         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3714                 thermal_int = RREG32(CG_THERMAL_INT) &
3715                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3716         } else if (rdev->family >= CHIP_RV770) {
3717                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3718                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3719         }
3720         if (rdev->irq.dpm_thermal) {
3721                 DRM_DEBUG("dpm thermal\n");
3722                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3723         }
3724
3725         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3726                 DRM_DEBUG("r600_irq_set: sw int\n");
3727                 cp_int_cntl |= RB_INT_ENABLE;
3728                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3729         }
3730
3731         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3732                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3733                 dma_cntl |= TRAP_ENABLE;
3734         }
3735
3736         if (rdev->irq.crtc_vblank_int[0] ||
3737             atomic_read(&rdev->irq.pflip[0])) {
3738                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3739                 mode_int |= D1MODE_VBLANK_INT_MASK;
3740         }
3741         if (rdev->irq.crtc_vblank_int[1] ||
3742             atomic_read(&rdev->irq.pflip[1])) {
3743                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3744                 mode_int |= D2MODE_VBLANK_INT_MASK;
3745         }
3746         if (rdev->irq.hpd[0]) {
3747                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3748                 hpd1 |= DC_HPDx_INT_EN;
3749         }
3750         if (rdev->irq.hpd[1]) {
3751                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3752                 hpd2 |= DC_HPDx_INT_EN;
3753         }
3754         if (rdev->irq.hpd[2]) {
3755                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3756                 hpd3 |= DC_HPDx_INT_EN;
3757         }
3758         if (rdev->irq.hpd[3]) {
3759                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3760                 hpd4 |= DC_HPDx_INT_EN;
3761         }
3762         if (rdev->irq.hpd[4]) {
3763                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3764                 hpd5 |= DC_HPDx_INT_EN;
3765         }
3766         if (rdev->irq.hpd[5]) {
3767                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3768                 hpd6 |= DC_HPDx_INT_EN;
3769         }
3770         if (rdev->irq.afmt[0]) {
3771                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3772                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3773         }
3774         if (rdev->irq.afmt[1]) {
3775                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3776                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3777         }
3778
3779         WREG32(CP_INT_CNTL, cp_int_cntl);
3780         WREG32(DMA_CNTL, dma_cntl);
3781         WREG32(DxMODE_INT_MASK, mode_int);
3782         WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3783         WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3784         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3785         if (ASIC_IS_DCE3(rdev)) {
3786                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3787                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3788                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3789                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3790                 if (ASIC_IS_DCE32(rdev)) {
3791                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3792                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3793                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3794                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3795                 } else {
3796                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3797                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3798                 }
3799         } else {
3800                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3801                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3802                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3803                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3804                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3805         }
3806         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3807                 WREG32(CG_THERMAL_INT, thermal_int);
3808         } else if (rdev->family >= CHIP_RV770) {
3809                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3810         }
3811
3812         /* posting read */
3813         RREG32(R_000E50_SRBM_STATUS);
3814
3815         return 0;
3816 }
3817
3818 static void r600_irq_ack(struct radeon_device *rdev)
3819 {
3820         u32 tmp;
3821
3822         if (ASIC_IS_DCE3(rdev)) {
3823                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3824                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3825                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3826                 if (ASIC_IS_DCE32(rdev)) {
3827                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3828                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3829                 } else {
3830                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3831                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3832                 }
3833         } else {
3834                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3835                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3836                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3837                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3838                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3839         }
3840         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3841         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3842
3843         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3844                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3845         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3846                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3847         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3848                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3849         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3850                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3851         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3852                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3853         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3854                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3855         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3856                 if (ASIC_IS_DCE3(rdev)) {
3857                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3858                         tmp |= DC_HPDx_INT_ACK;
3859                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3860                 } else {
3861                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3862                         tmp |= DC_HPDx_INT_ACK;
3863                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3864                 }
3865         }
3866         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3867                 if (ASIC_IS_DCE3(rdev)) {
3868                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3869                         tmp |= DC_HPDx_INT_ACK;
3870                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3871                 } else {
3872                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3873                         tmp |= DC_HPDx_INT_ACK;
3874                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3875                 }
3876         }
3877         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3878                 if (ASIC_IS_DCE3(rdev)) {
3879                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3880                         tmp |= DC_HPDx_INT_ACK;
3881                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3882                 } else {
3883                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3884                         tmp |= DC_HPDx_INT_ACK;
3885                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3886                 }
3887         }
3888         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3889                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3890                 tmp |= DC_HPDx_INT_ACK;
3891                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3892         }
3893         if (ASIC_IS_DCE32(rdev)) {
3894                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3895                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3896                         tmp |= DC_HPDx_INT_ACK;
3897                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3898                 }
3899                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3900                         tmp = RREG32(DC_HPD6_INT_CONTROL);
3901                         tmp |= DC_HPDx_INT_ACK;
3902                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3903                 }
3904                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3905                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3906                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3907                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3908                 }
3909                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3910                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3911                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3912                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3913                 }
3914         } else {
3915                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3916                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3917                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3918                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3919                 }
3920                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3921                         if (ASIC_IS_DCE3(rdev)) {
3922                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3923                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3924                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3925                         } else {
3926                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3927                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3928                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3929                         }
3930                 }
3931         }
3932 }
3933
3934 void r600_irq_disable(struct radeon_device *rdev)
3935 {
3936         r600_disable_interrupts(rdev);
3937         /* Wait and acknowledge irq */
3938         mdelay(1);
3939         r600_irq_ack(rdev);
3940         r600_disable_interrupt_state(rdev);
3941 }
3942
3943 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3944 {
3945         u32 wptr, tmp;
3946
3947         if (rdev->wb.enabled)
3948                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3949         else
3950                 wptr = RREG32(IH_RB_WPTR);
3951
3952         if (wptr & RB_OVERFLOW) {
3953                 wptr &= ~RB_OVERFLOW;
3954                 /* When a ring buffer overflow happen start parsing interrupt
3955                  * from the last not overwritten vector (wptr + 16). Hopefully
3956                  * this should allow us to catchup.
3957                  */
3958                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
3959                          wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
3960                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3961                 tmp = RREG32(IH_RB_CNTL);
3962                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3963                 WREG32(IH_RB_CNTL, tmp);
3964         }
3965         return (wptr & rdev->ih.ptr_mask);
3966 }
3967
3968 /*        r600 IV Ring
3969  * Each IV ring entry is 128 bits:
3970  * [7:0]    - interrupt source id
3971  * [31:8]   - reserved
3972  * [59:32]  - interrupt source data
3973  * [127:60]  - reserved
3974  *
3975  * The basic interrupt vector entries
3976  * are decoded as follows:
3977  * src_id  src_data  description
3978  *      1         0  D1 Vblank
3979  *      1         1  D1 Vline
3980  *      5         0  D2 Vblank
3981  *      5         1  D2 Vline
3982  *     19         0  FP Hot plug detection A
3983  *     19         1  FP Hot plug detection B
3984  *     19         2  DAC A auto-detection
3985  *     19         3  DAC B auto-detection
3986  *     21         4  HDMI block A
3987  *     21         5  HDMI block B
3988  *    176         -  CP_INT RB
3989  *    177         -  CP_INT IB1
3990  *    178         -  CP_INT IB2
3991  *    181         -  EOP Interrupt
3992  *    233         -  GUI Idle
3993  *
3994  * Note, these are based on r600 and may need to be
3995  * adjusted or added to on newer asics
3996  */
3997
3998 int r600_irq_process(struct radeon_device *rdev)
3999 {
4000         u32 wptr;
4001         u32 rptr;
4002         u32 src_id, src_data;
4003         u32 ring_index;
4004         bool queue_hotplug = false;
4005         bool queue_hdmi = false;
4006         bool queue_thermal = false;
4007
4008         if (!rdev->ih.enabled || rdev->shutdown)
4009                 return IRQ_NONE;
4010
4011         /* No MSIs, need a dummy read to flush PCI DMAs */
4012         if (!rdev->msi_enabled)
4013                 RREG32(IH_RB_WPTR);
4014
4015         wptr = r600_get_ih_wptr(rdev);
4016
4017 restart_ih:
4018         /* is somebody else already processing irqs? */
4019         if (atomic_xchg(&rdev->ih.lock, 1))
4020                 return IRQ_NONE;
4021
4022         rptr = rdev->ih.rptr;
4023         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4024
4025         /* Order reading of wptr vs. reading of IH ring data */
4026         rmb();
4027
4028         /* display interrupts */
4029         r600_irq_ack(rdev);
4030
4031         while (rptr != wptr) {
4032                 /* wptr/rptr are in bytes! */
4033                 ring_index = rptr / 4;
4034                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4035                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4036
4037                 switch (src_id) {
4038                 case 1: /* D1 vblank/vline */
4039                         switch (src_data) {
4040                         case 0: /* D1 vblank */
4041                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4042                                         DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4043
4044                                 if (rdev->irq.crtc_vblank_int[0]) {
4045                                         drm_handle_vblank(rdev->ddev, 0);
4046                                         rdev->pm.vblank_sync = true;
4047                                         wake_up(&rdev->irq.vblank_queue);
4048                                 }
4049                                 if (atomic_read(&rdev->irq.pflip[0]))
4050                                         radeon_crtc_handle_vblank(rdev, 0);
4051                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4052                                 DRM_DEBUG("IH: D1 vblank\n");
4053
4054                                 break;
4055                         case 1: /* D1 vline */
4056                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4057                                     DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4058
4059                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4060                                 DRM_DEBUG("IH: D1 vline\n");
4061
4062                                 break;
4063                         default:
4064                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4065                                 break;
4066                         }
4067                         break;
4068                 case 5: /* D2 vblank/vline */
4069                         switch (src_data) {
4070                         case 0: /* D2 vblank */
4071                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4072                                         DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4073
4074                                 if (rdev->irq.crtc_vblank_int[1]) {
4075                                         drm_handle_vblank(rdev->ddev, 1);
4076                                         rdev->pm.vblank_sync = true;
4077                                         wake_up(&rdev->irq.vblank_queue);
4078                                 }
4079                                 if (atomic_read(&rdev->irq.pflip[1]))
4080                                         radeon_crtc_handle_vblank(rdev, 1);
4081                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4082                                 DRM_DEBUG("IH: D2 vblank\n");
4083
4084                                 break;
4085                         case 1: /* D1 vline */
4086                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4087                                         DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4088
4089                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4090                                 DRM_DEBUG("IH: D2 vline\n");
4091
4092                                 break;
4093                         default:
4094                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4095                                 break;
4096                         }
4097                         break;
4098                 case 9: /* D1 pflip */
4099                         DRM_DEBUG("IH: D1 flip\n");
4100                         if (radeon_use_pflipirq > 0)
4101                                 radeon_crtc_handle_flip(rdev, 0);
4102                         break;
4103                 case 11: /* D2 pflip */
4104                         DRM_DEBUG("IH: D2 flip\n");
4105                         if (radeon_use_pflipirq > 0)
4106                                 radeon_crtc_handle_flip(rdev, 1);
4107                         break;
4108                 case 19: /* HPD/DAC hotplug */
4109                         switch (src_data) {
4110                         case 0:
4111                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4112                                         DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4113
4114                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4115                                 queue_hotplug = true;
4116                                 DRM_DEBUG("IH: HPD1\n");
4117                                 break;
4118                         case 1:
4119                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4120                                         DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4121
4122                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4123                                 queue_hotplug = true;
4124                                 DRM_DEBUG("IH: HPD2\n");
4125                                 break;
4126                         case 4:
4127                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4128                                         DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4129
4130                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4131                                 queue_hotplug = true;
4132                                 DRM_DEBUG("IH: HPD3\n");
4133                                 break;
4134                         case 5:
4135                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4136                                         DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4137
4138                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4139                                 queue_hotplug = true;
4140                                 DRM_DEBUG("IH: HPD4\n");
4141                                 break;
4142                         case 10:
4143                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4144                                         DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4145
4146                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4147                                 queue_hotplug = true;
4148                                 DRM_DEBUG("IH: HPD5\n");
4149                                 break;
4150                         case 12:
4151                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4152                                         DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4153
4154                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4155                                 queue_hotplug = true;
4156                                 DRM_DEBUG("IH: HPD6\n");
4157
4158                                 break;
4159                         default:
4160                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4161                                 break;
4162                         }
4163                         break;
4164                 case 21: /* hdmi */
4165                         switch (src_data) {
4166                         case 4:
4167                                 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4168                                         DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4169
4170                                 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4171                                 queue_hdmi = true;
4172                                 DRM_DEBUG("IH: HDMI0\n");
4173
4174                                 break;
4175                         case 5:
4176                                 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4177                                         DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4178
4179                                 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4180                                 queue_hdmi = true;
4181                                 DRM_DEBUG("IH: HDMI1\n");
4182
4183                                 break;
4184                         default:
4185                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4186                                 break;
4187                         }
4188                         break;
4189                 case 124: /* UVD */
4190                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4191                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4192                         break;
4193                 case 176: /* CP_INT in ring buffer */
4194                 case 177: /* CP_INT in IB1 */
4195                 case 178: /* CP_INT in IB2 */
4196                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4197                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4198                         break;
4199                 case 181: /* CP EOP event */
4200                         DRM_DEBUG("IH: CP EOP\n");
4201                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4202                         break;
4203                 case 224: /* DMA trap event */
4204                         DRM_DEBUG("IH: DMA trap\n");
4205                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4206                         break;
4207                 case 230: /* thermal low to high */
4208                         DRM_DEBUG("IH: thermal low to high\n");
4209                         rdev->pm.dpm.thermal.high_to_low = false;
4210                         queue_thermal = true;
4211                         break;
4212                 case 231: /* thermal high to low */
4213                         DRM_DEBUG("IH: thermal high to low\n");
4214                         rdev->pm.dpm.thermal.high_to_low = true;
4215                         queue_thermal = true;
4216                         break;
4217                 case 233: /* GUI IDLE */
4218                         DRM_DEBUG("IH: GUI idle\n");
4219                         break;
4220                 default:
4221                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4222                         break;
4223                 }
4224
4225                 /* wptr/rptr are in bytes! */
4226                 rptr += 16;
4227                 rptr &= rdev->ih.ptr_mask;
4228                 WREG32(IH_RB_RPTR, rptr);
4229         }
4230         if (queue_hotplug)
4231                 schedule_delayed_work(&rdev->hotplug_work, 0);
4232         if (queue_hdmi)
4233                 schedule_work(&rdev->audio_work);
4234         if (queue_thermal && rdev->pm.dpm_enabled)
4235                 schedule_work(&rdev->pm.dpm.thermal.work);
4236         rdev->ih.rptr = rptr;
4237         atomic_set(&rdev->ih.lock, 0);
4238
4239         /* make sure wptr hasn't changed while processing */
4240         wptr = r600_get_ih_wptr(rdev);
4241         if (wptr != rptr)
4242                 goto restart_ih;
4243
4244         return IRQ_HANDLED;
4245 }
4246
4247 /*
4248  * Debugfs info
4249  */
4250 #if defined(CONFIG_DEBUG_FS)
4251
4252 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4253 {
4254         struct drm_info_node *node = (struct drm_info_node *) m->private;
4255         struct drm_device *dev = node->minor->dev;
4256         struct radeon_device *rdev = dev->dev_private;
4257
4258         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4259         DREG32_SYS(m, rdev, VM_L2_STATUS);
4260         return 0;
4261 }
4262
4263 static struct drm_info_list r600_mc_info_list[] = {
4264         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4265 };
4266 #endif
4267
4268 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4269 {
4270 #if defined(CONFIG_DEBUG_FS)
4271         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4272 #else
4273         return 0;
4274 #endif
4275 }
4276
4277 /**
4278  * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4279  * rdev: radeon device structure
4280  *
4281  * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4282  * through the ring buffer. This leads to corruption in rendering, see
4283  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4284  * directly perform the HDP flush by writing the register through MMIO.
4285  */
4286 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4287 {
4288         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4289          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4290          * This seems to cause problems on some AGP cards. Just use the old
4291          * method for them.
4292          */
4293         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4294             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4295                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4296                 u32 tmp;
4297
4298                 WREG32(HDP_DEBUG1, 0);
4299                 tmp = readl((void __iomem *)ptr);
4300         } else
4301                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4302 }
4303
4304 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4305 {
4306         u32 link_width_cntl, mask;
4307
4308         if (rdev->flags & RADEON_IS_IGP)
4309                 return;
4310
4311         if (!(rdev->flags & RADEON_IS_PCIE))
4312                 return;
4313
4314         /* x2 cards have a special sequence */
4315         if (ASIC_IS_X2(rdev))
4316                 return;
4317
4318         radeon_gui_idle(rdev);
4319
4320         switch (lanes) {
4321         case 0:
4322                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4323                 break;
4324         case 1:
4325                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4326                 break;
4327         case 2:
4328                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4329                 break;
4330         case 4:
4331                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4332                 break;
4333         case 8:
4334                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4335                 break;
4336         case 12:
4337                 /* not actually supported */
4338                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4339                 break;
4340         case 16:
4341                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4342                 break;
4343         default:
4344                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4345                 return;
4346         }
4347
4348         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4349         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4350         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4351         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4352                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4353
4354         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4355 }
4356
4357 int r600_get_pcie_lanes(struct radeon_device *rdev)
4358 {
4359         u32 link_width_cntl;
4360
4361         if (rdev->flags & RADEON_IS_IGP)
4362                 return 0;
4363
4364         if (!(rdev->flags & RADEON_IS_PCIE))
4365                 return 0;
4366
4367         /* x2 cards have a special sequence */
4368         if (ASIC_IS_X2(rdev))
4369                 return 0;
4370
4371         radeon_gui_idle(rdev);
4372
4373         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4374
4375         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4376         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4377                 return 1;
4378         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4379                 return 2;
4380         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4381                 return 4;
4382         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4383                 return 8;
4384         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4385                 /* not actually supported */
4386                 return 12;
4387         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4388         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4389         default:
4390                 return 16;
4391         }
4392 }
4393
4394 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4395 {
4396         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4397         u16 link_cntl2;
4398
4399         if (radeon_pcie_gen2 == 0)
4400                 return;
4401
4402         if (rdev->flags & RADEON_IS_IGP)
4403                 return;
4404
4405         if (!(rdev->flags & RADEON_IS_PCIE))
4406                 return;
4407
4408         /* x2 cards have a special sequence */
4409         if (ASIC_IS_X2(rdev))
4410                 return;
4411
4412         /* only RV6xx+ chips are supported */
4413         if (rdev->family <= CHIP_R600)
4414                 return;
4415
4416         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4417                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4418                 return;
4419
4420         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4421         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4422                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4423                 return;
4424         }
4425
4426         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4427
4428         /* 55 nm r6xx asics */
4429         if ((rdev->family == CHIP_RV670) ||
4430             (rdev->family == CHIP_RV620) ||
4431             (rdev->family == CHIP_RV635)) {
4432                 /* advertise upconfig capability */
4433                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4434                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4435                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4436                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4437                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4438                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4439                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4440                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4441                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4442                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4443                 } else {
4444                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4445                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4446                 }
4447         }
4448
4449         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4450         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4451             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4452
4453                 /* 55 nm r6xx asics */
4454                 if ((rdev->family == CHIP_RV670) ||
4455                     (rdev->family == CHIP_RV620) ||
4456                     (rdev->family == CHIP_RV635)) {
4457                         WREG32(MM_CFGREGS_CNTL, 0x8);
4458                         link_cntl2 = RREG32(0x4088);
4459                         WREG32(MM_CFGREGS_CNTL, 0);
4460                         /* not supported yet */
4461                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4462                                 return;
4463                 }
4464
4465                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4466                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4467                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4468                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4469                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4470                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4471
4472                 tmp = RREG32(0x541c);
4473                 WREG32(0x541c, tmp | 0x8);
4474                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4475                 link_cntl2 = RREG16(0x4088);
4476                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4477                 link_cntl2 |= 0x2;
4478                 WREG16(0x4088, link_cntl2);
4479                 WREG32(MM_CFGREGS_CNTL, 0);
4480
4481                 if ((rdev->family == CHIP_RV670) ||
4482                     (rdev->family == CHIP_RV620) ||
4483                     (rdev->family == CHIP_RV635)) {
4484                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4485                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4486                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4487                 } else {
4488                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4489                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4490                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4491                 }
4492
4493                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4494                 speed_cntl |= LC_GEN2_EN_STRAP;
4495                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4496
4497         } else {
4498                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4499                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4500                 if (1)
4501                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4502                 else
4503                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4504                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4505         }
4506 }
4507
4508 /**
4509  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4510  *
4511  * @rdev: radeon_device pointer
4512  *
4513  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4514  * Returns the 64 bit clock counter snapshot.
4515  */
4516 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4517 {
4518         uint64_t clock;
4519
4520         mutex_lock(&rdev->gpu_clock_mutex);
4521         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4522         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4523                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4524         mutex_unlock(&rdev->gpu_clock_mutex);
4525         return clock;
4526 }