drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/firmware.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/slab.h>
  33 #include <linux/seq_file.h>
  34
  35 #include <drm/drm_device.h>
  36 #include <drm/drm_vblank.h>
  37 #include <drm/radeon_drm.h>
  38
  39 #include "atom.h"
  40 #include "avivod.h"
  41 #include "evergreen.h"
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "rv770.h"
  45 #include "radeon.h"
  46 #include "radeon_asic.h"
  47 #include "radeon_audio.h"
  48 #include "radeon_mode.h"
  49 #include "radeon_ucode.h"
  50
  51 /* Firmware Names */
  52 /*(DEBLOBBED)*/
  53
  54 static const u32 crtc_offsets[2] =
  55 {
  56         0,
  57         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  58 };
  59
  60 static void r600_debugfs_mc_info_init(struct radeon_device *rdev);
  61
  62 /* r600,rv610,rv630,rv620,rv635,rv670 */
  63 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  64 static void r600_gpu_init(struct radeon_device *rdev);
  65 void r600_fini(struct radeon_device *rdev);
  66 void r600_irq_disable(struct radeon_device *rdev);
  67 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  68
  69 /*
  70  * Indirect registers accessor
  71  */
  72 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
  73 {
  74         unsigned long flags;
  75         u32 r;
  76
  77         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  78         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  79         r = RREG32(R600_RCU_DATA);
  80         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  81         return r;
  82 }
  83
  84 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  85 {
  86         unsigned long flags;
  87
  88         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  89         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  90         WREG32(R600_RCU_DATA, (v));
  91         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  92 }
  93
  94 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
  95 {
  96         unsigned long flags;
  97         u32 r;
  98
  99         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 100         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 101         r = RREG32(R600_UVD_CTX_DATA);
 102         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 103         return r;
 104 }
 105
 106 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 107 {
 108         unsigned long flags;
 109
 110         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 111         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 112         WREG32(R600_UVD_CTX_DATA, (v));
 113         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 114 }
 115
 116 /**
 117  * r600_get_allowed_info_register - fetch the register for the info ioctl
 118  *
 119  * @rdev: radeon_device pointer
 120  * @reg: register offset in bytes
 121  * @val: register value
 122  *
 123  * Returns 0 for success or -EINVAL for an invalid register
 124  *
 125  */
 126 int r600_get_allowed_info_register(struct radeon_device *rdev,
 127                                    u32 reg, u32 *val)
 128 {
 129         switch (reg) {
 130         case GRBM_STATUS:
 131         case GRBM_STATUS2:
 132         case R_000E50_SRBM_STATUS:
 133         case DMA_STATUS_REG:
 134         case UVD_STATUS:
 135                 *val = RREG32(reg);
 136                 return 0;
 137         default:
 138                 return -EINVAL;
 139         }
 140 }
 141
 142 /**
 143  * r600_get_xclk - get the xclk
 144  *
 145  * @rdev: radeon_device pointer
 146  *
 147  * Returns the reference clock used by the gfx engine
 148  * (r6xx, IGPs, APUs).
 149  */
 150 u32 r600_get_xclk(struct radeon_device *rdev)
 151 {
 152         return rdev->clock.spll.reference_freq;
 153 }
 154
 155 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 156 {
 157         unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
 158         int r;
 159
 160         /* bypass vclk and dclk with bclk */
 161         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 162                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
 163                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 164
 165         /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
 166         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
 167                  UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
 168
 169         if (rdev->family >= CHIP_RS780)
 170                 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
 171                          ~UPLL_BYPASS_CNTL);
 172
 173         if (!vclk || !dclk) {
 174                 /* keep the Bypass mode, put PLL to sleep */
 175                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
 176                 return 0;
 177         }
 178
 179         if (rdev->clock.spll.reference_freq == 10000)
 180                 ref_div = 34;
 181         else
 182                 ref_div = 4;
 183
 184         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
 185                                           ref_div + 1, 0xFFF, 2, 30, ~0,
 186                                           &fb_div, &vclk_div, &dclk_div);
 187         if (r)
 188                 return r;
 189
 190         if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
 191                 fb_div >>= 1;
 192         else
 193                 fb_div |= 1;
 194
 195         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 196         if (r)
 197                 return r;
 198
 199         /* assert PLL_RESET */
 200         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
 201
 202         /* For RS780 we have to choose ref clk */
 203         if (rdev->family >= CHIP_RS780)
 204                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
 205                          ~UPLL_REFCLK_SRC_SEL_MASK);
 206
 207         /* set the required fb, ref and post divder values */
 208         WREG32_P(CG_UPLL_FUNC_CNTL,
 209                  UPLL_FB_DIV(fb_div) |
 210                  UPLL_REF_DIV(ref_div),
 211                  ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
 212         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 213                  UPLL_SW_HILEN(vclk_div >> 1) |
 214                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
 215                  UPLL_SW_HILEN2(dclk_div >> 1) |
 216                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
 217                  UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
 218                  ~UPLL_SW_MASK);
 219
 220         /* give the PLL some time to settle */
 221         mdelay(15);
 222
 223         /* deassert PLL_RESET */
 224         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 225
 226         mdelay(15);
 227
 228         /* deassert BYPASS EN */
 229         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 230
 231         if (rdev->family >= CHIP_RS780)
 232                 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
 233
 234         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 235         if (r)
 236                 return r;
 237
 238         /* switch VCLK and DCLK selection */
 239         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 240                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 241                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 242
 243         mdelay(100);
 244
 245         return 0;
 246 }
 247
 248 void dce3_program_fmt(struct drm_encoder *encoder)
 249 {
 250         struct drm_device *dev = encoder->dev;
 251         struct radeon_device *rdev = dev->dev_private;
 252         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 253         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 254         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 255         int bpc = 0;
 256         u32 tmp = 0;
 257         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 258
 259         if (connector) {
 260                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 261                 bpc = radeon_get_monitor_bpc(connector);
 262                 dither = radeon_connector->dither;
 263         }
 264
 265         /* LVDS FMT is set up by atom */
 266         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 267                 return;
 268
 269         /* not needed for analog */
 270         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 271             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 272                 return;
 273
 274         if (bpc == 0)
 275                 return;
 276
 277         switch (bpc) {
 278         case 6:
 279                 if (dither == RADEON_FMT_DITHER_ENABLE)
 280                         /* XXX sort out optimal dither settings */
 281                         tmp |= FMT_SPATIAL_DITHER_EN;
 282                 else
 283                         tmp |= FMT_TRUNCATE_EN;
 284                 break;
 285         case 8:
 286                 if (dither == RADEON_FMT_DITHER_ENABLE)
 287                         /* XXX sort out optimal dither settings */
 288                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 289                 else
 290                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 291                 break;
 292         case 10:
 293         default:
 294                 /* not needed */
 295                 break;
 296         }
 297
 298         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 299 }
 300
 301 /* get temperature in millidegrees */
 302 int rv6xx_get_temp(struct radeon_device *rdev)
 303 {
 304         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 305                 ASIC_T_SHIFT;
 306         int actual_temp = temp & 0xff;
 307
 308         if (temp & 0x100)
 309                 actual_temp -= 256;
 310
 311         return actual_temp * 1000;
 312 }
 313
 314 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 315 {
 316         int i;
 317
 318         rdev->pm.dynpm_can_upclock = true;
 319         rdev->pm.dynpm_can_downclock = true;
 320
 321         /* power state array is low to high, default is first */
 322         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 323                 int min_power_state_index = 0;
 324
 325                 if (rdev->pm.num_power_states > 2)
 326                         min_power_state_index = 1;
 327
 328                 switch (rdev->pm.dynpm_planned_action) {
 329                 case DYNPM_ACTION_MINIMUM:
 330                         rdev->pm.requested_power_state_index = min_power_state_index;
 331                         rdev->pm.requested_clock_mode_index = 0;
 332                         rdev->pm.dynpm_can_downclock = false;
 333                         break;
 334                 case DYNPM_ACTION_DOWNCLOCK:
 335                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 336                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 337                                 rdev->pm.dynpm_can_downclock = false;
 338                         } else {
 339                                 if (rdev->pm.active_crtc_count > 1) {
 340                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 341                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 342                                                         continue;
 343                                                 else if (i >= rdev->pm.current_power_state_index) {
 344                                                         rdev->pm.requested_power_state_index =
 345                                                                 rdev->pm.current_power_state_index;
 346                                                         break;
 347                                                 } else {
 348                                                         rdev->pm.requested_power_state_index = i;
 349                                                         break;
 350                                                 }
 351                                         }
 352                                 } else {
 353                                         if (rdev->pm.current_power_state_index == 0)
 354                                                 rdev->pm.requested_power_state_index =
 355                                                         rdev->pm.num_power_states - 1;
 356                                         else
 357                                                 rdev->pm.requested_power_state_index =
 358                                                         rdev->pm.current_power_state_index - 1;
 359                                 }
 360                         }
 361                         rdev->pm.requested_clock_mode_index = 0;
 362                         /* don't use the power state if crtcs are active and no display flag is set */
 363                         if ((rdev->pm.active_crtc_count > 0) &&
 364                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 365                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 366                              RADEON_PM_MODE_NO_DISPLAY)) {
 367                                 rdev->pm.requested_power_state_index++;
 368                         }
 369                         break;
 370                 case DYNPM_ACTION_UPCLOCK:
 371                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 372                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 373                                 rdev->pm.dynpm_can_upclock = false;
 374                         } else {
 375                                 if (rdev->pm.active_crtc_count > 1) {
 376                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 377                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 378                                                         continue;
 379                                                 else if (i <= rdev->pm.current_power_state_index) {
 380                                                         rdev->pm.requested_power_state_index =
 381                                                                 rdev->pm.current_power_state_index;
 382                                                         break;
 383                                                 } else {
 384                                                         rdev->pm.requested_power_state_index = i;
 385                                                         break;
 386                                                 }
 387                                         }
 388                                 } else
 389                                         rdev->pm.requested_power_state_index =
 390                                                 rdev->pm.current_power_state_index + 1;
 391                         }
 392                         rdev->pm.requested_clock_mode_index = 0;
 393                         break;
 394                 case DYNPM_ACTION_DEFAULT:
 395                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 396                         rdev->pm.requested_clock_mode_index = 0;
 397                         rdev->pm.dynpm_can_upclock = false;
 398                         break;
 399                 case DYNPM_ACTION_NONE:
 400                 default:
 401                         DRM_ERROR("Requested mode for not defined action\n");
 402                         return;
 403                 }
 404         } else {
 405                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 406                 /* for now just select the first power state and switch between clock modes */
 407                 /* power state array is low to high, default is first (0) */
 408                 if (rdev->pm.active_crtc_count > 1) {
 409                         rdev->pm.requested_power_state_index = -1;
 410                         /* start at 1 as we don't want the default mode */
 411                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 412                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 413                                         continue;
 414                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 415                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 416                                         rdev->pm.requested_power_state_index = i;
 417                                         break;
 418                                 }
 419                         }
 420                         /* if nothing selected, grab the default state. */
 421                         if (rdev->pm.requested_power_state_index == -1)
 422                                 rdev->pm.requested_power_state_index = 0;
 423                 } else
 424                         rdev->pm.requested_power_state_index = 1;
 425
 426                 switch (rdev->pm.dynpm_planned_action) {
 427                 case DYNPM_ACTION_MINIMUM:
 428                         rdev->pm.requested_clock_mode_index = 0;
 429                         rdev->pm.dynpm_can_downclock = false;
 430                         break;
 431                 case DYNPM_ACTION_DOWNCLOCK:
 432                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 433                                 if (rdev->pm.current_clock_mode_index == 0) {
 434                                         rdev->pm.requested_clock_mode_index = 0;
 435                                         rdev->pm.dynpm_can_downclock = false;
 436                                 } else
 437                                         rdev->pm.requested_clock_mode_index =
 438                                                 rdev->pm.current_clock_mode_index - 1;
 439                         } else {
 440                                 rdev->pm.requested_clock_mode_index = 0;
 441                                 rdev->pm.dynpm_can_downclock = false;
 442                         }
 443                         /* don't use the power state if crtcs are active and no display flag is set */
 444                         if ((rdev->pm.active_crtc_count > 0) &&
 445                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 446                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 447                              RADEON_PM_MODE_NO_DISPLAY)) {
 448                                 rdev->pm.requested_clock_mode_index++;
 449                         }
 450                         break;
 451                 case DYNPM_ACTION_UPCLOCK:
 452                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 453                                 if (rdev->pm.current_clock_mode_index ==
 454                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 455                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 456                                         rdev->pm.dynpm_can_upclock = false;
 457                                 } else
 458                                         rdev->pm.requested_clock_mode_index =
 459                                                 rdev->pm.current_clock_mode_index + 1;
 460                         } else {
 461                                 rdev->pm.requested_clock_mode_index =
 462                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 463                                 rdev->pm.dynpm_can_upclock = false;
 464                         }
 465                         break;
 466                 case DYNPM_ACTION_DEFAULT:
 467                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 468                         rdev->pm.requested_clock_mode_index = 0;
 469                         rdev->pm.dynpm_can_upclock = false;
 470                         break;
 471                 case DYNPM_ACTION_NONE:
 472                 default:
 473                         DRM_ERROR("Requested mode for not defined action\n");
 474                         return;
 475                 }
 476         }
 477
 478         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 479                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 480                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 481                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 482                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 483                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 484                   pcie_lanes);
 485 }
 486
 487 void rs780_pm_init_profile(struct radeon_device *rdev)
 488 {
 489         if (rdev->pm.num_power_states == 2) {
 490                 /* default */
 491                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 492                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 493                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 494                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 495                 /* low sh */
 496                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 497                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 498                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 499                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 500                 /* mid sh */
 501                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 502                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 503                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 504                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 505                 /* high sh */
 506                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 507                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 508                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 509                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 510                 /* low mh */
 511                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 512                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 513                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 514                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 515                 /* mid mh */
 516                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 517                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 518                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 519                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 520                 /* high mh */
 521                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 522                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 523                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 524                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 525         } else if (rdev->pm.num_power_states == 3) {
 526                 /* default */
 527                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 528                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 529                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 530                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 531                 /* low sh */
 532                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 533                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 534                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 535                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 536                 /* mid sh */
 537                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 538                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 539                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 540                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 541                 /* high sh */
 542                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 543                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 544                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 545                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 546                 /* low mh */
 547                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 548                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 549                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 550                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 551                 /* mid mh */
 552                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 553                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 554                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 555                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 556                 /* high mh */
 557                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 558                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 559                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 560                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 561         } else {
 562                 /* default */
 563                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 564                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 565                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 566                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 567                 /* low sh */
 568                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 569                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 570                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 571                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 572                 /* mid sh */
 573                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 574                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 575                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 576                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 577                 /* high sh */
 578                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 579                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 580                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 581                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 582                 /* low mh */
 583                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 584                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 585                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 586                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 587                 /* mid mh */
 588                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 589                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 590                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 591                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 592                 /* high mh */
 593                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 594                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 595                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 596                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 597         }
 598 }
 599
 600 void r600_pm_init_profile(struct radeon_device *rdev)
 601 {
 602         int idx;
 603
 604         if (rdev->family == CHIP_R600) {
 605                 /* XXX */
 606                 /* default */
 607                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 608                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 609                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 610                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 611                 /* low sh */
 612                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 613                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 614                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 615                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 616                 /* mid sh */
 617                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 618                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 619                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 620                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 621                 /* high sh */
 622                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 623                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 624                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 625                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 626                 /* low mh */
 627                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 628                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 629                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 630                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 631                 /* mid mh */
 632                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 633                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 634                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 635                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 636                 /* high mh */
 637                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 638                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 639                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 640                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 641         } else {
 642                 if (rdev->pm.num_power_states < 4) {
 643                         /* default */
 644                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 645                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 646                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 647                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 648                         /* low sh */
 649                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 650                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 651                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 652                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 653                         /* mid sh */
 654                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 655                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 656                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 657                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 658                         /* high sh */
 659                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 660                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 661                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 662                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 663                         /* low mh */
 664                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 665                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 666                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 667                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 668                         /* low mh */
 669                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 670                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 671                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 672                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 673                         /* high mh */
 674                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 675                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 676                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 677                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 678                 } else {
 679                         /* default */
 680                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 681                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 682                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 683                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 684                         /* low sh */
 685                         if (rdev->flags & RADEON_IS_MOBILITY)
 686                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 687                         else
 688                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 689                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 690                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 691                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 692                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 693                         /* mid sh */
 694                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 695                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 696                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 697                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 698                         /* high sh */
 699                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 700                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 701                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 702                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 703                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 704                         /* low mh */
 705                         if (rdev->flags & RADEON_IS_MOBILITY)
 706                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 707                         else
 708                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 709                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 710                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 711                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 712                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 713                         /* mid mh */
 714                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 715                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 716                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 717                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 718                         /* high mh */
 719                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 720                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 721                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 722                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 723                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 724                 }
 725         }
 726 }
 727
 728 void r600_pm_misc(struct radeon_device *rdev)
 729 {
 730         int req_ps_idx = rdev->pm.requested_power_state_index;
 731         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 732         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 733         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 734
 735         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 736                 /* 0xff01 is a flag rather then an actual voltage */
 737                 if (voltage->voltage == 0xff01)
 738                         return;
 739                 if (voltage->voltage != rdev->pm.current_vddc) {
 740                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 741                         rdev->pm.current_vddc = voltage->voltage;
 742                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 743                 }
 744         }
 745 }
 746
 747 bool r600_gui_idle(struct radeon_device *rdev)
 748 {
 749         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 750                 return false;
 751         else
 752                 return true;
 753 }
 754
 755 /* hpd for digital panel detect/disconnect */
 756 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 757 {
 758         bool connected = false;
 759
 760         if (ASIC_IS_DCE3(rdev)) {
 761                 switch (hpd) {
 762                 case RADEON_HPD_1:
 763                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 764                                 connected = true;
 765                         break;
 766                 case RADEON_HPD_2:
 767                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 768                                 connected = true;
 769                         break;
 770                 case RADEON_HPD_3:
 771                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 772                                 connected = true;
 773                         break;
 774                 case RADEON_HPD_4:
 775                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 776                                 connected = true;
 777                         break;
 778                         /* DCE 3.2 */
 779                 case RADEON_HPD_5:
 780                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 781                                 connected = true;
 782                         break;
 783                 case RADEON_HPD_6:
 784                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 785                                 connected = true;
 786                         break;
 787                 default:
 788                         break;
 789                 }
 790         } else {
 791                 switch (hpd) {
 792                 case RADEON_HPD_1:
 793                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 794                                 connected = true;
 795                         break;
 796                 case RADEON_HPD_2:
 797                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 798                                 connected = true;
 799                         break;
 800                 case RADEON_HPD_3:
 801                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 802                                 connected = true;
 803                         break;
 804                 default:
 805                         break;
 806                 }
 807         }
 808         return connected;
 809 }
 810
 811 void r600_hpd_set_polarity(struct radeon_device *rdev,
 812                            enum radeon_hpd_id hpd)
 813 {
 814         u32 tmp;
 815         bool connected = r600_hpd_sense(rdev, hpd);
 816
 817         if (ASIC_IS_DCE3(rdev)) {
 818                 switch (hpd) {
 819                 case RADEON_HPD_1:
 820                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 821                         if (connected)
 822                                 tmp &= ~DC_HPDx_INT_POLARITY;
 823                         else
 824                                 tmp |= DC_HPDx_INT_POLARITY;
 825                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 826                         break;
 827                 case RADEON_HPD_2:
 828                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 829                         if (connected)
 830                                 tmp &= ~DC_HPDx_INT_POLARITY;
 831                         else
 832                                 tmp |= DC_HPDx_INT_POLARITY;
 833                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 834                         break;
 835                 case RADEON_HPD_3:
 836                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 837                         if (connected)
 838                                 tmp &= ~DC_HPDx_INT_POLARITY;
 839                         else
 840                                 tmp |= DC_HPDx_INT_POLARITY;
 841                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 842                         break;
 843                 case RADEON_HPD_4:
 844                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 845                         if (connected)
 846                                 tmp &= ~DC_HPDx_INT_POLARITY;
 847                         else
 848                                 tmp |= DC_HPDx_INT_POLARITY;
 849                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 850                         break;
 851                 case RADEON_HPD_5:
 852                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 853                         if (connected)
 854                                 tmp &= ~DC_HPDx_INT_POLARITY;
 855                         else
 856                                 tmp |= DC_HPDx_INT_POLARITY;
 857                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 858                         break;
 859                         /* DCE 3.2 */
 860                 case RADEON_HPD_6:
 861                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 862                         if (connected)
 863                                 tmp &= ~DC_HPDx_INT_POLARITY;
 864                         else
 865                                 tmp |= DC_HPDx_INT_POLARITY;
 866                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 867                         break;
 868                 default:
 869                         break;
 870                 }
 871         } else {
 872                 switch (hpd) {
 873                 case RADEON_HPD_1:
 874                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 875                         if (connected)
 876                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 877                         else
 878                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 879                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 880                         break;
 881                 case RADEON_HPD_2:
 882                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 883                         if (connected)
 884                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 885                         else
 886                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 887                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 888                         break;
 889                 case RADEON_HPD_3:
 890                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 891                         if (connected)
 892                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 893                         else
 894                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 895                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 896                         break;
 897                 default:
 898                         break;
 899                 }
 900         }
 901 }
 902
 903 void r600_hpd_init(struct radeon_device *rdev)
 904 {
 905         struct drm_device *dev = rdev->ddev;
 906         struct drm_connector *connector;
 907         unsigned enable = 0;
 908
 909         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 910                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 911
 912                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 913                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 914                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 915                          * aux dp channel on imac and help (but not completely fix)
 916                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 917                          */
 918                         continue;
 919                 }
 920                 if (ASIC_IS_DCE3(rdev)) {
 921                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 922                         if (ASIC_IS_DCE32(rdev))
 923                                 tmp |= DC_HPDx_EN;
 924
 925                         switch (radeon_connector->hpd.hpd) {
 926                         case RADEON_HPD_1:
 927                                 WREG32(DC_HPD1_CONTROL, tmp);
 928                                 break;
 929                         case RADEON_HPD_2:
 930                                 WREG32(DC_HPD2_CONTROL, tmp);
 931                                 break;
 932                         case RADEON_HPD_3:
 933                                 WREG32(DC_HPD3_CONTROL, tmp);
 934                                 break;
 935                         case RADEON_HPD_4:
 936                                 WREG32(DC_HPD4_CONTROL, tmp);
 937                                 break;
 938                                 /* DCE 3.2 */
 939                         case RADEON_HPD_5:
 940                                 WREG32(DC_HPD5_CONTROL, tmp);
 941                                 break;
 942                         case RADEON_HPD_6:
 943                                 WREG32(DC_HPD6_CONTROL, tmp);
 944                                 break;
 945                         default:
 946                                 break;
 947                         }
 948                 } else {
 949                         switch (radeon_connector->hpd.hpd) {
 950                         case RADEON_HPD_1:
 951                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 952                                 break;
 953                         case RADEON_HPD_2:
 954                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 955                                 break;
 956                         case RADEON_HPD_3:
 957                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 958                                 break;
 959                         default:
 960                                 break;
 961                         }
 962                 }
 963                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 964                         enable |= 1 << radeon_connector->hpd.hpd;
 965                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 966         }
 967         radeon_irq_kms_enable_hpd(rdev, enable);
 968 }
 969
 970 void r600_hpd_fini(struct radeon_device *rdev)
 971 {
 972         struct drm_device *dev = rdev->ddev;
 973         struct drm_connector *connector;
 974         unsigned disable = 0;
 975
 976         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 977                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 978                 if (ASIC_IS_DCE3(rdev)) {
 979                         switch (radeon_connector->hpd.hpd) {
 980                         case RADEON_HPD_1:
 981                                 WREG32(DC_HPD1_CONTROL, 0);
 982                                 break;
 983                         case RADEON_HPD_2:
 984                                 WREG32(DC_HPD2_CONTROL, 0);
 985                                 break;
 986                         case RADEON_HPD_3:
 987                                 WREG32(DC_HPD3_CONTROL, 0);
 988                                 break;
 989                         case RADEON_HPD_4:
 990                                 WREG32(DC_HPD4_CONTROL, 0);
 991                                 break;
 992                                 /* DCE 3.2 */
 993                         case RADEON_HPD_5:
 994                                 WREG32(DC_HPD5_CONTROL, 0);
 995                                 break;
 996                         case RADEON_HPD_6:
 997                                 WREG32(DC_HPD6_CONTROL, 0);
 998                                 break;
 999                         default:
1000                                 break;
1001                         }
1002                 } else {
1003                         switch (radeon_connector->hpd.hpd) {
1004                         case RADEON_HPD_1:
1005                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1006                                 break;
1007                         case RADEON_HPD_2:
1008                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1009                                 break;
1010                         case RADEON_HPD_3:
1011                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1012                                 break;
1013                         default:
1014                                 break;
1015                         }
1016                 }
1017                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1018                         disable |= 1 << radeon_connector->hpd.hpd;
1019         }
1020         radeon_irq_kms_disable_hpd(rdev, disable);
1021 }
1022
1023 /*
1024  * R600 PCIE GART
1025  */
1026 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1027 {
1028         unsigned i;
1029         u32 tmp;
1030
1031         /* flush hdp cache so updates hit vram */
1032         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1033             !(rdev->flags & RADEON_IS_AGP)) {
1034                 void __iomem *ptr = (void *)rdev->gart.ptr;
1035
1036                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
1037                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1038                  * This seems to cause problems on some AGP cards. Just use the old
1039                  * method for them.
1040                  */
1041                 WREG32(HDP_DEBUG1, 0);
1042                 readl((void __iomem *)ptr);
1043         } else
1044                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1045
1046         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1047         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1048         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1049         for (i = 0; i < rdev->usec_timeout; i++) {
1050                 /* read MC_STATUS */
1051                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1052                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1053                 if (tmp == 2) {
1054                         pr_warn("[drm] r600 flush TLB failed\n");
1055                         return;
1056                 }
1057                 if (tmp) {
1058                         return;
1059                 }
1060                 udelay(1);
1061         }
1062 }
1063
1064 int r600_pcie_gart_init(struct radeon_device *rdev)
1065 {
1066         int r;
1067
1068         if (rdev->gart.robj) {
1069                 WARN(1, "R600 PCIE GART already initialized\n");
1070                 return 0;
1071         }
1072         /* Initialize common gart structure */
1073         r = radeon_gart_init(rdev);
1074         if (r)
1075                 return r;
1076         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1077         return radeon_gart_table_vram_alloc(rdev);
1078 }
1079
1080 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1081 {
1082         u32 tmp;
1083         int r, i;
1084
1085         if (rdev->gart.robj == NULL) {
1086                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1087                 return -EINVAL;
1088         }
1089         r = radeon_gart_table_vram_pin(rdev);
1090         if (r)
1091                 return r;
1092
1093         /* Setup L2 cache */
1094         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1095                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1096                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1097         WREG32(VM_L2_CNTL2, 0);
1098         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1099         /* Setup TLB control */
1100         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1101                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1102                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1103                 ENABLE_WAIT_L2_QUERY;
1104         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1105         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1106         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1107         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1108         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1109         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1110         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1111         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1112         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1113         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1114         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1115         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1116         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1117         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1118         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1119         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1120         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1121         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1122         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1123         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1124                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1125         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1126                         (u32)(rdev->dummy_page.addr >> 12));
1127         for (i = 1; i < 7; i++)
1128                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1129
1130         r600_pcie_gart_tlb_flush(rdev);
1131         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1132                  (unsigned)(rdev->mc.gtt_size >> 20),
1133                  (unsigned long long)rdev->gart.table_addr);
1134         rdev->gart.ready = true;
1135         return 0;
1136 }
1137
1138 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1139 {
1140         u32 tmp;
1141         int i;
1142
1143         /* Disable all tables */
1144         for (i = 0; i < 7; i++)
1145                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1146
1147         /* Disable L2 cache */
1148         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1149                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1150         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1151         /* Setup L1 TLB control */
1152         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1153                 ENABLE_WAIT_L2_QUERY;
1154         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1155         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1156         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1157         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1158         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1159         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1160         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1161         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1162         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1163         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1164         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1165         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1166         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1167         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1168         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1169         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1170         radeon_gart_table_vram_unpin(rdev);
1171 }
1172
1173 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1174 {
1175         radeon_gart_fini(rdev);
1176         r600_pcie_gart_disable(rdev);
1177         radeon_gart_table_vram_free(rdev);
1178 }
1179
1180 static void r600_agp_enable(struct radeon_device *rdev)
1181 {
1182         u32 tmp;
1183         int i;
1184
1185         /* Setup L2 cache */
1186         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1187                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1188                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1189         WREG32(VM_L2_CNTL2, 0);
1190         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1191         /* Setup TLB control */
1192         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1193                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1194                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1195                 ENABLE_WAIT_L2_QUERY;
1196         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1197         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1198         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1199         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1200         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1201         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1202         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1203         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1204         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1205         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1206         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1207         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1208         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1209         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1210         for (i = 0; i < 7; i++)
1211                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1212 }
1213
1214 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1215 {
1216         unsigned i;
1217         u32 tmp;
1218
1219         for (i = 0; i < rdev->usec_timeout; i++) {
1220                 /* read MC_STATUS */
1221                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1222                 if (!tmp)
1223                         return 0;
1224                 udelay(1);
1225         }
1226         return -1;
1227 }
1228
1229 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1230 {
1231         unsigned long flags;
1232         uint32_t r;
1233
1234         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1235         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1236         r = RREG32(R_0028FC_MC_DATA);
1237         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1238         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1239         return r;
1240 }
1241
1242 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1243 {
1244         unsigned long flags;
1245
1246         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1247         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1248                 S_0028F8_MC_IND_WR_EN(1));
1249         WREG32(R_0028FC_MC_DATA, v);
1250         WREG32(R_0028F8_MC_INDEX, 0x7F);
1251         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1252 }
1253
1254 static void r600_mc_program(struct radeon_device *rdev)
1255 {
1256         struct rv515_mc_save save;
1257         u32 tmp;
1258         int i, j;
1259
1260         /* Initialize HDP */
1261         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1262                 WREG32((0x2c14 + j), 0x00000000);
1263                 WREG32((0x2c18 + j), 0x00000000);
1264                 WREG32((0x2c1c + j), 0x00000000);
1265                 WREG32((0x2c20 + j), 0x00000000);
1266                 WREG32((0x2c24 + j), 0x00000000);
1267         }
1268         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1269
1270         rv515_mc_stop(rdev, &save);
1271         if (r600_mc_wait_for_idle(rdev)) {
1272                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1273         }
1274         /* Lockout access through VGA aperture (doesn't exist before R600) */
1275         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1276         /* Update configuration */
1277         if (rdev->flags & RADEON_IS_AGP) {
1278                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1279                         /* VRAM before AGP */
1280                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1281                                 rdev->mc.vram_start >> 12);
1282                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1283                                 rdev->mc.gtt_end >> 12);
1284                 } else {
1285                         /* VRAM after AGP */
1286                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1287                                 rdev->mc.gtt_start >> 12);
1288                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1289                                 rdev->mc.vram_end >> 12);
1290                 }
1291         } else {
1292                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1293                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1294         }
1295         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1296         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1297         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1298         WREG32(MC_VM_FB_LOCATION, tmp);
1299         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1300         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1301         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1302         if (rdev->flags & RADEON_IS_AGP) {
1303                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1304                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1305                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1306         } else {
1307                 WREG32(MC_VM_AGP_BASE, 0);
1308                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1309                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1310         }
1311         if (r600_mc_wait_for_idle(rdev)) {
1312                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1313         }
1314         rv515_mc_resume(rdev, &save);
1315         /* we need to own VRAM, so turn off the VGA renderer here
1316          * to stop it overwriting our objects */
1317         rv515_vga_render_disable(rdev);
1318 }
1319
1320 /**
1321  * r600_vram_gtt_location - try to find VRAM & GTT location
1322  * @rdev: radeon device structure holding all necessary informations
1323  * @mc: memory controller structure holding memory informations
1324  *
1325  * Function will place try to place VRAM at same place as in CPU (PCI)
1326  * address space as some GPU seems to have issue when we reprogram at
1327  * different address space.
1328  *
1329  * If there is not enough space to fit the unvisible VRAM after the
1330  * aperture then we limit the VRAM size to the aperture.
1331  *
1332  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1333  * them to be in one from GPU point of view so that we can program GPU to
1334  * catch access outside them (weird GPU policy see ??).
1335  *
1336  * This function will never fails, worst case are limiting VRAM or GTT.
1337  *
1338  * Note: GTT start, end, size should be initialized before calling this
1339  * function on AGP platform.
1340  */
1341 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1342 {
1343         u64 size_bf, size_af;
1344
1345         if (mc->mc_vram_size > 0xE0000000) {
1346                 /* leave room for at least 512M GTT */
1347                 dev_warn(rdev->dev, "limiting VRAM\n");
1348                 mc->real_vram_size = 0xE0000000;
1349                 mc->mc_vram_size = 0xE0000000;
1350         }
1351         if (rdev->flags & RADEON_IS_AGP) {
1352                 size_bf = mc->gtt_start;
1353                 size_af = mc->mc_mask - mc->gtt_end;
1354                 if (size_bf > size_af) {
1355                         if (mc->mc_vram_size > size_bf) {
1356                                 dev_warn(rdev->dev, "limiting VRAM\n");
1357                                 mc->real_vram_size = size_bf;
1358                                 mc->mc_vram_size = size_bf;
1359                         }
1360                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1361                 } else {
1362                         if (mc->mc_vram_size > size_af) {
1363                                 dev_warn(rdev->dev, "limiting VRAM\n");
1364                                 mc->real_vram_size = size_af;
1365                                 mc->mc_vram_size = size_af;
1366                         }
1367                         mc->vram_start = mc->gtt_end + 1;
1368                 }
1369                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1370                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1371                                 mc->mc_vram_size >> 20, mc->vram_start,
1372                                 mc->vram_end, mc->real_vram_size >> 20);
1373         } else {
1374                 u64 base = 0;
1375                 if (rdev->flags & RADEON_IS_IGP) {
1376                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1377                         base <<= 24;
1378                 }
1379                 radeon_vram_location(rdev, &rdev->mc, base);
1380                 rdev->mc.gtt_base_align = 0;
1381                 radeon_gtt_location(rdev, mc);
1382         }
1383 }
1384
1385 static int r600_mc_init(struct radeon_device *rdev)
1386 {
1387         u32 tmp;
1388         int chansize, numchan;
1389         uint32_t h_addr, l_addr;
1390         unsigned long long k8_addr;
1391
1392         /* Get VRAM informations */
1393         rdev->mc.vram_is_ddr = true;
1394         tmp = RREG32(RAMCFG);
1395         if (tmp & CHANSIZE_OVERRIDE) {
1396                 chansize = 16;
1397         } else if (tmp & CHANSIZE_MASK) {
1398                 chansize = 64;
1399         } else {
1400                 chansize = 32;
1401         }
1402         tmp = RREG32(CHMAP);
1403         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1404         case 0:
1405         default:
1406                 numchan = 1;
1407                 break;
1408         case 1:
1409                 numchan = 2;
1410                 break;
1411         case 2:
1412                 numchan = 4;
1413                 break;
1414         case 3:
1415                 numchan = 8;
1416                 break;
1417         }
1418         rdev->mc.vram_width = numchan * chansize;
1419         /* Could aper size report 0 ? */
1420         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1421         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1422         /* Setup GPU memory space */
1423         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1424         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1425         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1426         r600_vram_gtt_location(rdev, &rdev->mc);
1427
1428         if (rdev->flags & RADEON_IS_IGP) {
1429                 rs690_pm_info(rdev);
1430                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1431
1432                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1433                         /* Use K8 direct mapping for fast fb access. */
1434                         rdev->fastfb_working = false;
1435                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1436                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1437                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1438 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1439                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1440 #endif
1441                         {
1442                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1443                                 * memory is present.
1444                                 */
1445                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1446                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1447                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1448                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1449                                         rdev->fastfb_working = true;
1450                                 }
1451                         }
1452                 }
1453         }
1454
1455         radeon_update_bandwidth_info(rdev);
1456         return 0;
1457 }
1458
1459 int r600_vram_scratch_init(struct radeon_device *rdev)
1460 {
1461         int r;
1462
1463         if (rdev->vram_scratch.robj == NULL) {
1464                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1465                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1466                                      0, NULL, NULL, &rdev->vram_scratch.robj);
1467                 if (r) {
1468                         return r;
1469                 }
1470         }
1471
1472         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1473         if (unlikely(r != 0))
1474                 return r;
1475         r = radeon_bo_pin(rdev->vram_scratch.robj,
1476                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1477         if (r) {
1478                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1479                 return r;
1480         }
1481         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1482                                 (void **)&rdev->vram_scratch.ptr);
1483         if (r)
1484                 radeon_bo_unpin(rdev->vram_scratch.robj);
1485         radeon_bo_unreserve(rdev->vram_scratch.robj);
1486
1487         return r;
1488 }
1489
1490 void r600_vram_scratch_fini(struct radeon_device *rdev)
1491 {
1492         int r;
1493
1494         if (rdev->vram_scratch.robj == NULL) {
1495                 return;
1496         }
1497         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1498         if (likely(r == 0)) {
1499                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1500                 radeon_bo_unpin(rdev->vram_scratch.robj);
1501                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1502         }
1503         radeon_bo_unref(&rdev->vram_scratch.robj);
1504 }
1505
1506 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1507 {
1508         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1509
1510         if (hung)
1511                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1512         else
1513                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1514
1515         WREG32(R600_BIOS_3_SCRATCH, tmp);
1516 }
1517
1518 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1519 {
1520         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1521                  RREG32(R_008010_GRBM_STATUS));
1522         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1523                  RREG32(R_008014_GRBM_STATUS2));
1524         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1525                  RREG32(R_000E50_SRBM_STATUS));
1526         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1527                  RREG32(CP_STALLED_STAT1));
1528         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1529                  RREG32(CP_STALLED_STAT2));
1530         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1531                  RREG32(CP_BUSY_STAT));
1532         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1533                  RREG32(CP_STAT));
1534         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1535                 RREG32(DMA_STATUS_REG));
1536 }
1537
1538 static bool r600_is_display_hung(struct radeon_device *rdev)
1539 {
1540         u32 crtc_hung = 0;
1541         u32 crtc_status[2];
1542         u32 i, j, tmp;
1543
1544         for (i = 0; i < rdev->num_crtc; i++) {
1545                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1546                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1547                         crtc_hung |= (1 << i);
1548                 }
1549         }
1550
1551         for (j = 0; j < 10; j++) {
1552                 for (i = 0; i < rdev->num_crtc; i++) {
1553                         if (crtc_hung & (1 << i)) {
1554                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1555                                 if (tmp != crtc_status[i])
1556                                         crtc_hung &= ~(1 << i);
1557                         }
1558                 }
1559                 if (crtc_hung == 0)
1560                         return false;
1561                 udelay(100);
1562         }
1563
1564         return true;
1565 }
1566
1567 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1568 {
1569         u32 reset_mask = 0;
1570         u32 tmp;
1571
1572         /* GRBM_STATUS */
1573         tmp = RREG32(R_008010_GRBM_STATUS);
1574         if (rdev->family >= CHIP_RV770) {
1575                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1576                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1577                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1578                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1579                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1580                         reset_mask |= RADEON_RESET_GFX;
1581         } else {
1582                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1583                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1584                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1585                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1586                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1587                         reset_mask |= RADEON_RESET_GFX;
1588         }
1589
1590         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1591             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1592                 reset_mask |= RADEON_RESET_CP;
1593
1594         if (G_008010_GRBM_EE_BUSY(tmp))
1595                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1596
1597         /* DMA_STATUS_REG */
1598         tmp = RREG32(DMA_STATUS_REG);
1599         if (!(tmp & DMA_IDLE))
1600                 reset_mask |= RADEON_RESET_DMA;
1601
1602         /* SRBM_STATUS */
1603         tmp = RREG32(R_000E50_SRBM_STATUS);
1604         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1605                 reset_mask |= RADEON_RESET_RLC;
1606
1607         if (G_000E50_IH_BUSY(tmp))
1608                 reset_mask |= RADEON_RESET_IH;
1609
1610         if (G_000E50_SEM_BUSY(tmp))
1611                 reset_mask |= RADEON_RESET_SEM;
1612
1613         if (G_000E50_GRBM_RQ_PENDING(tmp))
1614                 reset_mask |= RADEON_RESET_GRBM;
1615
1616         if (G_000E50_VMC_BUSY(tmp))
1617                 reset_mask |= RADEON_RESET_VMC;
1618
1619         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1620             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1621             G_000E50_MCDW_BUSY(tmp))
1622                 reset_mask |= RADEON_RESET_MC;
1623
1624         if (r600_is_display_hung(rdev))
1625                 reset_mask |= RADEON_RESET_DISPLAY;
1626
1627         /* Skip MC reset as it's mostly likely not hung, just busy */
1628         if (reset_mask & RADEON_RESET_MC) {
1629                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1630                 reset_mask &= ~RADEON_RESET_MC;
1631         }
1632
1633         return reset_mask;
1634 }
1635
1636 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1637 {
1638         struct rv515_mc_save save;
1639         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1640         u32 tmp;
1641
1642         if (reset_mask == 0)
1643                 return;
1644
1645         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1646
1647         r600_print_gpu_status_regs(rdev);
1648
1649         /* Disable CP parsing/prefetching */
1650         if (rdev->family >= CHIP_RV770)
1651                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1652         else
1653                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1654
1655         /* disable the RLC */
1656         WREG32(RLC_CNTL, 0);
1657
1658         if (reset_mask & RADEON_RESET_DMA) {
1659                 /* Disable DMA */
1660                 tmp = RREG32(DMA_RB_CNTL);
1661                 tmp &= ~DMA_RB_ENABLE;
1662                 WREG32(DMA_RB_CNTL, tmp);
1663         }
1664
1665         mdelay(50);
1666
1667         rv515_mc_stop(rdev, &save);
1668         if (r600_mc_wait_for_idle(rdev)) {
1669                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1670         }
1671
1672         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1673                 if (rdev->family >= CHIP_RV770)
1674                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1675                                 S_008020_SOFT_RESET_CB(1) |
1676                                 S_008020_SOFT_RESET_PA(1) |
1677                                 S_008020_SOFT_RESET_SC(1) |
1678                                 S_008020_SOFT_RESET_SPI(1) |
1679                                 S_008020_SOFT_RESET_SX(1) |
1680                                 S_008020_SOFT_RESET_SH(1) |
1681                                 S_008020_SOFT_RESET_TC(1) |
1682                                 S_008020_SOFT_RESET_TA(1) |
1683                                 S_008020_SOFT_RESET_VC(1) |
1684                                 S_008020_SOFT_RESET_VGT(1);
1685                 else
1686                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1687                                 S_008020_SOFT_RESET_DB(1) |
1688                                 S_008020_SOFT_RESET_CB(1) |
1689                                 S_008020_SOFT_RESET_PA(1) |
1690                                 S_008020_SOFT_RESET_SC(1) |
1691                                 S_008020_SOFT_RESET_SMX(1) |
1692                                 S_008020_SOFT_RESET_SPI(1) |
1693                                 S_008020_SOFT_RESET_SX(1) |
1694                                 S_008020_SOFT_RESET_SH(1) |
1695                                 S_008020_SOFT_RESET_TC(1) |
1696                                 S_008020_SOFT_RESET_TA(1) |
1697                                 S_008020_SOFT_RESET_VC(1) |
1698                                 S_008020_SOFT_RESET_VGT(1);
1699         }
1700
1701         if (reset_mask & RADEON_RESET_CP) {
1702                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1703                         S_008020_SOFT_RESET_VGT(1);
1704
1705                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1706         }
1707
1708         if (reset_mask & RADEON_RESET_DMA) {
1709                 if (rdev->family >= CHIP_RV770)
1710                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1711                 else
1712                         srbm_soft_reset |= SOFT_RESET_DMA;
1713         }
1714
1715         if (reset_mask & RADEON_RESET_RLC)
1716                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1717
1718         if (reset_mask & RADEON_RESET_SEM)
1719                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1720
1721         if (reset_mask & RADEON_RESET_IH)
1722                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1723
1724         if (reset_mask & RADEON_RESET_GRBM)
1725                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1726
1727         if (!(rdev->flags & RADEON_IS_IGP)) {
1728                 if (reset_mask & RADEON_RESET_MC)
1729                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1730         }
1731
1732         if (reset_mask & RADEON_RESET_VMC)
1733                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1734
1735         if (grbm_soft_reset) {
1736                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1737                 tmp |= grbm_soft_reset;
1738                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1739                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1740                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1741
1742                 udelay(50);
1743
1744                 tmp &= ~grbm_soft_reset;
1745                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1746                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1747         }
1748
1749         if (srbm_soft_reset) {
1750                 tmp = RREG32(SRBM_SOFT_RESET);
1751                 tmp |= srbm_soft_reset;
1752                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1753                 WREG32(SRBM_SOFT_RESET, tmp);
1754                 tmp = RREG32(SRBM_SOFT_RESET);
1755
1756                 udelay(50);
1757
1758                 tmp &= ~srbm_soft_reset;
1759                 WREG32(SRBM_SOFT_RESET, tmp);
1760                 tmp = RREG32(SRBM_SOFT_RESET);
1761         }
1762
1763         /* Wait a little for things to settle down */
1764         mdelay(1);
1765
1766         rv515_mc_resume(rdev, &save);
1767         udelay(50);
1768
1769         r600_print_gpu_status_regs(rdev);
1770 }
1771
1772 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1773 {
1774         struct rv515_mc_save save;
1775         u32 tmp, i;
1776
1777         dev_info(rdev->dev, "GPU pci config reset\n");
1778
1779         /* disable dpm? */
1780
1781         /* Disable CP parsing/prefetching */
1782         if (rdev->family >= CHIP_RV770)
1783                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1784         else
1785                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1786
1787         /* disable the RLC */
1788         WREG32(RLC_CNTL, 0);
1789
1790         /* Disable DMA */
1791         tmp = RREG32(DMA_RB_CNTL);
1792         tmp &= ~DMA_RB_ENABLE;
1793         WREG32(DMA_RB_CNTL, tmp);
1794
1795         mdelay(50);
1796
1797         /* set mclk/sclk to bypass */
1798         if (rdev->family >= CHIP_RV770)
1799                 rv770_set_clk_bypass_mode(rdev);
1800         /* disable BM */
1801         pci_clear_master(rdev->pdev);
1802         /* disable mem access */
1803         rv515_mc_stop(rdev, &save);
1804         if (r600_mc_wait_for_idle(rdev)) {
1805                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1806         }
1807
1808         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1809         tmp = RREG32(BUS_CNTL);
1810         tmp |= VGA_COHE_SPEC_TIMER_DIS;
1811         WREG32(BUS_CNTL, tmp);
1812
1813         tmp = RREG32(BIF_SCRATCH0);
1814
1815         /* reset */
1816         radeon_pci_config_reset(rdev);
1817         mdelay(1);
1818
1819         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1820         tmp = SOFT_RESET_BIF;
1821         WREG32(SRBM_SOFT_RESET, tmp);
1822         mdelay(1);
1823         WREG32(SRBM_SOFT_RESET, 0);
1824
1825         /* wait for asic to come out of reset */
1826         for (i = 0; i < rdev->usec_timeout; i++) {
1827                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1828                         break;
1829                 udelay(1);
1830         }
1831 }
1832
1833 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1834 {
1835         u32 reset_mask;
1836
1837         if (hard) {
1838                 r600_gpu_pci_config_reset(rdev);
1839                 return 0;
1840         }
1841
1842         reset_mask = r600_gpu_check_soft_reset(rdev);
1843
1844         if (reset_mask)
1845                 r600_set_bios_scratch_engine_hung(rdev, true);
1846
1847         /* try soft reset */
1848         r600_gpu_soft_reset(rdev, reset_mask);
1849
1850         reset_mask = r600_gpu_check_soft_reset(rdev);
1851
1852         /* try pci config reset */
1853         if (reset_mask && radeon_hard_reset)
1854                 r600_gpu_pci_config_reset(rdev);
1855
1856         reset_mask = r600_gpu_check_soft_reset(rdev);
1857
1858         if (!reset_mask)
1859                 r600_set_bios_scratch_engine_hung(rdev, false);
1860
1861         return 0;
1862 }
1863
1864 /**
1865  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1866  *
1867  * @rdev: radeon_device pointer
1868  * @ring: radeon_ring structure holding ring information
1869  *
1870  * Check if the GFX engine is locked up.
1871  * Returns true if the engine appears to be locked up, false if not.
1872  */
1873 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1874 {
1875         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1876
1877         if (!(reset_mask & (RADEON_RESET_GFX |
1878                             RADEON_RESET_COMPUTE |
1879                             RADEON_RESET_CP))) {
1880                 radeon_ring_lockup_update(rdev, ring);
1881                 return false;
1882         }
1883         return radeon_ring_test_lockup(rdev, ring);
1884 }
1885
1886 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1887                               u32 tiling_pipe_num,
1888                               u32 max_rb_num,
1889                               u32 total_max_rb_num,
1890                               u32 disabled_rb_mask)
1891 {
1892         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1893         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1894         u32 data = 0, mask = 1 << (max_rb_num - 1);
1895         unsigned i, j;
1896
1897         /* mask out the RBs that don't exist on that asic */
1898         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1899         /* make sure at least one RB is available */
1900         if ((tmp & 0xff) != 0xff)
1901                 disabled_rb_mask = tmp;
1902
1903         rendering_pipe_num = 1 << tiling_pipe_num;
1904         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1905         BUG_ON(rendering_pipe_num < req_rb_num);
1906
1907         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1908         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1909
1910         if (rdev->family <= CHIP_RV740) {
1911                 /* r6xx/r7xx */
1912                 rb_num_width = 2;
1913         } else {
1914                 /* eg+ */
1915                 rb_num_width = 4;
1916         }
1917
1918         for (i = 0; i < max_rb_num; i++) {
1919                 if (!(mask & disabled_rb_mask)) {
1920                         for (j = 0; j < pipe_rb_ratio; j++) {
1921                                 data <<= rb_num_width;
1922                                 data |= max_rb_num - i - 1;
1923                         }
1924                         if (pipe_rb_remain) {
1925                                 data <<= rb_num_width;
1926                                 data |= max_rb_num - i - 1;
1927                                 pipe_rb_remain--;
1928                         }
1929                 }
1930                 mask >>= 1;
1931         }
1932
1933         return data;
1934 }
1935
1936 int r600_count_pipe_bits(uint32_t val)
1937 {
1938         return hweight32(val);
1939 }
1940
1941 static void r600_gpu_init(struct radeon_device *rdev)
1942 {
1943         u32 tiling_config;
1944         u32 ramcfg;
1945         u32 cc_gc_shader_pipe_config;
1946         u32 tmp;
1947         int i, j;
1948         u32 sq_config;
1949         u32 sq_gpr_resource_mgmt_1 = 0;
1950         u32 sq_gpr_resource_mgmt_2 = 0;
1951         u32 sq_thread_resource_mgmt = 0;
1952         u32 sq_stack_resource_mgmt_1 = 0;
1953         u32 sq_stack_resource_mgmt_2 = 0;
1954         u32 disabled_rb_mask;
1955
1956         rdev->config.r600.tiling_group_size = 256;
1957         switch (rdev->family) {
1958         case CHIP_R600:
1959                 rdev->config.r600.max_pipes = 4;
1960                 rdev->config.r600.max_tile_pipes = 8;
1961                 rdev->config.r600.max_simds = 4;
1962                 rdev->config.r600.max_backends = 4;
1963                 rdev->config.r600.max_gprs = 256;
1964                 rdev->config.r600.max_threads = 192;
1965                 rdev->config.r600.max_stack_entries = 256;
1966                 rdev->config.r600.max_hw_contexts = 8;
1967                 rdev->config.r600.max_gs_threads = 16;
1968                 rdev->config.r600.sx_max_export_size = 128;
1969                 rdev->config.r600.sx_max_export_pos_size = 16;
1970                 rdev->config.r600.sx_max_export_smx_size = 128;
1971                 rdev->config.r600.sq_num_cf_insts = 2;
1972                 break;
1973         case CHIP_RV630:
1974         case CHIP_RV635:
1975                 rdev->config.r600.max_pipes = 2;
1976                 rdev->config.r600.max_tile_pipes = 2;
1977                 rdev->config.r600.max_simds = 3;
1978                 rdev->config.r600.max_backends = 1;
1979                 rdev->config.r600.max_gprs = 128;
1980                 rdev->config.r600.max_threads = 192;
1981                 rdev->config.r600.max_stack_entries = 128;
1982                 rdev->config.r600.max_hw_contexts = 8;
1983                 rdev->config.r600.max_gs_threads = 4;
1984                 rdev->config.r600.sx_max_export_size = 128;
1985                 rdev->config.r600.sx_max_export_pos_size = 16;
1986                 rdev->config.r600.sx_max_export_smx_size = 128;
1987                 rdev->config.r600.sq_num_cf_insts = 2;
1988                 break;
1989         case CHIP_RV610:
1990         case CHIP_RV620:
1991         case CHIP_RS780:
1992         case CHIP_RS880:
1993                 rdev->config.r600.max_pipes = 1;
1994                 rdev->config.r600.max_tile_pipes = 1;
1995                 rdev->config.r600.max_simds = 2;
1996                 rdev->config.r600.max_backends = 1;
1997                 rdev->config.r600.max_gprs = 128;
1998                 rdev->config.r600.max_threads = 192;
1999                 rdev->config.r600.max_stack_entries = 128;
2000                 rdev->config.r600.max_hw_contexts = 4;
2001                 rdev->config.r600.max_gs_threads = 4;
2002                 rdev->config.r600.sx_max_export_size = 128;
2003                 rdev->config.r600.sx_max_export_pos_size = 16;
2004                 rdev->config.r600.sx_max_export_smx_size = 128;
2005                 rdev->config.r600.sq_num_cf_insts = 1;
2006                 break;
2007         case CHIP_RV670:
2008                 rdev->config.r600.max_pipes = 4;
2009                 rdev->config.r600.max_tile_pipes = 4;
2010                 rdev->config.r600.max_simds = 4;
2011                 rdev->config.r600.max_backends = 4;
2012                 rdev->config.r600.max_gprs = 192;
2013                 rdev->config.r600.max_threads = 192;
2014                 rdev->config.r600.max_stack_entries = 256;
2015                 rdev->config.r600.max_hw_contexts = 8;
2016                 rdev->config.r600.max_gs_threads = 16;
2017                 rdev->config.r600.sx_max_export_size = 128;
2018                 rdev->config.r600.sx_max_export_pos_size = 16;
2019                 rdev->config.r600.sx_max_export_smx_size = 128;
2020                 rdev->config.r600.sq_num_cf_insts = 2;
2021                 break;
2022         default:
2023                 break;
2024         }
2025
2026         /* Initialize HDP */
2027         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2028                 WREG32((0x2c14 + j), 0x00000000);
2029                 WREG32((0x2c18 + j), 0x00000000);
2030                 WREG32((0x2c1c + j), 0x00000000);
2031                 WREG32((0x2c20 + j), 0x00000000);
2032                 WREG32((0x2c24 + j), 0x00000000);
2033         }
2034
2035         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2036
2037         /* Setup tiling */
2038         tiling_config = 0;
2039         ramcfg = RREG32(RAMCFG);
2040         switch (rdev->config.r600.max_tile_pipes) {
2041         case 1:
2042                 tiling_config |= PIPE_TILING(0);
2043                 break;
2044         case 2:
2045                 tiling_config |= PIPE_TILING(1);
2046                 break;
2047         case 4:
2048                 tiling_config |= PIPE_TILING(2);
2049                 break;
2050         case 8:
2051                 tiling_config |= PIPE_TILING(3);
2052                 break;
2053         default:
2054                 break;
2055         }
2056         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2057         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2058         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2059         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2060
2061         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2062         if (tmp > 3) {
2063                 tiling_config |= ROW_TILING(3);
2064                 tiling_config |= SAMPLE_SPLIT(3);
2065         } else {
2066                 tiling_config |= ROW_TILING(tmp);
2067                 tiling_config |= SAMPLE_SPLIT(tmp);
2068         }
2069         tiling_config |= BANK_SWAPS(1);
2070
2071         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2072         tmp = rdev->config.r600.max_simds -
2073                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2074         rdev->config.r600.active_simds = tmp;
2075
2076         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2077         tmp = 0;
2078         for (i = 0; i < rdev->config.r600.max_backends; i++)
2079                 tmp |= (1 << i);
2080         /* if all the backends are disabled, fix it up here */
2081         if ((disabled_rb_mask & tmp) == tmp) {
2082                 for (i = 0; i < rdev->config.r600.max_backends; i++)
2083                         disabled_rb_mask &= ~(1 << i);
2084         }
2085         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2086         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2087                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
2088         tiling_config |= tmp << 16;
2089         rdev->config.r600.backend_map = tmp;
2090
2091         rdev->config.r600.tile_config = tiling_config;
2092         WREG32(GB_TILING_CONFIG, tiling_config);
2093         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2094         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2095         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2096
2097         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2098         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2099         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2100
2101         /* Setup some CP states */
2102         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2103         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2104
2105         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2106                              SYNC_WALKER | SYNC_ALIGNER));
2107         /* Setup various GPU states */
2108         if (rdev->family == CHIP_RV670)
2109                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2110
2111         tmp = RREG32(SX_DEBUG_1);
2112         tmp |= SMX_EVENT_RELEASE;
2113         if ((rdev->family > CHIP_R600))
2114                 tmp |= ENABLE_NEW_SMX_ADDRESS;
2115         WREG32(SX_DEBUG_1, tmp);
2116
2117         if (((rdev->family) == CHIP_R600) ||
2118             ((rdev->family) == CHIP_RV630) ||
2119             ((rdev->family) == CHIP_RV610) ||
2120             ((rdev->family) == CHIP_RV620) ||
2121             ((rdev->family) == CHIP_RS780) ||
2122             ((rdev->family) == CHIP_RS880)) {
2123                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2124         } else {
2125                 WREG32(DB_DEBUG, 0);
2126         }
2127         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2128                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2129
2130         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2131         WREG32(VGT_NUM_INSTANCES, 0);
2132
2133         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2134         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2135
2136         tmp = RREG32(SQ_MS_FIFO_SIZES);
2137         if (((rdev->family) == CHIP_RV610) ||
2138             ((rdev->family) == CHIP_RV620) ||
2139             ((rdev->family) == CHIP_RS780) ||
2140             ((rdev->family) == CHIP_RS880)) {
2141                 tmp = (CACHE_FIFO_SIZE(0xa) |
2142                        FETCH_FIFO_HIWATER(0xa) |
2143                        DONE_FIFO_HIWATER(0xe0) |
2144                        ALU_UPDATE_FIFO_HIWATER(0x8));
2145         } else if (((rdev->family) == CHIP_R600) ||
2146                    ((rdev->family) == CHIP_RV630)) {
2147                 tmp &= ~DONE_FIFO_HIWATER(0xff);
2148                 tmp |= DONE_FIFO_HIWATER(0x4);
2149         }
2150         WREG32(SQ_MS_FIFO_SIZES, tmp);
2151
2152         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2153          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
2154          */
2155         sq_config = RREG32(SQ_CONFIG);
2156         sq_config &= ~(PS_PRIO(3) |
2157                        VS_PRIO(3) |
2158                        GS_PRIO(3) |
2159                        ES_PRIO(3));
2160         sq_config |= (DX9_CONSTS |
2161                       VC_ENABLE |
2162                       PS_PRIO(0) |
2163                       VS_PRIO(1) |
2164                       GS_PRIO(2) |
2165                       ES_PRIO(3));
2166
2167         if ((rdev->family) == CHIP_R600) {
2168                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2169                                           NUM_VS_GPRS(124) |
2170                                           NUM_CLAUSE_TEMP_GPRS(4));
2171                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2172                                           NUM_ES_GPRS(0));
2173                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2174                                            NUM_VS_THREADS(48) |
2175                                            NUM_GS_THREADS(4) |
2176                                            NUM_ES_THREADS(4));
2177                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2178                                             NUM_VS_STACK_ENTRIES(128));
2179                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2180                                             NUM_ES_STACK_ENTRIES(0));
2181         } else if (((rdev->family) == CHIP_RV610) ||
2182                    ((rdev->family) == CHIP_RV620) ||
2183                    ((rdev->family) == CHIP_RS780) ||
2184                    ((rdev->family) == CHIP_RS880)) {
2185                 /* no vertex cache */
2186                 sq_config &= ~VC_ENABLE;
2187
2188                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2189                                           NUM_VS_GPRS(44) |
2190                                           NUM_CLAUSE_TEMP_GPRS(2));
2191                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2192                                           NUM_ES_GPRS(17));
2193                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2194                                            NUM_VS_THREADS(78) |
2195                                            NUM_GS_THREADS(4) |
2196                                            NUM_ES_THREADS(31));
2197                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2198                                             NUM_VS_STACK_ENTRIES(40));
2199                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2200                                             NUM_ES_STACK_ENTRIES(16));
2201         } else if (((rdev->family) == CHIP_RV630) ||
2202                    ((rdev->family) == CHIP_RV635)) {
2203                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2204                                           NUM_VS_GPRS(44) |
2205                                           NUM_CLAUSE_TEMP_GPRS(2));
2206                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2207                                           NUM_ES_GPRS(18));
2208                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2209                                            NUM_VS_THREADS(78) |
2210                                            NUM_GS_THREADS(4) |
2211                                            NUM_ES_THREADS(31));
2212                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2213                                             NUM_VS_STACK_ENTRIES(40));
2214                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2215                                             NUM_ES_STACK_ENTRIES(16));
2216         } else if ((rdev->family) == CHIP_RV670) {
2217                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2218                                           NUM_VS_GPRS(44) |
2219                                           NUM_CLAUSE_TEMP_GPRS(2));
2220                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2221                                           NUM_ES_GPRS(17));
2222                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2223                                            NUM_VS_THREADS(78) |
2224                                            NUM_GS_THREADS(4) |
2225                                            NUM_ES_THREADS(31));
2226                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2227                                             NUM_VS_STACK_ENTRIES(64));
2228                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2229                                             NUM_ES_STACK_ENTRIES(64));
2230         }
2231
2232         WREG32(SQ_CONFIG, sq_config);
2233         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2234         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2235         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2236         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2237         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2238
2239         if (((rdev->family) == CHIP_RV610) ||
2240             ((rdev->family) == CHIP_RV620) ||
2241             ((rdev->family) == CHIP_RS780) ||
2242             ((rdev->family) == CHIP_RS880)) {
2243                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2244         } else {
2245                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2246         }
2247
2248         /* More default values. 2D/3D driver should adjust as needed */
2249         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2250                                          S1_X(0x4) | S1_Y(0xc)));
2251         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2252                                          S1_X(0x2) | S1_Y(0x2) |
2253                                          S2_X(0xa) | S2_Y(0x6) |
2254                                          S3_X(0x6) | S3_Y(0xa)));
2255         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2256                                              S1_X(0x4) | S1_Y(0xc) |
2257                                              S2_X(0x1) | S2_Y(0x6) |
2258                                              S3_X(0xa) | S3_Y(0xe)));
2259         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2260                                              S5_X(0x0) | S5_Y(0x0) |
2261                                              S6_X(0xb) | S6_Y(0x4) |
2262                                              S7_X(0x7) | S7_Y(0x8)));
2263
2264         WREG32(VGT_STRMOUT_EN, 0);
2265         tmp = rdev->config.r600.max_pipes * 16;
2266         switch (rdev->family) {
2267         case CHIP_RV610:
2268         case CHIP_RV620:
2269         case CHIP_RS780:
2270         case CHIP_RS880:
2271                 tmp += 32;
2272                 break;
2273         case CHIP_RV670:
2274                 tmp += 128;
2275                 break;
2276         default:
2277                 break;
2278         }
2279         if (tmp > 256) {
2280                 tmp = 256;
2281         }
2282         WREG32(VGT_ES_PER_GS, 128);
2283         WREG32(VGT_GS_PER_ES, tmp);
2284         WREG32(VGT_GS_PER_VS, 2);
2285         WREG32(VGT_GS_VERTEX_REUSE, 16);
2286
2287         /* more default values. 2D/3D driver should adjust as needed */
2288         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2289         WREG32(VGT_STRMOUT_EN, 0);
2290         WREG32(SX_MISC, 0);
2291         WREG32(PA_SC_MODE_CNTL, 0);
2292         WREG32(PA_SC_AA_CONFIG, 0);
2293         WREG32(PA_SC_LINE_STIPPLE, 0);
2294         WREG32(SPI_INPUT_Z, 0);
2295         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2296         WREG32(CB_COLOR7_FRAG, 0);
2297
2298         /* Clear render buffer base addresses */
2299         WREG32(CB_COLOR0_BASE, 0);
2300         WREG32(CB_COLOR1_BASE, 0);
2301         WREG32(CB_COLOR2_BASE, 0);
2302         WREG32(CB_COLOR3_BASE, 0);
2303         WREG32(CB_COLOR4_BASE, 0);
2304         WREG32(CB_COLOR5_BASE, 0);
2305         WREG32(CB_COLOR6_BASE, 0);
2306         WREG32(CB_COLOR7_BASE, 0);
2307         WREG32(CB_COLOR7_FRAG, 0);
2308
2309         switch (rdev->family) {
2310         case CHIP_RV610:
2311         case CHIP_RV620:
2312         case CHIP_RS780:
2313         case CHIP_RS880:
2314                 tmp = TC_L2_SIZE(8);
2315                 break;
2316         case CHIP_RV630:
2317         case CHIP_RV635:
2318                 tmp = TC_L2_SIZE(4);
2319                 break;
2320         case CHIP_R600:
2321                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2322                 break;
2323         default:
2324                 tmp = TC_L2_SIZE(0);
2325                 break;
2326         }
2327         WREG32(TC_CNTL, tmp);
2328
2329         tmp = RREG32(HDP_HOST_PATH_CNTL);
2330         WREG32(HDP_HOST_PATH_CNTL, tmp);
2331
2332         tmp = RREG32(ARB_POP);
2333         tmp |= ENABLE_TC128;
2334         WREG32(ARB_POP, tmp);
2335
2336         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2337         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2338                                NUM_CLIP_SEQ(3)));
2339         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2340         WREG32(VC_ENHANCE, 0);
2341 }
2342
2343
2344 /*
2345  * Indirect registers accessor
2346  */
2347 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2348 {
2349         unsigned long flags;
2350         u32 r;
2351
2352         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2353         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2354         (void)RREG32(PCIE_PORT_INDEX);
2355         r = RREG32(PCIE_PORT_DATA);
2356         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2357         return r;
2358 }
2359
2360 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2361 {
2362         unsigned long flags;
2363
2364         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2365         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2366         (void)RREG32(PCIE_PORT_INDEX);
2367         WREG32(PCIE_PORT_DATA, (v));
2368         (void)RREG32(PCIE_PORT_DATA);
2369         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2370 }
2371
2372 /*
2373  * CP & Ring
2374  */
2375 void r600_cp_stop(struct radeon_device *rdev)
2376 {
2377         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2378                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2379         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2380         WREG32(SCRATCH_UMSK, 0);
2381         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2382 }
2383
2384 int r600_init_microcode(struct radeon_device *rdev)
2385 {
2386         const char *chip_name;
2387         const char *rlc_chip_name;
2388         const char *smc_chip_name = "RV770";
2389         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2390         char fw_name[30];
2391         int err;
2392
2393         DRM_DEBUG("\n");
2394
2395         switch (rdev->family) {
2396         case CHIP_R600:
2397                 chip_name = "R600";
2398                 rlc_chip_name = "R600";
2399                 break;
2400         case CHIP_RV610:
2401                 chip_name = "RV610";
2402                 rlc_chip_name = "R600";
2403                 break;
2404         case CHIP_RV630:
2405                 chip_name = "RV630";
2406                 rlc_chip_name = "R600";
2407                 break;
2408         case CHIP_RV620:
2409                 chip_name = "RV620";
2410                 rlc_chip_name = "R600";
2411                 break;
2412         case CHIP_RV635:
2413                 chip_name = "RV635";
2414                 rlc_chip_name = "R600";
2415                 break;
2416         case CHIP_RV670:
2417                 chip_name = "RV670";
2418                 rlc_chip_name = "R600";
2419                 break;
2420         case CHIP_RS780:
2421         case CHIP_RS880:
2422                 chip_name = "RS780";
2423                 rlc_chip_name = "R600";
2424                 break;
2425         case CHIP_RV770:
2426                 chip_name = "RV770";
2427                 rlc_chip_name = "R700";
2428                 smc_chip_name = "RV770";
2429                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2430                 break;
2431         case CHIP_RV730:
2432                 chip_name = "RV730";
2433                 rlc_chip_name = "R700";
2434                 smc_chip_name = "RV730";
2435                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2436                 break;
2437         case CHIP_RV710:
2438                 chip_name = "RV710";
2439                 rlc_chip_name = "R700";
2440                 smc_chip_name = "RV710";
2441                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2442                 break;
2443         case CHIP_RV740:
2444                 chip_name = "RV730";
2445                 rlc_chip_name = "R700";
2446                 smc_chip_name = "RV740";
2447                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2448                 break;
2449         case CHIP_CEDAR:
2450                 chip_name = "CEDAR";
2451                 rlc_chip_name = "CEDAR";
2452                 smc_chip_name = "CEDAR";
2453                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2454                 break;
2455         case CHIP_REDWOOD:
2456                 chip_name = "REDWOOD";
2457                 rlc_chip_name = "REDWOOD";
2458                 smc_chip_name = "REDWOOD";
2459                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2460                 break;
2461         case CHIP_JUNIPER:
2462                 chip_name = "JUNIPER";
2463                 rlc_chip_name = "JUNIPER";
2464                 smc_chip_name = "JUNIPER";
2465                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2466                 break;
2467         case CHIP_CYPRESS:
2468         case CHIP_HEMLOCK:
2469                 chip_name = "CYPRESS";
2470                 rlc_chip_name = "CYPRESS";
2471                 smc_chip_name = "CYPRESS";
2472                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2473                 break;
2474         case CHIP_PALM:
2475                 chip_name = "PALM";
2476                 rlc_chip_name = "SUMO";
2477                 break;
2478         case CHIP_SUMO:
2479                 chip_name = "SUMO";
2480                 rlc_chip_name = "SUMO";
2481                 break;
2482         case CHIP_SUMO2:
2483                 chip_name = "SUMO2";
2484                 rlc_chip_name = "SUMO";
2485                 break;
2486         default: BUG();
2487         }
2488
2489         if (rdev->family >= CHIP_CEDAR) {
2490                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2491                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2492                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2493         } else if (rdev->family >= CHIP_RV770) {
2494                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2495                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2496                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2497         } else {
2498                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2499                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2500                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2501         }
2502
2503         DRM_INFO("Loading %s Microcode\n", chip_name);
2504
2505         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
2506         err = reject_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2507         if (err)
2508                 goto out;
2509         if (rdev->pfp_fw->size != pfp_req_size) {
2510                 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2511                        rdev->pfp_fw->size, fw_name);
2512                 err = -EINVAL;
2513                 goto out;
2514         }
2515
2516         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
2517         err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
2518         if (err)
2519                 goto out;
2520         if (rdev->me_fw->size != me_req_size) {
2521                 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2522                        rdev->me_fw->size, fw_name);
2523                 err = -EINVAL;
2524                 goto out;
2525         }
2526
2527         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", rlc_chip_name);
2528         err = reject_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2529         if (err)
2530                 goto out;
2531         if (rdev->rlc_fw->size != rlc_req_size) {
2532                 pr_err("r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2533                        rdev->rlc_fw->size, fw_name);
2534                 err = -EINVAL;
2535                 goto out;
2536         }
2537
2538         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2539                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", smc_chip_name);
2540                 err = reject_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2541                 if (err) {
2542                         pr_err("smc: error loading firmware \"%s\"\n", fw_name);
2543                         release_firmware(rdev->smc_fw);
2544                         rdev->smc_fw = NULL;
2545                         err = 0;
2546                 } else if (rdev->smc_fw->size != smc_req_size) {
2547                         pr_err("smc: Bogus length %zu in firmware \"%s\"\n",
2548                                rdev->smc_fw->size, fw_name);
2549                         err = -EINVAL;
2550                 }
2551         }
2552
2553 out:
2554         if (err) {
2555                 if (err != -EINVAL)
2556                         pr_err("r600_cp: Failed to load firmware \"%s\"\n",
2557                                fw_name);
2558                 release_firmware(rdev->pfp_fw);
2559                 rdev->pfp_fw = NULL;
2560                 release_firmware(rdev->me_fw);
2561                 rdev->me_fw = NULL;
2562                 release_firmware(rdev->rlc_fw);
2563                 rdev->rlc_fw = NULL;
2564                 release_firmware(rdev->smc_fw);
2565                 rdev->smc_fw = NULL;
2566         }
2567         return err;
2568 }
2569
2570 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2571                       struct radeon_ring *ring)
2572 {
2573         u32 rptr;
2574
2575         if (rdev->wb.enabled)
2576                 rptr = rdev->wb.wb[ring->rptr_offs/4];
2577         else
2578                 rptr = RREG32(R600_CP_RB_RPTR);
2579
2580         return rptr;
2581 }
2582
2583 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2584                       struct radeon_ring *ring)
2585 {
2586         return RREG32(R600_CP_RB_WPTR);
2587 }
2588
2589 void r600_gfx_set_wptr(struct radeon_device *rdev,
2590                        struct radeon_ring *ring)
2591 {
2592         WREG32(R600_CP_RB_WPTR, ring->wptr);
2593         (void)RREG32(R600_CP_RB_WPTR);
2594 }
2595
2596 static int r600_cp_load_microcode(struct radeon_device *rdev)
2597 {
2598         const __be32 *fw_data;
2599         int i;
2600
2601         if (!rdev->me_fw || !rdev->pfp_fw)
2602                 return -EINVAL;
2603
2604         r600_cp_stop(rdev);
2605
2606         WREG32(CP_RB_CNTL,
2607 #ifdef __BIG_ENDIAN
2608                BUF_SWAP_32BIT |
2609 #endif
2610                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2611
2612         /* Reset cp */
2613         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2614         RREG32(GRBM_SOFT_RESET);
2615         mdelay(15);
2616         WREG32(GRBM_SOFT_RESET, 0);
2617
2618         WREG32(CP_ME_RAM_WADDR, 0);
2619
2620         fw_data = (const __be32 *)rdev->me_fw->data;
2621         WREG32(CP_ME_RAM_WADDR, 0);
2622         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2623                 WREG32(CP_ME_RAM_DATA,
2624                        be32_to_cpup(fw_data++));
2625
2626         fw_data = (const __be32 *)rdev->pfp_fw->data;
2627         WREG32(CP_PFP_UCODE_ADDR, 0);
2628         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2629                 WREG32(CP_PFP_UCODE_DATA,
2630                        be32_to_cpup(fw_data++));
2631
2632         WREG32(CP_PFP_UCODE_ADDR, 0);
2633         WREG32(CP_ME_RAM_WADDR, 0);
2634         WREG32(CP_ME_RAM_RADDR, 0);
2635         return 0;
2636 }
2637
2638 int r600_cp_start(struct radeon_device *rdev)
2639 {
2640         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2641         int r;
2642         uint32_t cp_me;
2643
2644         r = radeon_ring_lock(rdev, ring, 7);
2645         if (r) {
2646                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2647                 return r;
2648         }
2649         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2650         radeon_ring_write(ring, 0x1);
2651         if (rdev->family >= CHIP_RV770) {
2652                 radeon_ring_write(ring, 0x0);
2653                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2654         } else {
2655                 radeon_ring_write(ring, 0x3);
2656                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2657         }
2658         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2659         radeon_ring_write(ring, 0);
2660         radeon_ring_write(ring, 0);
2661         radeon_ring_unlock_commit(rdev, ring, false);
2662
2663         cp_me = 0xff;
2664         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2665         return 0;
2666 }
2667
2668 int r600_cp_resume(struct radeon_device *rdev)
2669 {
2670         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2671         u32 tmp;
2672         u32 rb_bufsz;
2673         int r;
2674
2675         /* Reset cp */
2676         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2677         RREG32(GRBM_SOFT_RESET);
2678         mdelay(15);
2679         WREG32(GRBM_SOFT_RESET, 0);
2680
2681         /* Set ring buffer size */
2682         rb_bufsz = order_base_2(ring->ring_size / 8);
2683         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2684 #ifdef __BIG_ENDIAN
2685         tmp |= BUF_SWAP_32BIT;
2686 #endif
2687         WREG32(CP_RB_CNTL, tmp);
2688         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2689
2690         /* Set the write pointer delay */
2691         WREG32(CP_RB_WPTR_DELAY, 0);
2692
2693         /* Initialize the ring buffer's read and write pointers */
2694         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2695         WREG32(CP_RB_RPTR_WR, 0);
2696         ring->wptr = 0;
2697         WREG32(CP_RB_WPTR, ring->wptr);
2698
2699         /* set the wb address whether it's enabled or not */
2700         WREG32(CP_RB_RPTR_ADDR,
2701                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2702         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2703         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2704
2705         if (rdev->wb.enabled)
2706                 WREG32(SCRATCH_UMSK, 0xff);
2707         else {
2708                 tmp |= RB_NO_UPDATE;
2709                 WREG32(SCRATCH_UMSK, 0);
2710         }
2711
2712         mdelay(1);
2713         WREG32(CP_RB_CNTL, tmp);
2714
2715         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2716         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2717
2718         r600_cp_start(rdev);
2719         ring->ready = true;
2720         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2721         if (r) {
2722                 ring->ready = false;
2723                 return r;
2724         }
2725
2726         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2727                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2728
2729         return 0;
2730 }
2731
2732 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2733 {
2734         u32 rb_bufsz;
2735         int r;
2736
2737         /* Align ring size */
2738         rb_bufsz = order_base_2(ring_size / 8);
2739         ring_size = (1 << (rb_bufsz + 1)) * 4;
2740         ring->ring_size = ring_size;
2741         ring->align_mask = 16 - 1;
2742
2743         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2744                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2745                 if (r) {
2746                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2747                         ring->rptr_save_reg = 0;
2748                 }
2749         }
2750 }
2751
2752 void r600_cp_fini(struct radeon_device *rdev)
2753 {
2754         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2755         r600_cp_stop(rdev);
2756         radeon_ring_fini(rdev, ring);
2757         radeon_scratch_free(rdev, ring->rptr_save_reg);
2758 }
2759
2760 /*
2761  * GPU scratch registers helpers function.
2762  */
2763 void r600_scratch_init(struct radeon_device *rdev)
2764 {
2765         int i;
2766
2767         rdev->scratch.num_reg = 7;
2768         rdev->scratch.reg_base = SCRATCH_REG0;
2769         for (i = 0; i < rdev->scratch.num_reg; i++) {
2770                 rdev->scratch.free[i] = true;
2771                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2772         }
2773 }
2774
2775 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2776 {
2777         uint32_t scratch;
2778         uint32_t tmp = 0;
2779         unsigned i;
2780         int r;
2781
2782         r = radeon_scratch_get(rdev, &scratch);
2783         if (r) {
2784                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2785                 return r;
2786         }
2787         WREG32(scratch, 0xCAFEDEAD);
2788         r = radeon_ring_lock(rdev, ring, 3);
2789         if (r) {
2790                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2791                 radeon_scratch_free(rdev, scratch);
2792                 return r;
2793         }
2794         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2795         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2796         radeon_ring_write(ring, 0xDEADBEEF);
2797         radeon_ring_unlock_commit(rdev, ring, false);
2798         for (i = 0; i < rdev->usec_timeout; i++) {
2799                 tmp = RREG32(scratch);
2800                 if (tmp == 0xDEADBEEF)
2801                         break;
2802                 udelay(1);
2803         }
2804         if (i < rdev->usec_timeout) {
2805                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2806         } else {
2807                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2808                           ring->idx, scratch, tmp);
2809                 r = -EINVAL;
2810         }
2811         radeon_scratch_free(rdev, scratch);
2812         return r;
2813 }
2814
2815 /*
2816  * CP fences/semaphores
2817  */
2818
2819 void r600_fence_ring_emit(struct radeon_device *rdev,
2820                           struct radeon_fence *fence)
2821 {
2822         struct radeon_ring *ring = &rdev->ring[fence->ring];
2823         u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2824                 PACKET3_SH_ACTION_ENA;
2825
2826         if (rdev->family >= CHIP_RV770)
2827                 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2828
2829         if (rdev->wb.use_event) {
2830                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2831                 /* flush read cache over gart */
2832                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2833                 radeon_ring_write(ring, cp_coher_cntl);
2834                 radeon_ring_write(ring, 0xFFFFFFFF);
2835                 radeon_ring_write(ring, 0);
2836                 radeon_ring_write(ring, 10); /* poll interval */
2837                 /* EVENT_WRITE_EOP - flush caches, send int */
2838                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2839                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2840                 radeon_ring_write(ring, lower_32_bits(addr));
2841                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2842                 radeon_ring_write(ring, fence->seq);
2843                 radeon_ring_write(ring, 0);
2844         } else {
2845                 /* flush read cache over gart */
2846                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2847                 radeon_ring_write(ring, cp_coher_cntl);
2848                 radeon_ring_write(ring, 0xFFFFFFFF);
2849                 radeon_ring_write(ring, 0);
2850                 radeon_ring_write(ring, 10); /* poll interval */
2851                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2852                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2853                 /* wait for 3D idle clean */
2854                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2855                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2856                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2857                 /* Emit fence sequence & fire IRQ */
2858                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2859                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2860                 radeon_ring_write(ring, fence->seq);
2861                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2862                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2863                 radeon_ring_write(ring, RB_INT_STAT);
2864         }
2865 }
2866
2867 /**
2868  * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2869  *
2870  * @rdev: radeon_device pointer
2871  * @ring: radeon ring buffer object
2872  * @semaphore: radeon semaphore object
2873  * @emit_wait: Is this a sempahore wait?
2874  *
2875  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2876  * from running ahead of semaphore waits.
2877  */
2878 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2879                               struct radeon_ring *ring,
2880                               struct radeon_semaphore *semaphore,
2881                               bool emit_wait)
2882 {
2883         uint64_t addr = semaphore->gpu_addr;
2884         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2885
2886         if (rdev->family < CHIP_CAYMAN)
2887                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2888
2889         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2890         radeon_ring_write(ring, lower_32_bits(addr));
2891         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2892
2893         /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2894         if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2895                 /* Prevent the PFP from running ahead of the semaphore wait */
2896                 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2897                 radeon_ring_write(ring, 0x0);
2898         }
2899
2900         return true;
2901 }
2902
2903 /**
2904  * r600_copy_cpdma - copy pages using the CP DMA engine
2905  *
2906  * @rdev: radeon_device pointer
2907  * @src_offset: src GPU address
2908  * @dst_offset: dst GPU address
2909  * @num_gpu_pages: number of GPU pages to xfer
2910  * @resv: DMA reservation object to manage fences
2911  *
2912  * Copy GPU paging using the CP DMA engine (r6xx+).
2913  * Used by the radeon ttm implementation to move pages if
2914  * registered as the asic copy callback.
2915  */
2916 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2917                                      uint64_t src_offset, uint64_t dst_offset,
2918                                      unsigned num_gpu_pages,
2919                                      struct dma_resv *resv)
2920 {
2921         struct radeon_fence *fence;
2922         struct radeon_sync sync;
2923         int ring_index = rdev->asic->copy.blit_ring_index;
2924         struct radeon_ring *ring = &rdev->ring[ring_index];
2925         u32 size_in_bytes, cur_size_in_bytes, tmp;
2926         int i, num_loops;
2927         int r = 0;
2928
2929         radeon_sync_create(&sync);
2930
2931         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2932         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2933         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2934         if (r) {
2935                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2936                 radeon_sync_free(rdev, &sync, NULL);
2937                 return ERR_PTR(r);
2938         }
2939
2940         radeon_sync_resv(rdev, &sync, resv, false);
2941         radeon_sync_rings(rdev, &sync, ring->idx);
2942
2943         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2944         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2945         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2946         for (i = 0; i < num_loops; i++) {
2947                 cur_size_in_bytes = size_in_bytes;
2948                 if (cur_size_in_bytes > 0x1fffff)
2949                         cur_size_in_bytes = 0x1fffff;
2950                 size_in_bytes -= cur_size_in_bytes;
2951                 tmp = upper_32_bits(src_offset) & 0xff;
2952                 if (size_in_bytes == 0)
2953                         tmp |= PACKET3_CP_DMA_CP_SYNC;
2954                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2955                 radeon_ring_write(ring, lower_32_bits(src_offset));
2956                 radeon_ring_write(ring, tmp);
2957                 radeon_ring_write(ring, lower_32_bits(dst_offset));
2958                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2959                 radeon_ring_write(ring, cur_size_in_bytes);
2960                 src_offset += cur_size_in_bytes;
2961                 dst_offset += cur_size_in_bytes;
2962         }
2963         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2964         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2965         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2966
2967         r = radeon_fence_emit(rdev, &fence, ring->idx);
2968         if (r) {
2969                 radeon_ring_unlock_undo(rdev, ring);
2970                 radeon_sync_free(rdev, &sync, NULL);
2971                 return ERR_PTR(r);
2972         }
2973
2974         radeon_ring_unlock_commit(rdev, ring, false);
2975         radeon_sync_free(rdev, &sync, fence);
2976
2977         return fence;
2978 }
2979
2980 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2981                          uint32_t tiling_flags, uint32_t pitch,
2982                          uint32_t offset, uint32_t obj_size)
2983 {
2984         /* FIXME: implement */
2985         return 0;
2986 }
2987
2988 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2989 {
2990         /* FIXME: implement */
2991 }
2992
2993 static void r600_uvd_init(struct radeon_device *rdev)
2994 {
2995         int r;
2996
2997         if (!rdev->has_uvd)
2998                 return;
2999
3000         r = radeon_uvd_init(rdev);
3001         if (r) {
3002                 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3003                 /*
3004                  * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3005                  * to early fails uvd_v1_0_resume() and thus nothing happens
3006                  * there. So it is pointless to try to go through that code
3007                  * hence why we disable uvd here.
3008                  */
3009                 rdev->has_uvd = false;
3010                 return;
3011         }
3012         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3013         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3014 }
3015
3016 static void r600_uvd_start(struct radeon_device *rdev)
3017 {
3018         int r;
3019
3020         if (!rdev->has_uvd)
3021                 return;
3022
3023         r = uvd_v1_0_resume(rdev);
3024         if (r) {
3025                 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3026                 goto error;
3027         }
3028         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3029         if (r) {
3030                 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3031                 goto error;
3032         }
3033         return;
3034
3035 error:
3036         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3037 }
3038
3039 static void r600_uvd_resume(struct radeon_device *rdev)
3040 {
3041         struct radeon_ring *ring;
3042         int r;
3043
3044         if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3045                 return;
3046
3047         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3048         r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
3049         if (r) {
3050                 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3051                 return;
3052         }
3053         r = uvd_v1_0_init(rdev);
3054         if (r) {
3055                 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3056                 return;
3057         }
3058 }
3059
3060 static int r600_startup(struct radeon_device *rdev)
3061 {
3062         struct radeon_ring *ring;
3063         int r;
3064
3065         /* enable pcie gen2 link */
3066         r600_pcie_gen2_enable(rdev);
3067
3068         /* scratch needs to be initialized before MC */
3069         r = r600_vram_scratch_init(rdev);
3070         if (r)
3071                 return r;
3072
3073         r600_mc_program(rdev);
3074
3075         if (rdev->flags & RADEON_IS_AGP) {
3076                 r600_agp_enable(rdev);
3077         } else {
3078                 r = r600_pcie_gart_enable(rdev);
3079                 if (r)
3080                         return r;
3081         }
3082         r600_gpu_init(rdev);
3083
3084         /* allocate wb buffer */
3085         r = radeon_wb_init(rdev);
3086         if (r)
3087                 return r;
3088
3089         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3090         if (r) {
3091                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3092                 return r;
3093         }
3094
3095         r600_uvd_start(rdev);
3096
3097         /* Enable IRQ */
3098         if (!rdev->irq.installed) {
3099                 r = radeon_irq_kms_init(rdev);
3100                 if (r)
3101                         return r;
3102         }
3103
3104         r = r600_irq_init(rdev);
3105         if (r) {
3106                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3107                 radeon_irq_kms_fini(rdev);
3108                 return r;
3109         }
3110         r600_irq_set(rdev);
3111
3112         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3113         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3114                              RADEON_CP_PACKET2);
3115         if (r)
3116                 return r;
3117
3118         r = r600_cp_load_microcode(rdev);
3119         if (r)
3120                 return r;
3121         r = r600_cp_resume(rdev);
3122         if (r)
3123                 return r;
3124
3125         r600_uvd_resume(rdev);
3126
3127         r = radeon_ib_pool_init(rdev);
3128         if (r) {
3129                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3130                 return r;
3131         }
3132
3133         r = radeon_audio_init(rdev);
3134         if (r) {
3135                 DRM_ERROR("radeon: audio init failed\n");
3136                 return r;
3137         }
3138
3139         return 0;
3140 }
3141
3142 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3143 {
3144         uint32_t temp;
3145
3146         temp = RREG32(CONFIG_CNTL);
3147         if (!state) {
3148                 temp &= ~(1<<0);
3149                 temp |= (1<<1);
3150         } else {
3151                 temp &= ~(1<<1);
3152         }
3153         WREG32(CONFIG_CNTL, temp);
3154 }
3155
3156 int r600_resume(struct radeon_device *rdev)
3157 {
3158         int r;
3159
3160         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3161          * posting will perform necessary task to bring back GPU into good
3162          * shape.
3163          */
3164         /* post card */
3165         atom_asic_init(rdev->mode_info.atom_context);
3166
3167         if (rdev->pm.pm_method == PM_METHOD_DPM)
3168                 radeon_pm_resume(rdev);
3169
3170         rdev->accel_working = true;
3171         r = r600_startup(rdev);
3172         if (r) {
3173                 DRM_ERROR("r600 startup failed on resume\n");
3174                 rdev->accel_working = false;
3175                 return r;
3176         }
3177
3178         return r;
3179 }
3180
3181 int r600_suspend(struct radeon_device *rdev)
3182 {
3183         radeon_pm_suspend(rdev);
3184         radeon_audio_fini(rdev);
3185         r600_cp_stop(rdev);
3186         if (rdev->has_uvd) {
3187                 radeon_uvd_suspend(rdev);
3188                 uvd_v1_0_fini(rdev);
3189         }
3190         r600_irq_suspend(rdev);
3191         radeon_wb_disable(rdev);
3192         r600_pcie_gart_disable(rdev);
3193
3194         return 0;
3195 }
3196
3197 /* Plan is to move initialization in that function and use
3198  * helper function so that radeon_device_init pretty much
3199  * do nothing more than calling asic specific function. This
3200  * should also allow to remove a bunch of callback function
3201  * like vram_info.
3202  */
3203 int r600_init(struct radeon_device *rdev)
3204 {
3205         int r;
3206
3207         r600_debugfs_mc_info_init(rdev);
3208         /* Read BIOS */
3209         if (!radeon_get_bios(rdev)) {
3210                 if (ASIC_IS_AVIVO(rdev))
3211                         return -EINVAL;
3212         }
3213         /* Must be an ATOMBIOS */
3214         if (!rdev->is_atom_bios) {
3215                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3216                 return -EINVAL;
3217         }
3218         r = radeon_atombios_init(rdev);
3219         if (r)
3220                 return r;
3221         /* Post card if necessary */
3222         if (!radeon_card_posted(rdev)) {
3223                 if (!rdev->bios) {
3224                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3225                         return -EINVAL;
3226                 }
3227                 DRM_INFO("GPU not posted. posting now...\n");
3228                 atom_asic_init(rdev->mode_info.atom_context);
3229         }
3230         /* Initialize scratch registers */
3231         r600_scratch_init(rdev);
3232         /* Initialize surface registers */
3233         radeon_surface_init(rdev);
3234         /* Initialize clocks */
3235         radeon_get_clock_info(rdev->ddev);
3236         /* Fence driver */
3237         radeon_fence_driver_init(rdev);
3238         if (rdev->flags & RADEON_IS_AGP) {
3239                 r = radeon_agp_init(rdev);
3240                 if (r)
3241                         radeon_agp_disable(rdev);
3242         }
3243         r = r600_mc_init(rdev);
3244         if (r)
3245                 return r;
3246         /* Memory manager */
3247         r = radeon_bo_init(rdev);
3248         if (r)
3249                 return r;
3250
3251         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3252                 r = r600_init_microcode(rdev);
3253                 if (r) {
3254                         DRM_ERROR("Failed to load firmware!\n");
3255                         /*(DEBLOBBED)*/
3256                 }
3257         }
3258
3259         /* Initialize power management */
3260         radeon_pm_init(rdev);
3261
3262         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3263         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3264
3265         r600_uvd_init(rdev);
3266
3267         rdev->ih.ring_obj = NULL;
3268         r600_ih_ring_init(rdev, 64 * 1024);
3269
3270         r = r600_pcie_gart_init(rdev);
3271         if (r)
3272                 return r;
3273
3274         rdev->accel_working = true;
3275         r = r600_startup(rdev);
3276         if (r) {
3277                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3278                 r600_cp_fini(rdev);
3279                 r600_irq_fini(rdev);
3280                 radeon_wb_fini(rdev);
3281                 radeon_ib_pool_fini(rdev);
3282                 radeon_irq_kms_fini(rdev);
3283                 r600_pcie_gart_fini(rdev);
3284                 rdev->accel_working = false;
3285         }
3286
3287         return 0;
3288 }
3289
3290 void r600_fini(struct radeon_device *rdev)
3291 {
3292         radeon_pm_fini(rdev);
3293         radeon_audio_fini(rdev);
3294         r600_cp_fini(rdev);
3295         r600_irq_fini(rdev);
3296         if (rdev->has_uvd) {
3297                 uvd_v1_0_fini(rdev);
3298                 radeon_uvd_fini(rdev);
3299         }
3300         radeon_wb_fini(rdev);
3301         radeon_ib_pool_fini(rdev);
3302         radeon_irq_kms_fini(rdev);
3303         r600_pcie_gart_fini(rdev);
3304         r600_vram_scratch_fini(rdev);
3305         radeon_agp_fini(rdev);
3306         radeon_gem_fini(rdev);
3307         radeon_fence_driver_fini(rdev);
3308         radeon_bo_fini(rdev);
3309         radeon_atombios_fini(rdev);
3310         kfree(rdev->bios);
3311         rdev->bios = NULL;
3312 }
3313
3314
3315 /*
3316  * CS stuff
3317  */
3318 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3319 {
3320         struct radeon_ring *ring = &rdev->ring[ib->ring];
3321         u32 next_rptr;
3322
3323         if (ring->rptr_save_reg) {
3324                 next_rptr = ring->wptr + 3 + 4;
3325                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3326                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3327                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3328                 radeon_ring_write(ring, next_rptr);
3329         } else if (rdev->wb.enabled) {
3330                 next_rptr = ring->wptr + 5 + 4;
3331                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3332                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3333                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3334                 radeon_ring_write(ring, next_rptr);
3335                 radeon_ring_write(ring, 0);
3336         }
3337
3338         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3339         radeon_ring_write(ring,
3340 #ifdef __BIG_ENDIAN
3341                           (2 << 0) |
3342 #endif
3343                           (ib->gpu_addr & 0xFFFFFFFC));
3344         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3345         radeon_ring_write(ring, ib->length_dw);
3346 }
3347
3348 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3349 {
3350         struct radeon_ib ib;
3351         uint32_t scratch;
3352         uint32_t tmp = 0;
3353         unsigned i;
3354         int r;
3355
3356         r = radeon_scratch_get(rdev, &scratch);
3357         if (r) {
3358                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3359                 return r;
3360         }
3361         WREG32(scratch, 0xCAFEDEAD);
3362         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3363         if (r) {
3364                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3365                 goto free_scratch;
3366         }
3367         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3368         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3369         ib.ptr[2] = 0xDEADBEEF;
3370         ib.length_dw = 3;
3371         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3372         if (r) {
3373                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3374                 goto free_ib;
3375         }
3376         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3377                 RADEON_USEC_IB_TEST_TIMEOUT));
3378         if (r < 0) {
3379                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3380                 goto free_ib;
3381         } else if (r == 0) {
3382                 DRM_ERROR("radeon: fence wait timed out.\n");
3383                 r = -ETIMEDOUT;
3384                 goto free_ib;
3385         }
3386         r = 0;
3387         for (i = 0; i < rdev->usec_timeout; i++) {
3388                 tmp = RREG32(scratch);
3389                 if (tmp == 0xDEADBEEF)
3390                         break;
3391                 udelay(1);
3392         }
3393         if (i < rdev->usec_timeout) {
3394                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3395         } else {
3396                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3397                           scratch, tmp);
3398                 r = -EINVAL;
3399         }
3400 free_ib:
3401         radeon_ib_free(rdev, &ib);
3402 free_scratch:
3403         radeon_scratch_free(rdev, scratch);
3404         return r;
3405 }
3406
3407 /*
3408  * Interrupts
3409  *
3410  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3411  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3412  * writing to the ring and the GPU consuming, the GPU writes to the ring
3413  * and host consumes.  As the host irq handler processes interrupts, it
3414  * increments the rptr.  When the rptr catches up with the wptr, all the
3415  * current interrupts have been processed.
3416  */
3417
3418 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3419 {
3420         u32 rb_bufsz;
3421
3422         /* Align ring size */
3423         rb_bufsz = order_base_2(ring_size / 4);
3424         ring_size = (1 << rb_bufsz) * 4;
3425         rdev->ih.ring_size = ring_size;
3426         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3427         rdev->ih.rptr = 0;
3428 }
3429
3430 int r600_ih_ring_alloc(struct radeon_device *rdev)
3431 {
3432         int r;
3433
3434         /* Allocate ring buffer */
3435         if (rdev->ih.ring_obj == NULL) {
3436                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3437                                      PAGE_SIZE, true,
3438                                      RADEON_GEM_DOMAIN_GTT, 0,
3439                                      NULL, NULL, &rdev->ih.ring_obj);
3440                 if (r) {
3441                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3442                         return r;
3443                 }
3444                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3445                 if (unlikely(r != 0))
3446                         return r;
3447                 r = radeon_bo_pin(rdev->ih.ring_obj,
3448                                   RADEON_GEM_DOMAIN_GTT,
3449                                   &rdev->ih.gpu_addr);
3450                 if (r) {
3451                         radeon_bo_unreserve(rdev->ih.ring_obj);
3452                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3453                         return r;
3454                 }
3455                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3456                                    (void **)&rdev->ih.ring);
3457                 radeon_bo_unreserve(rdev->ih.ring_obj);
3458                 if (r) {
3459                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3460                         return r;
3461                 }
3462         }
3463         return 0;
3464 }
3465
3466 void r600_ih_ring_fini(struct radeon_device *rdev)
3467 {
3468         int r;
3469         if (rdev->ih.ring_obj) {
3470                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3471                 if (likely(r == 0)) {
3472                         radeon_bo_kunmap(rdev->ih.ring_obj);
3473                         radeon_bo_unpin(rdev->ih.ring_obj);
3474                         radeon_bo_unreserve(rdev->ih.ring_obj);
3475                 }
3476                 radeon_bo_unref(&rdev->ih.ring_obj);
3477                 rdev->ih.ring = NULL;
3478                 rdev->ih.ring_obj = NULL;
3479         }
3480 }
3481
3482 void r600_rlc_stop(struct radeon_device *rdev)
3483 {
3484
3485         if ((rdev->family >= CHIP_RV770) &&
3486             (rdev->family <= CHIP_RV740)) {
3487                 /* r7xx asics need to soft reset RLC before halting */
3488                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3489                 RREG32(SRBM_SOFT_RESET);
3490                 mdelay(15);
3491                 WREG32(SRBM_SOFT_RESET, 0);
3492                 RREG32(SRBM_SOFT_RESET);
3493         }
3494
3495         WREG32(RLC_CNTL, 0);
3496 }
3497
3498 static void r600_rlc_start(struct radeon_device *rdev)
3499 {
3500         WREG32(RLC_CNTL, RLC_ENABLE);
3501 }
3502
3503 static int r600_rlc_resume(struct radeon_device *rdev)
3504 {
3505         u32 i;
3506         const __be32 *fw_data;
3507
3508         if (!rdev->rlc_fw)
3509                 return -EINVAL;
3510
3511         r600_rlc_stop(rdev);
3512
3513         WREG32(RLC_HB_CNTL, 0);
3514
3515         WREG32(RLC_HB_BASE, 0);
3516         WREG32(RLC_HB_RPTR, 0);
3517         WREG32(RLC_HB_WPTR, 0);
3518         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3519         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3520         WREG32(RLC_MC_CNTL, 0);
3521         WREG32(RLC_UCODE_CNTL, 0);
3522
3523         fw_data = (const __be32 *)rdev->rlc_fw->data;
3524         if (rdev->family >= CHIP_RV770) {
3525                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3526                         WREG32(RLC_UCODE_ADDR, i);
3527                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3528                 }
3529         } else {
3530                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3531                         WREG32(RLC_UCODE_ADDR, i);
3532                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3533                 }
3534         }
3535         WREG32(RLC_UCODE_ADDR, 0);
3536
3537         r600_rlc_start(rdev);
3538
3539         return 0;
3540 }
3541
3542 static void r600_enable_interrupts(struct radeon_device *rdev)
3543 {
3544         u32 ih_cntl = RREG32(IH_CNTL);
3545         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3546
3547         ih_cntl |= ENABLE_INTR;
3548         ih_rb_cntl |= IH_RB_ENABLE;
3549         WREG32(IH_CNTL, ih_cntl);
3550         WREG32(IH_RB_CNTL, ih_rb_cntl);
3551         rdev->ih.enabled = true;
3552 }
3553
3554 void r600_disable_interrupts(struct radeon_device *rdev)
3555 {
3556         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3557         u32 ih_cntl = RREG32(IH_CNTL);
3558
3559         ih_rb_cntl &= ~IH_RB_ENABLE;
3560         ih_cntl &= ~ENABLE_INTR;
3561         WREG32(IH_RB_CNTL, ih_rb_cntl);
3562         WREG32(IH_CNTL, ih_cntl);
3563         /* set rptr, wptr to 0 */
3564         WREG32(IH_RB_RPTR, 0);
3565         WREG32(IH_RB_WPTR, 0);
3566         rdev->ih.enabled = false;
3567         rdev->ih.rptr = 0;
3568 }
3569
3570 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3571 {
3572         u32 tmp;
3573
3574         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3575         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3576         WREG32(DMA_CNTL, tmp);
3577         WREG32(GRBM_INT_CNTL, 0);
3578         WREG32(DxMODE_INT_MASK, 0);
3579         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3580         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3581         if (ASIC_IS_DCE3(rdev)) {
3582                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3583                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3584                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3585                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3586                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3587                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3588                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3589                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3590                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3591                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3592                 if (ASIC_IS_DCE32(rdev)) {
3593                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3594                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3595                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3596                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3597                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3598                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3599                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3600                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3601                 } else {
3602                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3603                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3604                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3605                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3606                 }
3607         } else {
3608                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3609                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3610                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3611                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3612                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3613                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3614                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3615                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3616                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3617                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3618                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3619                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3620         }
3621 }
3622
3623 int r600_irq_init(struct radeon_device *rdev)
3624 {
3625         int ret = 0;
3626         int rb_bufsz;
3627         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3628
3629         /* allocate ring */
3630         ret = r600_ih_ring_alloc(rdev);
3631         if (ret)
3632                 return ret;
3633
3634         /* disable irqs */
3635         r600_disable_interrupts(rdev);
3636
3637         /* init rlc */
3638         if (rdev->family >= CHIP_CEDAR)
3639                 ret = evergreen_rlc_resume(rdev);
3640         else
3641                 ret = r600_rlc_resume(rdev);
3642         if (ret) {
3643                 r600_ih_ring_fini(rdev);
3644                 return ret;
3645         }
3646
3647         /* setup interrupt control */
3648         /* set dummy read address to dummy page address */
3649         WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);
3650         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3651         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3652          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3653          */
3654         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3655         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3656         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3657         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3658
3659         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3660         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3661
3662         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3663                       IH_WPTR_OVERFLOW_CLEAR |
3664                       (rb_bufsz << 1));
3665
3666         if (rdev->wb.enabled)
3667                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3668
3669         /* set the writeback address whether it's enabled or not */
3670         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3671         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3672
3673         WREG32(IH_RB_CNTL, ih_rb_cntl);
3674
3675         /* set rptr, wptr to 0 */
3676         WREG32(IH_RB_RPTR, 0);
3677         WREG32(IH_RB_WPTR, 0);
3678
3679         /* Default settings for IH_CNTL (disabled at first) */
3680         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3681         /* RPTR_REARM only works if msi's are enabled */
3682         if (rdev->msi_enabled)
3683                 ih_cntl |= RPTR_REARM;
3684         WREG32(IH_CNTL, ih_cntl);
3685
3686         /* force the active interrupt state to all disabled */
3687         if (rdev->family >= CHIP_CEDAR)
3688                 evergreen_disable_interrupt_state(rdev);
3689         else
3690                 r600_disable_interrupt_state(rdev);
3691
3692         /* at this point everything should be setup correctly to enable master */
3693         pci_set_master(rdev->pdev);
3694
3695         /* enable irqs */
3696         r600_enable_interrupts(rdev);
3697
3698         return ret;
3699 }
3700
3701 void r600_irq_suspend(struct radeon_device *rdev)
3702 {
3703         r600_irq_disable(rdev);
3704         r600_rlc_stop(rdev);
3705 }
3706
3707 void r600_irq_fini(struct radeon_device *rdev)
3708 {
3709         r600_irq_suspend(rdev);
3710         r600_ih_ring_fini(rdev);
3711 }
3712
3713 int r600_irq_set(struct radeon_device *rdev)
3714 {
3715         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3716         u32 mode_int = 0;
3717         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3718         u32 grbm_int_cntl = 0;
3719         u32 hdmi0, hdmi1;
3720         u32 dma_cntl;
3721         u32 thermal_int = 0;
3722
3723         if (!rdev->irq.installed) {
3724                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3725                 return -EINVAL;
3726         }
3727         /* don't enable anything if the ih is disabled */
3728         if (!rdev->ih.enabled) {
3729                 r600_disable_interrupts(rdev);
3730                 /* force the active interrupt state to all disabled */
3731                 r600_disable_interrupt_state(rdev);
3732                 return 0;
3733         }
3734
3735         if (ASIC_IS_DCE3(rdev)) {
3736                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3737                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3738                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3739                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3740                 if (ASIC_IS_DCE32(rdev)) {
3741                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3742                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3743                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3744                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3745                 } else {
3746                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3747                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3748                 }
3749         } else {
3750                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3751                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3752                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3753                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3754                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3755         }
3756
3757         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3758
3759         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3760                 thermal_int = RREG32(CG_THERMAL_INT) &
3761                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3762         } else if (rdev->family >= CHIP_RV770) {
3763                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3764                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3765         }
3766         if (rdev->irq.dpm_thermal) {
3767                 DRM_DEBUG("dpm thermal\n");
3768                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3769         }
3770
3771         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3772                 DRM_DEBUG("r600_irq_set: sw int\n");
3773                 cp_int_cntl |= RB_INT_ENABLE;
3774                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3775         }
3776
3777         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3778                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3779                 dma_cntl |= TRAP_ENABLE;
3780         }
3781
3782         if (rdev->irq.crtc_vblank_int[0] ||
3783             atomic_read(&rdev->irq.pflip[0])) {
3784                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3785                 mode_int |= D1MODE_VBLANK_INT_MASK;
3786         }
3787         if (rdev->irq.crtc_vblank_int[1] ||
3788             atomic_read(&rdev->irq.pflip[1])) {
3789                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3790                 mode_int |= D2MODE_VBLANK_INT_MASK;
3791         }
3792         if (rdev->irq.hpd[0]) {
3793                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3794                 hpd1 |= DC_HPDx_INT_EN;
3795         }
3796         if (rdev->irq.hpd[1]) {
3797                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3798                 hpd2 |= DC_HPDx_INT_EN;
3799         }
3800         if (rdev->irq.hpd[2]) {
3801                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3802                 hpd3 |= DC_HPDx_INT_EN;
3803         }
3804         if (rdev->irq.hpd[3]) {
3805                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3806                 hpd4 |= DC_HPDx_INT_EN;
3807         }
3808         if (rdev->irq.hpd[4]) {
3809                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3810                 hpd5 |= DC_HPDx_INT_EN;
3811         }
3812         if (rdev->irq.hpd[5]) {
3813                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3814                 hpd6 |= DC_HPDx_INT_EN;
3815         }
3816         if (rdev->irq.afmt[0]) {
3817                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3818                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3819         }
3820         if (rdev->irq.afmt[1]) {
3821                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3822                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3823         }
3824
3825         WREG32(CP_INT_CNTL, cp_int_cntl);
3826         WREG32(DMA_CNTL, dma_cntl);
3827         WREG32(DxMODE_INT_MASK, mode_int);
3828         WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3829         WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3830         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3831         if (ASIC_IS_DCE3(rdev)) {
3832                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3833                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3834                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3835                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3836                 if (ASIC_IS_DCE32(rdev)) {
3837                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3838                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3839                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3840                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3841                 } else {
3842                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3843                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3844                 }
3845         } else {
3846                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3847                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3848                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3849                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3850                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3851         }
3852         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3853                 WREG32(CG_THERMAL_INT, thermal_int);
3854         } else if (rdev->family >= CHIP_RV770) {
3855                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3856         }
3857
3858         /* posting read */
3859         RREG32(R_000E50_SRBM_STATUS);
3860
3861         return 0;
3862 }
3863
3864 static void r600_irq_ack(struct radeon_device *rdev)
3865 {
3866         u32 tmp;
3867
3868         if (ASIC_IS_DCE3(rdev)) {
3869                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3870                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3871                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3872                 if (ASIC_IS_DCE32(rdev)) {
3873                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3874                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3875                 } else {
3876                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3877                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3878                 }
3879         } else {
3880                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3881                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3882                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3883                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3884                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3885         }
3886         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3887         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3888
3889         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3890                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3891         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3892                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3893         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3894                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3895         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3896                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3897         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3898                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3899         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3900                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3901         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3902                 if (ASIC_IS_DCE3(rdev)) {
3903                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3904                         tmp |= DC_HPDx_INT_ACK;
3905                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3906                 } else {
3907                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3908                         tmp |= DC_HPDx_INT_ACK;
3909                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3910                 }
3911         }
3912         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3913                 if (ASIC_IS_DCE3(rdev)) {
3914                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3915                         tmp |= DC_HPDx_INT_ACK;
3916                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3917                 } else {
3918                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3919                         tmp |= DC_HPDx_INT_ACK;
3920                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3921                 }
3922         }
3923         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3924                 if (ASIC_IS_DCE3(rdev)) {
3925                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3926                         tmp |= DC_HPDx_INT_ACK;
3927                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3928                 } else {
3929                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3930                         tmp |= DC_HPDx_INT_ACK;
3931                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3932                 }
3933         }
3934         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3935                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3936                 tmp |= DC_HPDx_INT_ACK;
3937                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3938         }
3939         if (ASIC_IS_DCE32(rdev)) {
3940                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3941                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3942                         tmp |= DC_HPDx_INT_ACK;
3943                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3944                 }
3945                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3946                         tmp = RREG32(DC_HPD6_INT_CONTROL);
3947                         tmp |= DC_HPDx_INT_ACK;
3948                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3949                 }
3950                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3951                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3952                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3953                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3954                 }
3955                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3956                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3957                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3958                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3959                 }
3960         } else {
3961                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3962                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3963                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3964                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3965                 }
3966                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3967                         if (ASIC_IS_DCE3(rdev)) {
3968                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3969                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3970                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3971                         } else {
3972                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3973                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3974                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3975                         }
3976                 }
3977         }
3978 }
3979
3980 void r600_irq_disable(struct radeon_device *rdev)
3981 {
3982         r600_disable_interrupts(rdev);
3983         /* Wait and acknowledge irq */
3984         mdelay(1);
3985         r600_irq_ack(rdev);
3986         r600_disable_interrupt_state(rdev);
3987 }
3988
3989 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3990 {
3991         u32 wptr, tmp;
3992
3993         if (rdev->wb.enabled)
3994                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3995         else
3996                 wptr = RREG32(IH_RB_WPTR);
3997
3998         if (wptr & RB_OVERFLOW) {
3999                 wptr &= ~RB_OVERFLOW;
4000                 /* When a ring buffer overflow happen start parsing interrupt
4001                  * from the last not overwritten vector (wptr + 16). Hopefully
4002                  * this should allow us to catchup.
4003                  */
4004                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4005                          wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4006                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4007                 tmp = RREG32(IH_RB_CNTL);
4008                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4009                 WREG32(IH_RB_CNTL, tmp);
4010         }
4011         return (wptr & rdev->ih.ptr_mask);
4012 }
4013
4014 /*        r600 IV Ring
4015  * Each IV ring entry is 128 bits:
4016  * [7:0]    - interrupt source id
4017  * [31:8]   - reserved
4018  * [59:32]  - interrupt source data
4019  * [127:60]  - reserved
4020  *
4021  * The basic interrupt vector entries
4022  * are decoded as follows:
4023  * src_id  src_data  description
4024  *      1         0  D1 Vblank
4025  *      1         1  D1 Vline
4026  *      5         0  D2 Vblank
4027  *      5         1  D2 Vline
4028  *     19         0  FP Hot plug detection A
4029  *     19         1  FP Hot plug detection B
4030  *     19         2  DAC A auto-detection
4031  *     19         3  DAC B auto-detection
4032  *     21         4  HDMI block A
4033  *     21         5  HDMI block B
4034  *    176         -  CP_INT RB
4035  *    177         -  CP_INT IB1
4036  *    178         -  CP_INT IB2
4037  *    181         -  EOP Interrupt
4038  *    233         -  GUI Idle
4039  *
4040  * Note, these are based on r600 and may need to be
4041  * adjusted or added to on newer asics
4042  */
4043
4044 int r600_irq_process(struct radeon_device *rdev)
4045 {
4046         u32 wptr;
4047         u32 rptr;
4048         u32 src_id, src_data;
4049         u32 ring_index;
4050         bool queue_hotplug = false;
4051         bool queue_hdmi = false;
4052         bool queue_thermal = false;
4053
4054         if (!rdev->ih.enabled || rdev->shutdown)
4055                 return IRQ_NONE;
4056
4057         /* No MSIs, need a dummy read to flush PCI DMAs */
4058         if (!rdev->msi_enabled)
4059                 RREG32(IH_RB_WPTR);
4060
4061         wptr = r600_get_ih_wptr(rdev);
4062
4063 restart_ih:
4064         /* is somebody else already processing irqs? */
4065         if (atomic_xchg(&rdev->ih.lock, 1))
4066                 return IRQ_NONE;
4067
4068         rptr = rdev->ih.rptr;
4069         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4070
4071         /* Order reading of wptr vs. reading of IH ring data */
4072         rmb();
4073
4074         /* display interrupts */
4075         r600_irq_ack(rdev);
4076
4077         while (rptr != wptr) {
4078                 /* wptr/rptr are in bytes! */
4079                 ring_index = rptr / 4;
4080                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4081                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4082
4083                 switch (src_id) {
4084                 case 1: /* D1 vblank/vline */
4085                         switch (src_data) {
4086                         case 0: /* D1 vblank */
4087                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4088                                         DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4089
4090                                 if (rdev->irq.crtc_vblank_int[0]) {
4091                                         drm_handle_vblank(rdev->ddev, 0);
4092                                         rdev->pm.vblank_sync = true;
4093                                         wake_up(&rdev->irq.vblank_queue);
4094                                 }
4095                                 if (atomic_read(&rdev->irq.pflip[0]))
4096                                         radeon_crtc_handle_vblank(rdev, 0);
4097                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4098                                 DRM_DEBUG("IH: D1 vblank\n");
4099
4100                                 break;
4101                         case 1: /* D1 vline */
4102                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4103                                     DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4104
4105                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4106                                 DRM_DEBUG("IH: D1 vline\n");
4107
4108                                 break;
4109                         default:
4110                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4111                                 break;
4112                         }
4113                         break;
4114                 case 5: /* D2 vblank/vline */
4115                         switch (src_data) {
4116                         case 0: /* D2 vblank */
4117                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4118                                         DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4119
4120                                 if (rdev->irq.crtc_vblank_int[1]) {
4121                                         drm_handle_vblank(rdev->ddev, 1);
4122                                         rdev->pm.vblank_sync = true;
4123                                         wake_up(&rdev->irq.vblank_queue);
4124                                 }
4125                                 if (atomic_read(&rdev->irq.pflip[1]))
4126                                         radeon_crtc_handle_vblank(rdev, 1);
4127                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4128                                 DRM_DEBUG("IH: D2 vblank\n");
4129
4130                                 break;
4131                         case 1: /* D1 vline */
4132                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4133                                         DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4134
4135                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4136                                 DRM_DEBUG("IH: D2 vline\n");
4137
4138                                 break;
4139                         default:
4140                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4141                                 break;
4142                         }
4143                         break;
4144                 case 9: /* D1 pflip */
4145                         DRM_DEBUG("IH: D1 flip\n");
4146                         if (radeon_use_pflipirq > 0)
4147                                 radeon_crtc_handle_flip(rdev, 0);
4148                         break;
4149                 case 11: /* D2 pflip */
4150                         DRM_DEBUG("IH: D2 flip\n");
4151                         if (radeon_use_pflipirq > 0)
4152                                 radeon_crtc_handle_flip(rdev, 1);
4153                         break;
4154                 case 19: /* HPD/DAC hotplug */
4155                         switch (src_data) {
4156                         case 0:
4157                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4158                                         DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4159
4160                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4161                                 queue_hotplug = true;
4162                                 DRM_DEBUG("IH: HPD1\n");
4163                                 break;
4164                         case 1:
4165                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4166                                         DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4167
4168                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4169                                 queue_hotplug = true;
4170                                 DRM_DEBUG("IH: HPD2\n");
4171                                 break;
4172                         case 4:
4173                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4174                                         DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4175
4176                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4177                                 queue_hotplug = true;
4178                                 DRM_DEBUG("IH: HPD3\n");
4179                                 break;
4180                         case 5:
4181                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4182                                         DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4183
4184                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4185                                 queue_hotplug = true;
4186                                 DRM_DEBUG("IH: HPD4\n");
4187                                 break;
4188                         case 10:
4189                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4190                                         DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4191
4192                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4193                                 queue_hotplug = true;
4194                                 DRM_DEBUG("IH: HPD5\n");
4195                                 break;
4196                         case 12:
4197                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4198                                         DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4199
4200                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4201                                 queue_hotplug = true;
4202                                 DRM_DEBUG("IH: HPD6\n");
4203
4204                                 break;
4205                         default:
4206                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4207                                 break;
4208                         }
4209                         break;
4210                 case 21: /* hdmi */
4211                         switch (src_data) {
4212                         case 4:
4213                                 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4214                                         DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4215
4216                                 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4217                                 queue_hdmi = true;
4218                                 DRM_DEBUG("IH: HDMI0\n");
4219
4220                                 break;
4221                         case 5:
4222                                 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4223                                         DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4224
4225                                 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4226                                 queue_hdmi = true;
4227                                 DRM_DEBUG("IH: HDMI1\n");
4228
4229                                 break;
4230                         default:
4231                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4232                                 break;
4233                         }
4234                         break;
4235                 case 124: /* UVD */
4236                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4237                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4238                         break;
4239                 case 176: /* CP_INT in ring buffer */
4240                 case 177: /* CP_INT in IB1 */
4241                 case 178: /* CP_INT in IB2 */
4242                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4243                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4244                         break;
4245                 case 181: /* CP EOP event */
4246                         DRM_DEBUG("IH: CP EOP\n");
4247                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4248                         break;
4249                 case 224: /* DMA trap event */
4250                         DRM_DEBUG("IH: DMA trap\n");
4251                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4252                         break;
4253                 case 230: /* thermal low to high */
4254                         DRM_DEBUG("IH: thermal low to high\n");
4255                         rdev->pm.dpm.thermal.high_to_low = false;
4256                         queue_thermal = true;
4257                         break;
4258                 case 231: /* thermal high to low */
4259                         DRM_DEBUG("IH: thermal high to low\n");
4260                         rdev->pm.dpm.thermal.high_to_low = true;
4261                         queue_thermal = true;
4262                         break;
4263                 case 233: /* GUI IDLE */
4264                         DRM_DEBUG("IH: GUI idle\n");
4265                         break;
4266                 default:
4267                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4268                         break;
4269                 }
4270
4271                 /* wptr/rptr are in bytes! */
4272                 rptr += 16;
4273                 rptr &= rdev->ih.ptr_mask;
4274                 WREG32(IH_RB_RPTR, rptr);
4275         }
4276         if (queue_hotplug)
4277                 schedule_delayed_work(&rdev->hotplug_work, 0);
4278         if (queue_hdmi)
4279                 schedule_work(&rdev->audio_work);
4280         if (queue_thermal && rdev->pm.dpm_enabled)
4281                 schedule_work(&rdev->pm.dpm.thermal.work);
4282         rdev->ih.rptr = rptr;
4283         atomic_set(&rdev->ih.lock, 0);
4284
4285         /* make sure wptr hasn't changed while processing */
4286         wptr = r600_get_ih_wptr(rdev);
4287         if (wptr != rptr)
4288                 goto restart_ih;
4289
4290         return IRQ_HANDLED;
4291 }
4292
4293 /*
4294  * Debugfs info
4295  */
4296 #if defined(CONFIG_DEBUG_FS)
4297
4298 static int r600_debugfs_mc_info_show(struct seq_file *m, void *unused)
4299 {
4300         struct radeon_device *rdev = (struct radeon_device *)m->private;
4301
4302         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4303         DREG32_SYS(m, rdev, VM_L2_STATUS);
4304         return 0;
4305 }
4306
4307 DEFINE_SHOW_ATTRIBUTE(r600_debugfs_mc_info);
4308 #endif
4309
4310 static void r600_debugfs_mc_info_init(struct radeon_device *rdev)
4311 {
4312 #if defined(CONFIG_DEBUG_FS)
4313         struct dentry *root = rdev->ddev->primary->debugfs_root;
4314
4315         debugfs_create_file("r600_mc_info", 0444, root, rdev,
4316                             &r600_debugfs_mc_info_fops);
4317
4318 #endif
4319 }
4320
4321 /**
4322  * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4323  * @rdev: radeon device structure
4324  *
4325  * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4326  * through the ring buffer. This leads to corruption in rendering, see
4327  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4328  * directly perform the HDP flush by writing the register through MMIO.
4329  */
4330 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4331 {
4332         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4333          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4334          * This seems to cause problems on some AGP cards. Just use the old
4335          * method for them.
4336          */
4337         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4338             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4339                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4340
4341                 WREG32(HDP_DEBUG1, 0);
4342                 readl((void __iomem *)ptr);
4343         } else
4344                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4345 }
4346
4347 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4348 {
4349         u32 link_width_cntl, mask;
4350
4351         if (rdev->flags & RADEON_IS_IGP)
4352                 return;
4353
4354         if (!(rdev->flags & RADEON_IS_PCIE))
4355                 return;
4356
4357         /* x2 cards have a special sequence */
4358         if (ASIC_IS_X2(rdev))
4359                 return;
4360
4361         radeon_gui_idle(rdev);
4362
4363         switch (lanes) {
4364         case 0:
4365                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4366                 break;
4367         case 1:
4368                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4369                 break;
4370         case 2:
4371                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4372                 break;
4373         case 4:
4374                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4375                 break;
4376         case 8:
4377                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4378                 break;
4379         case 12:
4380                 /* not actually supported */
4381                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4382                 break;
4383         case 16:
4384                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4385                 break;
4386         default:
4387                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4388                 return;
4389         }
4390
4391         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4392         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4393         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4394         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4395                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4396
4397         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4398 }
4399
4400 int r600_get_pcie_lanes(struct radeon_device *rdev)
4401 {
4402         u32 link_width_cntl;
4403
4404         if (rdev->flags & RADEON_IS_IGP)
4405                 return 0;
4406
4407         if (!(rdev->flags & RADEON_IS_PCIE))
4408                 return 0;
4409
4410         /* x2 cards have a special sequence */
4411         if (ASIC_IS_X2(rdev))
4412                 return 0;
4413
4414         radeon_gui_idle(rdev);
4415
4416         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4417
4418         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4419         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4420                 return 1;
4421         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4422                 return 2;
4423         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4424                 return 4;
4425         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4426                 return 8;
4427         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4428                 /* not actually supported */
4429                 return 12;
4430         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4431         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4432         default:
4433                 return 16;
4434         }
4435 }
4436
4437 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4438 {
4439         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4440         u16 link_cntl2;
4441
4442         if (radeon_pcie_gen2 == 0)
4443                 return;
4444
4445         if (rdev->flags & RADEON_IS_IGP)
4446                 return;
4447
4448         if (!(rdev->flags & RADEON_IS_PCIE))
4449                 return;
4450
4451         /* x2 cards have a special sequence */
4452         if (ASIC_IS_X2(rdev))
4453                 return;
4454
4455         /* only RV6xx+ chips are supported */
4456         if (rdev->family <= CHIP_R600)
4457                 return;
4458
4459         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4460                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4461                 return;
4462
4463         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4464         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4465                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4466                 return;
4467         }
4468
4469         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4470
4471         /* 55 nm r6xx asics */
4472         if ((rdev->family == CHIP_RV670) ||
4473             (rdev->family == CHIP_RV620) ||
4474             (rdev->family == CHIP_RV635)) {
4475                 /* advertise upconfig capability */
4476                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4477                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4478                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4479                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4480                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4481                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4482                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4483                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4484                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4485                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4486                 } else {
4487                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4488                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4489                 }
4490         }
4491
4492         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4493         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4494             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4495
4496                 /* 55 nm r6xx asics */
4497                 if ((rdev->family == CHIP_RV670) ||
4498                     (rdev->family == CHIP_RV620) ||
4499                     (rdev->family == CHIP_RV635)) {
4500                         WREG32(MM_CFGREGS_CNTL, 0x8);
4501                         link_cntl2 = RREG32(0x4088);
4502                         WREG32(MM_CFGREGS_CNTL, 0);
4503                         /* not supported yet */
4504                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4505                                 return;
4506                 }
4507
4508                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4509                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4510                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4511                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4512                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4513                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4514
4515                 tmp = RREG32(0x541c);
4516                 WREG32(0x541c, tmp | 0x8);
4517                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4518                 link_cntl2 = RREG16(0x4088);
4519                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4520                 link_cntl2 |= 0x2;
4521                 WREG16(0x4088, link_cntl2);
4522                 WREG32(MM_CFGREGS_CNTL, 0);
4523
4524                 if ((rdev->family == CHIP_RV670) ||
4525                     (rdev->family == CHIP_RV620) ||
4526                     (rdev->family == CHIP_RV635)) {
4527                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4528                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4529                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4530                 } else {
4531                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4532                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4533                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4534                 }
4535
4536                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4537                 speed_cntl |= LC_GEN2_EN_STRAP;
4538                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4539
4540         } else {
4541                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4542                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4543                 if (1)
4544                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4545                 else
4546                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4547                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4548         }
4549 }
4550
4551 /**
4552  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4553  *
4554  * @rdev: radeon_device pointer
4555  *
4556  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4557  * Returns the 64 bit clock counter snapshot.
4558  */
4559 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4560 {
4561         uint64_t clock;
4562
4563         mutex_lock(&rdev->gpu_clock_mutex);
4564         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4565         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4566                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4567         mutex_unlock(&rdev->gpu_clock_mutex);
4568         return clock;
4569 }