2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/seq_file.h>
33 #include <linux/slab.h>
35 #include <drm/drm_device.h>
36 #include <drm/drm_file.h>
37 #include <drm/drm_fourcc.h>
38 #include <drm/drm_vblank.h>
39 #include <drm/radeon_drm.h>
42 #include "r100_reg_safe.h"
45 #include "radeon_asic.h"
46 #include "radeon_reg.h"
47 #include "rn50_reg_safe.h"
53 #define FIRMWARE_R100 "/*(DEBLOBBED)*/"
54 #define FIRMWARE_R200 "/*(DEBLOBBED)*/"
55 #define FIRMWARE_R300 "/*(DEBLOBBED)*/"
56 #define FIRMWARE_R420 "/*(DEBLOBBED)*/"
57 #define FIRMWARE_RS690 "/*(DEBLOBBED)*/"
58 #define FIRMWARE_RS600 "/*(DEBLOBBED)*/"
59 #define FIRMWARE_R520 "/*(DEBLOBBED)*/"
63 #include "r100_track.h"
65 /* This files gather functions specifics to:
66 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
67 * and others in some cases.
70 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
73 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
78 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
85 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
90 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
91 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
103 * r100_wait_for_vblank - vblank wait asic callback.
105 * @rdev: radeon_device pointer
106 * @crtc: crtc to wait for vblank on
108 * Wait for vblank on the requested crtc (r1xx-r4xx).
110 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
114 if (crtc >= rdev->num_crtc)
118 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
121 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
125 /* depending on when we hit vblank, we may be close to active; if so,
126 * wait for another frame.
128 while (r100_is_in_vblank(rdev, crtc)) {
129 if (i++ % 100 == 0) {
130 if (!r100_is_counter_moving(rdev, crtc))
135 while (!r100_is_in_vblank(rdev, crtc)) {
136 if (i++ % 100 == 0) {
137 if (!r100_is_counter_moving(rdev, crtc))
144 * r100_page_flip - pageflip callback.
146 * @rdev: radeon_device pointer
147 * @crtc_id: crtc to cleanup pageflip on
148 * @crtc_base: new address of the crtc (GPU MC address)
149 * @async: asynchronous flip
151 * Does the actual pageflip (r1xx-r4xx).
152 * During vblank we take the crtc lock and wait for the update_pending
153 * bit to go high, when it does, we release the lock, and allow the
154 * double buffered update to take place.
156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159 uint32_t crtc_pitch, pitch_pixels;
160 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
161 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
164 /* Lock the graphics update lock */
165 /* update the scanout addresses */
166 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
169 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
170 crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,
171 fb->format->cpp[0] * 8 * 8);
172 crtc_pitch |= crtc_pitch << 16;
173 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
175 /* Wait for update_pending to go high. */
176 for (i = 0; i < rdev->usec_timeout; i++) {
177 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
181 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
183 /* Unlock the lock, so double-buffering can take place inside vblank */
184 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
185 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
190 * r100_page_flip_pending - check if page flip is still pending
192 * @rdev: radeon_device pointer
193 * @crtc_id: crtc to check
195 * Check if the last pagefilp is still pending (r1xx-r4xx).
196 * Returns the current update pending status.
198 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
200 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
202 /* Return current update_pending status: */
203 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
204 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
208 * r100_pm_get_dynpm_state - look up dynpm power state callback.
210 * @rdev: radeon_device pointer
212 * Look up the optimal power state based on the
213 * current state of the GPU (r1xx-r5xx).
214 * Used for dynpm only.
216 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
219 rdev->pm.dynpm_can_upclock = true;
220 rdev->pm.dynpm_can_downclock = true;
222 switch (rdev->pm.dynpm_planned_action) {
223 case DYNPM_ACTION_MINIMUM:
224 rdev->pm.requested_power_state_index = 0;
225 rdev->pm.dynpm_can_downclock = false;
227 case DYNPM_ACTION_DOWNCLOCK:
228 if (rdev->pm.current_power_state_index == 0) {
229 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
230 rdev->pm.dynpm_can_downclock = false;
232 if (rdev->pm.active_crtc_count > 1) {
233 for (i = 0; i < rdev->pm.num_power_states; i++) {
234 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
236 else if (i >= rdev->pm.current_power_state_index) {
237 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
240 rdev->pm.requested_power_state_index = i;
245 rdev->pm.requested_power_state_index =
246 rdev->pm.current_power_state_index - 1;
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
251 RADEON_PM_MODE_NO_DISPLAY)) {
252 rdev->pm.requested_power_state_index++;
255 case DYNPM_ACTION_UPCLOCK:
256 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
257 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
258 rdev->pm.dynpm_can_upclock = false;
260 if (rdev->pm.active_crtc_count > 1) {
261 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
262 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
264 else if (i <= rdev->pm.current_power_state_index) {
265 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
268 rdev->pm.requested_power_state_index = i;
273 rdev->pm.requested_power_state_index =
274 rdev->pm.current_power_state_index + 1;
277 case DYNPM_ACTION_DEFAULT:
278 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
279 rdev->pm.dynpm_can_upclock = false;
281 case DYNPM_ACTION_NONE:
283 DRM_ERROR("Requested mode for not defined action\n");
286 /* only one clock mode per power state */
287 rdev->pm.requested_clock_mode_index = 0;
289 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
290 rdev->pm.power_state[rdev->pm.requested_power_state_index].
291 clock_info[rdev->pm.requested_clock_mode_index].sclk,
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].mclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
299 * r100_pm_init_profile - Initialize power profiles callback.
301 * @rdev: radeon_device pointer
303 * Initialize the power states used in profile mode
305 * Used for profile mode only.
307 void r100_pm_init_profile(struct radeon_device *rdev)
310 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
311 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
347 * r100_pm_misc - set additional pm hw parameters callback.
349 * @rdev: radeon_device pointer
351 * Set non-clock parameters associated with a power state
352 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
354 void r100_pm_misc(struct radeon_device *rdev)
356 int requested_index = rdev->pm.requested_power_state_index;
357 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
358 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
359 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
361 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
362 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
363 tmp = RREG32(voltage->gpio.reg);
364 if (voltage->active_high)
365 tmp |= voltage->gpio.mask;
367 tmp &= ~(voltage->gpio.mask);
368 WREG32(voltage->gpio.reg, tmp);
370 udelay(voltage->delay);
372 tmp = RREG32(voltage->gpio.reg);
373 if (voltage->active_high)
374 tmp &= ~voltage->gpio.mask;
376 tmp |= voltage->gpio.mask;
377 WREG32(voltage->gpio.reg, tmp);
379 udelay(voltage->delay);
383 sclk_cntl = RREG32_PLL(SCLK_CNTL);
384 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
385 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
386 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
387 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
388 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
389 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
390 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
391 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
393 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
394 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
395 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
396 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
399 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
401 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
402 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
403 if (voltage->delay) {
404 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
405 switch (voltage->delay) {
407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
410 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
420 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
422 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
424 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
425 sclk_cntl &= ~FORCE_HDP;
427 sclk_cntl |= FORCE_HDP;
429 WREG32_PLL(SCLK_CNTL, sclk_cntl);
430 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
431 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
434 if ((rdev->flags & RADEON_IS_PCIE) &&
435 !(rdev->flags & RADEON_IS_IGP) &&
436 rdev->asic->pm.set_pcie_lanes &&
438 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
439 radeon_set_pcie_lanes(rdev,
441 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
446 * r100_pm_prepare - pre-power state change callback.
448 * @rdev: radeon_device pointer
450 * Prepare for a power state change (r1xx-r4xx).
452 void r100_pm_prepare(struct radeon_device *rdev)
454 struct drm_device *ddev = rdev->ddev;
455 struct drm_crtc *crtc;
456 struct radeon_crtc *radeon_crtc;
459 /* disable any active CRTCs */
460 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
461 radeon_crtc = to_radeon_crtc(crtc);
462 if (radeon_crtc->enabled) {
463 if (radeon_crtc->crtc_id) {
464 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
465 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
466 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
468 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
469 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
470 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
477 * r100_pm_finish - post-power state change callback.
479 * @rdev: radeon_device pointer
481 * Clean up after a power state change (r1xx-r4xx).
483 void r100_pm_finish(struct radeon_device *rdev)
485 struct drm_device *ddev = rdev->ddev;
486 struct drm_crtc *crtc;
487 struct radeon_crtc *radeon_crtc;
490 /* enable any active CRTCs */
491 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
492 radeon_crtc = to_radeon_crtc(crtc);
493 if (radeon_crtc->enabled) {
494 if (radeon_crtc->crtc_id) {
495 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
496 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
497 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
499 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
500 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
501 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
508 * r100_gui_idle - gui idle callback.
510 * @rdev: radeon_device pointer
512 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
513 * Returns true if idle, false if not.
515 bool r100_gui_idle(struct radeon_device *rdev)
517 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
523 /* hpd for digital panel detect/disconnect */
525 * r100_hpd_sense - hpd sense callback.
527 * @rdev: radeon_device pointer
528 * @hpd: hpd (hotplug detect) pin
530 * Checks if a digital monitor is connected (r1xx-r4xx).
531 * Returns true if connected, false if not connected.
533 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
535 bool connected = false;
539 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
543 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
553 * r100_hpd_set_polarity - hpd set polarity callback.
555 * @rdev: radeon_device pointer
556 * @hpd: hpd (hotplug detect) pin
558 * Set the polarity of the hpd pin (r1xx-r4xx).
560 void r100_hpd_set_polarity(struct radeon_device *rdev,
561 enum radeon_hpd_id hpd)
564 bool connected = r100_hpd_sense(rdev, hpd);
568 tmp = RREG32(RADEON_FP_GEN_CNTL);
570 tmp &= ~RADEON_FP_DETECT_INT_POL;
572 tmp |= RADEON_FP_DETECT_INT_POL;
573 WREG32(RADEON_FP_GEN_CNTL, tmp);
576 tmp = RREG32(RADEON_FP2_GEN_CNTL);
578 tmp &= ~RADEON_FP2_DETECT_INT_POL;
580 tmp |= RADEON_FP2_DETECT_INT_POL;
581 WREG32(RADEON_FP2_GEN_CNTL, tmp);
589 * r100_hpd_init - hpd setup callback.
591 * @rdev: radeon_device pointer
593 * Setup the hpd pins used by the card (r1xx-r4xx).
594 * Set the polarity, and enable the hpd interrupts.
596 void r100_hpd_init(struct radeon_device *rdev)
598 struct drm_device *dev = rdev->ddev;
599 struct drm_connector *connector;
602 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
603 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
604 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
605 enable |= 1 << radeon_connector->hpd.hpd;
606 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
608 radeon_irq_kms_enable_hpd(rdev, enable);
612 * r100_hpd_fini - hpd tear down callback.
614 * @rdev: radeon_device pointer
616 * Tear down the hpd pins used by the card (r1xx-r4xx).
617 * Disable the hpd interrupts.
619 void r100_hpd_fini(struct radeon_device *rdev)
621 struct drm_device *dev = rdev->ddev;
622 struct drm_connector *connector;
623 unsigned disable = 0;
625 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
626 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
627 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
628 disable |= 1 << radeon_connector->hpd.hpd;
630 radeon_irq_kms_disable_hpd(rdev, disable);
636 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
638 /* TODO: can we do somethings here ? */
639 /* It seems hw only cache one entry so we should discard this
640 * entry otherwise if first GPU GART read hit this entry it
641 * could end up in wrong address. */
644 int r100_pci_gart_init(struct radeon_device *rdev)
648 if (rdev->gart.ptr) {
649 WARN(1, "R100 PCI GART already initialized\n");
652 /* Initialize common gart structure */
653 r = radeon_gart_init(rdev);
656 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
657 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
658 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
659 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
660 return radeon_gart_table_ram_alloc(rdev);
663 int r100_pci_gart_enable(struct radeon_device *rdev)
667 /* discard memory request outside of configured range */
668 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
669 WREG32(RADEON_AIC_CNTL, tmp);
670 /* set address range for PCI address translate */
671 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
672 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
673 /* set PCI GART page-table base address */
674 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
676 WREG32(RADEON_AIC_CNTL, tmp);
677 r100_pci_gart_tlb_flush(rdev);
678 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
679 (unsigned)(rdev->mc.gtt_size >> 20),
680 (unsigned long long)rdev->gart.table_addr);
681 rdev->gart.ready = true;
685 void r100_pci_gart_disable(struct radeon_device *rdev)
689 /* discard memory request outside of configured range */
690 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
691 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
692 WREG32(RADEON_AIC_LO_ADDR, 0);
693 WREG32(RADEON_AIC_HI_ADDR, 0);
696 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
701 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
704 u32 *gtt = rdev->gart.ptr;
705 gtt[i] = cpu_to_le32(lower_32_bits(entry));
708 void r100_pci_gart_fini(struct radeon_device *rdev)
710 radeon_gart_fini(rdev);
711 r100_pci_gart_disable(rdev);
712 radeon_gart_table_ram_free(rdev);
715 int r100_irq_set(struct radeon_device *rdev)
719 if (!rdev->irq.installed) {
720 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
721 WREG32(R_000040_GEN_INT_CNTL, 0);
724 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
725 tmp |= RADEON_SW_INT_ENABLE;
727 if (rdev->irq.crtc_vblank_int[0] ||
728 atomic_read(&rdev->irq.pflip[0])) {
729 tmp |= RADEON_CRTC_VBLANK_MASK;
731 if (rdev->irq.crtc_vblank_int[1] ||
732 atomic_read(&rdev->irq.pflip[1])) {
733 tmp |= RADEON_CRTC2_VBLANK_MASK;
735 if (rdev->irq.hpd[0]) {
736 tmp |= RADEON_FP_DETECT_MASK;
738 if (rdev->irq.hpd[1]) {
739 tmp |= RADEON_FP2_DETECT_MASK;
741 WREG32(RADEON_GEN_INT_CNTL, tmp);
743 /* read back to post the write */
744 RREG32(RADEON_GEN_INT_CNTL);
749 void r100_irq_disable(struct radeon_device *rdev)
753 WREG32(R_000040_GEN_INT_CNTL, 0);
754 /* Wait and acknowledge irq */
756 tmp = RREG32(R_000044_GEN_INT_STATUS);
757 WREG32(R_000044_GEN_INT_STATUS, tmp);
760 static uint32_t r100_irq_ack(struct radeon_device *rdev)
762 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
763 uint32_t irq_mask = RADEON_SW_INT_TEST |
764 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
765 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
768 WREG32(RADEON_GEN_INT_STATUS, irqs);
770 return irqs & irq_mask;
773 int r100_irq_process(struct radeon_device *rdev)
775 uint32_t status, msi_rearm;
776 bool queue_hotplug = false;
778 status = r100_irq_ack(rdev);
782 if (rdev->shutdown) {
787 if (status & RADEON_SW_INT_TEST) {
788 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
790 /* Vertical blank interrupts */
791 if (status & RADEON_CRTC_VBLANK_STAT) {
792 if (rdev->irq.crtc_vblank_int[0]) {
793 drm_handle_vblank(rdev->ddev, 0);
794 rdev->pm.vblank_sync = true;
795 wake_up(&rdev->irq.vblank_queue);
797 if (atomic_read(&rdev->irq.pflip[0]))
798 radeon_crtc_handle_vblank(rdev, 0);
800 if (status & RADEON_CRTC2_VBLANK_STAT) {
801 if (rdev->irq.crtc_vblank_int[1]) {
802 drm_handle_vblank(rdev->ddev, 1);
803 rdev->pm.vblank_sync = true;
804 wake_up(&rdev->irq.vblank_queue);
806 if (atomic_read(&rdev->irq.pflip[1]))
807 radeon_crtc_handle_vblank(rdev, 1);
809 if (status & RADEON_FP_DETECT_STAT) {
810 queue_hotplug = true;
813 if (status & RADEON_FP2_DETECT_STAT) {
814 queue_hotplug = true;
817 status = r100_irq_ack(rdev);
820 schedule_delayed_work(&rdev->hotplug_work, 0);
821 if (rdev->msi_enabled) {
822 switch (rdev->family) {
825 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
826 WREG32(RADEON_AIC_CNTL, msi_rearm);
827 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
830 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
837 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
840 return RREG32(RADEON_CRTC_CRNT_FRAME);
842 return RREG32(RADEON_CRTC2_CRNT_FRAME);
846 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
847 * @rdev: radeon device structure
848 * @ring: ring buffer struct for emitting packets
850 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
852 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
853 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
854 RADEON_HDP_READ_BUFFER_INVALIDATE);
855 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
856 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
859 /* Who ever call radeon_fence_emit should call ring_lock and ask
860 * for enough space (today caller are ib schedule and buffer move) */
861 void r100_fence_ring_emit(struct radeon_device *rdev,
862 struct radeon_fence *fence)
864 struct radeon_ring *ring = &rdev->ring[fence->ring];
866 /* We have to make sure that caches are flushed before
867 * CPU might read something from VRAM. */
868 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
869 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
870 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
871 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
872 /* Wait until IDLE & CLEAN */
873 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
874 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
875 r100_ring_hdp_flush(rdev, ring);
876 /* Emit fence sequence & fire IRQ */
877 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
878 radeon_ring_write(ring, fence->seq);
879 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
880 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
883 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
884 struct radeon_ring *ring,
885 struct radeon_semaphore *semaphore,
888 /* Unused on older asics, since we don't have semaphores or multiple rings */
893 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
896 unsigned num_gpu_pages,
897 struct dma_resv *resv)
899 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
900 struct radeon_fence *fence;
902 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
904 uint32_t stride_pixels;
909 /* radeon limited to 16k stride */
910 stride_bytes &= 0x3fff;
911 /* radeon pitch is /64 */
912 pitch = stride_bytes / 64;
913 stride_pixels = stride_bytes / 4;
914 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
916 /* Ask for enough room for blit + flush + fence */
917 ndw = 64 + (10 * num_loops);
918 r = radeon_ring_lock(rdev, ring, ndw);
920 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
921 return ERR_PTR(-EINVAL);
923 while (num_gpu_pages > 0) {
924 cur_pages = num_gpu_pages;
925 if (cur_pages > 8191) {
928 num_gpu_pages -= cur_pages;
930 /* pages are in Y direction - height
931 page width in X direction - width */
932 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
933 radeon_ring_write(ring,
934 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
935 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
936 RADEON_GMC_SRC_CLIPPING |
937 RADEON_GMC_DST_CLIPPING |
938 RADEON_GMC_BRUSH_NONE |
939 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
940 RADEON_GMC_SRC_DATATYPE_COLOR |
942 RADEON_DP_SRC_SOURCE_MEMORY |
943 RADEON_GMC_CLR_CMP_CNTL_DIS |
944 RADEON_GMC_WR_MSK_DIS);
945 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
946 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
947 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
948 radeon_ring_write(ring, 0);
949 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
950 radeon_ring_write(ring, num_gpu_pages);
951 radeon_ring_write(ring, num_gpu_pages);
952 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
954 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
955 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
956 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
957 radeon_ring_write(ring,
958 RADEON_WAIT_2D_IDLECLEAN |
959 RADEON_WAIT_HOST_IDLECLEAN |
960 RADEON_WAIT_DMA_GUI_IDLE);
961 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
963 radeon_ring_unlock_undo(rdev, ring);
966 radeon_ring_unlock_commit(rdev, ring, false);
970 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
975 for (i = 0; i < rdev->usec_timeout; i++) {
976 tmp = RREG32(R_000E40_RBBM_STATUS);
977 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
985 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
989 r = radeon_ring_lock(rdev, ring, 2);
993 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
994 radeon_ring_write(ring,
995 RADEON_ISYNC_ANY2D_IDLE3D |
996 RADEON_ISYNC_ANY3D_IDLE2D |
997 RADEON_ISYNC_WAIT_IDLEGUI |
998 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
999 radeon_ring_unlock_commit(rdev, ring, false);
1003 /* Load the microcode for the CP */
1004 static int r100_cp_init_microcode(struct radeon_device *rdev)
1006 const char *fw_name = NULL;
1009 DRM_DEBUG_KMS("\n");
1011 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1012 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1013 (rdev->family == CHIP_RS200)) {
1014 DRM_INFO("Loading R100 Microcode\n");
1015 fw_name = FIRMWARE_R100;
1016 } else if ((rdev->family == CHIP_R200) ||
1017 (rdev->family == CHIP_RV250) ||
1018 (rdev->family == CHIP_RV280) ||
1019 (rdev->family == CHIP_RS300)) {
1020 DRM_INFO("Loading R200 Microcode\n");
1021 fw_name = FIRMWARE_R200;
1022 } else if ((rdev->family == CHIP_R300) ||
1023 (rdev->family == CHIP_R350) ||
1024 (rdev->family == CHIP_RV350) ||
1025 (rdev->family == CHIP_RV380) ||
1026 (rdev->family == CHIP_RS400) ||
1027 (rdev->family == CHIP_RS480)) {
1028 DRM_INFO("Loading R300 Microcode\n");
1029 fw_name = FIRMWARE_R300;
1030 } else if ((rdev->family == CHIP_R420) ||
1031 (rdev->family == CHIP_R423) ||
1032 (rdev->family == CHIP_RV410)) {
1033 DRM_INFO("Loading R400 Microcode\n");
1034 fw_name = FIRMWARE_R420;
1035 } else if ((rdev->family == CHIP_RS690) ||
1036 (rdev->family == CHIP_RS740)) {
1037 DRM_INFO("Loading RS690/RS740 Microcode\n");
1038 fw_name = FIRMWARE_RS690;
1039 } else if (rdev->family == CHIP_RS600) {
1040 DRM_INFO("Loading RS600 Microcode\n");
1041 fw_name = FIRMWARE_RS600;
1042 } else if ((rdev->family == CHIP_RV515) ||
1043 (rdev->family == CHIP_R520) ||
1044 (rdev->family == CHIP_RV530) ||
1045 (rdev->family == CHIP_R580) ||
1046 (rdev->family == CHIP_RV560) ||
1047 (rdev->family == CHIP_RV570)) {
1048 DRM_INFO("Loading R500 Microcode\n");
1049 fw_name = FIRMWARE_R520;
1052 err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
1054 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
1055 } else if (rdev->me_fw->size % 8) {
1056 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1057 rdev->me_fw->size, fw_name);
1059 release_firmware(rdev->me_fw);
1065 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1066 struct radeon_ring *ring)
1070 if (rdev->wb.enabled)
1071 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1073 rptr = RREG32(RADEON_CP_RB_RPTR);
1078 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1079 struct radeon_ring *ring)
1081 return RREG32(RADEON_CP_RB_WPTR);
1084 void r100_gfx_set_wptr(struct radeon_device *rdev,
1085 struct radeon_ring *ring)
1087 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1088 (void)RREG32(RADEON_CP_RB_WPTR);
1091 static void r100_cp_load_microcode(struct radeon_device *rdev)
1093 const __be32 *fw_data;
1096 if (r100_gui_wait_for_idle(rdev)) {
1097 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1101 size = rdev->me_fw->size / 4;
1102 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1103 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1104 for (i = 0; i < size; i += 2) {
1105 WREG32(RADEON_CP_ME_RAM_DATAH,
1106 be32_to_cpup(&fw_data[i]));
1107 WREG32(RADEON_CP_ME_RAM_DATAL,
1108 be32_to_cpup(&fw_data[i + 1]));
1113 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1115 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1119 unsigned pre_write_timer;
1120 unsigned pre_write_limit;
1121 unsigned indirect2_start;
1122 unsigned indirect1_start;
1126 r100_debugfs_cp_init(rdev);
1128 r = r100_cp_init_microcode(rdev);
1130 DRM_ERROR("Failed to load firmware!\n");
1135 /* Align ring size */
1136 rb_bufsz = order_base_2(ring_size / 8);
1137 ring_size = (1 << (rb_bufsz + 1)) * 4;
1138 r100_cp_load_microcode(rdev);
1139 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1144 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1145 * the rptr copy in system ram */
1147 /* cp will read 128bytes at a time (4 dwords) */
1149 ring->align_mask = 16 - 1;
1150 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1151 pre_write_timer = 64;
1152 /* Force CP_RB_WPTR write if written more than one time before the
1155 pre_write_limit = 0;
1156 /* Setup the cp cache like this (cache size is 96 dwords) :
1158 * INDIRECT1 16 to 79
1159 * INDIRECT2 80 to 95
1160 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1161 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1162 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1163 * Idea being that most of the gpu cmd will be through indirect1 buffer
1164 * so it gets the bigger cache.
1166 indirect2_start = 80;
1167 indirect1_start = 16;
1169 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1170 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1171 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1172 REG_SET(RADEON_MAX_FETCH, max_fetch));
1174 tmp |= RADEON_BUF_SWAP_32BIT;
1176 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1178 /* Set ring address */
1179 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1180 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1181 /* Force read & write ptr to 0 */
1182 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1183 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1185 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1187 /* set the wb address whether it's enabled or not */
1188 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1189 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1190 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1192 if (rdev->wb.enabled)
1193 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1195 tmp |= RADEON_RB_NO_UPDATE;
1196 WREG32(R_000770_SCRATCH_UMSK, 0);
1199 WREG32(RADEON_CP_RB_CNTL, tmp);
1201 /* Set cp mode to bus mastering & enable cp*/
1202 WREG32(RADEON_CP_CSQ_MODE,
1203 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1204 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1205 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1206 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1207 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1209 /* at this point everything should be setup correctly to enable master */
1210 pci_set_master(rdev->pdev);
1212 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1213 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1215 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1219 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1221 if (!ring->rptr_save_reg /* not resuming from suspend */
1222 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1223 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1225 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1226 ring->rptr_save_reg = 0;
1232 void r100_cp_fini(struct radeon_device *rdev)
1234 if (r100_cp_wait_for_idle(rdev)) {
1235 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1238 r100_cp_disable(rdev);
1239 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1240 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1241 DRM_INFO("radeon: cp finalized\n");
1244 void r100_cp_disable(struct radeon_device *rdev)
1247 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1248 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1249 WREG32(RADEON_CP_CSQ_MODE, 0);
1250 WREG32(RADEON_CP_CSQ_CNTL, 0);
1251 WREG32(R_000770_SCRATCH_UMSK, 0);
1252 if (r100_gui_wait_for_idle(rdev)) {
1253 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1260 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1261 struct radeon_cs_packet *pkt,
1268 struct radeon_bo_list *reloc;
1271 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1273 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1275 radeon_cs_dump_packet(p, pkt);
1279 value = radeon_get_ib_value(p, idx);
1280 tmp = value & 0x003fffff;
1281 tmp += (((u32)reloc->gpu_offset) >> 10);
1283 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1284 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1285 tile_flags |= RADEON_DST_TILE_MACRO;
1286 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1287 if (reg == RADEON_SRC_PITCH_OFFSET) {
1288 DRM_ERROR("Cannot src blit from microtiled surface\n");
1289 radeon_cs_dump_packet(p, pkt);
1292 tile_flags |= RADEON_DST_TILE_MICRO;
1296 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1298 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1302 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1303 struct radeon_cs_packet *pkt,
1307 struct radeon_bo_list *reloc;
1308 struct r100_cs_track *track;
1310 volatile uint32_t *ib;
1314 track = (struct r100_cs_track *)p->track;
1315 c = radeon_get_ib_value(p, idx++) & 0x1F;
1317 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1319 radeon_cs_dump_packet(p, pkt);
1322 track->num_arrays = c;
1323 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1324 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1326 DRM_ERROR("No reloc for packet3 %d\n",
1328 radeon_cs_dump_packet(p, pkt);
1331 idx_value = radeon_get_ib_value(p, idx);
1332 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1334 track->arrays[i + 0].esize = idx_value >> 8;
1335 track->arrays[i + 0].robj = reloc->robj;
1336 track->arrays[i + 0].esize &= 0x7F;
1337 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1339 DRM_ERROR("No reloc for packet3 %d\n",
1341 radeon_cs_dump_packet(p, pkt);
1344 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1345 track->arrays[i + 1].robj = reloc->robj;
1346 track->arrays[i + 1].esize = idx_value >> 24;
1347 track->arrays[i + 1].esize &= 0x7F;
1350 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1352 DRM_ERROR("No reloc for packet3 %d\n",
1354 radeon_cs_dump_packet(p, pkt);
1357 idx_value = radeon_get_ib_value(p, idx);
1358 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1359 track->arrays[i + 0].robj = reloc->robj;
1360 track->arrays[i + 0].esize = idx_value >> 8;
1361 track->arrays[i + 0].esize &= 0x7F;
1366 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1367 struct radeon_cs_packet *pkt,
1368 const unsigned *auth, unsigned n,
1369 radeon_packet0_check_t check)
1378 /* Check that register fall into register range
1379 * determined by the number of entry (n) in the
1380 * safe register bitmap.
1382 if (pkt->one_reg_wr) {
1383 if ((reg >> 7) > n) {
1387 if (((reg + (pkt->count << 2)) >> 7) > n) {
1391 for (i = 0; i <= pkt->count; i++, idx++) {
1393 m = 1 << ((reg >> 2) & 31);
1395 r = check(p, pkt, idx, reg);
1400 if (pkt->one_reg_wr) {
1401 if (!(auth[j] & m)) {
1412 * r100_cs_packet_parse_vline() - parse userspace VLINE packet
1413 * @p: parser structure holding parsing context.
1415 * Userspace sends a special sequence for VLINE waits.
1416 * PACKET0 - VLINE_START_END + value
1417 * PACKET0 - WAIT_UNTIL +_value
1418 * RELOC (P3) - crtc_id in reloc.
1420 * This function parses this and relocates the VLINE START END
1421 * and WAIT UNTIL packets to the correct crtc.
1422 * It also detects a switched off crtc and nulls out the
1423 * wait in that case.
1425 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1427 struct drm_crtc *crtc;
1428 struct radeon_crtc *radeon_crtc;
1429 struct radeon_cs_packet p3reloc, waitreloc;
1432 uint32_t header, h_idx, reg;
1433 volatile uint32_t *ib;
1437 /* parse the wait until */
1438 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1442 /* check its a wait until and only 1 count */
1443 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1444 waitreloc.count != 0) {
1445 DRM_ERROR("vline wait had illegal wait until segment\n");
1449 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1450 DRM_ERROR("vline wait had illegal wait until\n");
1454 /* jump over the NOP */
1455 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1460 p->idx += waitreloc.count + 2;
1461 p->idx += p3reloc.count + 2;
1463 header = radeon_get_ib_value(p, h_idx);
1464 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1465 reg = R100_CP_PACKET0_GET_REG(header);
1466 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1468 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1471 radeon_crtc = to_radeon_crtc(crtc);
1472 crtc_id = radeon_crtc->crtc_id;
1474 if (!crtc->enabled) {
1475 /* if the CRTC isn't enabled - we need to nop out the wait until */
1476 ib[h_idx + 2] = PACKET2(0);
1477 ib[h_idx + 3] = PACKET2(0);
1478 } else if (crtc_id == 1) {
1480 case AVIVO_D1MODE_VLINE_START_END:
1481 header &= ~R300_CP_PACKET0_REG_MASK;
1482 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1484 case RADEON_CRTC_GUI_TRIG_VLINE:
1485 header &= ~R300_CP_PACKET0_REG_MASK;
1486 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1489 DRM_ERROR("unknown crtc reloc\n");
1493 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1499 static int r100_get_vtx_size(uint32_t vtx_fmt)
1503 /* ordered according to bits in spec */
1504 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1518 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1520 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1522 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1524 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1526 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1528 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1530 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1532 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1535 if (vtx_fmt & (0x7 << 15))
1536 vtx_size += (vtx_fmt >> 15) & 0x7;
1537 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1539 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1541 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1543 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1545 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1547 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1552 static int r100_packet0_check(struct radeon_cs_parser *p,
1553 struct radeon_cs_packet *pkt,
1554 unsigned idx, unsigned reg)
1556 struct radeon_bo_list *reloc;
1557 struct r100_cs_track *track;
1558 volatile uint32_t *ib;
1566 track = (struct r100_cs_track *)p->track;
1568 idx_value = radeon_get_ib_value(p, idx);
1571 case RADEON_CRTC_GUI_TRIG_VLINE:
1572 r = r100_cs_packet_parse_vline(p);
1574 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1576 radeon_cs_dump_packet(p, pkt);
1580 /* FIXME: only allow PACKET3 blit? easier to check for out of
1582 case RADEON_DST_PITCH_OFFSET:
1583 case RADEON_SRC_PITCH_OFFSET:
1584 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1588 case RADEON_RB3D_DEPTHOFFSET:
1589 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1591 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593 radeon_cs_dump_packet(p, pkt);
1596 track->zb.robj = reloc->robj;
1597 track->zb.offset = idx_value;
1598 track->zb_dirty = true;
1599 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1601 case RADEON_RB3D_COLOROFFSET:
1602 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1604 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1606 radeon_cs_dump_packet(p, pkt);
1609 track->cb[0].robj = reloc->robj;
1610 track->cb[0].offset = idx_value;
1611 track->cb_dirty = true;
1612 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1614 case RADEON_PP_TXOFFSET_0:
1615 case RADEON_PP_TXOFFSET_1:
1616 case RADEON_PP_TXOFFSET_2:
1617 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1618 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1620 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1622 radeon_cs_dump_packet(p, pkt);
1625 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1626 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1627 tile_flags |= RADEON_TXO_MACRO_TILE;
1628 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1629 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1631 tmp = idx_value & ~(0x7 << 2);
1633 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1635 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1636 track->textures[i].robj = reloc->robj;
1637 track->tex_dirty = true;
1639 case RADEON_PP_CUBIC_OFFSET_T0_0:
1640 case RADEON_PP_CUBIC_OFFSET_T0_1:
1641 case RADEON_PP_CUBIC_OFFSET_T0_2:
1642 case RADEON_PP_CUBIC_OFFSET_T0_3:
1643 case RADEON_PP_CUBIC_OFFSET_T0_4:
1644 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1645 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1647 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1649 radeon_cs_dump_packet(p, pkt);
1652 track->textures[0].cube_info[i].offset = idx_value;
1653 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1654 track->textures[0].cube_info[i].robj = reloc->robj;
1655 track->tex_dirty = true;
1657 case RADEON_PP_CUBIC_OFFSET_T1_0:
1658 case RADEON_PP_CUBIC_OFFSET_T1_1:
1659 case RADEON_PP_CUBIC_OFFSET_T1_2:
1660 case RADEON_PP_CUBIC_OFFSET_T1_3:
1661 case RADEON_PP_CUBIC_OFFSET_T1_4:
1662 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1663 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1667 radeon_cs_dump_packet(p, pkt);
1670 track->textures[1].cube_info[i].offset = idx_value;
1671 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1672 track->textures[1].cube_info[i].robj = reloc->robj;
1673 track->tex_dirty = true;
1675 case RADEON_PP_CUBIC_OFFSET_T2_0:
1676 case RADEON_PP_CUBIC_OFFSET_T2_1:
1677 case RADEON_PP_CUBIC_OFFSET_T2_2:
1678 case RADEON_PP_CUBIC_OFFSET_T2_3:
1679 case RADEON_PP_CUBIC_OFFSET_T2_4:
1680 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1681 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1685 radeon_cs_dump_packet(p, pkt);
1688 track->textures[2].cube_info[i].offset = idx_value;
1689 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1690 track->textures[2].cube_info[i].robj = reloc->robj;
1691 track->tex_dirty = true;
1693 case RADEON_RE_WIDTH_HEIGHT:
1694 track->maxy = ((idx_value >> 16) & 0x7FF);
1695 track->cb_dirty = true;
1696 track->zb_dirty = true;
1698 case RADEON_RB3D_COLORPITCH:
1699 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1703 radeon_cs_dump_packet(p, pkt);
1706 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1707 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1708 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1709 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1710 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1712 tmp = idx_value & ~(0x7 << 16);
1716 ib[idx] = idx_value;
1718 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1719 track->cb_dirty = true;
1721 case RADEON_RB3D_DEPTHPITCH:
1722 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1723 track->zb_dirty = true;
1725 case RADEON_RB3D_CNTL:
1726 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1732 track->cb[0].cpp = 1;
1737 track->cb[0].cpp = 2;
1740 track->cb[0].cpp = 4;
1743 DRM_ERROR("Invalid color buffer format (%d) !\n",
1744 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1747 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1748 track->cb_dirty = true;
1749 track->zb_dirty = true;
1751 case RADEON_RB3D_ZSTENCILCNTL:
1752 switch (idx_value & 0xf) {
1767 track->zb_dirty = true;
1769 case RADEON_RB3D_ZPASS_ADDR:
1770 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1772 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1774 radeon_cs_dump_packet(p, pkt);
1777 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1779 case RADEON_PP_CNTL:
1781 uint32_t temp = idx_value >> 4;
1782 for (i = 0; i < track->num_texture; i++)
1783 track->textures[i].enabled = !!(temp & (1 << i));
1784 track->tex_dirty = true;
1787 case RADEON_SE_VF_CNTL:
1788 track->vap_vf_cntl = idx_value;
1790 case RADEON_SE_VTX_FMT:
1791 track->vtx_size = r100_get_vtx_size(idx_value);
1793 case RADEON_PP_TEX_SIZE_0:
1794 case RADEON_PP_TEX_SIZE_1:
1795 case RADEON_PP_TEX_SIZE_2:
1796 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1797 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1798 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1799 track->tex_dirty = true;
1801 case RADEON_PP_TEX_PITCH_0:
1802 case RADEON_PP_TEX_PITCH_1:
1803 case RADEON_PP_TEX_PITCH_2:
1804 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1805 track->textures[i].pitch = idx_value + 32;
1806 track->tex_dirty = true;
1808 case RADEON_PP_TXFILTER_0:
1809 case RADEON_PP_TXFILTER_1:
1810 case RADEON_PP_TXFILTER_2:
1811 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1812 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1813 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1814 tmp = (idx_value >> 23) & 0x7;
1815 if (tmp == 2 || tmp == 6)
1816 track->textures[i].roundup_w = false;
1817 tmp = (idx_value >> 27) & 0x7;
1818 if (tmp == 2 || tmp == 6)
1819 track->textures[i].roundup_h = false;
1820 track->tex_dirty = true;
1822 case RADEON_PP_TXFORMAT_0:
1823 case RADEON_PP_TXFORMAT_1:
1824 case RADEON_PP_TXFORMAT_2:
1825 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1826 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1827 track->textures[i].use_pitch = true;
1829 track->textures[i].use_pitch = false;
1830 track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1831 track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1833 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1834 track->textures[i].tex_coord_type = 2;
1835 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1836 case RADEON_TXFORMAT_I8:
1837 case RADEON_TXFORMAT_RGB332:
1838 case RADEON_TXFORMAT_Y8:
1839 track->textures[i].cpp = 1;
1840 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1842 case RADEON_TXFORMAT_AI88:
1843 case RADEON_TXFORMAT_ARGB1555:
1844 case RADEON_TXFORMAT_RGB565:
1845 case RADEON_TXFORMAT_ARGB4444:
1846 case RADEON_TXFORMAT_VYUY422:
1847 case RADEON_TXFORMAT_YVYU422:
1848 case RADEON_TXFORMAT_SHADOW16:
1849 case RADEON_TXFORMAT_LDUDV655:
1850 case RADEON_TXFORMAT_DUDV88:
1851 track->textures[i].cpp = 2;
1852 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1854 case RADEON_TXFORMAT_ARGB8888:
1855 case RADEON_TXFORMAT_RGBA8888:
1856 case RADEON_TXFORMAT_SHADOW32:
1857 case RADEON_TXFORMAT_LDUDUV8888:
1858 track->textures[i].cpp = 4;
1859 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1861 case RADEON_TXFORMAT_DXT1:
1862 track->textures[i].cpp = 1;
1863 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1865 case RADEON_TXFORMAT_DXT23:
1866 case RADEON_TXFORMAT_DXT45:
1867 track->textures[i].cpp = 1;
1868 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1871 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1872 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1873 track->tex_dirty = true;
1875 case RADEON_PP_CUBIC_FACES_0:
1876 case RADEON_PP_CUBIC_FACES_1:
1877 case RADEON_PP_CUBIC_FACES_2:
1879 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1880 for (face = 0; face < 4; face++) {
1881 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1882 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1884 track->tex_dirty = true;
1887 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1893 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1894 struct radeon_cs_packet *pkt,
1895 struct radeon_bo *robj)
1900 value = radeon_get_ib_value(p, idx + 2);
1901 if ((value + 1) > radeon_bo_size(robj)) {
1902 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1903 "(need %u have %lu) !\n",
1905 radeon_bo_size(robj));
1911 static int r100_packet3_check(struct radeon_cs_parser *p,
1912 struct radeon_cs_packet *pkt)
1914 struct radeon_bo_list *reloc;
1915 struct r100_cs_track *track;
1917 volatile uint32_t *ib;
1922 track = (struct r100_cs_track *)p->track;
1923 switch (pkt->opcode) {
1924 case PACKET3_3D_LOAD_VBPNTR:
1925 r = r100_packet3_load_vbpntr(p, pkt, idx);
1929 case PACKET3_INDX_BUFFER:
1930 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1932 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1933 radeon_cs_dump_packet(p, pkt);
1936 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1937 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1943 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1944 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1946 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1947 radeon_cs_dump_packet(p, pkt);
1950 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1951 track->num_arrays = 1;
1952 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1954 track->arrays[0].robj = reloc->robj;
1955 track->arrays[0].esize = track->vtx_size;
1957 track->max_indx = radeon_get_ib_value(p, idx+1);
1959 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1960 track->immd_dwords = pkt->count - 1;
1961 r = r100_cs_track_check(p->rdev, track);
1965 case PACKET3_3D_DRAW_IMMD:
1966 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1967 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1970 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1972 track->immd_dwords = pkt->count - 1;
1973 r = r100_cs_track_check(p->rdev, track);
1977 /* triggers drawing using in-packet vertex data */
1978 case PACKET3_3D_DRAW_IMMD_2:
1979 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1980 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1984 track->immd_dwords = pkt->count;
1985 r = r100_cs_track_check(p->rdev, track);
1989 /* triggers drawing using in-packet vertex data */
1990 case PACKET3_3D_DRAW_VBUF_2:
1991 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1992 r = r100_cs_track_check(p->rdev, track);
1996 /* triggers drawing of vertex buffers setup elsewhere */
1997 case PACKET3_3D_DRAW_INDX_2:
1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1999 r = r100_cs_track_check(p->rdev, track);
2003 /* triggers drawing using indices to vertex buffer */
2004 case PACKET3_3D_DRAW_VBUF:
2005 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2006 r = r100_cs_track_check(p->rdev, track);
2010 /* triggers drawing of vertex buffers setup elsewhere */
2011 case PACKET3_3D_DRAW_INDX:
2012 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2013 r = r100_cs_track_check(p->rdev, track);
2017 /* triggers drawing using indices to vertex buffer */
2018 case PACKET3_3D_CLEAR_HIZ:
2019 case PACKET3_3D_CLEAR_ZMASK:
2020 if (p->rdev->hyperz_filp != p->filp)
2026 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2032 int r100_cs_parse(struct radeon_cs_parser *p)
2034 struct radeon_cs_packet pkt;
2035 struct r100_cs_track *track;
2038 track = kzalloc(sizeof(*track), GFP_KERNEL);
2041 r100_cs_track_clear(p->rdev, track);
2044 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2048 p->idx += pkt.count + 2;
2050 case RADEON_PACKET_TYPE0:
2051 if (p->rdev->family >= CHIP_R200)
2052 r = r100_cs_parse_packet0(p, &pkt,
2053 p->rdev->config.r100.reg_safe_bm,
2054 p->rdev->config.r100.reg_safe_bm_size,
2055 &r200_packet0_check);
2057 r = r100_cs_parse_packet0(p, &pkt,
2058 p->rdev->config.r100.reg_safe_bm,
2059 p->rdev->config.r100.reg_safe_bm_size,
2060 &r100_packet0_check);
2062 case RADEON_PACKET_TYPE2:
2064 case RADEON_PACKET_TYPE3:
2065 r = r100_packet3_check(p, &pkt);
2068 DRM_ERROR("Unknown packet type %d !\n",
2074 } while (p->idx < p->chunk_ib->length_dw);
2078 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2080 DRM_ERROR("pitch %d\n", t->pitch);
2081 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2082 DRM_ERROR("width %d\n", t->width);
2083 DRM_ERROR("width_11 %d\n", t->width_11);
2084 DRM_ERROR("height %d\n", t->height);
2085 DRM_ERROR("height_11 %d\n", t->height_11);
2086 DRM_ERROR("num levels %d\n", t->num_levels);
2087 DRM_ERROR("depth %d\n", t->txdepth);
2088 DRM_ERROR("bpp %d\n", t->cpp);
2089 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2090 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2091 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2092 DRM_ERROR("compress format %d\n", t->compress_format);
2095 static int r100_track_compress_size(int compress_format, int w, int h)
2097 int block_width, block_height, block_bytes;
2098 int wblocks, hblocks;
2105 switch (compress_format) {
2106 case R100_TRACK_COMP_DXT1:
2111 case R100_TRACK_COMP_DXT35:
2117 hblocks = (h + block_height - 1) / block_height;
2118 wblocks = (w + block_width - 1) / block_width;
2119 if (wblocks < min_wblocks)
2120 wblocks = min_wblocks;
2121 sz = wblocks * hblocks * block_bytes;
2125 static int r100_cs_track_cube(struct radeon_device *rdev,
2126 struct r100_cs_track *track, unsigned idx)
2128 unsigned face, w, h;
2129 struct radeon_bo *cube_robj;
2131 unsigned compress_format = track->textures[idx].compress_format;
2133 for (face = 0; face < 5; face++) {
2134 cube_robj = track->textures[idx].cube_info[face].robj;
2135 w = track->textures[idx].cube_info[face].width;
2136 h = track->textures[idx].cube_info[face].height;
2138 if (compress_format) {
2139 size = r100_track_compress_size(compress_format, w, h);
2142 size *= track->textures[idx].cpp;
2144 size += track->textures[idx].cube_info[face].offset;
2146 if (size > radeon_bo_size(cube_robj)) {
2147 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2148 size, radeon_bo_size(cube_robj));
2149 r100_cs_track_texture_print(&track->textures[idx]);
2156 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2157 struct r100_cs_track *track)
2159 struct radeon_bo *robj;
2161 unsigned u, i, w, h, d;
2164 for (u = 0; u < track->num_texture; u++) {
2165 if (!track->textures[u].enabled)
2167 if (track->textures[u].lookup_disable)
2169 robj = track->textures[u].robj;
2171 DRM_ERROR("No texture bound to unit %u\n", u);
2175 for (i = 0; i <= track->textures[u].num_levels; i++) {
2176 if (track->textures[u].use_pitch) {
2177 if (rdev->family < CHIP_R300)
2178 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2180 w = track->textures[u].pitch / (1 << i);
2182 w = track->textures[u].width;
2183 if (rdev->family >= CHIP_RV515)
2184 w |= track->textures[u].width_11;
2186 if (track->textures[u].roundup_w)
2187 w = roundup_pow_of_two(w);
2189 h = track->textures[u].height;
2190 if (rdev->family >= CHIP_RV515)
2191 h |= track->textures[u].height_11;
2193 if (track->textures[u].roundup_h)
2194 h = roundup_pow_of_two(h);
2195 if (track->textures[u].tex_coord_type == 1) {
2196 d = (1 << track->textures[u].txdepth) / (1 << i);
2202 if (track->textures[u].compress_format) {
2204 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2205 /* compressed textures are block based */
2209 size *= track->textures[u].cpp;
2211 switch (track->textures[u].tex_coord_type) {
2216 if (track->separate_cube) {
2217 ret = r100_cs_track_cube(rdev, track, u);
2224 DRM_ERROR("Invalid texture coordinate type %u for unit "
2225 "%u\n", track->textures[u].tex_coord_type, u);
2228 if (size > radeon_bo_size(robj)) {
2229 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2230 "%lu\n", u, size, radeon_bo_size(robj));
2231 r100_cs_track_texture_print(&track->textures[u]);
2238 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2244 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2246 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2247 !track->blend_read_enable)
2250 for (i = 0; i < num_cb; i++) {
2251 if (track->cb[i].robj == NULL) {
2252 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2255 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2256 size += track->cb[i].offset;
2257 if (size > radeon_bo_size(track->cb[i].robj)) {
2258 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2259 "(need %lu have %lu) !\n", i, size,
2260 radeon_bo_size(track->cb[i].robj));
2261 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2262 i, track->cb[i].pitch, track->cb[i].cpp,
2263 track->cb[i].offset, track->maxy);
2267 track->cb_dirty = false;
2269 if (track->zb_dirty && track->z_enabled) {
2270 if (track->zb.robj == NULL) {
2271 DRM_ERROR("[drm] No buffer for z buffer !\n");
2274 size = track->zb.pitch * track->zb.cpp * track->maxy;
2275 size += track->zb.offset;
2276 if (size > radeon_bo_size(track->zb.robj)) {
2277 DRM_ERROR("[drm] Buffer too small for z buffer "
2278 "(need %lu have %lu) !\n", size,
2279 radeon_bo_size(track->zb.robj));
2280 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2281 track->zb.pitch, track->zb.cpp,
2282 track->zb.offset, track->maxy);
2286 track->zb_dirty = false;
2288 if (track->aa_dirty && track->aaresolve) {
2289 if (track->aa.robj == NULL) {
2290 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2293 /* I believe the format comes from colorbuffer0. */
2294 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2295 size += track->aa.offset;
2296 if (size > radeon_bo_size(track->aa.robj)) {
2297 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2298 "(need %lu have %lu) !\n", i, size,
2299 radeon_bo_size(track->aa.robj));
2300 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2301 i, track->aa.pitch, track->cb[0].cpp,
2302 track->aa.offset, track->maxy);
2306 track->aa_dirty = false;
2308 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2309 if (track->vap_vf_cntl & (1 << 14)) {
2310 nverts = track->vap_alt_nverts;
2312 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2314 switch (prim_walk) {
2316 for (i = 0; i < track->num_arrays; i++) {
2317 size = track->arrays[i].esize * track->max_indx * 4;
2318 if (track->arrays[i].robj == NULL) {
2319 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2320 "bound\n", prim_walk, i);
2323 if (size > radeon_bo_size(track->arrays[i].robj)) {
2324 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2325 "need %lu dwords have %lu dwords\n",
2326 prim_walk, i, size >> 2,
2327 radeon_bo_size(track->arrays[i].robj)
2329 DRM_ERROR("Max indices %u\n", track->max_indx);
2335 for (i = 0; i < track->num_arrays; i++) {
2336 size = track->arrays[i].esize * (nverts - 1) * 4;
2337 if (track->arrays[i].robj == NULL) {
2338 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2339 "bound\n", prim_walk, i);
2342 if (size > radeon_bo_size(track->arrays[i].robj)) {
2343 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2344 "need %lu dwords have %lu dwords\n",
2345 prim_walk, i, size >> 2,
2346 radeon_bo_size(track->arrays[i].robj)
2353 size = track->vtx_size * nverts;
2354 if (size != track->immd_dwords) {
2355 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2356 track->immd_dwords, size);
2357 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2358 nverts, track->vtx_size);
2363 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2368 if (track->tex_dirty) {
2369 track->tex_dirty = false;
2370 return r100_cs_track_texture_check(rdev, track);
2375 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2379 track->cb_dirty = true;
2380 track->zb_dirty = true;
2381 track->tex_dirty = true;
2382 track->aa_dirty = true;
2384 if (rdev->family < CHIP_R300) {
2386 if (rdev->family <= CHIP_RS200)
2387 track->num_texture = 3;
2389 track->num_texture = 6;
2391 track->separate_cube = true;
2394 track->num_texture = 16;
2396 track->separate_cube = false;
2397 track->aaresolve = false;
2398 track->aa.robj = NULL;
2401 for (i = 0; i < track->num_cb; i++) {
2402 track->cb[i].robj = NULL;
2403 track->cb[i].pitch = 8192;
2404 track->cb[i].cpp = 16;
2405 track->cb[i].offset = 0;
2407 track->z_enabled = true;
2408 track->zb.robj = NULL;
2409 track->zb.pitch = 8192;
2411 track->zb.offset = 0;
2412 track->vtx_size = 0x7F;
2413 track->immd_dwords = 0xFFFFFFFFUL;
2414 track->num_arrays = 11;
2415 track->max_indx = 0x00FFFFFFUL;
2416 for (i = 0; i < track->num_arrays; i++) {
2417 track->arrays[i].robj = NULL;
2418 track->arrays[i].esize = 0x7F;
2420 for (i = 0; i < track->num_texture; i++) {
2421 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2422 track->textures[i].pitch = 16536;
2423 track->textures[i].width = 16536;
2424 track->textures[i].height = 16536;
2425 track->textures[i].width_11 = 1 << 11;
2426 track->textures[i].height_11 = 1 << 11;
2427 track->textures[i].num_levels = 12;
2428 if (rdev->family <= CHIP_RS200) {
2429 track->textures[i].tex_coord_type = 0;
2430 track->textures[i].txdepth = 0;
2432 track->textures[i].txdepth = 16;
2433 track->textures[i].tex_coord_type = 1;
2435 track->textures[i].cpp = 64;
2436 track->textures[i].robj = NULL;
2437 /* CS IB emission code makes sure texture unit are disabled */
2438 track->textures[i].enabled = false;
2439 track->textures[i].lookup_disable = false;
2440 track->textures[i].roundup_w = true;
2441 track->textures[i].roundup_h = true;
2442 if (track->separate_cube)
2443 for (face = 0; face < 5; face++) {
2444 track->textures[i].cube_info[face].robj = NULL;
2445 track->textures[i].cube_info[face].width = 16536;
2446 track->textures[i].cube_info[face].height = 16536;
2447 track->textures[i].cube_info[face].offset = 0;
2453 * Global GPU functions
2455 static void r100_errata(struct radeon_device *rdev)
2457 rdev->pll_errata = 0;
2459 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2460 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2463 if (rdev->family == CHIP_RV100 ||
2464 rdev->family == CHIP_RS100 ||
2465 rdev->family == CHIP_RS200) {
2466 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2470 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2475 for (i = 0; i < rdev->usec_timeout; i++) {
2476 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2485 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2490 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2491 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2493 for (i = 0; i < rdev->usec_timeout; i++) {
2494 tmp = RREG32(RADEON_RBBM_STATUS);
2495 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2503 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2508 for (i = 0; i < rdev->usec_timeout; i++) {
2509 /* read MC_STATUS */
2510 tmp = RREG32(RADEON_MC_STATUS);
2511 if (tmp & RADEON_MC_IDLE) {
2519 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2523 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2524 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2525 radeon_ring_lockup_update(rdev, ring);
2528 return radeon_ring_test_lockup(rdev, ring);
2531 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2532 void r100_enable_bm(struct radeon_device *rdev)
2535 /* Enable bus mastering */
2536 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2537 WREG32(RADEON_BUS_CNTL, tmp);
2540 void r100_bm_disable(struct radeon_device *rdev)
2544 /* disable bus mastering */
2545 tmp = RREG32(R_000030_BUS_CNTL);
2546 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2548 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2550 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2551 tmp = RREG32(RADEON_BUS_CNTL);
2553 pci_clear_master(rdev->pdev);
2557 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2559 struct r100_mc_save save;
2563 status = RREG32(R_000E40_RBBM_STATUS);
2564 if (!G_000E40_GUI_ACTIVE(status)) {
2567 r100_mc_stop(rdev, &save);
2568 status = RREG32(R_000E40_RBBM_STATUS);
2569 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2571 WREG32(RADEON_CP_CSQ_CNTL, 0);
2572 tmp = RREG32(RADEON_CP_RB_CNTL);
2573 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2574 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2575 WREG32(RADEON_CP_RB_WPTR, 0);
2576 WREG32(RADEON_CP_RB_CNTL, tmp);
2577 /* save PCI state */
2578 pci_save_state(rdev->pdev);
2579 /* disable bus mastering */
2580 r100_bm_disable(rdev);
2581 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2582 S_0000F0_SOFT_RESET_RE(1) |
2583 S_0000F0_SOFT_RESET_PP(1) |
2584 S_0000F0_SOFT_RESET_RB(1));
2585 RREG32(R_0000F0_RBBM_SOFT_RESET);
2587 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2589 status = RREG32(R_000E40_RBBM_STATUS);
2590 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2592 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2593 RREG32(R_0000F0_RBBM_SOFT_RESET);
2595 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2597 status = RREG32(R_000E40_RBBM_STATUS);
2598 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2599 /* restore PCI & busmastering */
2600 pci_restore_state(rdev->pdev);
2601 r100_enable_bm(rdev);
2602 /* Check if GPU is idle */
2603 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2604 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2605 dev_err(rdev->dev, "failed to reset GPU\n");
2608 dev_info(rdev->dev, "GPU reset succeed\n");
2609 r100_mc_resume(rdev, &save);
2613 void r100_set_common_regs(struct radeon_device *rdev)
2615 bool force_dac2 = false;
2618 /* set these so they don't interfere with anything */
2619 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2620 WREG32(RADEON_SUBPIC_CNTL, 0);
2621 WREG32(RADEON_VIPH_CONTROL, 0);
2622 WREG32(RADEON_I2C_CNTL_1, 0);
2623 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2624 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2625 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2627 /* always set up dac2 on rn50 and some rv100 as lots
2628 * of servers seem to wire it up to a VGA port but
2629 * don't report it in the bios connector
2632 switch (rdev->pdev->device) {
2641 /* DELL triple head servers */
2642 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2643 ((rdev->pdev->subsystem_device == 0x016c) ||
2644 (rdev->pdev->subsystem_device == 0x016d) ||
2645 (rdev->pdev->subsystem_device == 0x016e) ||
2646 (rdev->pdev->subsystem_device == 0x016f) ||
2647 (rdev->pdev->subsystem_device == 0x0170) ||
2648 (rdev->pdev->subsystem_device == 0x017d) ||
2649 (rdev->pdev->subsystem_device == 0x017e) ||
2650 (rdev->pdev->subsystem_device == 0x0183) ||
2651 (rdev->pdev->subsystem_device == 0x018a) ||
2652 (rdev->pdev->subsystem_device == 0x019a)))
2658 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2659 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2660 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2662 /* For CRT on DAC2, don't turn it on if BIOS didn't
2663 enable it, even it's detected.
2666 /* force it to crtc0 */
2667 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2668 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2669 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2671 /* set up the TV DAC */
2672 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2673 RADEON_TV_DAC_STD_MASK |
2674 RADEON_TV_DAC_RDACPD |
2675 RADEON_TV_DAC_GDACPD |
2676 RADEON_TV_DAC_BDACPD |
2677 RADEON_TV_DAC_BGADJ_MASK |
2678 RADEON_TV_DAC_DACADJ_MASK);
2679 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2680 RADEON_TV_DAC_NHOLD |
2681 RADEON_TV_DAC_STD_PS2 |
2684 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2685 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2686 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2689 /* switch PM block to ACPI mode */
2690 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2691 tmp &= ~RADEON_PM_MODE_SEL;
2692 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2699 static void r100_vram_get_type(struct radeon_device *rdev)
2703 rdev->mc.vram_is_ddr = false;
2704 if (rdev->flags & RADEON_IS_IGP)
2705 rdev->mc.vram_is_ddr = true;
2706 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2707 rdev->mc.vram_is_ddr = true;
2708 if ((rdev->family == CHIP_RV100) ||
2709 (rdev->family == CHIP_RS100) ||
2710 (rdev->family == CHIP_RS200)) {
2711 tmp = RREG32(RADEON_MEM_CNTL);
2712 if (tmp & RV100_HALF_MODE) {
2713 rdev->mc.vram_width = 32;
2715 rdev->mc.vram_width = 64;
2717 if (rdev->flags & RADEON_SINGLE_CRTC) {
2718 rdev->mc.vram_width /= 4;
2719 rdev->mc.vram_is_ddr = true;
2721 } else if (rdev->family <= CHIP_RV280) {
2722 tmp = RREG32(RADEON_MEM_CNTL);
2723 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2724 rdev->mc.vram_width = 128;
2726 rdev->mc.vram_width = 64;
2730 rdev->mc.vram_width = 128;
2734 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2739 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2741 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2742 * that is has the 2nd generation multifunction PCI interface
2744 if (rdev->family == CHIP_RV280 ||
2745 rdev->family >= CHIP_RV350) {
2746 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2747 ~RADEON_HDP_APER_CNTL);
2748 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2749 return aper_size * 2;
2752 /* Older cards have all sorts of funny issues to deal with. First
2753 * check if it's a multifunction card by reading the PCI config
2754 * header type... Limit those to one aperture size
2756 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2758 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2759 DRM_INFO("Limiting VRAM to one aperture\n");
2763 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2764 * have set it up. We don't write this as it's broken on some ASICs but
2765 * we expect the BIOS to have done the right thing (might be too optimistic...)
2767 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2768 return aper_size * 2;
2772 void r100_vram_init_sizes(struct radeon_device *rdev)
2774 u64 config_aper_size;
2776 /* work out accessible VRAM */
2777 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2778 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2779 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2780 /* FIXME we don't use the second aperture yet when we could use it */
2781 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2782 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2783 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2784 if (rdev->flags & RADEON_IS_IGP) {
2786 /* read NB_TOM to get the amount of ram stolen for the GPU */
2787 tom = RREG32(RADEON_NB_TOM);
2788 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2789 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2790 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2792 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2793 /* Some production boards of m6 will report 0
2796 if (rdev->mc.real_vram_size == 0) {
2797 rdev->mc.real_vram_size = 8192 * 1024;
2798 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2800 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2801 * Novell bug 204882 + along with lots of ubuntu ones
2803 if (rdev->mc.aper_size > config_aper_size)
2804 config_aper_size = rdev->mc.aper_size;
2806 if (config_aper_size > rdev->mc.real_vram_size)
2807 rdev->mc.mc_vram_size = config_aper_size;
2809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2813 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2817 temp = RREG32(RADEON_CONFIG_CNTL);
2819 temp &= ~RADEON_CFG_VGA_RAM_EN;
2820 temp |= RADEON_CFG_VGA_IO_DIS;
2822 temp &= ~RADEON_CFG_VGA_IO_DIS;
2824 WREG32(RADEON_CONFIG_CNTL, temp);
2827 static void r100_mc_init(struct radeon_device *rdev)
2831 r100_vram_get_type(rdev);
2832 r100_vram_init_sizes(rdev);
2833 base = rdev->mc.aper_base;
2834 if (rdev->flags & RADEON_IS_IGP)
2835 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2836 radeon_vram_location(rdev, &rdev->mc, base);
2837 rdev->mc.gtt_base_align = 0;
2838 if (!(rdev->flags & RADEON_IS_AGP))
2839 radeon_gtt_location(rdev, &rdev->mc);
2840 radeon_update_bandwidth_info(rdev);
2845 * Indirect registers accessor
2847 void r100_pll_errata_after_index(struct radeon_device *rdev)
2849 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2850 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2851 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2855 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2857 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2858 * or the chip could hang on a subsequent access
2860 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2864 /* This function is required to workaround a hardware bug in some (all?)
2865 * revisions of the R300. This workaround should be called after every
2866 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2867 * may not be correct.
2869 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2872 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2873 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2874 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2875 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2876 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2880 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2882 unsigned long flags;
2885 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2886 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2887 r100_pll_errata_after_index(rdev);
2888 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2889 r100_pll_errata_after_data(rdev);
2890 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2894 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2896 unsigned long flags;
2898 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2899 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2900 r100_pll_errata_after_index(rdev);
2901 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2902 r100_pll_errata_after_data(rdev);
2903 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2906 static void r100_set_safe_registers(struct radeon_device *rdev)
2908 if (ASIC_IS_RN50(rdev)) {
2909 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2910 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2911 } else if (rdev->family < CHIP_R200) {
2912 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2913 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2915 r200_set_safe_registers(rdev);
2922 #if defined(CONFIG_DEBUG_FS)
2923 static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
2925 struct radeon_device *rdev = (struct radeon_device *)m->private;
2926 uint32_t reg, value;
2929 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2930 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2931 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2932 for (i = 0; i < 64; i++) {
2933 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2934 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2935 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2936 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2937 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2942 static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
2944 struct radeon_device *rdev = (struct radeon_device *)m->private;
2945 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2947 unsigned count, i, j;
2949 radeon_ring_free_size(rdev, ring);
2950 rdp = RREG32(RADEON_CP_RB_RPTR);
2951 wdp = RREG32(RADEON_CP_RB_WPTR);
2952 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2953 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2954 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2955 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2956 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2957 seq_printf(m, "%u dwords in ring\n", count);
2959 for (j = 0; j <= count; j++) {
2960 i = (rdp + j) & ring->ptr_mask;
2961 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2968 static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
2970 struct radeon_device *rdev = (struct radeon_device *)m->private;
2971 uint32_t csq_stat, csq2_stat, tmp;
2972 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2975 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2976 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2977 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2978 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2979 r_rptr = (csq_stat >> 0) & 0x3ff;
2980 r_wptr = (csq_stat >> 10) & 0x3ff;
2981 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2982 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2983 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2984 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2985 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2986 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2987 seq_printf(m, "Ring rptr %u\n", r_rptr);
2988 seq_printf(m, "Ring wptr %u\n", r_wptr);
2989 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2990 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2991 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2992 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2993 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2994 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2995 seq_printf(m, "Ring fifo:\n");
2996 for (i = 0; i < 256; i++) {
2997 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2998 tmp = RREG32(RADEON_CP_CSQ_DATA);
2999 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3001 seq_printf(m, "Indirect1 fifo:\n");
3002 for (i = 256; i <= 512; i++) {
3003 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3004 tmp = RREG32(RADEON_CP_CSQ_DATA);
3005 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3007 seq_printf(m, "Indirect2 fifo:\n");
3008 for (i = 640; i < ib1_wptr; i++) {
3009 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3010 tmp = RREG32(RADEON_CP_CSQ_DATA);
3011 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3016 static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
3018 struct radeon_device *rdev = (struct radeon_device *)m->private;
3021 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3022 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3023 tmp = RREG32(RADEON_MC_FB_LOCATION);
3024 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3025 tmp = RREG32(RADEON_BUS_CNTL);
3026 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3027 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3028 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3029 tmp = RREG32(RADEON_AGP_BASE);
3030 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3031 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3032 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3033 tmp = RREG32(0x01D0);
3034 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3035 tmp = RREG32(RADEON_AIC_LO_ADDR);
3036 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3037 tmp = RREG32(RADEON_AIC_HI_ADDR);
3038 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3039 tmp = RREG32(0x01E4);
3040 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3044 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
3045 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
3046 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
3047 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);
3051 void r100_debugfs_rbbm_init(struct radeon_device *rdev)
3053 #if defined(CONFIG_DEBUG_FS)
3054 struct dentry *root = rdev->ddev->primary->debugfs_root;
3056 debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
3057 &r100_debugfs_rbbm_info_fops);
3061 void r100_debugfs_cp_init(struct radeon_device *rdev)
3063 #if defined(CONFIG_DEBUG_FS)
3064 struct dentry *root = rdev->ddev->primary->debugfs_root;
3066 debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
3067 &r100_debugfs_cp_ring_info_fops);
3068 debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
3069 &r100_debugfs_cp_csq_fifo_fops);
3073 void r100_debugfs_mc_info_init(struct radeon_device *rdev)
3075 #if defined(CONFIG_DEBUG_FS)
3076 struct dentry *root = rdev->ddev->primary->debugfs_root;
3078 debugfs_create_file("r100_mc_info", 0444, root, rdev,
3079 &r100_debugfs_mc_info_fops);
3083 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3084 uint32_t tiling_flags, uint32_t pitch,
3085 uint32_t offset, uint32_t obj_size)
3087 int surf_index = reg * 16;
3090 if (rdev->family <= CHIP_RS200) {
3091 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3092 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3093 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3094 if (tiling_flags & RADEON_TILING_MACRO)
3095 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3096 /* setting pitch to 0 disables tiling */
3097 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3100 } else if (rdev->family <= CHIP_RV280) {
3101 if (tiling_flags & (RADEON_TILING_MACRO))
3102 flags |= R200_SURF_TILE_COLOR_MACRO;
3103 if (tiling_flags & RADEON_TILING_MICRO)
3104 flags |= R200_SURF_TILE_COLOR_MICRO;
3106 if (tiling_flags & RADEON_TILING_MACRO)
3107 flags |= R300_SURF_TILE_MACRO;
3108 if (tiling_flags & RADEON_TILING_MICRO)
3109 flags |= R300_SURF_TILE_MICRO;
3112 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3113 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3114 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3115 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3117 /* r100/r200 divide by 16 */
3118 if (rdev->family < CHIP_R300)
3119 flags |= pitch / 16;
3124 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3125 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3126 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3127 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3131 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3133 int surf_index = reg * 16;
3134 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3137 void r100_bandwidth_update(struct radeon_device *rdev)
3139 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3140 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3141 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3142 fixed20_12 crit_point_ff = {0};
3143 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3144 fixed20_12 memtcas_ff[8] = {
3149 dfixed_init_half(1),
3150 dfixed_init_half(2),
3153 fixed20_12 memtcas_rs480_ff[8] = {
3159 dfixed_init_half(1),
3160 dfixed_init_half(2),
3161 dfixed_init_half(3),
3163 fixed20_12 memtcas2_ff[8] = {
3173 fixed20_12 memtrbs[8] = {
3175 dfixed_init_half(1),
3177 dfixed_init_half(2),
3179 dfixed_init_half(3),
3183 fixed20_12 memtrbs_r4xx[8] = {
3193 fixed20_12 min_mem_eff;
3194 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3195 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3196 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3197 disp_drain_rate2, read_return_rate;
3198 fixed20_12 time_disp1_drop_priority;
3200 int cur_size = 16; /* in octawords */
3201 int critical_point = 0, critical_point2;
3202 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3203 int stop_req, max_stop_req;
3204 struct drm_display_mode *mode1 = NULL;
3205 struct drm_display_mode *mode2 = NULL;
3206 uint32_t pixel_bytes1 = 0;
3207 uint32_t pixel_bytes2 = 0;
3209 /* Guess line buffer size to be 8192 pixels */
3212 if (!rdev->mode_info.mode_config_initialized)
3215 radeon_update_display_priority(rdev);
3217 if (rdev->mode_info.crtcs[0]->base.enabled) {
3218 const struct drm_framebuffer *fb =
3219 rdev->mode_info.crtcs[0]->base.primary->fb;
3221 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3222 pixel_bytes1 = fb->format->cpp[0];
3224 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3225 if (rdev->mode_info.crtcs[1]->base.enabled) {
3226 const struct drm_framebuffer *fb =
3227 rdev->mode_info.crtcs[1]->base.primary->fb;
3229 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3230 pixel_bytes2 = fb->format->cpp[0];
3234 min_mem_eff.full = dfixed_const_8(0);
3236 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3237 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3238 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3239 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3240 /* check crtc enables */
3242 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3244 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3245 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3249 * determine is there is enough bw for current mode
3251 sclk_ff = rdev->pm.sclk;
3252 mclk_ff = rdev->pm.mclk;
3254 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3255 temp_ff.full = dfixed_const(temp);
3256 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3260 peak_disp_bw.full = 0;
3262 temp_ff.full = dfixed_const(1000);
3263 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3264 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3265 temp_ff.full = dfixed_const(pixel_bytes1);
3266 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3269 temp_ff.full = dfixed_const(1000);
3270 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3271 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3272 temp_ff.full = dfixed_const(pixel_bytes2);
3273 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3276 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3277 if (peak_disp_bw.full >= mem_bw.full) {
3278 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3279 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3282 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3283 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3284 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3285 mem_trcd = ((temp >> 2) & 0x3) + 1;
3286 mem_trp = ((temp & 0x3)) + 1;
3287 mem_tras = ((temp & 0x70) >> 4) + 1;
3288 } else if (rdev->family == CHIP_R300 ||
3289 rdev->family == CHIP_R350) { /* r300, r350 */
3290 mem_trcd = (temp & 0x7) + 1;
3291 mem_trp = ((temp >> 8) & 0x7) + 1;
3292 mem_tras = ((temp >> 11) & 0xf) + 4;
3293 } else if (rdev->family == CHIP_RV350 ||
3294 rdev->family == CHIP_RV380) {
3296 mem_trcd = (temp & 0x7) + 3;
3297 mem_trp = ((temp >> 8) & 0x7) + 3;
3298 mem_tras = ((temp >> 11) & 0xf) + 6;
3299 } else if (rdev->family == CHIP_R420 ||
3300 rdev->family == CHIP_R423 ||
3301 rdev->family == CHIP_RV410) {
3303 mem_trcd = (temp & 0xf) + 3;
3306 mem_trp = ((temp >> 8) & 0xf) + 3;
3309 mem_tras = ((temp >> 12) & 0x1f) + 6;
3312 } else { /* RV200, R200 */
3313 mem_trcd = (temp & 0x7) + 1;
3314 mem_trp = ((temp >> 8) & 0x7) + 1;
3315 mem_tras = ((temp >> 12) & 0xf) + 4;
3318 trcd_ff.full = dfixed_const(mem_trcd);
3319 trp_ff.full = dfixed_const(mem_trp);
3320 tras_ff.full = dfixed_const(mem_tras);
3322 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3323 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3324 data = (temp & (7 << 20)) >> 20;
3325 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3326 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3327 tcas_ff = memtcas_rs480_ff[data];
3329 tcas_ff = memtcas_ff[data];
3331 tcas_ff = memtcas2_ff[data];
3333 if (rdev->family == CHIP_RS400 ||
3334 rdev->family == CHIP_RS480) {
3335 /* extra cas latency stored in bits 23-25 0-4 clocks */
3336 data = (temp >> 23) & 0x7;
3338 tcas_ff.full += dfixed_const(data);
3341 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3342 /* on the R300, Tcas is included in Trbs.
3344 temp = RREG32(RADEON_MEM_CNTL);
3345 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3347 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3348 temp = RREG32(R300_MC_IND_INDEX);
3349 temp &= ~R300_MC_IND_ADDR_MASK;
3350 temp |= R300_MC_READ_CNTL_CD_mcind;
3351 WREG32(R300_MC_IND_INDEX, temp);
3352 temp = RREG32(R300_MC_IND_DATA);
3353 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3355 temp = RREG32(R300_MC_READ_CNTL_AB);
3356 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3359 temp = RREG32(R300_MC_READ_CNTL_AB);
3360 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3362 if (rdev->family == CHIP_RV410 ||
3363 rdev->family == CHIP_R420 ||
3364 rdev->family == CHIP_R423)
3365 trbs_ff = memtrbs_r4xx[data];
3367 trbs_ff = memtrbs[data];
3368 tcas_ff.full += trbs_ff.full;
3371 sclk_eff_ff.full = sclk_ff.full;
3373 if (rdev->flags & RADEON_IS_AGP) {
3374 fixed20_12 agpmode_ff;
3375 agpmode_ff.full = dfixed_const(radeon_agpmode);
3376 temp_ff.full = dfixed_const_666(16);
3377 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3379 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3381 if (ASIC_IS_R300(rdev)) {
3382 sclk_delay_ff.full = dfixed_const(250);
3384 if ((rdev->family == CHIP_RV100) ||
3385 rdev->flags & RADEON_IS_IGP) {
3386 if (rdev->mc.vram_is_ddr)
3387 sclk_delay_ff.full = dfixed_const(41);
3389 sclk_delay_ff.full = dfixed_const(33);
3391 if (rdev->mc.vram_width == 128)
3392 sclk_delay_ff.full = dfixed_const(57);
3394 sclk_delay_ff.full = dfixed_const(41);
3398 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3400 if (rdev->mc.vram_is_ddr) {
3401 if (rdev->mc.vram_width == 32) {
3402 k1.full = dfixed_const(40);
3405 k1.full = dfixed_const(20);
3409 k1.full = dfixed_const(40);
3413 temp_ff.full = dfixed_const(2);
3414 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3415 temp_ff.full = dfixed_const(c);
3416 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3417 temp_ff.full = dfixed_const(4);
3418 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3419 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3420 mc_latency_mclk.full += k1.full;
3422 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3423 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3426 HW cursor time assuming worst case of full size colour cursor.
3428 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3429 temp_ff.full += trcd_ff.full;
3430 if (temp_ff.full < tras_ff.full)
3431 temp_ff.full = tras_ff.full;
3432 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3434 temp_ff.full = dfixed_const(cur_size);
3435 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3437 Find the total latency for the display data.
3439 disp_latency_overhead.full = dfixed_const(8);
3440 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3441 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3442 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3444 if (mc_latency_mclk.full > mc_latency_sclk.full)
3445 disp_latency.full = mc_latency_mclk.full;
3447 disp_latency.full = mc_latency_sclk.full;
3449 /* setup Max GRPH_STOP_REQ default value */
3450 if (ASIC_IS_RV100(rdev))
3451 max_stop_req = 0x5c;
3453 max_stop_req = 0x7c;
3457 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3458 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3460 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3462 if (stop_req > max_stop_req)
3463 stop_req = max_stop_req;
3466 Find the drain rate of the display buffer.
3468 temp_ff.full = dfixed_const((16/pixel_bytes1));
3469 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3472 Find the critical point of the display buffer.
3474 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3475 crit_point_ff.full += dfixed_const_half(0);
3477 critical_point = dfixed_trunc(crit_point_ff);
3479 if (rdev->disp_priority == 2) {
3484 The critical point should never be above max_stop_req-4. Setting
3485 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3487 if (max_stop_req - critical_point < 4)
3490 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3491 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3492 critical_point = 0x10;
3495 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3496 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3497 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3498 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3499 if ((rdev->family == CHIP_R350) &&
3500 (stop_req > 0x15)) {
3503 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3504 temp |= RADEON_GRPH_BUFFER_SIZE;
3505 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3506 RADEON_GRPH_CRITICAL_AT_SOF |
3507 RADEON_GRPH_STOP_CNTL);
3509 Write the result into the register.
3511 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3512 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3515 if ((rdev->family == CHIP_RS400) ||
3516 (rdev->family == CHIP_RS480)) {
3517 /* attempt to program RS400 disp regs correctly ??? */
3518 temp = RREG32(RS400_DISP1_REG_CNTL);
3519 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3520 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3521 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3522 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3523 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3524 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3525 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3526 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3527 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3528 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3529 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3533 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3534 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3535 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3540 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3542 if (stop_req > max_stop_req)
3543 stop_req = max_stop_req;
3546 Find the drain rate of the display buffer.
3548 temp_ff.full = dfixed_const((16/pixel_bytes2));
3549 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3551 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3552 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3553 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3554 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3555 if ((rdev->family == CHIP_R350) &&
3556 (stop_req > 0x15)) {
3559 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3560 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3561 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3562 RADEON_GRPH_CRITICAL_AT_SOF |
3563 RADEON_GRPH_STOP_CNTL);
3565 if ((rdev->family == CHIP_RS100) ||
3566 (rdev->family == CHIP_RS200))
3567 critical_point2 = 0;
3569 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3570 temp_ff.full = dfixed_const(temp);
3571 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3572 if (sclk_ff.full < temp_ff.full)
3573 temp_ff.full = sclk_ff.full;
3575 read_return_rate.full = temp_ff.full;
3578 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3579 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3581 time_disp1_drop_priority.full = 0;
3583 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3584 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3585 crit_point_ff.full += dfixed_const_half(0);
3587 critical_point2 = dfixed_trunc(crit_point_ff);
3589 if (rdev->disp_priority == 2) {
3590 critical_point2 = 0;
3593 if (max_stop_req - critical_point2 < 4)
3594 critical_point2 = 0;
3598 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3599 /* some R300 cards have problem with this set to 0 */
3600 critical_point2 = 0x10;
3603 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3604 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3606 if ((rdev->family == CHIP_RS400) ||
3607 (rdev->family == CHIP_RS480)) {
3609 /* attempt to program RS400 disp2 regs correctly ??? */
3610 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3611 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3612 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3613 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3614 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3615 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3616 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3617 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3618 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3619 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3620 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3621 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3623 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3624 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3625 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3626 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3629 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3630 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3633 /* Save number of lines the linebuffer leads before the scanout */
3635 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3638 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3641 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3648 r = radeon_scratch_get(rdev, &scratch);
3650 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3653 WREG32(scratch, 0xCAFEDEAD);
3654 r = radeon_ring_lock(rdev, ring, 2);
3656 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3657 radeon_scratch_free(rdev, scratch);
3660 radeon_ring_write(ring, PACKET0(scratch, 0));
3661 radeon_ring_write(ring, 0xDEADBEEF);
3662 radeon_ring_unlock_commit(rdev, ring, false);
3663 for (i = 0; i < rdev->usec_timeout; i++) {
3664 tmp = RREG32(scratch);
3665 if (tmp == 0xDEADBEEF) {
3670 if (i < rdev->usec_timeout) {
3671 DRM_INFO("ring test succeeded in %d usecs\n", i);
3673 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3677 radeon_scratch_free(rdev, scratch);
3681 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3683 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3685 if (ring->rptr_save_reg) {
3686 u32 next_rptr = ring->wptr + 2 + 3;
3687 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3688 radeon_ring_write(ring, next_rptr);
3691 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3692 radeon_ring_write(ring, ib->gpu_addr);
3693 radeon_ring_write(ring, ib->length_dw);
3696 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3698 struct radeon_ib ib;
3704 r = radeon_scratch_get(rdev, &scratch);
3706 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3709 WREG32(scratch, 0xCAFEDEAD);
3710 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3712 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3715 ib.ptr[0] = PACKET0(scratch, 0);
3716 ib.ptr[1] = 0xDEADBEEF;
3717 ib.ptr[2] = PACKET2(0);
3718 ib.ptr[3] = PACKET2(0);
3719 ib.ptr[4] = PACKET2(0);
3720 ib.ptr[5] = PACKET2(0);
3721 ib.ptr[6] = PACKET2(0);
3722 ib.ptr[7] = PACKET2(0);
3724 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3726 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3729 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3730 RADEON_USEC_IB_TEST_TIMEOUT));
3732 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3734 } else if (r == 0) {
3735 DRM_ERROR("radeon: fence wait timed out.\n");
3740 for (i = 0; i < rdev->usec_timeout; i++) {
3741 tmp = RREG32(scratch);
3742 if (tmp == 0xDEADBEEF) {
3747 if (i < rdev->usec_timeout) {
3748 DRM_INFO("ib test succeeded in %u usecs\n", i);
3750 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3755 radeon_ib_free(rdev, &ib);
3757 radeon_scratch_free(rdev, scratch);
3761 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3763 /* Shutdown CP we shouldn't need to do that but better be safe than
3766 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3767 WREG32(R_000740_CP_CSQ_CNTL, 0);
3769 /* Save few CRTC registers */
3770 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3771 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3772 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3773 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3774 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3775 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3776 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3779 /* Disable VGA aperture access */
3780 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3781 /* Disable cursor, overlay, crtc */
3782 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3783 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3784 S_000054_CRTC_DISPLAY_DIS(1));
3785 WREG32(R_000050_CRTC_GEN_CNTL,
3786 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3787 S_000050_CRTC_DISP_REQ_EN_B(1));
3788 WREG32(R_000420_OV0_SCALE_CNTL,
3789 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3790 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3791 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3792 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3793 S_000360_CUR2_LOCK(1));
3794 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3795 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3796 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3797 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3798 WREG32(R_000360_CUR2_OFFSET,
3799 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3803 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3805 /* Update base address for crtc */
3806 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3807 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3808 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3810 /* Restore CRTC registers */
3811 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3812 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3813 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3814 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3815 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3819 void r100_vga_render_disable(struct radeon_device *rdev)
3823 tmp = RREG8(R_0003C2_GENMO_WT);
3824 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3827 static void r100_mc_program(struct radeon_device *rdev)
3829 struct r100_mc_save save;
3831 /* Stops all mc clients */
3832 r100_mc_stop(rdev, &save);
3833 if (rdev->flags & RADEON_IS_AGP) {
3834 WREG32(R_00014C_MC_AGP_LOCATION,
3835 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3836 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3837 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3838 if (rdev->family > CHIP_RV200)
3839 WREG32(R_00015C_AGP_BASE_2,
3840 upper_32_bits(rdev->mc.agp_base) & 0xff);
3842 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3843 WREG32(R_000170_AGP_BASE, 0);
3844 if (rdev->family > CHIP_RV200)
3845 WREG32(R_00015C_AGP_BASE_2, 0);
3847 /* Wait for mc idle */
3848 if (r100_mc_wait_for_idle(rdev))
3849 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3850 /* Program MC, should be a 32bits limited address space */
3851 WREG32(R_000148_MC_FB_LOCATION,
3852 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3853 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3854 r100_mc_resume(rdev, &save);
3857 static void r100_clock_startup(struct radeon_device *rdev)
3861 if (radeon_dynclks != -1 && radeon_dynclks)
3862 radeon_legacy_set_clock_gating(rdev, 1);
3863 /* We need to force on some of the block */
3864 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3865 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3866 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3867 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3868 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3871 static int r100_startup(struct radeon_device *rdev)
3875 /* set common regs */
3876 r100_set_common_regs(rdev);
3878 r100_mc_program(rdev);
3880 r100_clock_startup(rdev);
3881 /* Initialize GART (initialize after TTM so we can allocate
3882 * memory through TTM but finalize after TTM) */
3883 r100_enable_bm(rdev);
3884 if (rdev->flags & RADEON_IS_PCI) {
3885 r = r100_pci_gart_enable(rdev);
3890 /* allocate wb buffer */
3891 r = radeon_wb_init(rdev);
3895 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3897 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3902 if (!rdev->irq.installed) {
3903 r = radeon_irq_kms_init(rdev);
3909 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3910 /* 1M ring buffer */
3911 r = r100_cp_init(rdev, 1024 * 1024);
3913 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3917 r = radeon_ib_pool_init(rdev);
3919 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3926 int r100_resume(struct radeon_device *rdev)
3930 /* Make sur GART are not working */
3931 if (rdev->flags & RADEON_IS_PCI)
3932 r100_pci_gart_disable(rdev);
3933 /* Resume clock before doing reset */
3934 r100_clock_startup(rdev);
3935 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3936 if (radeon_asic_reset(rdev)) {
3937 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3938 RREG32(R_000E40_RBBM_STATUS),
3939 RREG32(R_0007C0_CP_STAT));
3942 radeon_combios_asic_init(rdev->ddev);
3943 /* Resume clock after posting */
3944 r100_clock_startup(rdev);
3945 /* Initialize surface registers */
3946 radeon_surface_init(rdev);
3948 rdev->accel_working = true;
3949 r = r100_startup(rdev);
3951 rdev->accel_working = false;
3956 int r100_suspend(struct radeon_device *rdev)
3958 radeon_pm_suspend(rdev);
3959 r100_cp_disable(rdev);
3960 radeon_wb_disable(rdev);
3961 r100_irq_disable(rdev);
3962 if (rdev->flags & RADEON_IS_PCI)
3963 r100_pci_gart_disable(rdev);
3967 void r100_fini(struct radeon_device *rdev)
3969 radeon_pm_fini(rdev);
3971 radeon_wb_fini(rdev);
3972 radeon_ib_pool_fini(rdev);
3973 radeon_gem_fini(rdev);
3974 if (rdev->flags & RADEON_IS_PCI)
3975 r100_pci_gart_fini(rdev);
3976 radeon_agp_fini(rdev);
3977 radeon_irq_kms_fini(rdev);
3978 radeon_fence_driver_fini(rdev);
3979 radeon_bo_fini(rdev);
3980 radeon_atombios_fini(rdev);
3986 * Due to how kexec works, it can leave the hw fully initialised when it
3987 * boots the new kernel. However doing our init sequence with the CP and
3988 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3989 * do some quick sanity checks and restore sane values to avoid this
3992 void r100_restore_sanity(struct radeon_device *rdev)
3996 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3998 WREG32(RADEON_CP_CSQ_CNTL, 0);
4000 tmp = RREG32(RADEON_CP_RB_CNTL);
4002 WREG32(RADEON_CP_RB_CNTL, 0);
4004 tmp = RREG32(RADEON_SCRATCH_UMSK);
4006 WREG32(RADEON_SCRATCH_UMSK, 0);
4010 int r100_init(struct radeon_device *rdev)
4014 /* Register debugfs file specific to this group of asics */
4015 r100_debugfs_mc_info_init(rdev);
4017 r100_vga_render_disable(rdev);
4018 /* Initialize scratch registers */
4019 radeon_scratch_init(rdev);
4020 /* Initialize surface registers */
4021 radeon_surface_init(rdev);
4022 /* sanity check some register to avoid hangs like after kexec */
4023 r100_restore_sanity(rdev);
4024 /* TODO: disable VGA need to use VGA request */
4026 if (!radeon_get_bios(rdev)) {
4027 if (ASIC_IS_AVIVO(rdev))
4030 if (rdev->is_atom_bios) {
4031 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4034 r = radeon_combios_init(rdev);
4038 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4039 if (radeon_asic_reset(rdev)) {
4041 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4042 RREG32(R_000E40_RBBM_STATUS),
4043 RREG32(R_0007C0_CP_STAT));
4045 /* check if cards are posted or not */
4046 if (radeon_boot_test_post_card(rdev) == false)
4048 /* Set asic errata */
4050 /* Initialize clocks */
4051 radeon_get_clock_info(rdev->ddev);
4052 /* initialize AGP */
4053 if (rdev->flags & RADEON_IS_AGP) {
4054 r = radeon_agp_init(rdev);
4056 radeon_agp_disable(rdev);
4059 /* initialize VRAM */
4062 radeon_fence_driver_init(rdev);
4063 /* Memory manager */
4064 r = radeon_bo_init(rdev);
4067 if (rdev->flags & RADEON_IS_PCI) {
4068 r = r100_pci_gart_init(rdev);
4072 r100_set_safe_registers(rdev);
4074 /* Initialize power management */
4075 radeon_pm_init(rdev);
4077 rdev->accel_working = true;
4078 r = r100_startup(rdev);
4080 /* Somethings want wront with the accel init stop accel */
4081 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4083 radeon_wb_fini(rdev);
4084 radeon_ib_pool_fini(rdev);
4085 radeon_irq_kms_fini(rdev);
4086 if (rdev->flags & RADEON_IS_PCI)
4087 r100_pci_gart_fini(rdev);
4088 rdev->accel_working = false;
4093 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4095 unsigned long flags;
4098 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4099 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4100 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4101 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4105 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4107 unsigned long flags;
4109 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4110 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4111 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4112 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4115 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4117 if (reg < rdev->rio_mem_size)
4118 return ioread32(rdev->rio_mem + reg);
4120 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4121 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4125 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4127 if (reg < rdev->rio_mem_size)
4128 iowrite32(v, rdev->rio_mem + reg);
4130 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4131 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);