drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r100d.h"
  36 #include "rs100d.h"
  37 #include "rv200d.h"
  38 #include "rv250d.h"
  39 #include "atom.h"
  40
  41 #include <linux/firmware.h>
  42 #include <linux/module.h>
  43
  44 #include "r100_reg_safe.h"
  45 #include "rn50_reg_safe.h"
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_R200           "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_R300           "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_R420           "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_RS690          "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_RS600          "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_R520           "/*(DEBLOBBED)*/"
  55
  56 /*(DEBLOBBED)*/
  57
  58 #include "r100_track.h"
  59
  60 /* This files gather functions specifics to:
  61  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  62  * and others in some cases.
  63  */
  64
  65 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  66 {
  67         if (crtc == 0) {
  68                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  69                         return true;
  70                 else
  71                         return false;
  72         } else {
  73                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  74                         return true;
  75                 else
  76                         return false;
  77         }
  78 }
  79
  80 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  81 {
  82         u32 vline1, vline2;
  83
  84         if (crtc == 0) {
  85                 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  86                 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  87         } else {
  88                 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  89                 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  90         }
  91         if (vline1 != vline2)
  92                 return true;
  93         else
  94                 return false;
  95 }
  96
  97 /**
  98  * r100_wait_for_vblank - vblank wait asic callback.
  99  *
 100  * @rdev: radeon_device pointer
 101  * @crtc: crtc to wait for vblank on
 102  *
 103  * Wait for vblank on the requested crtc (r1xx-r4xx).
 104  */
 105 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 106 {
 107         unsigned i = 0;
 108
 109         if (crtc >= rdev->num_crtc)
 110                 return;
 111
 112         if (crtc == 0) {
 113                 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
 114                         return;
 115         } else {
 116                 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
 117                         return;
 118         }
 119
 120         /* depending on when we hit vblank, we may be close to active; if so,
 121          * wait for another frame.
 122          */
 123         while (r100_is_in_vblank(rdev, crtc)) {
 124                 if (i++ % 100 == 0) {
 125                         if (!r100_is_counter_moving(rdev, crtc))
 126                                 break;
 127                 }
 128         }
 129
 130         while (!r100_is_in_vblank(rdev, crtc)) {
 131                 if (i++ % 100 == 0) {
 132                         if (!r100_is_counter_moving(rdev, crtc))
 133                                 break;
 134                 }
 135         }
 136 }
 137
 138 /**
 139  * r100_page_flip - pageflip callback.
 140  *
 141  * @rdev: radeon_device pointer
 142  * @crtc_id: crtc to cleanup pageflip on
 143  * @crtc_base: new address of the crtc (GPU MC address)
 144  *
 145  * Does the actual pageflip (r1xx-r4xx).
 146  * During vblank we take the crtc lock and wait for the update_pending
 147  * bit to go high, when it does, we release the lock, and allow the
 148  * double buffered update to take place.
 149  */
 150 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 151 {
 152         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 153         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 154         int i;
 155
 156         /* Lock the graphics update lock */
 157         /* update the scanout addresses */
 158         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 159
 160         /* Wait for update_pending to go high. */
 161         for (i = 0; i < rdev->usec_timeout; i++) {
 162                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 163                         break;
 164                 udelay(1);
 165         }
 166         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 167
 168         /* Unlock the lock, so double-buffering can take place inside vblank */
 169         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 170         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 171
 172 }
 173
 174 /**
 175  * r100_page_flip_pending - check if page flip is still pending
 176  *
 177  * @rdev: radeon_device pointer
 178  * @crtc_id: crtc to check
 179  *
 180  * Check if the last pagefilp is still pending (r1xx-r4xx).
 181  * Returns the current update pending status.
 182  */
 183 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 184 {
 185         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 186
 187         /* Return current update_pending status: */
 188         return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
 189                 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
 190 }
 191
 192 /**
 193  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 194  *
 195  * @rdev: radeon_device pointer
 196  *
 197  * Look up the optimal power state based on the
 198  * current state of the GPU (r1xx-r5xx).
 199  * Used for dynpm only.
 200  */
 201 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 202 {
 203         int i;
 204         rdev->pm.dynpm_can_upclock = true;
 205         rdev->pm.dynpm_can_downclock = true;
 206
 207         switch (rdev->pm.dynpm_planned_action) {
 208         case DYNPM_ACTION_MINIMUM:
 209                 rdev->pm.requested_power_state_index = 0;
 210                 rdev->pm.dynpm_can_downclock = false;
 211                 break;
 212         case DYNPM_ACTION_DOWNCLOCK:
 213                 if (rdev->pm.current_power_state_index == 0) {
 214                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 215                         rdev->pm.dynpm_can_downclock = false;
 216                 } else {
 217                         if (rdev->pm.active_crtc_count > 1) {
 218                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 219                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 220                                                 continue;
 221                                         else if (i >= rdev->pm.current_power_state_index) {
 222                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 223                                                 break;
 224                                         } else {
 225                                                 rdev->pm.requested_power_state_index = i;
 226                                                 break;
 227                                         }
 228                                 }
 229                         } else
 230                                 rdev->pm.requested_power_state_index =
 231                                         rdev->pm.current_power_state_index - 1;
 232                 }
 233                 /* don't use the power state if crtcs are active and no display flag is set */
 234                 if ((rdev->pm.active_crtc_count > 0) &&
 235                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 236                      RADEON_PM_MODE_NO_DISPLAY)) {
 237                         rdev->pm.requested_power_state_index++;
 238                 }
 239                 break;
 240         case DYNPM_ACTION_UPCLOCK:
 241                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 242                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 243                         rdev->pm.dynpm_can_upclock = false;
 244                 } else {
 245                         if (rdev->pm.active_crtc_count > 1) {
 246                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 247                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 248                                                 continue;
 249                                         else if (i <= rdev->pm.current_power_state_index) {
 250                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 251                                                 break;
 252                                         } else {
 253                                                 rdev->pm.requested_power_state_index = i;
 254                                                 break;
 255                                         }
 256                                 }
 257                         } else
 258                                 rdev->pm.requested_power_state_index =
 259                                         rdev->pm.current_power_state_index + 1;
 260                 }
 261                 break;
 262         case DYNPM_ACTION_DEFAULT:
 263                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 264                 rdev->pm.dynpm_can_upclock = false;
 265                 break;
 266         case DYNPM_ACTION_NONE:
 267         default:
 268                 DRM_ERROR("Requested mode for not defined action\n");
 269                 return;
 270         }
 271         /* only one clock mode per power state */
 272         rdev->pm.requested_clock_mode_index = 0;
 273
 274         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 275                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 276                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 277                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 278                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 279                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 280                   pcie_lanes);
 281 }
 282
 283 /**
 284  * r100_pm_init_profile - Initialize power profiles callback.
 285  *
 286  * @rdev: radeon_device pointer
 287  *
 288  * Initialize the power states used in profile mode
 289  * (r1xx-r3xx).
 290  * Used for profile mode only.
 291  */
 292 void r100_pm_init_profile(struct radeon_device *rdev)
 293 {
 294         /* default */
 295         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 296         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 297         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 298         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 299         /* low sh */
 300         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 301         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 303         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 304         /* mid sh */
 305         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 306         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 308         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 309         /* high sh */
 310         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 311         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 314         /* low mh */
 315         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 316         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 317         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 318         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 319         /* mid mh */
 320         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 321         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 322         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 323         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 324         /* high mh */
 325         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 326         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 327         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 328         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 329 }
 330
 331 /**
 332  * r100_pm_misc - set additional pm hw parameters callback.
 333  *
 334  * @rdev: radeon_device pointer
 335  *
 336  * Set non-clock parameters associated with a power state
 337  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 338  */
 339 void r100_pm_misc(struct radeon_device *rdev)
 340 {
 341         int requested_index = rdev->pm.requested_power_state_index;
 342         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 343         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 344         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 345
 346         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 347                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 348                         tmp = RREG32(voltage->gpio.reg);
 349                         if (voltage->active_high)
 350                                 tmp |= voltage->gpio.mask;
 351                         else
 352                                 tmp &= ~(voltage->gpio.mask);
 353                         WREG32(voltage->gpio.reg, tmp);
 354                         if (voltage->delay)
 355                                 udelay(voltage->delay);
 356                 } else {
 357                         tmp = RREG32(voltage->gpio.reg);
 358                         if (voltage->active_high)
 359                                 tmp &= ~voltage->gpio.mask;
 360                         else
 361                                 tmp |= voltage->gpio.mask;
 362                         WREG32(voltage->gpio.reg, tmp);
 363                         if (voltage->delay)
 364                                 udelay(voltage->delay);
 365                 }
 366         }
 367
 368         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 369         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 370         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 371         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 372         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 373         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 374                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 375                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 376                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 377                 else
 378                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 379                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 380                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 381                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 382                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 383         } else
 384                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 385
 386         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 387                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 388                 if (voltage->delay) {
 389                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 390                         switch (voltage->delay) {
 391                         case 33:
 392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 393                                 break;
 394                         case 66:
 395                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 396                                 break;
 397                         case 99:
 398                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 399                                 break;
 400                         case 132:
 401                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 402                                 break;
 403                         }
 404                 } else
 405                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 406         } else
 407                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 408
 409         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 410                 sclk_cntl &= ~FORCE_HDP;
 411         else
 412                 sclk_cntl |= FORCE_HDP;
 413
 414         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 415         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 416         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 417
 418         /* set pcie lanes */
 419         if ((rdev->flags & RADEON_IS_PCIE) &&
 420             !(rdev->flags & RADEON_IS_IGP) &&
 421             rdev->asic->pm.set_pcie_lanes &&
 422             (ps->pcie_lanes !=
 423              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 424                 radeon_set_pcie_lanes(rdev,
 425                                       ps->pcie_lanes);
 426                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 427         }
 428 }
 429
 430 /**
 431  * r100_pm_prepare - pre-power state change callback.
 432  *
 433  * @rdev: radeon_device pointer
 434  *
 435  * Prepare for a power state change (r1xx-r4xx).
 436  */
 437 void r100_pm_prepare(struct radeon_device *rdev)
 438 {
 439         struct drm_device *ddev = rdev->ddev;
 440         struct drm_crtc *crtc;
 441         struct radeon_crtc *radeon_crtc;
 442         u32 tmp;
 443
 444         /* disable any active CRTCs */
 445         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 446                 radeon_crtc = to_radeon_crtc(crtc);
 447                 if (radeon_crtc->enabled) {
 448                         if (radeon_crtc->crtc_id) {
 449                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 450                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 451                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 452                         } else {
 453                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 454                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 455                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 456                         }
 457                 }
 458         }
 459 }
 460
 461 /**
 462  * r100_pm_finish - post-power state change callback.
 463  *
 464  * @rdev: radeon_device pointer
 465  *
 466  * Clean up after a power state change (r1xx-r4xx).
 467  */
 468 void r100_pm_finish(struct radeon_device *rdev)
 469 {
 470         struct drm_device *ddev = rdev->ddev;
 471         struct drm_crtc *crtc;
 472         struct radeon_crtc *radeon_crtc;
 473         u32 tmp;
 474
 475         /* enable any active CRTCs */
 476         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 477                 radeon_crtc = to_radeon_crtc(crtc);
 478                 if (radeon_crtc->enabled) {
 479                         if (radeon_crtc->crtc_id) {
 480                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 481                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 482                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 483                         } else {
 484                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 485                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 486                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 487                         }
 488                 }
 489         }
 490 }
 491
 492 /**
 493  * r100_gui_idle - gui idle callback.
 494  *
 495  * @rdev: radeon_device pointer
 496  *
 497  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 498  * Returns true if idle, false if not.
 499  */
 500 bool r100_gui_idle(struct radeon_device *rdev)
 501 {
 502         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 503                 return false;
 504         else
 505                 return true;
 506 }
 507
 508 /* hpd for digital panel detect/disconnect */
 509 /**
 510  * r100_hpd_sense - hpd sense callback.
 511  *
 512  * @rdev: radeon_device pointer
 513  * @hpd: hpd (hotplug detect) pin
 514  *
 515  * Checks if a digital monitor is connected (r1xx-r4xx).
 516  * Returns true if connected, false if not connected.
 517  */
 518 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 519 {
 520         bool connected = false;
 521
 522         switch (hpd) {
 523         case RADEON_HPD_1:
 524                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 525                         connected = true;
 526                 break;
 527         case RADEON_HPD_2:
 528                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 529                         connected = true;
 530                 break;
 531         default:
 532                 break;
 533         }
 534         return connected;
 535 }
 536
 537 /**
 538  * r100_hpd_set_polarity - hpd set polarity callback.
 539  *
 540  * @rdev: radeon_device pointer
 541  * @hpd: hpd (hotplug detect) pin
 542  *
 543  * Set the polarity of the hpd pin (r1xx-r4xx).
 544  */
 545 void r100_hpd_set_polarity(struct radeon_device *rdev,
 546                            enum radeon_hpd_id hpd)
 547 {
 548         u32 tmp;
 549         bool connected = r100_hpd_sense(rdev, hpd);
 550
 551         switch (hpd) {
 552         case RADEON_HPD_1:
 553                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 554                 if (connected)
 555                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 556                 else
 557                         tmp |= RADEON_FP_DETECT_INT_POL;
 558                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 559                 break;
 560         case RADEON_HPD_2:
 561                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 562                 if (connected)
 563                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 564                 else
 565                         tmp |= RADEON_FP2_DETECT_INT_POL;
 566                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 567                 break;
 568         default:
 569                 break;
 570         }
 571 }
 572
 573 /**
 574  * r100_hpd_init - hpd setup callback.
 575  *
 576  * @rdev: radeon_device pointer
 577  *
 578  * Setup the hpd pins used by the card (r1xx-r4xx).
 579  * Set the polarity, and enable the hpd interrupts.
 580  */
 581 void r100_hpd_init(struct radeon_device *rdev)
 582 {
 583         struct drm_device *dev = rdev->ddev;
 584         struct drm_connector *connector;
 585         unsigned enable = 0;
 586
 587         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 588                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 589                 enable |= 1 << radeon_connector->hpd.hpd;
 590                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 591         }
 592         radeon_irq_kms_enable_hpd(rdev, enable);
 593 }
 594
 595 /**
 596  * r100_hpd_fini - hpd tear down callback.
 597  *
 598  * @rdev: radeon_device pointer
 599  *
 600  * Tear down the hpd pins used by the card (r1xx-r4xx).
 601  * Disable the hpd interrupts.
 602  */
 603 void r100_hpd_fini(struct radeon_device *rdev)
 604 {
 605         struct drm_device *dev = rdev->ddev;
 606         struct drm_connector *connector;
 607         unsigned disable = 0;
 608
 609         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 610                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 611                 disable |= 1 << radeon_connector->hpd.hpd;
 612         }
 613         radeon_irq_kms_disable_hpd(rdev, disable);
 614 }
 615
 616 /*
 617  * PCI GART
 618  */
 619 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 620 {
 621         /* TODO: can we do somethings here ? */
 622         /* It seems hw only cache one entry so we should discard this
 623          * entry otherwise if first GPU GART read hit this entry it
 624          * could end up in wrong address. */
 625 }
 626
 627 int r100_pci_gart_init(struct radeon_device *rdev)
 628 {
 629         int r;
 630
 631         if (rdev->gart.ptr) {
 632                 WARN(1, "R100 PCI GART already initialized\n");
 633                 return 0;
 634         }
 635         /* Initialize common gart structure */
 636         r = radeon_gart_init(rdev);
 637         if (r)
 638                 return r;
 639         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 640         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 641         rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 642         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 643         return radeon_gart_table_ram_alloc(rdev);
 644 }
 645
 646 int r100_pci_gart_enable(struct radeon_device *rdev)
 647 {
 648         uint32_t tmp;
 649
 650         /* discard memory request outside of configured range */
 651         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 652         WREG32(RADEON_AIC_CNTL, tmp);
 653         /* set address range for PCI address translate */
 654         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 655         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 656         /* set PCI GART page-table base address */
 657         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 658         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 659         WREG32(RADEON_AIC_CNTL, tmp);
 660         r100_pci_gart_tlb_flush(rdev);
 661         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 662                  (unsigned)(rdev->mc.gtt_size >> 20),
 663                  (unsigned long long)rdev->gart.table_addr);
 664         rdev->gart.ready = true;
 665         return 0;
 666 }
 667
 668 void r100_pci_gart_disable(struct radeon_device *rdev)
 669 {
 670         uint32_t tmp;
 671
 672         /* discard memory request outside of configured range */
 673         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 674         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 675         WREG32(RADEON_AIC_LO_ADDR, 0);
 676         WREG32(RADEON_AIC_HI_ADDR, 0);
 677 }
 678
 679 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
 680 {
 681         return addr;
 682 }
 683
 684 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
 685                             uint64_t entry)
 686 {
 687         u32 *gtt = rdev->gart.ptr;
 688         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 689 }
 690
 691 void r100_pci_gart_fini(struct radeon_device *rdev)
 692 {
 693         radeon_gart_fini(rdev);
 694         r100_pci_gart_disable(rdev);
 695         radeon_gart_table_ram_free(rdev);
 696 }
 697
 698 int r100_irq_set(struct radeon_device *rdev)
 699 {
 700         uint32_t tmp = 0;
 701
 702         if (!rdev->irq.installed) {
 703                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 704                 WREG32(R_000040_GEN_INT_CNTL, 0);
 705                 return -EINVAL;
 706         }
 707         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 708                 tmp |= RADEON_SW_INT_ENABLE;
 709         }
 710         if (rdev->irq.crtc_vblank_int[0] ||
 711             atomic_read(&rdev->irq.pflip[0])) {
 712                 tmp |= RADEON_CRTC_VBLANK_MASK;
 713         }
 714         if (rdev->irq.crtc_vblank_int[1] ||
 715             atomic_read(&rdev->irq.pflip[1])) {
 716                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 717         }
 718         if (rdev->irq.hpd[0]) {
 719                 tmp |= RADEON_FP_DETECT_MASK;
 720         }
 721         if (rdev->irq.hpd[1]) {
 722                 tmp |= RADEON_FP2_DETECT_MASK;
 723         }
 724         WREG32(RADEON_GEN_INT_CNTL, tmp);
 725
 726         /* read back to post the write */
 727         RREG32(RADEON_GEN_INT_CNTL);
 728
 729         return 0;
 730 }
 731
 732 void r100_irq_disable(struct radeon_device *rdev)
 733 {
 734         u32 tmp;
 735
 736         WREG32(R_000040_GEN_INT_CNTL, 0);
 737         /* Wait and acknowledge irq */
 738         mdelay(1);
 739         tmp = RREG32(R_000044_GEN_INT_STATUS);
 740         WREG32(R_000044_GEN_INT_STATUS, tmp);
 741 }
 742
 743 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 744 {
 745         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 746         uint32_t irq_mask = RADEON_SW_INT_TEST |
 747                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 748                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 749
 750         if (irqs) {
 751                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 752         }
 753         return irqs & irq_mask;
 754 }
 755
 756 int r100_irq_process(struct radeon_device *rdev)
 757 {
 758         uint32_t status, msi_rearm;
 759         bool queue_hotplug = false;
 760
 761         status = r100_irq_ack(rdev);
 762         if (!status) {
 763                 return IRQ_NONE;
 764         }
 765         if (rdev->shutdown) {
 766                 return IRQ_NONE;
 767         }
 768         while (status) {
 769                 /* SW interrupt */
 770                 if (status & RADEON_SW_INT_TEST) {
 771                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 772                 }
 773                 /* Vertical blank interrupts */
 774                 if (status & RADEON_CRTC_VBLANK_STAT) {
 775                         if (rdev->irq.crtc_vblank_int[0]) {
 776                                 drm_handle_vblank(rdev->ddev, 0);
 777                                 rdev->pm.vblank_sync = true;
 778                                 wake_up(&rdev->irq.vblank_queue);
 779                         }
 780                         if (atomic_read(&rdev->irq.pflip[0]))
 781                                 radeon_crtc_handle_vblank(rdev, 0);
 782                 }
 783                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 784                         if (rdev->irq.crtc_vblank_int[1]) {
 785                                 drm_handle_vblank(rdev->ddev, 1);
 786                                 rdev->pm.vblank_sync = true;
 787                                 wake_up(&rdev->irq.vblank_queue);
 788                         }
 789                         if (atomic_read(&rdev->irq.pflip[1]))
 790                                 radeon_crtc_handle_vblank(rdev, 1);
 791                 }
 792                 if (status & RADEON_FP_DETECT_STAT) {
 793                         queue_hotplug = true;
 794                         DRM_DEBUG("HPD1\n");
 795                 }
 796                 if (status & RADEON_FP2_DETECT_STAT) {
 797                         queue_hotplug = true;
 798                         DRM_DEBUG("HPD2\n");
 799                 }
 800                 status = r100_irq_ack(rdev);
 801         }
 802         if (queue_hotplug)
 803                 schedule_delayed_work(&rdev->hotplug_work, 0);
 804         if (rdev->msi_enabled) {
 805                 switch (rdev->family) {
 806                 case CHIP_RS400:
 807                 case CHIP_RS480:
 808                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 809                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 810                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 811                         break;
 812                 default:
 813                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 814                         break;
 815                 }
 816         }
 817         return IRQ_HANDLED;
 818 }
 819
 820 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 821 {
 822         if (crtc == 0)
 823                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 824         else
 825                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 826 }
 827
 828 /**
 829  * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
 830  * rdev: radeon device structure
 831  * ring: ring buffer struct for emitting packets
 832  */
 833 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
 834 {
 835         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 836         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 837                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 838         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 839         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 840 }
 841
 842 /* Who ever call radeon_fence_emit should call ring_lock and ask
 843  * for enough space (today caller are ib schedule and buffer move) */
 844 void r100_fence_ring_emit(struct radeon_device *rdev,
 845                           struct radeon_fence *fence)
 846 {
 847         struct radeon_ring *ring = &rdev->ring[fence->ring];
 848
 849         /* We have to make sure that caches are flushed before
 850          * CPU might read something from VRAM. */
 851         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 852         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 853         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 854         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 855         /* Wait until IDLE & CLEAN */
 856         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 857         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 858         r100_ring_hdp_flush(rdev, ring);
 859         /* Emit fence sequence & fire IRQ */
 860         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 861         radeon_ring_write(ring, fence->seq);
 862         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 863         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 864 }
 865
 866 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
 867                               struct radeon_ring *ring,
 868                               struct radeon_semaphore *semaphore,
 869                               bool emit_wait)
 870 {
 871         /* Unused on older asics, since we don't have semaphores or multiple rings */
 872         BUG();
 873         return false;
 874 }
 875
 876 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
 877                                     uint64_t src_offset,
 878                                     uint64_t dst_offset,
 879                                     unsigned num_gpu_pages,
 880                                     struct reservation_object *resv)
 881 {
 882         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 883         struct radeon_fence *fence;
 884         uint32_t cur_pages;
 885         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 886         uint32_t pitch;
 887         uint32_t stride_pixels;
 888         unsigned ndw;
 889         int num_loops;
 890         int r = 0;
 891
 892         /* radeon limited to 16k stride */
 893         stride_bytes &= 0x3fff;
 894         /* radeon pitch is /64 */
 895         pitch = stride_bytes / 64;
 896         stride_pixels = stride_bytes / 4;
 897         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 898
 899         /* Ask for enough room for blit + flush + fence */
 900         ndw = 64 + (10 * num_loops);
 901         r = radeon_ring_lock(rdev, ring, ndw);
 902         if (r) {
 903                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 904                 return ERR_PTR(-EINVAL);
 905         }
 906         while (num_gpu_pages > 0) {
 907                 cur_pages = num_gpu_pages;
 908                 if (cur_pages > 8191) {
 909                         cur_pages = 8191;
 910                 }
 911                 num_gpu_pages -= cur_pages;
 912
 913                 /* pages are in Y direction - height
 914                    page width in X direction - width */
 915                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 916                 radeon_ring_write(ring,
 917                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 918                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 919                                   RADEON_GMC_SRC_CLIPPING |
 920                                   RADEON_GMC_DST_CLIPPING |
 921                                   RADEON_GMC_BRUSH_NONE |
 922                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 923                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 924                                   RADEON_ROP3_S |
 925                                   RADEON_DP_SRC_SOURCE_MEMORY |
 926                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 927                                   RADEON_GMC_WR_MSK_DIS);
 928                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 929                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 930                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 931                 radeon_ring_write(ring, 0);
 932                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 933                 radeon_ring_write(ring, num_gpu_pages);
 934                 radeon_ring_write(ring, num_gpu_pages);
 935                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 936         }
 937         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 938         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 939         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 940         radeon_ring_write(ring,
 941                           RADEON_WAIT_2D_IDLECLEAN |
 942                           RADEON_WAIT_HOST_IDLECLEAN |
 943                           RADEON_WAIT_DMA_GUI_IDLE);
 944         r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
 945         if (r) {
 946                 radeon_ring_unlock_undo(rdev, ring);
 947                 return ERR_PTR(r);
 948         }
 949         radeon_ring_unlock_commit(rdev, ring, false);
 950         return fence;
 951 }
 952
 953 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 954 {
 955         unsigned i;
 956         u32 tmp;
 957
 958         for (i = 0; i < rdev->usec_timeout; i++) {
 959                 tmp = RREG32(R_000E40_RBBM_STATUS);
 960                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 961                         return 0;
 962                 }
 963                 udelay(1);
 964         }
 965         return -1;
 966 }
 967
 968 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 969 {
 970         int r;
 971
 972         r = radeon_ring_lock(rdev, ring, 2);
 973         if (r) {
 974                 return;
 975         }
 976         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 977         radeon_ring_write(ring,
 978                           RADEON_ISYNC_ANY2D_IDLE3D |
 979                           RADEON_ISYNC_ANY3D_IDLE2D |
 980                           RADEON_ISYNC_WAIT_IDLEGUI |
 981                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 982         radeon_ring_unlock_commit(rdev, ring, false);
 983 }
 984
 985
 986 /* Load the microcode for the CP */
 987 static int r100_cp_init_microcode(struct radeon_device *rdev)
 988 {
 989         const char *fw_name = NULL;
 990         int err;
 991
 992         DRM_DEBUG_KMS("\n");
 993
 994         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 995             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 996             (rdev->family == CHIP_RS200)) {
 997                 DRM_INFO("Loading R100 Microcode\n");
 998                 fw_name = FIRMWARE_R100;
 999         } else if ((rdev->family == CHIP_R200) ||
1000                    (rdev->family == CHIP_RV250) ||
1001                    (rdev->family == CHIP_RV280) ||
1002                    (rdev->family == CHIP_RS300)) {
1003                 DRM_INFO("Loading R200 Microcode\n");
1004                 fw_name = FIRMWARE_R200;
1005         } else if ((rdev->family == CHIP_R300) ||
1006                    (rdev->family == CHIP_R350) ||
1007                    (rdev->family == CHIP_RV350) ||
1008                    (rdev->family == CHIP_RV380) ||
1009                    (rdev->family == CHIP_RS400) ||
1010                    (rdev->family == CHIP_RS480)) {
1011                 DRM_INFO("Loading R300 Microcode\n");
1012                 fw_name = FIRMWARE_R300;
1013         } else if ((rdev->family == CHIP_R420) ||
1014                    (rdev->family == CHIP_R423) ||
1015                    (rdev->family == CHIP_RV410)) {
1016                 DRM_INFO("Loading R400 Microcode\n");
1017                 fw_name = FIRMWARE_R420;
1018         } else if ((rdev->family == CHIP_RS690) ||
1019                    (rdev->family == CHIP_RS740)) {
1020                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1021                 fw_name = FIRMWARE_RS690;
1022         } else if (rdev->family == CHIP_RS600) {
1023                 DRM_INFO("Loading RS600 Microcode\n");
1024                 fw_name = FIRMWARE_RS600;
1025         } else if ((rdev->family == CHIP_RV515) ||
1026                    (rdev->family == CHIP_R520) ||
1027                    (rdev->family == CHIP_RV530) ||
1028                    (rdev->family == CHIP_R580) ||
1029                    (rdev->family == CHIP_RV560) ||
1030                    (rdev->family == CHIP_RV570)) {
1031                 DRM_INFO("Loading R500 Microcode\n");
1032                 fw_name = FIRMWARE_R520;
1033         }
1034
1035         err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
1036         if (err) {
1037                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1038                        fw_name);
1039         } else if (rdev->me_fw->size % 8) {
1040                 printk(KERN_ERR
1041                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1042                        rdev->me_fw->size, fw_name);
1043                 err = -EINVAL;
1044                 release_firmware(rdev->me_fw);
1045                 rdev->me_fw = NULL;
1046         }
1047         return err;
1048 }
1049
1050 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1051                       struct radeon_ring *ring)
1052 {
1053         u32 rptr;
1054
1055         if (rdev->wb.enabled)
1056                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1057         else
1058                 rptr = RREG32(RADEON_CP_RB_RPTR);
1059
1060         return rptr;
1061 }
1062
1063 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1064                       struct radeon_ring *ring)
1065 {
1066         u32 wptr;
1067
1068         wptr = RREG32(RADEON_CP_RB_WPTR);
1069
1070         return wptr;
1071 }
1072
1073 void r100_gfx_set_wptr(struct radeon_device *rdev,
1074                        struct radeon_ring *ring)
1075 {
1076         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1077         (void)RREG32(RADEON_CP_RB_WPTR);
1078 }
1079
1080 static void r100_cp_load_microcode(struct radeon_device *rdev)
1081 {
1082         const __be32 *fw_data;
1083         int i, size;
1084
1085         if (r100_gui_wait_for_idle(rdev)) {
1086                 printk(KERN_WARNING "Failed to wait GUI idle while "
1087                        "programming pipes. Bad things might happen.\n");
1088         }
1089
1090         if (rdev->me_fw) {
1091                 size = rdev->me_fw->size / 4;
1092                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1093                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1094                 for (i = 0; i < size; i += 2) {
1095                         WREG32(RADEON_CP_ME_RAM_DATAH,
1096                                be32_to_cpup(&fw_data[i]));
1097                         WREG32(RADEON_CP_ME_RAM_DATAL,
1098                                be32_to_cpup(&fw_data[i + 1]));
1099                 }
1100         }
1101 }
1102
1103 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1104 {
1105         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1106         unsigned rb_bufsz;
1107         unsigned rb_blksz;
1108         unsigned max_fetch;
1109         unsigned pre_write_timer;
1110         unsigned pre_write_limit;
1111         unsigned indirect2_start;
1112         unsigned indirect1_start;
1113         uint32_t tmp;
1114         int r;
1115
1116         if (r100_debugfs_cp_init(rdev)) {
1117                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1118         }
1119         if (!rdev->me_fw) {
1120                 r = r100_cp_init_microcode(rdev);
1121                 if (r) {
1122                         DRM_ERROR("Failed to load firmware!\n");
1123                         return r;
1124                 }
1125         }
1126
1127         /* Align ring size */
1128         rb_bufsz = order_base_2(ring_size / 8);
1129         ring_size = (1 << (rb_bufsz + 1)) * 4;
1130         r100_cp_load_microcode(rdev);
1131         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1132                              RADEON_CP_PACKET2);
1133         if (r) {
1134                 return r;
1135         }
1136         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1137          * the rptr copy in system ram */
1138         rb_blksz = 9;
1139         /* cp will read 128bytes at a time (4 dwords) */
1140         max_fetch = 1;
1141         ring->align_mask = 16 - 1;
1142         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1143         pre_write_timer = 64;
1144         /* Force CP_RB_WPTR write if written more than one time before the
1145          * delay expire
1146          */
1147         pre_write_limit = 0;
1148         /* Setup the cp cache like this (cache size is 96 dwords) :
1149          *      RING            0  to 15
1150          *      INDIRECT1       16 to 79
1151          *      INDIRECT2       80 to 95
1152          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1153          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1154          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1155          * Idea being that most of the gpu cmd will be through indirect1 buffer
1156          * so it gets the bigger cache.
1157          */
1158         indirect2_start = 80;
1159         indirect1_start = 16;
1160         /* cp setup */
1161         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1162         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1163                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1164                REG_SET(RADEON_MAX_FETCH, max_fetch));
1165 #ifdef __BIG_ENDIAN
1166         tmp |= RADEON_BUF_SWAP_32BIT;
1167 #endif
1168         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1169
1170         /* Set ring address */
1171         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1172         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1173         /* Force read & write ptr to 0 */
1174         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1175         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1176         ring->wptr = 0;
1177         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1178
1179         /* set the wb address whether it's enabled or not */
1180         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1181                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1182         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1183
1184         if (rdev->wb.enabled)
1185                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1186         else {
1187                 tmp |= RADEON_RB_NO_UPDATE;
1188                 WREG32(R_000770_SCRATCH_UMSK, 0);
1189         }
1190
1191         WREG32(RADEON_CP_RB_CNTL, tmp);
1192         udelay(10);
1193         /* Set cp mode to bus mastering & enable cp*/
1194         WREG32(RADEON_CP_CSQ_MODE,
1195                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1196                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1197         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1198         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1199         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1200
1201         /* at this point everything should be setup correctly to enable master */
1202         pci_set_master(rdev->pdev);
1203
1204         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1205         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1206         if (r) {
1207                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1208                 return r;
1209         }
1210         ring->ready = true;
1211         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1212
1213         if (!ring->rptr_save_reg /* not resuming from suspend */
1214             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1215                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1216                 if (r) {
1217                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1218                         ring->rptr_save_reg = 0;
1219                 }
1220         }
1221         return 0;
1222 }
1223
1224 void r100_cp_fini(struct radeon_device *rdev)
1225 {
1226         if (r100_cp_wait_for_idle(rdev)) {
1227                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1228         }
1229         /* Disable ring */
1230         r100_cp_disable(rdev);
1231         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1232         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1233         DRM_INFO("radeon: cp finalized\n");
1234 }
1235
1236 void r100_cp_disable(struct radeon_device *rdev)
1237 {
1238         /* Disable ring */
1239         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1240         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1241         WREG32(RADEON_CP_CSQ_MODE, 0);
1242         WREG32(RADEON_CP_CSQ_CNTL, 0);
1243         WREG32(R_000770_SCRATCH_UMSK, 0);
1244         if (r100_gui_wait_for_idle(rdev)) {
1245                 printk(KERN_WARNING "Failed to wait GUI idle while "
1246                        "programming pipes. Bad things might happen.\n");
1247         }
1248 }
1249
1250 /*
1251  * CS functions
1252  */
1253 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1254                             struct radeon_cs_packet *pkt,
1255                             unsigned idx,
1256                             unsigned reg)
1257 {
1258         int r;
1259         u32 tile_flags = 0;
1260         u32 tmp;
1261         struct radeon_bo_list *reloc;
1262         u32 value;
1263
1264         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1265         if (r) {
1266                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1267                           idx, reg);
1268                 radeon_cs_dump_packet(p, pkt);
1269                 return r;
1270         }
1271
1272         value = radeon_get_ib_value(p, idx);
1273         tmp = value & 0x003fffff;
1274         tmp += (((u32)reloc->gpu_offset) >> 10);
1275
1276         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1277                 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1278                         tile_flags |= RADEON_DST_TILE_MACRO;
1279                 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1280                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1281                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1282                                 radeon_cs_dump_packet(p, pkt);
1283                                 return -EINVAL;
1284                         }
1285                         tile_flags |= RADEON_DST_TILE_MICRO;
1286                 }
1287
1288                 tmp |= tile_flags;
1289                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1290         } else
1291                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1292         return 0;
1293 }
1294
1295 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1296                              struct radeon_cs_packet *pkt,
1297                              int idx)
1298 {
1299         unsigned c, i;
1300         struct radeon_bo_list *reloc;
1301         struct r100_cs_track *track;
1302         int r = 0;
1303         volatile uint32_t *ib;
1304         u32 idx_value;
1305
1306         ib = p->ib.ptr;
1307         track = (struct r100_cs_track *)p->track;
1308         c = radeon_get_ib_value(p, idx++) & 0x1F;
1309         if (c > 16) {
1310             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1311                       pkt->opcode);
1312             radeon_cs_dump_packet(p, pkt);
1313             return -EINVAL;
1314         }
1315         track->num_arrays = c;
1316         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1317                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1318                 if (r) {
1319                         DRM_ERROR("No reloc for packet3 %d\n",
1320                                   pkt->opcode);
1321                         radeon_cs_dump_packet(p, pkt);
1322                         return r;
1323                 }
1324                 idx_value = radeon_get_ib_value(p, idx);
1325                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1326
1327                 track->arrays[i + 0].esize = idx_value >> 8;
1328                 track->arrays[i + 0].robj = reloc->robj;
1329                 track->arrays[i + 0].esize &= 0x7F;
1330                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1331                 if (r) {
1332                         DRM_ERROR("No reloc for packet3 %d\n",
1333                                   pkt->opcode);
1334                         radeon_cs_dump_packet(p, pkt);
1335                         return r;
1336                 }
1337                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1338                 track->arrays[i + 1].robj = reloc->robj;
1339                 track->arrays[i + 1].esize = idx_value >> 24;
1340                 track->arrays[i + 1].esize &= 0x7F;
1341         }
1342         if (c & 1) {
1343                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1344                 if (r) {
1345                         DRM_ERROR("No reloc for packet3 %d\n",
1346                                           pkt->opcode);
1347                         radeon_cs_dump_packet(p, pkt);
1348                         return r;
1349                 }
1350                 idx_value = radeon_get_ib_value(p, idx);
1351                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1352                 track->arrays[i + 0].robj = reloc->robj;
1353                 track->arrays[i + 0].esize = idx_value >> 8;
1354                 track->arrays[i + 0].esize &= 0x7F;
1355         }
1356         return r;
1357 }
1358
1359 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1360                           struct radeon_cs_packet *pkt,
1361                           const unsigned *auth, unsigned n,
1362                           radeon_packet0_check_t check)
1363 {
1364         unsigned reg;
1365         unsigned i, j, m;
1366         unsigned idx;
1367         int r;
1368
1369         idx = pkt->idx + 1;
1370         reg = pkt->reg;
1371         /* Check that register fall into register range
1372          * determined by the number of entry (n) in the
1373          * safe register bitmap.
1374          */
1375         if (pkt->one_reg_wr) {
1376                 if ((reg >> 7) > n) {
1377                         return -EINVAL;
1378                 }
1379         } else {
1380                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1381                         return -EINVAL;
1382                 }
1383         }
1384         for (i = 0; i <= pkt->count; i++, idx++) {
1385                 j = (reg >> 7);
1386                 m = 1 << ((reg >> 2) & 31);
1387                 if (auth[j] & m) {
1388                         r = check(p, pkt, idx, reg);
1389                         if (r) {
1390                                 return r;
1391                         }
1392                 }
1393                 if (pkt->one_reg_wr) {
1394                         if (!(auth[j] & m)) {
1395                                 break;
1396                         }
1397                 } else {
1398                         reg += 4;
1399                 }
1400         }
1401         return 0;
1402 }
1403
1404 /**
1405  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1406  * @parser:             parser structure holding parsing context.
1407  *
1408  * Userspace sends a special sequence for VLINE waits.
1409  * PACKET0 - VLINE_START_END + value
1410  * PACKET0 - WAIT_UNTIL +_value
1411  * RELOC (P3) - crtc_id in reloc.
1412  *
1413  * This function parses this and relocates the VLINE START END
1414  * and WAIT UNTIL packets to the correct crtc.
1415  * It also detects a switched off crtc and nulls out the
1416  * wait in that case.
1417  */
1418 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1419 {
1420         struct drm_crtc *crtc;
1421         struct radeon_crtc *radeon_crtc;
1422         struct radeon_cs_packet p3reloc, waitreloc;
1423         int crtc_id;
1424         int r;
1425         uint32_t header, h_idx, reg;
1426         volatile uint32_t *ib;
1427
1428         ib = p->ib.ptr;
1429
1430         /* parse the wait until */
1431         r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1432         if (r)
1433                 return r;
1434
1435         /* check its a wait until and only 1 count */
1436         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1437             waitreloc.count != 0) {
1438                 DRM_ERROR("vline wait had illegal wait until segment\n");
1439                 return -EINVAL;
1440         }
1441
1442         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1443                 DRM_ERROR("vline wait had illegal wait until\n");
1444                 return -EINVAL;
1445         }
1446
1447         /* jump over the NOP */
1448         r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1449         if (r)
1450                 return r;
1451
1452         h_idx = p->idx - 2;
1453         p->idx += waitreloc.count + 2;
1454         p->idx += p3reloc.count + 2;
1455
1456         header = radeon_get_ib_value(p, h_idx);
1457         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1458         reg = R100_CP_PACKET0_GET_REG(header);
1459         crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1460         if (!crtc) {
1461                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1462                 return -ENOENT;
1463         }
1464         radeon_crtc = to_radeon_crtc(crtc);
1465         crtc_id = radeon_crtc->crtc_id;
1466
1467         if (!crtc->enabled) {
1468                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1469                 ib[h_idx + 2] = PACKET2(0);
1470                 ib[h_idx + 3] = PACKET2(0);
1471         } else if (crtc_id == 1) {
1472                 switch (reg) {
1473                 case AVIVO_D1MODE_VLINE_START_END:
1474                         header &= ~R300_CP_PACKET0_REG_MASK;
1475                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1476                         break;
1477                 case RADEON_CRTC_GUI_TRIG_VLINE:
1478                         header &= ~R300_CP_PACKET0_REG_MASK;
1479                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1480                         break;
1481                 default:
1482                         DRM_ERROR("unknown crtc reloc\n");
1483                         return -EINVAL;
1484                 }
1485                 ib[h_idx] = header;
1486                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1487         }
1488
1489         return 0;
1490 }
1491
1492 static int r100_get_vtx_size(uint32_t vtx_fmt)
1493 {
1494         int vtx_size;
1495         vtx_size = 2;
1496         /* ordered according to bits in spec */
1497         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1498                 vtx_size++;
1499         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1500                 vtx_size += 3;
1501         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1502                 vtx_size++;
1503         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1504                 vtx_size++;
1505         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1506                 vtx_size += 3;
1507         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1508                 vtx_size++;
1509         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1510                 vtx_size++;
1511         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1512                 vtx_size += 2;
1513         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1514                 vtx_size += 2;
1515         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1516                 vtx_size++;
1517         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1518                 vtx_size += 2;
1519         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1520                 vtx_size++;
1521         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1522                 vtx_size += 2;
1523         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1524                 vtx_size++;
1525         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1526                 vtx_size++;
1527         /* blend weight */
1528         if (vtx_fmt & (0x7 << 15))
1529                 vtx_size += (vtx_fmt >> 15) & 0x7;
1530         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1531                 vtx_size += 3;
1532         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1533                 vtx_size += 2;
1534         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1535                 vtx_size++;
1536         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1537                 vtx_size++;
1538         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1539                 vtx_size++;
1540         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1541                 vtx_size++;
1542         return vtx_size;
1543 }
1544
1545 static int r100_packet0_check(struct radeon_cs_parser *p,
1546                               struct radeon_cs_packet *pkt,
1547                               unsigned idx, unsigned reg)
1548 {
1549         struct radeon_bo_list *reloc;
1550         struct r100_cs_track *track;
1551         volatile uint32_t *ib;
1552         uint32_t tmp;
1553         int r;
1554         int i, face;
1555         u32 tile_flags = 0;
1556         u32 idx_value;
1557
1558         ib = p->ib.ptr;
1559         track = (struct r100_cs_track *)p->track;
1560
1561         idx_value = radeon_get_ib_value(p, idx);
1562
1563         switch (reg) {
1564         case RADEON_CRTC_GUI_TRIG_VLINE:
1565                 r = r100_cs_packet_parse_vline(p);
1566                 if (r) {
1567                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1568                                   idx, reg);
1569                         radeon_cs_dump_packet(p, pkt);
1570                         return r;
1571                 }
1572                 break;
1573                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1574                  * range access */
1575         case RADEON_DST_PITCH_OFFSET:
1576         case RADEON_SRC_PITCH_OFFSET:
1577                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1578                 if (r)
1579                         return r;
1580                 break;
1581         case RADEON_RB3D_DEPTHOFFSET:
1582                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1583                 if (r) {
1584                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1585                                   idx, reg);
1586                         radeon_cs_dump_packet(p, pkt);
1587                         return r;
1588                 }
1589                 track->zb.robj = reloc->robj;
1590                 track->zb.offset = idx_value;
1591                 track->zb_dirty = true;
1592                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1593                 break;
1594         case RADEON_RB3D_COLOROFFSET:
1595                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1596                 if (r) {
1597                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1598                                   idx, reg);
1599                         radeon_cs_dump_packet(p, pkt);
1600                         return r;
1601                 }
1602                 track->cb[0].robj = reloc->robj;
1603                 track->cb[0].offset = idx_value;
1604                 track->cb_dirty = true;
1605                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1606                 break;
1607         case RADEON_PP_TXOFFSET_0:
1608         case RADEON_PP_TXOFFSET_1:
1609         case RADEON_PP_TXOFFSET_2:
1610                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1611                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1612                 if (r) {
1613                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1614                                   idx, reg);
1615                         radeon_cs_dump_packet(p, pkt);
1616                         return r;
1617                 }
1618                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1619                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1620                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1621                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1622                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1623
1624                         tmp = idx_value & ~(0x7 << 2);
1625                         tmp |= tile_flags;
1626                         ib[idx] = tmp + ((u32)reloc->gpu_offset);
1627                 } else
1628                         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1629                 track->textures[i].robj = reloc->robj;
1630                 track->tex_dirty = true;
1631                 break;
1632         case RADEON_PP_CUBIC_OFFSET_T0_0:
1633         case RADEON_PP_CUBIC_OFFSET_T0_1:
1634         case RADEON_PP_CUBIC_OFFSET_T0_2:
1635         case RADEON_PP_CUBIC_OFFSET_T0_3:
1636         case RADEON_PP_CUBIC_OFFSET_T0_4:
1637                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1638                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1639                 if (r) {
1640                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1641                                   idx, reg);
1642                         radeon_cs_dump_packet(p, pkt);
1643                         return r;
1644                 }
1645                 track->textures[0].cube_info[i].offset = idx_value;
1646                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1647                 track->textures[0].cube_info[i].robj = reloc->robj;
1648                 track->tex_dirty = true;
1649                 break;
1650         case RADEON_PP_CUBIC_OFFSET_T1_0:
1651         case RADEON_PP_CUBIC_OFFSET_T1_1:
1652         case RADEON_PP_CUBIC_OFFSET_T1_2:
1653         case RADEON_PP_CUBIC_OFFSET_T1_3:
1654         case RADEON_PP_CUBIC_OFFSET_T1_4:
1655                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1656                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1657                 if (r) {
1658                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1659                                   idx, reg);
1660                         radeon_cs_dump_packet(p, pkt);
1661                         return r;
1662                 }
1663                 track->textures[1].cube_info[i].offset = idx_value;
1664                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1665                 track->textures[1].cube_info[i].robj = reloc->robj;
1666                 track->tex_dirty = true;
1667                 break;
1668         case RADEON_PP_CUBIC_OFFSET_T2_0:
1669         case RADEON_PP_CUBIC_OFFSET_T2_1:
1670         case RADEON_PP_CUBIC_OFFSET_T2_2:
1671         case RADEON_PP_CUBIC_OFFSET_T2_3:
1672         case RADEON_PP_CUBIC_OFFSET_T2_4:
1673                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1674                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1675                 if (r) {
1676                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1677                                   idx, reg);
1678                         radeon_cs_dump_packet(p, pkt);
1679                         return r;
1680                 }
1681                 track->textures[2].cube_info[i].offset = idx_value;
1682                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1683                 track->textures[2].cube_info[i].robj = reloc->robj;
1684                 track->tex_dirty = true;
1685                 break;
1686         case RADEON_RE_WIDTH_HEIGHT:
1687                 track->maxy = ((idx_value >> 16) & 0x7FF);
1688                 track->cb_dirty = true;
1689                 track->zb_dirty = true;
1690                 break;
1691         case RADEON_RB3D_COLORPITCH:
1692                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1693                 if (r) {
1694                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1695                                   idx, reg);
1696                         radeon_cs_dump_packet(p, pkt);
1697                         return r;
1698                 }
1699                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1700                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1701                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1702                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1703                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1704
1705                         tmp = idx_value & ~(0x7 << 16);
1706                         tmp |= tile_flags;
1707                         ib[idx] = tmp;
1708                 } else
1709                         ib[idx] = idx_value;
1710
1711                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1712                 track->cb_dirty = true;
1713                 break;
1714         case RADEON_RB3D_DEPTHPITCH:
1715                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1716                 track->zb_dirty = true;
1717                 break;
1718         case RADEON_RB3D_CNTL:
1719                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1720                 case 7:
1721                 case 8:
1722                 case 9:
1723                 case 11:
1724                 case 12:
1725                         track->cb[0].cpp = 1;
1726                         break;
1727                 case 3:
1728                 case 4:
1729                 case 15:
1730                         track->cb[0].cpp = 2;
1731                         break;
1732                 case 6:
1733                         track->cb[0].cpp = 4;
1734                         break;
1735                 default:
1736                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1737                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1738                         return -EINVAL;
1739                 }
1740                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1741                 track->cb_dirty = true;
1742                 track->zb_dirty = true;
1743                 break;
1744         case RADEON_RB3D_ZSTENCILCNTL:
1745                 switch (idx_value & 0xf) {
1746                 case 0:
1747                         track->zb.cpp = 2;
1748                         break;
1749                 case 2:
1750                 case 3:
1751                 case 4:
1752                 case 5:
1753                 case 9:
1754                 case 11:
1755                         track->zb.cpp = 4;
1756                         break;
1757                 default:
1758                         break;
1759                 }
1760                 track->zb_dirty = true;
1761                 break;
1762         case RADEON_RB3D_ZPASS_ADDR:
1763                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1764                 if (r) {
1765                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1766                                   idx, reg);
1767                         radeon_cs_dump_packet(p, pkt);
1768                         return r;
1769                 }
1770                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1771                 break;
1772         case RADEON_PP_CNTL:
1773                 {
1774                         uint32_t temp = idx_value >> 4;
1775                         for (i = 0; i < track->num_texture; i++)
1776                                 track->textures[i].enabled = !!(temp & (1 << i));
1777                         track->tex_dirty = true;
1778                 }
1779                 break;
1780         case RADEON_SE_VF_CNTL:
1781                 track->vap_vf_cntl = idx_value;
1782                 break;
1783         case RADEON_SE_VTX_FMT:
1784                 track->vtx_size = r100_get_vtx_size(idx_value);
1785                 break;
1786         case RADEON_PP_TEX_SIZE_0:
1787         case RADEON_PP_TEX_SIZE_1:
1788         case RADEON_PP_TEX_SIZE_2:
1789                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1790                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1791                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1792                 track->tex_dirty = true;
1793                 break;
1794         case RADEON_PP_TEX_PITCH_0:
1795         case RADEON_PP_TEX_PITCH_1:
1796         case RADEON_PP_TEX_PITCH_2:
1797                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1798                 track->textures[i].pitch = idx_value + 32;
1799                 track->tex_dirty = true;
1800                 break;
1801         case RADEON_PP_TXFILTER_0:
1802         case RADEON_PP_TXFILTER_1:
1803         case RADEON_PP_TXFILTER_2:
1804                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1805                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1806                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1807                 tmp = (idx_value >> 23) & 0x7;
1808                 if (tmp == 2 || tmp == 6)
1809                         track->textures[i].roundup_w = false;
1810                 tmp = (idx_value >> 27) & 0x7;
1811                 if (tmp == 2 || tmp == 6)
1812                         track->textures[i].roundup_h = false;
1813                 track->tex_dirty = true;
1814                 break;
1815         case RADEON_PP_TXFORMAT_0:
1816         case RADEON_PP_TXFORMAT_1:
1817         case RADEON_PP_TXFORMAT_2:
1818                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1819                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1820                         track->textures[i].use_pitch = 1;
1821                 } else {
1822                         track->textures[i].use_pitch = 0;
1823                         track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1824                         track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1825                 }
1826                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1827                         track->textures[i].tex_coord_type = 2;
1828                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1829                 case RADEON_TXFORMAT_I8:
1830                 case RADEON_TXFORMAT_RGB332:
1831                 case RADEON_TXFORMAT_Y8:
1832                         track->textures[i].cpp = 1;
1833                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1834                         break;
1835                 case RADEON_TXFORMAT_AI88:
1836                 case RADEON_TXFORMAT_ARGB1555:
1837                 case RADEON_TXFORMAT_RGB565:
1838                 case RADEON_TXFORMAT_ARGB4444:
1839                 case RADEON_TXFORMAT_VYUY422:
1840                 case RADEON_TXFORMAT_YVYU422:
1841                 case RADEON_TXFORMAT_SHADOW16:
1842                 case RADEON_TXFORMAT_LDUDV655:
1843                 case RADEON_TXFORMAT_DUDV88:
1844                         track->textures[i].cpp = 2;
1845                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1846                         break;
1847                 case RADEON_TXFORMAT_ARGB8888:
1848                 case RADEON_TXFORMAT_RGBA8888:
1849                 case RADEON_TXFORMAT_SHADOW32:
1850                 case RADEON_TXFORMAT_LDUDUV8888:
1851                         track->textures[i].cpp = 4;
1852                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1853                         break;
1854                 case RADEON_TXFORMAT_DXT1:
1855                         track->textures[i].cpp = 1;
1856                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1857                         break;
1858                 case RADEON_TXFORMAT_DXT23:
1859                 case RADEON_TXFORMAT_DXT45:
1860                         track->textures[i].cpp = 1;
1861                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1862                         break;
1863                 }
1864                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1865                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1866                 track->tex_dirty = true;
1867                 break;
1868         case RADEON_PP_CUBIC_FACES_0:
1869         case RADEON_PP_CUBIC_FACES_1:
1870         case RADEON_PP_CUBIC_FACES_2:
1871                 tmp = idx_value;
1872                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1873                 for (face = 0; face < 4; face++) {
1874                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1875                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1876                 }
1877                 track->tex_dirty = true;
1878                 break;
1879         default:
1880                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1881                        reg, idx);
1882                 return -EINVAL;
1883         }
1884         return 0;
1885 }
1886
1887 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1888                                          struct radeon_cs_packet *pkt,
1889                                          struct radeon_bo *robj)
1890 {
1891         unsigned idx;
1892         u32 value;
1893         idx = pkt->idx + 1;
1894         value = radeon_get_ib_value(p, idx + 2);
1895         if ((value + 1) > radeon_bo_size(robj)) {
1896                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1897                           "(need %u have %lu) !\n",
1898                           value + 1,
1899                           radeon_bo_size(robj));
1900                 return -EINVAL;
1901         }
1902         return 0;
1903 }
1904
1905 static int r100_packet3_check(struct radeon_cs_parser *p,
1906                               struct radeon_cs_packet *pkt)
1907 {
1908         struct radeon_bo_list *reloc;
1909         struct r100_cs_track *track;
1910         unsigned idx;
1911         volatile uint32_t *ib;
1912         int r;
1913
1914         ib = p->ib.ptr;
1915         idx = pkt->idx + 1;
1916         track = (struct r100_cs_track *)p->track;
1917         switch (pkt->opcode) {
1918         case PACKET3_3D_LOAD_VBPNTR:
1919                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1920                 if (r)
1921                         return r;
1922                 break;
1923         case PACKET3_INDX_BUFFER:
1924                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1925                 if (r) {
1926                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1927                         radeon_cs_dump_packet(p, pkt);
1928                         return r;
1929                 }
1930                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1931                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1932                 if (r) {
1933                         return r;
1934                 }
1935                 break;
1936         case 0x23:
1937                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1938                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1939                 if (r) {
1940                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1941                         radeon_cs_dump_packet(p, pkt);
1942                         return r;
1943                 }
1944                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1945                 track->num_arrays = 1;
1946                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1947
1948                 track->arrays[0].robj = reloc->robj;
1949                 track->arrays[0].esize = track->vtx_size;
1950
1951                 track->max_indx = radeon_get_ib_value(p, idx+1);
1952
1953                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1954                 track->immd_dwords = pkt->count - 1;
1955                 r = r100_cs_track_check(p->rdev, track);
1956                 if (r)
1957                         return r;
1958                 break;
1959         case PACKET3_3D_DRAW_IMMD:
1960                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1961                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1962                         return -EINVAL;
1963                 }
1964                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1965                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1966                 track->immd_dwords = pkt->count - 1;
1967                 r = r100_cs_track_check(p->rdev, track);
1968                 if (r)
1969                         return r;
1970                 break;
1971                 /* triggers drawing using in-packet vertex data */
1972         case PACKET3_3D_DRAW_IMMD_2:
1973                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1974                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1975                         return -EINVAL;
1976                 }
1977                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1978                 track->immd_dwords = pkt->count;
1979                 r = r100_cs_track_check(p->rdev, track);
1980                 if (r)
1981                         return r;
1982                 break;
1983                 /* triggers drawing using in-packet vertex data */
1984         case PACKET3_3D_DRAW_VBUF_2:
1985                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1986                 r = r100_cs_track_check(p->rdev, track);
1987                 if (r)
1988                         return r;
1989                 break;
1990                 /* triggers drawing of vertex buffers setup elsewhere */
1991         case PACKET3_3D_DRAW_INDX_2:
1992                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1993                 r = r100_cs_track_check(p->rdev, track);
1994                 if (r)
1995                         return r;
1996                 break;
1997                 /* triggers drawing using indices to vertex buffer */
1998         case PACKET3_3D_DRAW_VBUF:
1999                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2000                 r = r100_cs_track_check(p->rdev, track);
2001                 if (r)
2002                         return r;
2003                 break;
2004                 /* triggers drawing of vertex buffers setup elsewhere */
2005         case PACKET3_3D_DRAW_INDX:
2006                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2007                 r = r100_cs_track_check(p->rdev, track);
2008                 if (r)
2009                         return r;
2010                 break;
2011                 /* triggers drawing using indices to vertex buffer */
2012         case PACKET3_3D_CLEAR_HIZ:
2013         case PACKET3_3D_CLEAR_ZMASK:
2014                 if (p->rdev->hyperz_filp != p->filp)
2015                         return -EINVAL;
2016                 break;
2017         case PACKET3_NOP:
2018                 break;
2019         default:
2020                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2021                 return -EINVAL;
2022         }
2023         return 0;
2024 }
2025
2026 int r100_cs_parse(struct radeon_cs_parser *p)
2027 {
2028         struct radeon_cs_packet pkt;
2029         struct r100_cs_track *track;
2030         int r;
2031
2032         track = kzalloc(sizeof(*track), GFP_KERNEL);
2033         if (!track)
2034                 return -ENOMEM;
2035         r100_cs_track_clear(p->rdev, track);
2036         p->track = track;
2037         do {
2038                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2039                 if (r) {
2040                         return r;
2041                 }
2042                 p->idx += pkt.count + 2;
2043                 switch (pkt.type) {
2044                 case RADEON_PACKET_TYPE0:
2045                         if (p->rdev->family >= CHIP_R200)
2046                                 r = r100_cs_parse_packet0(p, &pkt,
2047                                         p->rdev->config.r100.reg_safe_bm,
2048                                         p->rdev->config.r100.reg_safe_bm_size,
2049                                         &r200_packet0_check);
2050                         else
2051                                 r = r100_cs_parse_packet0(p, &pkt,
2052                                         p->rdev->config.r100.reg_safe_bm,
2053                                         p->rdev->config.r100.reg_safe_bm_size,
2054                                         &r100_packet0_check);
2055                         break;
2056                 case RADEON_PACKET_TYPE2:
2057                         break;
2058                 case RADEON_PACKET_TYPE3:
2059                         r = r100_packet3_check(p, &pkt);
2060                         break;
2061                 default:
2062                         DRM_ERROR("Unknown packet type %d !\n",
2063                                   pkt.type);
2064                         return -EINVAL;
2065                 }
2066                 if (r)
2067                         return r;
2068         } while (p->idx < p->chunk_ib->length_dw);
2069         return 0;
2070 }
2071
2072 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2073 {
2074         DRM_ERROR("pitch                      %d\n", t->pitch);
2075         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2076         DRM_ERROR("width                      %d\n", t->width);
2077         DRM_ERROR("width_11                   %d\n", t->width_11);
2078         DRM_ERROR("height                     %d\n", t->height);
2079         DRM_ERROR("height_11                  %d\n", t->height_11);
2080         DRM_ERROR("num levels                 %d\n", t->num_levels);
2081         DRM_ERROR("depth                      %d\n", t->txdepth);
2082         DRM_ERROR("bpp                        %d\n", t->cpp);
2083         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2084         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2085         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2086         DRM_ERROR("compress format            %d\n", t->compress_format);
2087 }
2088
2089 static int r100_track_compress_size(int compress_format, int w, int h)
2090 {
2091         int block_width, block_height, block_bytes;
2092         int wblocks, hblocks;
2093         int min_wblocks;
2094         int sz;
2095
2096         block_width = 4;
2097         block_height = 4;
2098
2099         switch (compress_format) {
2100         case R100_TRACK_COMP_DXT1:
2101                 block_bytes = 8;
2102                 min_wblocks = 4;
2103                 break;
2104         default:
2105         case R100_TRACK_COMP_DXT35:
2106                 block_bytes = 16;
2107                 min_wblocks = 2;
2108                 break;
2109         }
2110
2111         hblocks = (h + block_height - 1) / block_height;
2112         wblocks = (w + block_width - 1) / block_width;
2113         if (wblocks < min_wblocks)
2114                 wblocks = min_wblocks;
2115         sz = wblocks * hblocks * block_bytes;
2116         return sz;
2117 }
2118
2119 static int r100_cs_track_cube(struct radeon_device *rdev,
2120                               struct r100_cs_track *track, unsigned idx)
2121 {
2122         unsigned face, w, h;
2123         struct radeon_bo *cube_robj;
2124         unsigned long size;
2125         unsigned compress_format = track->textures[idx].compress_format;
2126
2127         for (face = 0; face < 5; face++) {
2128                 cube_robj = track->textures[idx].cube_info[face].robj;
2129                 w = track->textures[idx].cube_info[face].width;
2130                 h = track->textures[idx].cube_info[face].height;
2131
2132                 if (compress_format) {
2133                         size = r100_track_compress_size(compress_format, w, h);
2134                 } else
2135                         size = w * h;
2136                 size *= track->textures[idx].cpp;
2137
2138                 size += track->textures[idx].cube_info[face].offset;
2139
2140                 if (size > radeon_bo_size(cube_robj)) {
2141                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2142                                   size, radeon_bo_size(cube_robj));
2143                         r100_cs_track_texture_print(&track->textures[idx]);
2144                         return -1;
2145                 }
2146         }
2147         return 0;
2148 }
2149
2150 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2151                                        struct r100_cs_track *track)
2152 {
2153         struct radeon_bo *robj;
2154         unsigned long size;
2155         unsigned u, i, w, h, d;
2156         int ret;
2157
2158         for (u = 0; u < track->num_texture; u++) {
2159                 if (!track->textures[u].enabled)
2160                         continue;
2161                 if (track->textures[u].lookup_disable)
2162                         continue;
2163                 robj = track->textures[u].robj;
2164                 if (robj == NULL) {
2165                         DRM_ERROR("No texture bound to unit %u\n", u);
2166                         return -EINVAL;
2167                 }
2168                 size = 0;
2169                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2170                         if (track->textures[u].use_pitch) {
2171                                 if (rdev->family < CHIP_R300)
2172                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2173                                 else
2174                                         w = track->textures[u].pitch / (1 << i);
2175                         } else {
2176                                 w = track->textures[u].width;
2177                                 if (rdev->family >= CHIP_RV515)
2178                                         w |= track->textures[u].width_11;
2179                                 w = w / (1 << i);
2180                                 if (track->textures[u].roundup_w)
2181                                         w = roundup_pow_of_two(w);
2182                         }
2183                         h = track->textures[u].height;
2184                         if (rdev->family >= CHIP_RV515)
2185                                 h |= track->textures[u].height_11;
2186                         h = h / (1 << i);
2187                         if (track->textures[u].roundup_h)
2188                                 h = roundup_pow_of_two(h);
2189                         if (track->textures[u].tex_coord_type == 1) {
2190                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2191                                 if (!d)
2192                                         d = 1;
2193                         } else {
2194                                 d = 1;
2195                         }
2196                         if (track->textures[u].compress_format) {
2197
2198                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2199                                 /* compressed textures are block based */
2200                         } else
2201                                 size += w * h * d;
2202                 }
2203                 size *= track->textures[u].cpp;
2204
2205                 switch (track->textures[u].tex_coord_type) {
2206                 case 0:
2207                 case 1:
2208                         break;
2209                 case 2:
2210                         if (track->separate_cube) {
2211                                 ret = r100_cs_track_cube(rdev, track, u);
2212                                 if (ret)
2213                                         return ret;
2214                         } else
2215                                 size *= 6;
2216                         break;
2217                 default:
2218                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2219                                   "%u\n", track->textures[u].tex_coord_type, u);
2220                         return -EINVAL;
2221                 }
2222                 if (size > radeon_bo_size(robj)) {
2223                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2224                                   "%lu\n", u, size, radeon_bo_size(robj));
2225                         r100_cs_track_texture_print(&track->textures[u]);
2226                         return -EINVAL;
2227                 }
2228         }
2229         return 0;
2230 }
2231
2232 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2233 {
2234         unsigned i;
2235         unsigned long size;
2236         unsigned prim_walk;
2237         unsigned nverts;
2238         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2239
2240         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2241             !track->blend_read_enable)
2242                 num_cb = 0;
2243
2244         for (i = 0; i < num_cb; i++) {
2245                 if (track->cb[i].robj == NULL) {
2246                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2247                         return -EINVAL;
2248                 }
2249                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2250                 size += track->cb[i].offset;
2251                 if (size > radeon_bo_size(track->cb[i].robj)) {
2252                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2253                                   "(need %lu have %lu) !\n", i, size,
2254                                   radeon_bo_size(track->cb[i].robj));
2255                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2256                                   i, track->cb[i].pitch, track->cb[i].cpp,
2257                                   track->cb[i].offset, track->maxy);
2258                         return -EINVAL;
2259                 }
2260         }
2261         track->cb_dirty = false;
2262
2263         if (track->zb_dirty && track->z_enabled) {
2264                 if (track->zb.robj == NULL) {
2265                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2266                         return -EINVAL;
2267                 }
2268                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2269                 size += track->zb.offset;
2270                 if (size > radeon_bo_size(track->zb.robj)) {
2271                         DRM_ERROR("[drm] Buffer too small for z buffer "
2272                                   "(need %lu have %lu) !\n", size,
2273                                   radeon_bo_size(track->zb.robj));
2274                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2275                                   track->zb.pitch, track->zb.cpp,
2276                                   track->zb.offset, track->maxy);
2277                         return -EINVAL;
2278                 }
2279         }
2280         track->zb_dirty = false;
2281
2282         if (track->aa_dirty && track->aaresolve) {
2283                 if (track->aa.robj == NULL) {
2284                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2285                         return -EINVAL;
2286                 }
2287                 /* I believe the format comes from colorbuffer0. */
2288                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2289                 size += track->aa.offset;
2290                 if (size > radeon_bo_size(track->aa.robj)) {
2291                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2292                                   "(need %lu have %lu) !\n", i, size,
2293                                   radeon_bo_size(track->aa.robj));
2294                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2295                                   i, track->aa.pitch, track->cb[0].cpp,
2296                                   track->aa.offset, track->maxy);
2297                         return -EINVAL;
2298                 }
2299         }
2300         track->aa_dirty = false;
2301
2302         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2303         if (track->vap_vf_cntl & (1 << 14)) {
2304                 nverts = track->vap_alt_nverts;
2305         } else {
2306                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2307         }
2308         switch (prim_walk) {
2309         case 1:
2310                 for (i = 0; i < track->num_arrays; i++) {
2311                         size = track->arrays[i].esize * track->max_indx * 4;
2312                         if (track->arrays[i].robj == NULL) {
2313                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2314                                           "bound\n", prim_walk, i);
2315                                 return -EINVAL;
2316                         }
2317                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2318                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2319                                         "need %lu dwords have %lu dwords\n",
2320                                         prim_walk, i, size >> 2,
2321                                         radeon_bo_size(track->arrays[i].robj)
2322                                         >> 2);
2323                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327                 break;
2328         case 2:
2329                 for (i = 0; i < track->num_arrays; i++) {
2330                         size = track->arrays[i].esize * (nverts - 1) * 4;
2331                         if (track->arrays[i].robj == NULL) {
2332                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2333                                           "bound\n", prim_walk, i);
2334                                 return -EINVAL;
2335                         }
2336                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2337                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2338                                         "need %lu dwords have %lu dwords\n",
2339                                         prim_walk, i, size >> 2,
2340                                         radeon_bo_size(track->arrays[i].robj)
2341                                         >> 2);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345                 break;
2346         case 3:
2347                 size = track->vtx_size * nverts;
2348                 if (size != track->immd_dwords) {
2349                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2350                                   track->immd_dwords, size);
2351                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2352                                   nverts, track->vtx_size);
2353                         return -EINVAL;
2354                 }
2355                 break;
2356         default:
2357                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2358                           prim_walk);
2359                 return -EINVAL;
2360         }
2361
2362         if (track->tex_dirty) {
2363                 track->tex_dirty = false;
2364                 return r100_cs_track_texture_check(rdev, track);
2365         }
2366         return 0;
2367 }
2368
2369 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2370 {
2371         unsigned i, face;
2372
2373         track->cb_dirty = true;
2374         track->zb_dirty = true;
2375         track->tex_dirty = true;
2376         track->aa_dirty = true;
2377
2378         if (rdev->family < CHIP_R300) {
2379                 track->num_cb = 1;
2380                 if (rdev->family <= CHIP_RS200)
2381                         track->num_texture = 3;
2382                 else
2383                         track->num_texture = 6;
2384                 track->maxy = 2048;
2385                 track->separate_cube = 1;
2386         } else {
2387                 track->num_cb = 4;
2388                 track->num_texture = 16;
2389                 track->maxy = 4096;
2390                 track->separate_cube = 0;
2391                 track->aaresolve = false;
2392                 track->aa.robj = NULL;
2393         }
2394
2395         for (i = 0; i < track->num_cb; i++) {
2396                 track->cb[i].robj = NULL;
2397                 track->cb[i].pitch = 8192;
2398                 track->cb[i].cpp = 16;
2399                 track->cb[i].offset = 0;
2400         }
2401         track->z_enabled = true;
2402         track->zb.robj = NULL;
2403         track->zb.pitch = 8192;
2404         track->zb.cpp = 4;
2405         track->zb.offset = 0;
2406         track->vtx_size = 0x7F;
2407         track->immd_dwords = 0xFFFFFFFFUL;
2408         track->num_arrays = 11;
2409         track->max_indx = 0x00FFFFFFUL;
2410         for (i = 0; i < track->num_arrays; i++) {
2411                 track->arrays[i].robj = NULL;
2412                 track->arrays[i].esize = 0x7F;
2413         }
2414         for (i = 0; i < track->num_texture; i++) {
2415                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2416                 track->textures[i].pitch = 16536;
2417                 track->textures[i].width = 16536;
2418                 track->textures[i].height = 16536;
2419                 track->textures[i].width_11 = 1 << 11;
2420                 track->textures[i].height_11 = 1 << 11;
2421                 track->textures[i].num_levels = 12;
2422                 if (rdev->family <= CHIP_RS200) {
2423                         track->textures[i].tex_coord_type = 0;
2424                         track->textures[i].txdepth = 0;
2425                 } else {
2426                         track->textures[i].txdepth = 16;
2427                         track->textures[i].tex_coord_type = 1;
2428                 }
2429                 track->textures[i].cpp = 64;
2430                 track->textures[i].robj = NULL;
2431                 /* CS IB emission code makes sure texture unit are disabled */
2432                 track->textures[i].enabled = false;
2433                 track->textures[i].lookup_disable = false;
2434                 track->textures[i].roundup_w = true;
2435                 track->textures[i].roundup_h = true;
2436                 if (track->separate_cube)
2437                         for (face = 0; face < 5; face++) {
2438                                 track->textures[i].cube_info[face].robj = NULL;
2439                                 track->textures[i].cube_info[face].width = 16536;
2440                                 track->textures[i].cube_info[face].height = 16536;
2441                                 track->textures[i].cube_info[face].offset = 0;
2442                         }
2443         }
2444 }
2445
2446 /*
2447  * Global GPU functions
2448  */
2449 static void r100_errata(struct radeon_device *rdev)
2450 {
2451         rdev->pll_errata = 0;
2452
2453         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2454                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2455         }
2456
2457         if (rdev->family == CHIP_RV100 ||
2458             rdev->family == CHIP_RS100 ||
2459             rdev->family == CHIP_RS200) {
2460                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2461         }
2462 }
2463
2464 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2465 {
2466         unsigned i;
2467         uint32_t tmp;
2468
2469         for (i = 0; i < rdev->usec_timeout; i++) {
2470                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2471                 if (tmp >= n) {
2472                         return 0;
2473                 }
2474                 DRM_UDELAY(1);
2475         }
2476         return -1;
2477 }
2478
2479 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2480 {
2481         unsigned i;
2482         uint32_t tmp;
2483
2484         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2485                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2486                        " Bad things might happen.\n");
2487         }
2488         for (i = 0; i < rdev->usec_timeout; i++) {
2489                 tmp = RREG32(RADEON_RBBM_STATUS);
2490                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2491                         return 0;
2492                 }
2493                 DRM_UDELAY(1);
2494         }
2495         return -1;
2496 }
2497
2498 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2499 {
2500         unsigned i;
2501         uint32_t tmp;
2502
2503         for (i = 0; i < rdev->usec_timeout; i++) {
2504                 /* read MC_STATUS */
2505                 tmp = RREG32(RADEON_MC_STATUS);
2506                 if (tmp & RADEON_MC_IDLE) {
2507                         return 0;
2508                 }
2509                 DRM_UDELAY(1);
2510         }
2511         return -1;
2512 }
2513
2514 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2515 {
2516         u32 rbbm_status;
2517
2518         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2519         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2520                 radeon_ring_lockup_update(rdev, ring);
2521                 return false;
2522         }
2523         return radeon_ring_test_lockup(rdev, ring);
2524 }
2525
2526 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2527 void r100_enable_bm(struct radeon_device *rdev)
2528 {
2529         uint32_t tmp;
2530         /* Enable bus mastering */
2531         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2532         WREG32(RADEON_BUS_CNTL, tmp);
2533 }
2534
2535 void r100_bm_disable(struct radeon_device *rdev)
2536 {
2537         u32 tmp;
2538
2539         /* disable bus mastering */
2540         tmp = RREG32(R_000030_BUS_CNTL);
2541         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2542         mdelay(1);
2543         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2544         mdelay(1);
2545         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2546         tmp = RREG32(RADEON_BUS_CNTL);
2547         mdelay(1);
2548         pci_clear_master(rdev->pdev);
2549         mdelay(1);
2550 }
2551
2552 int r100_asic_reset(struct radeon_device *rdev)
2553 {
2554         struct r100_mc_save save;
2555         u32 status, tmp;
2556         int ret = 0;
2557
2558         status = RREG32(R_000E40_RBBM_STATUS);
2559         if (!G_000E40_GUI_ACTIVE(status)) {
2560                 return 0;
2561         }
2562         r100_mc_stop(rdev, &save);
2563         status = RREG32(R_000E40_RBBM_STATUS);
2564         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2565         /* stop CP */
2566         WREG32(RADEON_CP_CSQ_CNTL, 0);
2567         tmp = RREG32(RADEON_CP_RB_CNTL);
2568         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2569         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2570         WREG32(RADEON_CP_RB_WPTR, 0);
2571         WREG32(RADEON_CP_RB_CNTL, tmp);
2572         /* save PCI state */
2573         pci_save_state(rdev->pdev);
2574         /* disable bus mastering */
2575         r100_bm_disable(rdev);
2576         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2577                                         S_0000F0_SOFT_RESET_RE(1) |
2578                                         S_0000F0_SOFT_RESET_PP(1) |
2579                                         S_0000F0_SOFT_RESET_RB(1));
2580         RREG32(R_0000F0_RBBM_SOFT_RESET);
2581         mdelay(500);
2582         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2583         mdelay(1);
2584         status = RREG32(R_000E40_RBBM_STATUS);
2585         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2586         /* reset CP */
2587         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2588         RREG32(R_0000F0_RBBM_SOFT_RESET);
2589         mdelay(500);
2590         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2591         mdelay(1);
2592         status = RREG32(R_000E40_RBBM_STATUS);
2593         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2594         /* restore PCI & busmastering */
2595         pci_restore_state(rdev->pdev);
2596         r100_enable_bm(rdev);
2597         /* Check if GPU is idle */
2598         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2599                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2600                 dev_err(rdev->dev, "failed to reset GPU\n");
2601                 ret = -1;
2602         } else
2603                 dev_info(rdev->dev, "GPU reset succeed\n");
2604         r100_mc_resume(rdev, &save);
2605         return ret;
2606 }
2607
2608 void r100_set_common_regs(struct radeon_device *rdev)
2609 {
2610         struct drm_device *dev = rdev->ddev;
2611         bool force_dac2 = false;
2612         u32 tmp;
2613
2614         /* set these so they don't interfere with anything */
2615         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2616         WREG32(RADEON_SUBPIC_CNTL, 0);
2617         WREG32(RADEON_VIPH_CONTROL, 0);
2618         WREG32(RADEON_I2C_CNTL_1, 0);
2619         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2620         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2621         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2622
2623         /* always set up dac2 on rn50 and some rv100 as lots
2624          * of servers seem to wire it up to a VGA port but
2625          * don't report it in the bios connector
2626          * table.
2627          */
2628         switch (dev->pdev->device) {
2629                 /* RN50 */
2630         case 0x515e:
2631         case 0x5969:
2632                 force_dac2 = true;
2633                 break;
2634                 /* RV100*/
2635         case 0x5159:
2636         case 0x515a:
2637                 /* DELL triple head servers */
2638                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2639                     ((dev->pdev->subsystem_device == 0x016c) ||
2640                      (dev->pdev->subsystem_device == 0x016d) ||
2641                      (dev->pdev->subsystem_device == 0x016e) ||
2642                      (dev->pdev->subsystem_device == 0x016f) ||
2643                      (dev->pdev->subsystem_device == 0x0170) ||
2644                      (dev->pdev->subsystem_device == 0x017d) ||
2645                      (dev->pdev->subsystem_device == 0x017e) ||
2646                      (dev->pdev->subsystem_device == 0x0183) ||
2647                      (dev->pdev->subsystem_device == 0x018a) ||
2648                      (dev->pdev->subsystem_device == 0x019a)))
2649                         force_dac2 = true;
2650                 break;
2651         }
2652
2653         if (force_dac2) {
2654                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2655                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2656                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2657
2658                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2659                    enable it, even it's detected.
2660                 */
2661
2662                 /* force it to crtc0 */
2663                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2664                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2665                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2666
2667                 /* set up the TV DAC */
2668                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2669                                  RADEON_TV_DAC_STD_MASK |
2670                                  RADEON_TV_DAC_RDACPD |
2671                                  RADEON_TV_DAC_GDACPD |
2672                                  RADEON_TV_DAC_BDACPD |
2673                                  RADEON_TV_DAC_BGADJ_MASK |
2674                                  RADEON_TV_DAC_DACADJ_MASK);
2675                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2676                                 RADEON_TV_DAC_NHOLD |
2677                                 RADEON_TV_DAC_STD_PS2 |
2678                                 (0x58 << 16));
2679
2680                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2681                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2682                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2683         }
2684
2685         /* switch PM block to ACPI mode */
2686         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2687         tmp &= ~RADEON_PM_MODE_SEL;
2688         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2689
2690 }
2691
2692 /*
2693  * VRAM info
2694  */
2695 static void r100_vram_get_type(struct radeon_device *rdev)
2696 {
2697         uint32_t tmp;
2698
2699         rdev->mc.vram_is_ddr = false;
2700         if (rdev->flags & RADEON_IS_IGP)
2701                 rdev->mc.vram_is_ddr = true;
2702         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2703                 rdev->mc.vram_is_ddr = true;
2704         if ((rdev->family == CHIP_RV100) ||
2705             (rdev->family == CHIP_RS100) ||
2706             (rdev->family == CHIP_RS200)) {
2707                 tmp = RREG32(RADEON_MEM_CNTL);
2708                 if (tmp & RV100_HALF_MODE) {
2709                         rdev->mc.vram_width = 32;
2710                 } else {
2711                         rdev->mc.vram_width = 64;
2712                 }
2713                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2714                         rdev->mc.vram_width /= 4;
2715                         rdev->mc.vram_is_ddr = true;
2716                 }
2717         } else if (rdev->family <= CHIP_RV280) {
2718                 tmp = RREG32(RADEON_MEM_CNTL);
2719                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2720                         rdev->mc.vram_width = 128;
2721                 } else {
2722                         rdev->mc.vram_width = 64;
2723                 }
2724         } else {
2725                 /* newer IGPs */
2726                 rdev->mc.vram_width = 128;
2727         }
2728 }
2729
2730 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2731 {
2732         u32 aper_size;
2733         u8 byte;
2734
2735         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2736
2737         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2738          * that is has the 2nd generation multifunction PCI interface
2739          */
2740         if (rdev->family == CHIP_RV280 ||
2741             rdev->family >= CHIP_RV350) {
2742                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2743                        ~RADEON_HDP_APER_CNTL);
2744                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2745                 return aper_size * 2;
2746         }
2747
2748         /* Older cards have all sorts of funny issues to deal with. First
2749          * check if it's a multifunction card by reading the PCI config
2750          * header type... Limit those to one aperture size
2751          */
2752         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2753         if (byte & 0x80) {
2754                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2755                 DRM_INFO("Limiting VRAM to one aperture\n");
2756                 return aper_size;
2757         }
2758
2759         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2760          * have set it up. We don't write this as it's broken on some ASICs but
2761          * we expect the BIOS to have done the right thing (might be too optimistic...)
2762          */
2763         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2764                 return aper_size * 2;
2765         return aper_size;
2766 }
2767
2768 void r100_vram_init_sizes(struct radeon_device *rdev)
2769 {
2770         u64 config_aper_size;
2771
2772         /* work out accessible VRAM */
2773         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2774         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2775         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2776         /* FIXME we don't use the second aperture yet when we could use it */
2777         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2778                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2779         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2780         if (rdev->flags & RADEON_IS_IGP) {
2781                 uint32_t tom;
2782                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2783                 tom = RREG32(RADEON_NB_TOM);
2784                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2785                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2786                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2787         } else {
2788                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2789                 /* Some production boards of m6 will report 0
2790                  * if it's 8 MB
2791                  */
2792                 if (rdev->mc.real_vram_size == 0) {
2793                         rdev->mc.real_vram_size = 8192 * 1024;
2794                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2795                 }
2796                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2797                  * Novell bug 204882 + along with lots of ubuntu ones
2798                  */
2799                 if (rdev->mc.aper_size > config_aper_size)
2800                         config_aper_size = rdev->mc.aper_size;
2801
2802                 if (config_aper_size > rdev->mc.real_vram_size)
2803                         rdev->mc.mc_vram_size = config_aper_size;
2804                 else
2805                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2806         }
2807 }
2808
2809 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2810 {
2811         uint32_t temp;
2812
2813         temp = RREG32(RADEON_CONFIG_CNTL);
2814         if (state == false) {
2815                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2816                 temp |= RADEON_CFG_VGA_IO_DIS;
2817         } else {
2818                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2819         }
2820         WREG32(RADEON_CONFIG_CNTL, temp);
2821 }
2822
2823 static void r100_mc_init(struct radeon_device *rdev)
2824 {
2825         u64 base;
2826
2827         r100_vram_get_type(rdev);
2828         r100_vram_init_sizes(rdev);
2829         base = rdev->mc.aper_base;
2830         if (rdev->flags & RADEON_IS_IGP)
2831                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2832         radeon_vram_location(rdev, &rdev->mc, base);
2833         rdev->mc.gtt_base_align = 0;
2834         if (!(rdev->flags & RADEON_IS_AGP))
2835                 radeon_gtt_location(rdev, &rdev->mc);
2836         radeon_update_bandwidth_info(rdev);
2837 }
2838
2839
2840 /*
2841  * Indirect registers accessor
2842  */
2843 void r100_pll_errata_after_index(struct radeon_device *rdev)
2844 {
2845         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2846                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2847                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2848         }
2849 }
2850
2851 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2852 {
2853         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2854          * or the chip could hang on a subsequent access
2855          */
2856         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2857                 mdelay(5);
2858         }
2859
2860         /* This function is required to workaround a hardware bug in some (all?)
2861          * revisions of the R300.  This workaround should be called after every
2862          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2863          * may not be correct.
2864          */
2865         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2866                 uint32_t save, tmp;
2867
2868                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2869                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2870                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2871                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2872                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2873         }
2874 }
2875
2876 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2877 {
2878         unsigned long flags;
2879         uint32_t data;
2880
2881         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2882         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2883         r100_pll_errata_after_index(rdev);
2884         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2885         r100_pll_errata_after_data(rdev);
2886         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2887         return data;
2888 }
2889
2890 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2891 {
2892         unsigned long flags;
2893
2894         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2895         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2896         r100_pll_errata_after_index(rdev);
2897         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2898         r100_pll_errata_after_data(rdev);
2899         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2900 }
2901
2902 static void r100_set_safe_registers(struct radeon_device *rdev)
2903 {
2904         if (ASIC_IS_RN50(rdev)) {
2905                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2906                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2907         } else if (rdev->family < CHIP_R200) {
2908                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2909                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2910         } else {
2911                 r200_set_safe_registers(rdev);
2912         }
2913 }
2914
2915 /*
2916  * Debugfs info
2917  */
2918 #if defined(CONFIG_DEBUG_FS)
2919 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2920 {
2921         struct drm_info_node *node = (struct drm_info_node *) m->private;
2922         struct drm_device *dev = node->minor->dev;
2923         struct radeon_device *rdev = dev->dev_private;
2924         uint32_t reg, value;
2925         unsigned i;
2926
2927         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2928         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2929         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2930         for (i = 0; i < 64; i++) {
2931                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2932                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2933                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2934                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2935                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2936         }
2937         return 0;
2938 }
2939
2940 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2941 {
2942         struct drm_info_node *node = (struct drm_info_node *) m->private;
2943         struct drm_device *dev = node->minor->dev;
2944         struct radeon_device *rdev = dev->dev_private;
2945         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2946         uint32_t rdp, wdp;
2947         unsigned count, i, j;
2948
2949         radeon_ring_free_size(rdev, ring);
2950         rdp = RREG32(RADEON_CP_RB_RPTR);
2951         wdp = RREG32(RADEON_CP_RB_WPTR);
2952         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2953         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2954         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2955         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2956         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2957         seq_printf(m, "%u dwords in ring\n", count);
2958         if (ring->ready) {
2959                 for (j = 0; j <= count; j++) {
2960                         i = (rdp + j) & ring->ptr_mask;
2961                         seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2962                 }
2963         }
2964         return 0;
2965 }
2966
2967
2968 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2969 {
2970         struct drm_info_node *node = (struct drm_info_node *) m->private;
2971         struct drm_device *dev = node->minor->dev;
2972         struct radeon_device *rdev = dev->dev_private;
2973         uint32_t csq_stat, csq2_stat, tmp;
2974         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2975         unsigned i;
2976
2977         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2978         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2979         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2980         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2981         r_rptr = (csq_stat >> 0) & 0x3ff;
2982         r_wptr = (csq_stat >> 10) & 0x3ff;
2983         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2984         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2985         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2986         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2987         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2988         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2989         seq_printf(m, "Ring rptr %u\n", r_rptr);
2990         seq_printf(m, "Ring wptr %u\n", r_wptr);
2991         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2992         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2993         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2994         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2995         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2996          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2997         seq_printf(m, "Ring fifo:\n");
2998         for (i = 0; i < 256; i++) {
2999                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3000                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3001                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3002         }
3003         seq_printf(m, "Indirect1 fifo:\n");
3004         for (i = 256; i <= 512; i++) {
3005                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3006                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3007                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3008         }
3009         seq_printf(m, "Indirect2 fifo:\n");
3010         for (i = 640; i < ib1_wptr; i++) {
3011                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3012                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3013                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3014         }
3015         return 0;
3016 }
3017
3018 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3019 {
3020         struct drm_info_node *node = (struct drm_info_node *) m->private;
3021         struct drm_device *dev = node->minor->dev;
3022         struct radeon_device *rdev = dev->dev_private;
3023         uint32_t tmp;
3024
3025         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3026         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3027         tmp = RREG32(RADEON_MC_FB_LOCATION);
3028         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3029         tmp = RREG32(RADEON_BUS_CNTL);
3030         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3031         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3032         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3033         tmp = RREG32(RADEON_AGP_BASE);
3034         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3035         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3036         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3037         tmp = RREG32(0x01D0);
3038         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3039         tmp = RREG32(RADEON_AIC_LO_ADDR);
3040         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3041         tmp = RREG32(RADEON_AIC_HI_ADDR);
3042         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3043         tmp = RREG32(0x01E4);
3044         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3045         return 0;
3046 }
3047
3048 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3049         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3050 };
3051
3052 static struct drm_info_list r100_debugfs_cp_list[] = {
3053         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3054         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3055 };
3056
3057 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3058         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3059 };
3060 #endif
3061
3062 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3063 {
3064 #if defined(CONFIG_DEBUG_FS)
3065         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3066 #else
3067         return 0;
3068 #endif
3069 }
3070
3071 int r100_debugfs_cp_init(struct radeon_device *rdev)
3072 {
3073 #if defined(CONFIG_DEBUG_FS)
3074         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3075 #else
3076         return 0;
3077 #endif
3078 }
3079
3080 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3081 {
3082 #if defined(CONFIG_DEBUG_FS)
3083         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3084 #else
3085         return 0;
3086 #endif
3087 }
3088
3089 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3090                          uint32_t tiling_flags, uint32_t pitch,
3091                          uint32_t offset, uint32_t obj_size)
3092 {
3093         int surf_index = reg * 16;
3094         int flags = 0;
3095
3096         if (rdev->family <= CHIP_RS200) {
3097                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3098                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3099                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3100                 if (tiling_flags & RADEON_TILING_MACRO)
3101                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3102                 /* setting pitch to 0 disables tiling */
3103                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3104                                 == 0)
3105                         pitch = 0;
3106         } else if (rdev->family <= CHIP_RV280) {
3107                 if (tiling_flags & (RADEON_TILING_MACRO))
3108                         flags |= R200_SURF_TILE_COLOR_MACRO;
3109                 if (tiling_flags & RADEON_TILING_MICRO)
3110                         flags |= R200_SURF_TILE_COLOR_MICRO;
3111         } else {
3112                 if (tiling_flags & RADEON_TILING_MACRO)
3113                         flags |= R300_SURF_TILE_MACRO;
3114                 if (tiling_flags & RADEON_TILING_MICRO)
3115                         flags |= R300_SURF_TILE_MICRO;
3116         }
3117
3118         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3119                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3120         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3121                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3122
3123         /* r100/r200 divide by 16 */
3124         if (rdev->family < CHIP_R300)
3125                 flags |= pitch / 16;
3126         else
3127                 flags |= pitch / 8;
3128
3129
3130         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3131         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3132         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3133         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3134         return 0;
3135 }
3136
3137 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3138 {
3139         int surf_index = reg * 16;
3140         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3141 }
3142
3143 void r100_bandwidth_update(struct radeon_device *rdev)
3144 {
3145         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3146         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3147         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3148         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3149         fixed20_12 memtcas_ff[8] = {
3150                 dfixed_init(1),
3151                 dfixed_init(2),
3152                 dfixed_init(3),
3153                 dfixed_init(0),
3154                 dfixed_init_half(1),
3155                 dfixed_init_half(2),
3156                 dfixed_init(0),
3157         };
3158         fixed20_12 memtcas_rs480_ff[8] = {
3159                 dfixed_init(0),
3160                 dfixed_init(1),
3161                 dfixed_init(2),
3162                 dfixed_init(3),
3163                 dfixed_init(0),
3164                 dfixed_init_half(1),
3165                 dfixed_init_half(2),
3166                 dfixed_init_half(3),
3167         };
3168         fixed20_12 memtcas2_ff[8] = {
3169                 dfixed_init(0),
3170                 dfixed_init(1),
3171                 dfixed_init(2),
3172                 dfixed_init(3),
3173                 dfixed_init(4),
3174                 dfixed_init(5),
3175                 dfixed_init(6),
3176                 dfixed_init(7),
3177         };
3178         fixed20_12 memtrbs[8] = {
3179                 dfixed_init(1),
3180                 dfixed_init_half(1),
3181                 dfixed_init(2),
3182                 dfixed_init_half(2),
3183                 dfixed_init(3),
3184                 dfixed_init_half(3),
3185                 dfixed_init(4),
3186                 dfixed_init_half(4)
3187         };
3188         fixed20_12 memtrbs_r4xx[8] = {
3189                 dfixed_init(4),
3190                 dfixed_init(5),
3191                 dfixed_init(6),
3192                 dfixed_init(7),
3193                 dfixed_init(8),
3194                 dfixed_init(9),
3195                 dfixed_init(10),
3196                 dfixed_init(11)
3197         };
3198         fixed20_12 min_mem_eff;
3199         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3200         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3201         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3202                 disp_drain_rate2, read_return_rate;
3203         fixed20_12 time_disp1_drop_priority;
3204         int c;
3205         int cur_size = 16;       /* in octawords */
3206         int critical_point = 0, critical_point2;
3207 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3208         int stop_req, max_stop_req;
3209         struct drm_display_mode *mode1 = NULL;
3210         struct drm_display_mode *mode2 = NULL;
3211         uint32_t pixel_bytes1 = 0;
3212         uint32_t pixel_bytes2 = 0;
3213
3214         /* Guess line buffer size to be 8192 pixels */
3215         u32 lb_size = 8192;
3216
3217         if (!rdev->mode_info.mode_config_initialized)
3218                 return;
3219
3220         radeon_update_display_priority(rdev);
3221
3222         if (rdev->mode_info.crtcs[0]->base.enabled) {
3223                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3224                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3225         }
3226         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3227                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3228                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3229                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3230                 }
3231         }
3232
3233         min_mem_eff.full = dfixed_const_8(0);
3234         /* get modes */
3235         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3236                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3237                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3238                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3239                 /* check crtc enables */
3240                 if (mode2)
3241                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3242                 if (mode1)
3243                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3244                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3245         }
3246
3247         /*
3248          * determine is there is enough bw for current mode
3249          */
3250         sclk_ff = rdev->pm.sclk;
3251         mclk_ff = rdev->pm.mclk;
3252
3253         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3254         temp_ff.full = dfixed_const(temp);
3255         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3256
3257         pix_clk.full = 0;
3258         pix_clk2.full = 0;
3259         peak_disp_bw.full = 0;
3260         if (mode1) {
3261                 temp_ff.full = dfixed_const(1000);
3262                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3263                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3264                 temp_ff.full = dfixed_const(pixel_bytes1);
3265                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3266         }
3267         if (mode2) {
3268                 temp_ff.full = dfixed_const(1000);
3269                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3270                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3271                 temp_ff.full = dfixed_const(pixel_bytes2);
3272                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3273         }
3274
3275         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3276         if (peak_disp_bw.full >= mem_bw.full) {
3277                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3278                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3279         }
3280
3281         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3282         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3283         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3284                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3285                 mem_trp  = ((temp & 0x3)) + 1;
3286                 mem_tras = ((temp & 0x70) >> 4) + 1;
3287         } else if (rdev->family == CHIP_R300 ||
3288                    rdev->family == CHIP_R350) { /* r300, r350 */
3289                 mem_trcd = (temp & 0x7) + 1;
3290                 mem_trp = ((temp >> 8) & 0x7) + 1;
3291                 mem_tras = ((temp >> 11) & 0xf) + 4;
3292         } else if (rdev->family == CHIP_RV350 ||
3293                    rdev->family <= CHIP_RV380) {
3294                 /* rv3x0 */
3295                 mem_trcd = (temp & 0x7) + 3;
3296                 mem_trp = ((temp >> 8) & 0x7) + 3;
3297                 mem_tras = ((temp >> 11) & 0xf) + 6;
3298         } else if (rdev->family == CHIP_R420 ||
3299                    rdev->family == CHIP_R423 ||
3300                    rdev->family == CHIP_RV410) {
3301                 /* r4xx */
3302                 mem_trcd = (temp & 0xf) + 3;
3303                 if (mem_trcd > 15)
3304                         mem_trcd = 15;
3305                 mem_trp = ((temp >> 8) & 0xf) + 3;
3306                 if (mem_trp > 15)
3307                         mem_trp = 15;
3308                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3309                 if (mem_tras > 31)
3310                         mem_tras = 31;
3311         } else { /* RV200, R200 */
3312                 mem_trcd = (temp & 0x7) + 1;
3313                 mem_trp = ((temp >> 8) & 0x7) + 1;
3314                 mem_tras = ((temp >> 12) & 0xf) + 4;
3315         }
3316         /* convert to FF */
3317         trcd_ff.full = dfixed_const(mem_trcd);
3318         trp_ff.full = dfixed_const(mem_trp);
3319         tras_ff.full = dfixed_const(mem_tras);
3320
3321         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3322         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3323         data = (temp & (7 << 20)) >> 20;
3324         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3325                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3326                         tcas_ff = memtcas_rs480_ff[data];
3327                 else
3328                         tcas_ff = memtcas_ff[data];
3329         } else
3330                 tcas_ff = memtcas2_ff[data];
3331
3332         if (rdev->family == CHIP_RS400 ||
3333             rdev->family == CHIP_RS480) {
3334                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3335                 data = (temp >> 23) & 0x7;
3336                 if (data < 5)
3337                         tcas_ff.full += dfixed_const(data);
3338         }
3339
3340         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3341                 /* on the R300, Tcas is included in Trbs.
3342                  */
3343                 temp = RREG32(RADEON_MEM_CNTL);
3344                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3345                 if (data == 1) {
3346                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3347                                 temp = RREG32(R300_MC_IND_INDEX);
3348                                 temp &= ~R300_MC_IND_ADDR_MASK;
3349                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3350                                 WREG32(R300_MC_IND_INDEX, temp);
3351                                 temp = RREG32(R300_MC_IND_DATA);
3352                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3353                         } else {
3354                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3355                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3356                         }
3357                 } else {
3358                         temp = RREG32(R300_MC_READ_CNTL_AB);
3359                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3360                 }
3361                 if (rdev->family == CHIP_RV410 ||
3362                     rdev->family == CHIP_R420 ||
3363                     rdev->family == CHIP_R423)
3364                         trbs_ff = memtrbs_r4xx[data];
3365                 else
3366                         trbs_ff = memtrbs[data];
3367                 tcas_ff.full += trbs_ff.full;
3368         }
3369
3370         sclk_eff_ff.full = sclk_ff.full;
3371
3372         if (rdev->flags & RADEON_IS_AGP) {
3373                 fixed20_12 agpmode_ff;
3374                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3375                 temp_ff.full = dfixed_const_666(16);
3376                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3377         }
3378         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3379
3380         if (ASIC_IS_R300(rdev)) {
3381                 sclk_delay_ff.full = dfixed_const(250);
3382         } else {
3383                 if ((rdev->family == CHIP_RV100) ||
3384                     rdev->flags & RADEON_IS_IGP) {
3385                         if (rdev->mc.vram_is_ddr)
3386                                 sclk_delay_ff.full = dfixed_const(41);
3387                         else
3388                                 sclk_delay_ff.full = dfixed_const(33);
3389                 } else {
3390                         if (rdev->mc.vram_width == 128)
3391                                 sclk_delay_ff.full = dfixed_const(57);
3392                         else
3393                                 sclk_delay_ff.full = dfixed_const(41);
3394                 }
3395         }
3396
3397         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3398
3399         if (rdev->mc.vram_is_ddr) {
3400                 if (rdev->mc.vram_width == 32) {
3401                         k1.full = dfixed_const(40);
3402                         c  = 3;
3403                 } else {
3404                         k1.full = dfixed_const(20);
3405                         c  = 1;
3406                 }
3407         } else {
3408                 k1.full = dfixed_const(40);
3409                 c  = 3;
3410         }
3411
3412         temp_ff.full = dfixed_const(2);
3413         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3414         temp_ff.full = dfixed_const(c);
3415         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3416         temp_ff.full = dfixed_const(4);
3417         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3418         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3419         mc_latency_mclk.full += k1.full;
3420
3421         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3422         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3423
3424         /*
3425           HW cursor time assuming worst case of full size colour cursor.
3426         */
3427         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3428         temp_ff.full += trcd_ff.full;
3429         if (temp_ff.full < tras_ff.full)
3430                 temp_ff.full = tras_ff.full;
3431         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3432
3433         temp_ff.full = dfixed_const(cur_size);
3434         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3435         /*
3436           Find the total latency for the display data.
3437         */
3438         disp_latency_overhead.full = dfixed_const(8);
3439         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3440         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3441         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3442
3443         if (mc_latency_mclk.full > mc_latency_sclk.full)
3444                 disp_latency.full = mc_latency_mclk.full;
3445         else
3446                 disp_latency.full = mc_latency_sclk.full;
3447
3448         /* setup Max GRPH_STOP_REQ default value */
3449         if (ASIC_IS_RV100(rdev))
3450                 max_stop_req = 0x5c;
3451         else
3452                 max_stop_req = 0x7c;
3453
3454         if (mode1) {
3455                 /*  CRTC1
3456                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3457                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3458                 */
3459                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3460
3461                 if (stop_req > max_stop_req)
3462                         stop_req = max_stop_req;
3463
3464                 /*
3465                   Find the drain rate of the display buffer.
3466                 */
3467                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3468                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3469
3470                 /*
3471                   Find the critical point of the display buffer.
3472                 */
3473                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3474                 crit_point_ff.full += dfixed_const_half(0);
3475
3476                 critical_point = dfixed_trunc(crit_point_ff);
3477
3478                 if (rdev->disp_priority == 2) {
3479                         critical_point = 0;
3480                 }
3481
3482                 /*
3483                   The critical point should never be above max_stop_req-4.  Setting
3484                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3485                 */
3486                 if (max_stop_req - critical_point < 4)
3487                         critical_point = 0;
3488
3489                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3490                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3491                         critical_point = 0x10;
3492                 }
3493
3494                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3495                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3496                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3497                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3498                 if ((rdev->family == CHIP_R350) &&
3499                     (stop_req > 0x15)) {
3500                         stop_req -= 0x10;
3501                 }
3502                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3503                 temp |= RADEON_GRPH_BUFFER_SIZE;
3504                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3505                           RADEON_GRPH_CRITICAL_AT_SOF |
3506                           RADEON_GRPH_STOP_CNTL);
3507                 /*
3508                   Write the result into the register.
3509                 */
3510                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3511                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3512
3513 #if 0
3514                 if ((rdev->family == CHIP_RS400) ||
3515                     (rdev->family == CHIP_RS480)) {
3516                         /* attempt to program RS400 disp regs correctly ??? */
3517                         temp = RREG32(RS400_DISP1_REG_CNTL);
3518                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3519                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3520                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3521                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3522                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3523                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3524                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3525                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3526                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3527                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3528                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3529                 }
3530 #endif
3531
3532                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3533                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3534                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3535         }
3536
3537         if (mode2) {
3538                 u32 grph2_cntl;
3539                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3540
3541                 if (stop_req > max_stop_req)
3542                         stop_req = max_stop_req;
3543
3544                 /*
3545                   Find the drain rate of the display buffer.
3546                 */
3547                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3548                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3549
3550                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3551                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3552                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3553                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3554                 if ((rdev->family == CHIP_R350) &&
3555                     (stop_req > 0x15)) {
3556                         stop_req -= 0x10;
3557                 }
3558                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3559                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3560                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3561                           RADEON_GRPH_CRITICAL_AT_SOF |
3562                           RADEON_GRPH_STOP_CNTL);
3563
3564                 if ((rdev->family == CHIP_RS100) ||
3565                     (rdev->family == CHIP_RS200))
3566                         critical_point2 = 0;
3567                 else {
3568                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3569                         temp_ff.full = dfixed_const(temp);
3570                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3571                         if (sclk_ff.full < temp_ff.full)
3572                                 temp_ff.full = sclk_ff.full;
3573
3574                         read_return_rate.full = temp_ff.full;
3575
3576                         if (mode1) {
3577                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3578                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3579                         } else {
3580                                 time_disp1_drop_priority.full = 0;
3581                         }
3582                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3583                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3584                         crit_point_ff.full += dfixed_const_half(0);
3585
3586                         critical_point2 = dfixed_trunc(crit_point_ff);
3587
3588                         if (rdev->disp_priority == 2) {
3589                                 critical_point2 = 0;
3590                         }
3591
3592                         if (max_stop_req - critical_point2 < 4)
3593                                 critical_point2 = 0;
3594
3595                 }
3596
3597                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3598                         /* some R300 cards have problem with this set to 0 */
3599                         critical_point2 = 0x10;
3600                 }
3601
3602                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3603                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3604
3605                 if ((rdev->family == CHIP_RS400) ||
3606                     (rdev->family == CHIP_RS480)) {
3607 #if 0
3608                         /* attempt to program RS400 disp2 regs correctly ??? */
3609                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3610                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3611                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3612                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3613                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3614                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3615                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3616                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3617                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3618                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3619                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3620                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3621 #endif
3622                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3623                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3624                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3625                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3626                 }
3627
3628                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3629                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3630         }
3631
3632         /* Save number of lines the linebuffer leads before the scanout */
3633         if (mode1)
3634             rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3635
3636         if (mode2)
3637             rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3638 }
3639
3640 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3641 {
3642         uint32_t scratch;
3643         uint32_t tmp = 0;
3644         unsigned i;
3645         int r;
3646
3647         r = radeon_scratch_get(rdev, &scratch);
3648         if (r) {
3649                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3650                 return r;
3651         }
3652         WREG32(scratch, 0xCAFEDEAD);
3653         r = radeon_ring_lock(rdev, ring, 2);
3654         if (r) {
3655                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3656                 radeon_scratch_free(rdev, scratch);
3657                 return r;
3658         }
3659         radeon_ring_write(ring, PACKET0(scratch, 0));
3660         radeon_ring_write(ring, 0xDEADBEEF);
3661         radeon_ring_unlock_commit(rdev, ring, false);
3662         for (i = 0; i < rdev->usec_timeout; i++) {
3663                 tmp = RREG32(scratch);
3664                 if (tmp == 0xDEADBEEF) {
3665                         break;
3666                 }
3667                 DRM_UDELAY(1);
3668         }
3669         if (i < rdev->usec_timeout) {
3670                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3671         } else {
3672                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3673                           scratch, tmp);
3674                 r = -EINVAL;
3675         }
3676         radeon_scratch_free(rdev, scratch);
3677         return r;
3678 }
3679
3680 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3681 {
3682         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3683
3684         if (ring->rptr_save_reg) {
3685                 u32 next_rptr = ring->wptr + 2 + 3;
3686                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3687                 radeon_ring_write(ring, next_rptr);
3688         }
3689
3690         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3691         radeon_ring_write(ring, ib->gpu_addr);
3692         radeon_ring_write(ring, ib->length_dw);
3693 }
3694
3695 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3696 {
3697         struct radeon_ib ib;
3698         uint32_t scratch;
3699         uint32_t tmp = 0;
3700         unsigned i;
3701         int r;
3702
3703         r = radeon_scratch_get(rdev, &scratch);
3704         if (r) {
3705                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3706                 return r;
3707         }
3708         WREG32(scratch, 0xCAFEDEAD);
3709         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3710         if (r) {
3711                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3712                 goto free_scratch;
3713         }
3714         ib.ptr[0] = PACKET0(scratch, 0);
3715         ib.ptr[1] = 0xDEADBEEF;
3716         ib.ptr[2] = PACKET2(0);
3717         ib.ptr[3] = PACKET2(0);
3718         ib.ptr[4] = PACKET2(0);
3719         ib.ptr[5] = PACKET2(0);
3720         ib.ptr[6] = PACKET2(0);
3721         ib.ptr[7] = PACKET2(0);
3722         ib.length_dw = 8;
3723         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3724         if (r) {
3725                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3726                 goto free_ib;
3727         }
3728         r = radeon_fence_wait(ib.fence, false);
3729         if (r) {
3730                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3731                 goto free_ib;
3732         }
3733         for (i = 0; i < rdev->usec_timeout; i++) {
3734                 tmp = RREG32(scratch);
3735                 if (tmp == 0xDEADBEEF) {
3736                         break;
3737                 }
3738                 DRM_UDELAY(1);
3739         }
3740         if (i < rdev->usec_timeout) {
3741                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3742         } else {
3743                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3744                           scratch, tmp);
3745                 r = -EINVAL;
3746         }
3747 free_ib:
3748         radeon_ib_free(rdev, &ib);
3749 free_scratch:
3750         radeon_scratch_free(rdev, scratch);
3751         return r;
3752 }
3753
3754 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3755 {
3756         /* Shutdown CP we shouldn't need to do that but better be safe than
3757          * sorry
3758          */
3759         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3760         WREG32(R_000740_CP_CSQ_CNTL, 0);
3761
3762         /* Save few CRTC registers */
3763         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3764         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3765         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3766         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3767         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3768                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3769                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3770         }
3771
3772         /* Disable VGA aperture access */
3773         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3774         /* Disable cursor, overlay, crtc */
3775         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3776         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3777                                         S_000054_CRTC_DISPLAY_DIS(1));
3778         WREG32(R_000050_CRTC_GEN_CNTL,
3779                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3780                         S_000050_CRTC_DISP_REQ_EN_B(1));
3781         WREG32(R_000420_OV0_SCALE_CNTL,
3782                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3783         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3784         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3785                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3786                                                 S_000360_CUR2_LOCK(1));
3787                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3788                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3789                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3790                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3791                 WREG32(R_000360_CUR2_OFFSET,
3792                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3793         }
3794 }
3795
3796 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3797 {
3798         /* Update base address for crtc */
3799         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3800         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3801                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3802         }
3803         /* Restore CRTC registers */
3804         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3805         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3806         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3807         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3808                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3809         }
3810 }
3811
3812 void r100_vga_render_disable(struct radeon_device *rdev)
3813 {
3814         u32 tmp;
3815
3816         tmp = RREG8(R_0003C2_GENMO_WT);
3817         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3818 }
3819
3820 static void r100_debugfs(struct radeon_device *rdev)
3821 {
3822         int r;
3823
3824         r = r100_debugfs_mc_info_init(rdev);
3825         if (r)
3826                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3827 }
3828
3829 static void r100_mc_program(struct radeon_device *rdev)
3830 {
3831         struct r100_mc_save save;
3832
3833         /* Stops all mc clients */
3834         r100_mc_stop(rdev, &save);
3835         if (rdev->flags & RADEON_IS_AGP) {
3836                 WREG32(R_00014C_MC_AGP_LOCATION,
3837                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3838                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3839                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3840                 if (rdev->family > CHIP_RV200)
3841                         WREG32(R_00015C_AGP_BASE_2,
3842                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3843         } else {
3844                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3845                 WREG32(R_000170_AGP_BASE, 0);
3846                 if (rdev->family > CHIP_RV200)
3847                         WREG32(R_00015C_AGP_BASE_2, 0);
3848         }
3849         /* Wait for mc idle */
3850         if (r100_mc_wait_for_idle(rdev))
3851                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3852         /* Program MC, should be a 32bits limited address space */
3853         WREG32(R_000148_MC_FB_LOCATION,
3854                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3855                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3856         r100_mc_resume(rdev, &save);
3857 }
3858
3859 static void r100_clock_startup(struct radeon_device *rdev)
3860 {
3861         u32 tmp;
3862
3863         if (radeon_dynclks != -1 && radeon_dynclks)
3864                 radeon_legacy_set_clock_gating(rdev, 1);
3865         /* We need to force on some of the block */
3866         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3867         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3868         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3869                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3870         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3871 }
3872
3873 static int r100_startup(struct radeon_device *rdev)
3874 {
3875         int r;
3876
3877         /* set common regs */
3878         r100_set_common_regs(rdev);
3879         /* program mc */
3880         r100_mc_program(rdev);
3881         /* Resume clock */
3882         r100_clock_startup(rdev);
3883         /* Initialize GART (initialize after TTM so we can allocate
3884          * memory through TTM but finalize after TTM) */
3885         r100_enable_bm(rdev);
3886         if (rdev->flags & RADEON_IS_PCI) {
3887                 r = r100_pci_gart_enable(rdev);
3888                 if (r)
3889                         return r;
3890         }
3891
3892         /* allocate wb buffer */
3893         r = radeon_wb_init(rdev);
3894         if (r)
3895                 return r;
3896
3897         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3898         if (r) {
3899                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3900                 return r;
3901         }
3902
3903         /* Enable IRQ */
3904         if (!rdev->irq.installed) {
3905                 r = radeon_irq_kms_init(rdev);
3906                 if (r)
3907                         return r;
3908         }
3909
3910         r100_irq_set(rdev);
3911         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3912         /* 1M ring buffer */
3913         r = r100_cp_init(rdev, 1024 * 1024);
3914         if (r) {
3915                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3916                 return r;
3917         }
3918
3919         r = radeon_ib_pool_init(rdev);
3920         if (r) {
3921                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3922                 return r;
3923         }
3924
3925         return 0;
3926 }
3927
3928 int r100_resume(struct radeon_device *rdev)
3929 {
3930         int r;
3931
3932         /* Make sur GART are not working */
3933         if (rdev->flags & RADEON_IS_PCI)
3934                 r100_pci_gart_disable(rdev);
3935         /* Resume clock before doing reset */
3936         r100_clock_startup(rdev);
3937         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3938         if (radeon_asic_reset(rdev)) {
3939                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3940                         RREG32(R_000E40_RBBM_STATUS),
3941                         RREG32(R_0007C0_CP_STAT));
3942         }
3943         /* post */
3944         radeon_combios_asic_init(rdev->ddev);
3945         /* Resume clock after posting */
3946         r100_clock_startup(rdev);
3947         /* Initialize surface registers */
3948         radeon_surface_init(rdev);
3949
3950         rdev->accel_working = true;
3951         r = r100_startup(rdev);
3952         if (r) {
3953                 rdev->accel_working = false;
3954         }
3955         return r;
3956 }
3957
3958 int r100_suspend(struct radeon_device *rdev)
3959 {
3960         radeon_pm_suspend(rdev);
3961         r100_cp_disable(rdev);
3962         radeon_wb_disable(rdev);
3963         r100_irq_disable(rdev);
3964         if (rdev->flags & RADEON_IS_PCI)
3965                 r100_pci_gart_disable(rdev);
3966         return 0;
3967 }
3968
3969 void r100_fini(struct radeon_device *rdev)
3970 {
3971         radeon_pm_fini(rdev);
3972         r100_cp_fini(rdev);
3973         radeon_wb_fini(rdev);
3974         radeon_ib_pool_fini(rdev);
3975         radeon_gem_fini(rdev);
3976         if (rdev->flags & RADEON_IS_PCI)
3977                 r100_pci_gart_fini(rdev);
3978         radeon_agp_fini(rdev);
3979         radeon_irq_kms_fini(rdev);
3980         radeon_fence_driver_fini(rdev);
3981         radeon_bo_fini(rdev);
3982         radeon_atombios_fini(rdev);
3983         kfree(rdev->bios);
3984         rdev->bios = NULL;
3985 }
3986
3987 /*
3988  * Due to how kexec works, it can leave the hw fully initialised when it
3989  * boots the new kernel. However doing our init sequence with the CP and
3990  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3991  * do some quick sanity checks and restore sane values to avoid this
3992  * problem.
3993  */
3994 void r100_restore_sanity(struct radeon_device *rdev)
3995 {
3996         u32 tmp;
3997
3998         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3999         if (tmp) {
4000                 WREG32(RADEON_CP_CSQ_CNTL, 0);
4001         }
4002         tmp = RREG32(RADEON_CP_RB_CNTL);
4003         if (tmp) {
4004                 WREG32(RADEON_CP_RB_CNTL, 0);
4005         }
4006         tmp = RREG32(RADEON_SCRATCH_UMSK);
4007         if (tmp) {
4008                 WREG32(RADEON_SCRATCH_UMSK, 0);
4009         }
4010 }
4011
4012 int r100_init(struct radeon_device *rdev)
4013 {
4014         int r;
4015
4016         /* Register debugfs file specific to this group of asics */
4017         r100_debugfs(rdev);
4018         /* Disable VGA */
4019         r100_vga_render_disable(rdev);
4020         /* Initialize scratch registers */
4021         radeon_scratch_init(rdev);
4022         /* Initialize surface registers */
4023         radeon_surface_init(rdev);
4024         /* sanity check some register to avoid hangs like after kexec */
4025         r100_restore_sanity(rdev);
4026         /* TODO: disable VGA need to use VGA request */
4027         /* BIOS*/
4028         if (!radeon_get_bios(rdev)) {
4029                 if (ASIC_IS_AVIVO(rdev))
4030                         return -EINVAL;
4031         }
4032         if (rdev->is_atom_bios) {
4033                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4034                 return -EINVAL;
4035         } else {
4036                 r = radeon_combios_init(rdev);
4037                 if (r)
4038                         return r;
4039         }
4040         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4041         if (radeon_asic_reset(rdev)) {
4042                 dev_warn(rdev->dev,
4043                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4044                         RREG32(R_000E40_RBBM_STATUS),
4045                         RREG32(R_0007C0_CP_STAT));
4046         }
4047         /* check if cards are posted or not */
4048         if (radeon_boot_test_post_card(rdev) == false)
4049                 return -EINVAL;
4050         /* Set asic errata */
4051         r100_errata(rdev);
4052         /* Initialize clocks */
4053         radeon_get_clock_info(rdev->ddev);
4054         /* initialize AGP */
4055         if (rdev->flags & RADEON_IS_AGP) {
4056                 r = radeon_agp_init(rdev);
4057                 if (r) {
4058                         radeon_agp_disable(rdev);
4059                 }
4060         }
4061         /* initialize VRAM */
4062         r100_mc_init(rdev);
4063         /* Fence driver */
4064         r = radeon_fence_driver_init(rdev);
4065         if (r)
4066                 return r;
4067         /* Memory manager */
4068         r = radeon_bo_init(rdev);
4069         if (r)
4070                 return r;
4071         if (rdev->flags & RADEON_IS_PCI) {
4072                 r = r100_pci_gart_init(rdev);
4073                 if (r)
4074                         return r;
4075         }
4076         r100_set_safe_registers(rdev);
4077
4078         /* Initialize power management */
4079         radeon_pm_init(rdev);
4080
4081         rdev->accel_working = true;
4082         r = r100_startup(rdev);
4083         if (r) {
4084                 /* Somethings want wront with the accel init stop accel */
4085                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4086                 r100_cp_fini(rdev);
4087                 radeon_wb_fini(rdev);
4088                 radeon_ib_pool_fini(rdev);
4089                 radeon_irq_kms_fini(rdev);
4090                 if (rdev->flags & RADEON_IS_PCI)
4091                         r100_pci_gart_fini(rdev);
4092                 rdev->accel_working = false;
4093         }
4094         return 0;
4095 }
4096
4097 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4098 {
4099         unsigned long flags;
4100         uint32_t ret;
4101
4102         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4103         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4104         ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4105         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4106         return ret;
4107 }
4108
4109 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4110 {
4111         unsigned long flags;
4112
4113         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4114         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4115         writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4116         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4117 }
4118
4119 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4120 {
4121         if (reg < rdev->rio_mem_size)
4122                 return ioread32(rdev->rio_mem + reg);
4123         else {
4124                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4125                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4126         }
4127 }
4128
4129 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4130 {
4131         if (reg < rdev->rio_mem_size)
4132                 iowrite32(v, rdev->rio_mem + reg);
4133         else {
4134                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4135                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4136         }
4137 }