drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r100d.h"
  36 #include "rs100d.h"
  37 #include "rv200d.h"
  38 #include "rv250d.h"
  39 #include "atom.h"
  40
  41 #include <linux/firmware.h>
  42 #include <linux/module.h>
  43
  44 #include "r100_reg_safe.h"
  45 #include "rn50_reg_safe.h"
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_R200           "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_R300           "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_R420           "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_RS690          "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_RS600          "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_R520           "/*(DEBLOBBED)*/"
  55
  56 /*(DEBLOBBED)*/
  57
  58 #include "r100_track.h"
  59
  60 /* This files gather functions specifics to:
  61  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  62  * and others in some cases.
  63  */
  64
  65 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  66 {
  67         if (crtc == 0) {
  68                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  69                         return true;
  70                 else
  71                         return false;
  72         } else {
  73                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  74                         return true;
  75                 else
  76                         return false;
  77         }
  78 }
  79
  80 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  81 {
  82         u32 vline1, vline2;
  83
  84         if (crtc == 0) {
  85                 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  86                 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  87         } else {
  88                 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  89                 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  90         }
  91         if (vline1 != vline2)
  92                 return true;
  93         else
  94                 return false;
  95 }
  96
  97 /**
  98  * r100_wait_for_vblank - vblank wait asic callback.
  99  *
 100  * @rdev: radeon_device pointer
 101  * @crtc: crtc to wait for vblank on
 102  *
 103  * Wait for vblank on the requested crtc (r1xx-r4xx).
 104  */
 105 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 106 {
 107         unsigned i = 0;
 108
 109         if (crtc >= rdev->num_crtc)
 110                 return;
 111
 112         if (crtc == 0) {
 113                 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
 114                         return;
 115         } else {
 116                 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
 117                         return;
 118         }
 119
 120         /* depending on when we hit vblank, we may be close to active; if so,
 121          * wait for another frame.
 122          */
 123         while (r100_is_in_vblank(rdev, crtc)) {
 124                 if (i++ % 100 == 0) {
 125                         if (!r100_is_counter_moving(rdev, crtc))
 126                                 break;
 127                 }
 128         }
 129
 130         while (!r100_is_in_vblank(rdev, crtc)) {
 131                 if (i++ % 100 == 0) {
 132                         if (!r100_is_counter_moving(rdev, crtc))
 133                                 break;
 134                 }
 135         }
 136 }
 137
 138 /**
 139  * r100_page_flip - pageflip callback.
 140  *
 141  * @rdev: radeon_device pointer
 142  * @crtc_id: crtc to cleanup pageflip on
 143  * @crtc_base: new address of the crtc (GPU MC address)
 144  *
 145  * Does the actual pageflip (r1xx-r4xx).
 146  * During vblank we take the crtc lock and wait for the update_pending
 147  * bit to go high, when it does, we release the lock, and allow the
 148  * double buffered update to take place.
 149  */
 150 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
 151 {
 152         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 153         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 154         int i;
 155
 156         /* Lock the graphics update lock */
 157         /* update the scanout addresses */
 158         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 159
 160         /* Wait for update_pending to go high. */
 161         for (i = 0; i < rdev->usec_timeout; i++) {
 162                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 163                         break;
 164                 udelay(1);
 165         }
 166         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 167
 168         /* Unlock the lock, so double-buffering can take place inside vblank */
 169         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 170         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 171
 172 }
 173
 174 /**
 175  * r100_page_flip_pending - check if page flip is still pending
 176  *
 177  * @rdev: radeon_device pointer
 178  * @crtc_id: crtc to check
 179  *
 180  * Check if the last pagefilp is still pending (r1xx-r4xx).
 181  * Returns the current update pending status.
 182  */
 183 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 184 {
 185         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 186
 187         /* Return current update_pending status: */
 188         return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
 189                 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
 190 }
 191
 192 /**
 193  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 194  *
 195  * @rdev: radeon_device pointer
 196  *
 197  * Look up the optimal power state based on the
 198  * current state of the GPU (r1xx-r5xx).
 199  * Used for dynpm only.
 200  */
 201 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 202 {
 203         int i;
 204         rdev->pm.dynpm_can_upclock = true;
 205         rdev->pm.dynpm_can_downclock = true;
 206
 207         switch (rdev->pm.dynpm_planned_action) {
 208         case DYNPM_ACTION_MINIMUM:
 209                 rdev->pm.requested_power_state_index = 0;
 210                 rdev->pm.dynpm_can_downclock = false;
 211                 break;
 212         case DYNPM_ACTION_DOWNCLOCK:
 213                 if (rdev->pm.current_power_state_index == 0) {
 214                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 215                         rdev->pm.dynpm_can_downclock = false;
 216                 } else {
 217                         if (rdev->pm.active_crtc_count > 1) {
 218                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 219                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 220                                                 continue;
 221                                         else if (i >= rdev->pm.current_power_state_index) {
 222                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 223                                                 break;
 224                                         } else {
 225                                                 rdev->pm.requested_power_state_index = i;
 226                                                 break;
 227                                         }
 228                                 }
 229                         } else
 230                                 rdev->pm.requested_power_state_index =
 231                                         rdev->pm.current_power_state_index - 1;
 232                 }
 233                 /* don't use the power state if crtcs are active and no display flag is set */
 234                 if ((rdev->pm.active_crtc_count > 0) &&
 235                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 236                      RADEON_PM_MODE_NO_DISPLAY)) {
 237                         rdev->pm.requested_power_state_index++;
 238                 }
 239                 break;
 240         case DYNPM_ACTION_UPCLOCK:
 241                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 242                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 243                         rdev->pm.dynpm_can_upclock = false;
 244                 } else {
 245                         if (rdev->pm.active_crtc_count > 1) {
 246                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 247                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 248                                                 continue;
 249                                         else if (i <= rdev->pm.current_power_state_index) {
 250                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 251                                                 break;
 252                                         } else {
 253                                                 rdev->pm.requested_power_state_index = i;
 254                                                 break;
 255                                         }
 256                                 }
 257                         } else
 258                                 rdev->pm.requested_power_state_index =
 259                                         rdev->pm.current_power_state_index + 1;
 260                 }
 261                 break;
 262         case DYNPM_ACTION_DEFAULT:
 263                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 264                 rdev->pm.dynpm_can_upclock = false;
 265                 break;
 266         case DYNPM_ACTION_NONE:
 267         default:
 268                 DRM_ERROR("Requested mode for not defined action\n");
 269                 return;
 270         }
 271         /* only one clock mode per power state */
 272         rdev->pm.requested_clock_mode_index = 0;
 273
 274         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 275                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 276                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 277                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 278                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 279                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 280                   pcie_lanes);
 281 }
 282
 283 /**
 284  * r100_pm_init_profile - Initialize power profiles callback.
 285  *
 286  * @rdev: radeon_device pointer
 287  *
 288  * Initialize the power states used in profile mode
 289  * (r1xx-r3xx).
 290  * Used for profile mode only.
 291  */
 292 void r100_pm_init_profile(struct radeon_device *rdev)
 293 {
 294         /* default */
 295         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 296         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 297         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 298         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 299         /* low sh */
 300         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 301         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 303         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 304         /* mid sh */
 305         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 306         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 308         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 309         /* high sh */
 310         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 311         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 314         /* low mh */
 315         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 316         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 317         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 318         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 319         /* mid mh */
 320         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 321         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 322         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 323         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 324         /* high mh */
 325         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 326         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 327         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 328         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 329 }
 330
 331 /**
 332  * r100_pm_misc - set additional pm hw parameters callback.
 333  *
 334  * @rdev: radeon_device pointer
 335  *
 336  * Set non-clock parameters associated with a power state
 337  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 338  */
 339 void r100_pm_misc(struct radeon_device *rdev)
 340 {
 341         int requested_index = rdev->pm.requested_power_state_index;
 342         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 343         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 344         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 345
 346         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 347                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 348                         tmp = RREG32(voltage->gpio.reg);
 349                         if (voltage->active_high)
 350                                 tmp |= voltage->gpio.mask;
 351                         else
 352                                 tmp &= ~(voltage->gpio.mask);
 353                         WREG32(voltage->gpio.reg, tmp);
 354                         if (voltage->delay)
 355                                 udelay(voltage->delay);
 356                 } else {
 357                         tmp = RREG32(voltage->gpio.reg);
 358                         if (voltage->active_high)
 359                                 tmp &= ~voltage->gpio.mask;
 360                         else
 361                                 tmp |= voltage->gpio.mask;
 362                         WREG32(voltage->gpio.reg, tmp);
 363                         if (voltage->delay)
 364                                 udelay(voltage->delay);
 365                 }
 366         }
 367
 368         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 369         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 370         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 371         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 372         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 373         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 374                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 375                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 376                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 377                 else
 378                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 379                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 380                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 381                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 382                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 383         } else
 384                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 385
 386         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 387                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 388                 if (voltage->delay) {
 389                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 390                         switch (voltage->delay) {
 391                         case 33:
 392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 393                                 break;
 394                         case 66:
 395                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 396                                 break;
 397                         case 99:
 398                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 399                                 break;
 400                         case 132:
 401                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 402                                 break;
 403                         }
 404                 } else
 405                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 406         } else
 407                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 408
 409         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 410                 sclk_cntl &= ~FORCE_HDP;
 411         else
 412                 sclk_cntl |= FORCE_HDP;
 413
 414         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 415         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 416         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 417
 418         /* set pcie lanes */
 419         if ((rdev->flags & RADEON_IS_PCIE) &&
 420             !(rdev->flags & RADEON_IS_IGP) &&
 421             rdev->asic->pm.set_pcie_lanes &&
 422             (ps->pcie_lanes !=
 423              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 424                 radeon_set_pcie_lanes(rdev,
 425                                       ps->pcie_lanes);
 426                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 427         }
 428 }
 429
 430 /**
 431  * r100_pm_prepare - pre-power state change callback.
 432  *
 433  * @rdev: radeon_device pointer
 434  *
 435  * Prepare for a power state change (r1xx-r4xx).
 436  */
 437 void r100_pm_prepare(struct radeon_device *rdev)
 438 {
 439         struct drm_device *ddev = rdev->ddev;
 440         struct drm_crtc *crtc;
 441         struct radeon_crtc *radeon_crtc;
 442         u32 tmp;
 443
 444         /* disable any active CRTCs */
 445         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 446                 radeon_crtc = to_radeon_crtc(crtc);
 447                 if (radeon_crtc->enabled) {
 448                         if (radeon_crtc->crtc_id) {
 449                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 450                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 451                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 452                         } else {
 453                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 454                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 455                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 456                         }
 457                 }
 458         }
 459 }
 460
 461 /**
 462  * r100_pm_finish - post-power state change callback.
 463  *
 464  * @rdev: radeon_device pointer
 465  *
 466  * Clean up after a power state change (r1xx-r4xx).
 467  */
 468 void r100_pm_finish(struct radeon_device *rdev)
 469 {
 470         struct drm_device *ddev = rdev->ddev;
 471         struct drm_crtc *crtc;
 472         struct radeon_crtc *radeon_crtc;
 473         u32 tmp;
 474
 475         /* enable any active CRTCs */
 476         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 477                 radeon_crtc = to_radeon_crtc(crtc);
 478                 if (radeon_crtc->enabled) {
 479                         if (radeon_crtc->crtc_id) {
 480                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 481                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 482                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 483                         } else {
 484                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 485                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 486                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 487                         }
 488                 }
 489         }
 490 }
 491
 492 /**
 493  * r100_gui_idle - gui idle callback.
 494  *
 495  * @rdev: radeon_device pointer
 496  *
 497  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 498  * Returns true if idle, false if not.
 499  */
 500 bool r100_gui_idle(struct radeon_device *rdev)
 501 {
 502         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 503                 return false;
 504         else
 505                 return true;
 506 }
 507
 508 /* hpd for digital panel detect/disconnect */
 509 /**
 510  * r100_hpd_sense - hpd sense callback.
 511  *
 512  * @rdev: radeon_device pointer
 513  * @hpd: hpd (hotplug detect) pin
 514  *
 515  * Checks if a digital monitor is connected (r1xx-r4xx).
 516  * Returns true if connected, false if not connected.
 517  */
 518 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 519 {
 520         bool connected = false;
 521
 522         switch (hpd) {
 523         case RADEON_HPD_1:
 524                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 525                         connected = true;
 526                 break;
 527         case RADEON_HPD_2:
 528                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 529                         connected = true;
 530                 break;
 531         default:
 532                 break;
 533         }
 534         return connected;
 535 }
 536
 537 /**
 538  * r100_hpd_set_polarity - hpd set polarity callback.
 539  *
 540  * @rdev: radeon_device pointer
 541  * @hpd: hpd (hotplug detect) pin
 542  *
 543  * Set the polarity of the hpd pin (r1xx-r4xx).
 544  */
 545 void r100_hpd_set_polarity(struct radeon_device *rdev,
 546                            enum radeon_hpd_id hpd)
 547 {
 548         u32 tmp;
 549         bool connected = r100_hpd_sense(rdev, hpd);
 550
 551         switch (hpd) {
 552         case RADEON_HPD_1:
 553                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 554                 if (connected)
 555                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 556                 else
 557                         tmp |= RADEON_FP_DETECT_INT_POL;
 558                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 559                 break;
 560         case RADEON_HPD_2:
 561                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 562                 if (connected)
 563                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 564                 else
 565                         tmp |= RADEON_FP2_DETECT_INT_POL;
 566                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 567                 break;
 568         default:
 569                 break;
 570         }
 571 }
 572
 573 /**
 574  * r100_hpd_init - hpd setup callback.
 575  *
 576  * @rdev: radeon_device pointer
 577  *
 578  * Setup the hpd pins used by the card (r1xx-r4xx).
 579  * Set the polarity, and enable the hpd interrupts.
 580  */
 581 void r100_hpd_init(struct radeon_device *rdev)
 582 {
 583         struct drm_device *dev = rdev->ddev;
 584         struct drm_connector *connector;
 585         unsigned enable = 0;
 586
 587         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 588                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 589                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 590                         enable |= 1 << radeon_connector->hpd.hpd;
 591                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 592         }
 593         radeon_irq_kms_enable_hpd(rdev, enable);
 594 }
 595
 596 /**
 597  * r100_hpd_fini - hpd tear down callback.
 598  *
 599  * @rdev: radeon_device pointer
 600  *
 601  * Tear down the hpd pins used by the card (r1xx-r4xx).
 602  * Disable the hpd interrupts.
 603  */
 604 void r100_hpd_fini(struct radeon_device *rdev)
 605 {
 606         struct drm_device *dev = rdev->ddev;
 607         struct drm_connector *connector;
 608         unsigned disable = 0;
 609
 610         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 611                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 612                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 613                         disable |= 1 << radeon_connector->hpd.hpd;
 614         }
 615         radeon_irq_kms_disable_hpd(rdev, disable);
 616 }
 617
 618 /*
 619  * PCI GART
 620  */
 621 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 622 {
 623         /* TODO: can we do somethings here ? */
 624         /* It seems hw only cache one entry so we should discard this
 625          * entry otherwise if first GPU GART read hit this entry it
 626          * could end up in wrong address. */
 627 }
 628
 629 int r100_pci_gart_init(struct radeon_device *rdev)
 630 {
 631         int r;
 632
 633         if (rdev->gart.ptr) {
 634                 WARN(1, "R100 PCI GART already initialized\n");
 635                 return 0;
 636         }
 637         /* Initialize common gart structure */
 638         r = radeon_gart_init(rdev);
 639         if (r)
 640                 return r;
 641         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 642         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 643         rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 644         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 645         return radeon_gart_table_ram_alloc(rdev);
 646 }
 647
 648 int r100_pci_gart_enable(struct radeon_device *rdev)
 649 {
 650         uint32_t tmp;
 651
 652         /* discard memory request outside of configured range */
 653         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 654         WREG32(RADEON_AIC_CNTL, tmp);
 655         /* set address range for PCI address translate */
 656         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 657         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 658         /* set PCI GART page-table base address */
 659         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 660         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 661         WREG32(RADEON_AIC_CNTL, tmp);
 662         r100_pci_gart_tlb_flush(rdev);
 663         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 664                  (unsigned)(rdev->mc.gtt_size >> 20),
 665                  (unsigned long long)rdev->gart.table_addr);
 666         rdev->gart.ready = true;
 667         return 0;
 668 }
 669
 670 void r100_pci_gart_disable(struct radeon_device *rdev)
 671 {
 672         uint32_t tmp;
 673
 674         /* discard memory request outside of configured range */
 675         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 676         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 677         WREG32(RADEON_AIC_LO_ADDR, 0);
 678         WREG32(RADEON_AIC_HI_ADDR, 0);
 679 }
 680
 681 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
 682 {
 683         return addr;
 684 }
 685
 686 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
 687                             uint64_t entry)
 688 {
 689         u32 *gtt = rdev->gart.ptr;
 690         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 691 }
 692
 693 void r100_pci_gart_fini(struct radeon_device *rdev)
 694 {
 695         radeon_gart_fini(rdev);
 696         r100_pci_gart_disable(rdev);
 697         radeon_gart_table_ram_free(rdev);
 698 }
 699
 700 int r100_irq_set(struct radeon_device *rdev)
 701 {
 702         uint32_t tmp = 0;
 703
 704         if (!rdev->irq.installed) {
 705                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 706                 WREG32(R_000040_GEN_INT_CNTL, 0);
 707                 return -EINVAL;
 708         }
 709         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 710                 tmp |= RADEON_SW_INT_ENABLE;
 711         }
 712         if (rdev->irq.crtc_vblank_int[0] ||
 713             atomic_read(&rdev->irq.pflip[0])) {
 714                 tmp |= RADEON_CRTC_VBLANK_MASK;
 715         }
 716         if (rdev->irq.crtc_vblank_int[1] ||
 717             atomic_read(&rdev->irq.pflip[1])) {
 718                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 719         }
 720         if (rdev->irq.hpd[0]) {
 721                 tmp |= RADEON_FP_DETECT_MASK;
 722         }
 723         if (rdev->irq.hpd[1]) {
 724                 tmp |= RADEON_FP2_DETECT_MASK;
 725         }
 726         WREG32(RADEON_GEN_INT_CNTL, tmp);
 727
 728         /* read back to post the write */
 729         RREG32(RADEON_GEN_INT_CNTL);
 730
 731         return 0;
 732 }
 733
 734 void r100_irq_disable(struct radeon_device *rdev)
 735 {
 736         u32 tmp;
 737
 738         WREG32(R_000040_GEN_INT_CNTL, 0);
 739         /* Wait and acknowledge irq */
 740         mdelay(1);
 741         tmp = RREG32(R_000044_GEN_INT_STATUS);
 742         WREG32(R_000044_GEN_INT_STATUS, tmp);
 743 }
 744
 745 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 746 {
 747         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 748         uint32_t irq_mask = RADEON_SW_INT_TEST |
 749                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 750                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 751
 752         if (irqs) {
 753                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 754         }
 755         return irqs & irq_mask;
 756 }
 757
 758 int r100_irq_process(struct radeon_device *rdev)
 759 {
 760         uint32_t status, msi_rearm;
 761         bool queue_hotplug = false;
 762
 763         status = r100_irq_ack(rdev);
 764         if (!status) {
 765                 return IRQ_NONE;
 766         }
 767         if (rdev->shutdown) {
 768                 return IRQ_NONE;
 769         }
 770         while (status) {
 771                 /* SW interrupt */
 772                 if (status & RADEON_SW_INT_TEST) {
 773                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 774                 }
 775                 /* Vertical blank interrupts */
 776                 if (status & RADEON_CRTC_VBLANK_STAT) {
 777                         if (rdev->irq.crtc_vblank_int[0]) {
 778                                 drm_handle_vblank(rdev->ddev, 0);
 779                                 rdev->pm.vblank_sync = true;
 780                                 wake_up(&rdev->irq.vblank_queue);
 781                         }
 782                         if (atomic_read(&rdev->irq.pflip[0]))
 783                                 radeon_crtc_handle_vblank(rdev, 0);
 784                 }
 785                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 786                         if (rdev->irq.crtc_vblank_int[1]) {
 787                                 drm_handle_vblank(rdev->ddev, 1);
 788                                 rdev->pm.vblank_sync = true;
 789                                 wake_up(&rdev->irq.vblank_queue);
 790                         }
 791                         if (atomic_read(&rdev->irq.pflip[1]))
 792                                 radeon_crtc_handle_vblank(rdev, 1);
 793                 }
 794                 if (status & RADEON_FP_DETECT_STAT) {
 795                         queue_hotplug = true;
 796                         DRM_DEBUG("HPD1\n");
 797                 }
 798                 if (status & RADEON_FP2_DETECT_STAT) {
 799                         queue_hotplug = true;
 800                         DRM_DEBUG("HPD2\n");
 801                 }
 802                 status = r100_irq_ack(rdev);
 803         }
 804         if (queue_hotplug)
 805                 schedule_delayed_work(&rdev->hotplug_work, 0);
 806         if (rdev->msi_enabled) {
 807                 switch (rdev->family) {
 808                 case CHIP_RS400:
 809                 case CHIP_RS480:
 810                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 811                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 812                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 813                         break;
 814                 default:
 815                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 816                         break;
 817                 }
 818         }
 819         return IRQ_HANDLED;
 820 }
 821
 822 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 823 {
 824         if (crtc == 0)
 825                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 826         else
 827                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 828 }
 829
 830 /**
 831  * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
 832  * rdev: radeon device structure
 833  * ring: ring buffer struct for emitting packets
 834  */
 835 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
 836 {
 837         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 838         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 839                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 840         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 841         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 842 }
 843
 844 /* Who ever call radeon_fence_emit should call ring_lock and ask
 845  * for enough space (today caller are ib schedule and buffer move) */
 846 void r100_fence_ring_emit(struct radeon_device *rdev,
 847                           struct radeon_fence *fence)
 848 {
 849         struct radeon_ring *ring = &rdev->ring[fence->ring];
 850
 851         /* We have to make sure that caches are flushed before
 852          * CPU might read something from VRAM. */
 853         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 854         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 855         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 856         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 857         /* Wait until IDLE & CLEAN */
 858         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 859         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 860         r100_ring_hdp_flush(rdev, ring);
 861         /* Emit fence sequence & fire IRQ */
 862         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 863         radeon_ring_write(ring, fence->seq);
 864         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 865         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 866 }
 867
 868 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
 869                               struct radeon_ring *ring,
 870                               struct radeon_semaphore *semaphore,
 871                               bool emit_wait)
 872 {
 873         /* Unused on older asics, since we don't have semaphores or multiple rings */
 874         BUG();
 875         return false;
 876 }
 877
 878 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
 879                                     uint64_t src_offset,
 880                                     uint64_t dst_offset,
 881                                     unsigned num_gpu_pages,
 882                                     struct reservation_object *resv)
 883 {
 884         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 885         struct radeon_fence *fence;
 886         uint32_t cur_pages;
 887         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 888         uint32_t pitch;
 889         uint32_t stride_pixels;
 890         unsigned ndw;
 891         int num_loops;
 892         int r = 0;
 893
 894         /* radeon limited to 16k stride */
 895         stride_bytes &= 0x3fff;
 896         /* radeon pitch is /64 */
 897         pitch = stride_bytes / 64;
 898         stride_pixels = stride_bytes / 4;
 899         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 900
 901         /* Ask for enough room for blit + flush + fence */
 902         ndw = 64 + (10 * num_loops);
 903         r = radeon_ring_lock(rdev, ring, ndw);
 904         if (r) {
 905                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 906                 return ERR_PTR(-EINVAL);
 907         }
 908         while (num_gpu_pages > 0) {
 909                 cur_pages = num_gpu_pages;
 910                 if (cur_pages > 8191) {
 911                         cur_pages = 8191;
 912                 }
 913                 num_gpu_pages -= cur_pages;
 914
 915                 /* pages are in Y direction - height
 916                    page width in X direction - width */
 917                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 918                 radeon_ring_write(ring,
 919                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 920                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 921                                   RADEON_GMC_SRC_CLIPPING |
 922                                   RADEON_GMC_DST_CLIPPING |
 923                                   RADEON_GMC_BRUSH_NONE |
 924                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 925                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 926                                   RADEON_ROP3_S |
 927                                   RADEON_DP_SRC_SOURCE_MEMORY |
 928                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 929                                   RADEON_GMC_WR_MSK_DIS);
 930                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 931                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 932                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 933                 radeon_ring_write(ring, 0);
 934                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 935                 radeon_ring_write(ring, num_gpu_pages);
 936                 radeon_ring_write(ring, num_gpu_pages);
 937                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 938         }
 939         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 940         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 941         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 942         radeon_ring_write(ring,
 943                           RADEON_WAIT_2D_IDLECLEAN |
 944                           RADEON_WAIT_HOST_IDLECLEAN |
 945                           RADEON_WAIT_DMA_GUI_IDLE);
 946         r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
 947         if (r) {
 948                 radeon_ring_unlock_undo(rdev, ring);
 949                 return ERR_PTR(r);
 950         }
 951         radeon_ring_unlock_commit(rdev, ring, false);
 952         return fence;
 953 }
 954
 955 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 956 {
 957         unsigned i;
 958         u32 tmp;
 959
 960         for (i = 0; i < rdev->usec_timeout; i++) {
 961                 tmp = RREG32(R_000E40_RBBM_STATUS);
 962                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 963                         return 0;
 964                 }
 965                 udelay(1);
 966         }
 967         return -1;
 968 }
 969
 970 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 971 {
 972         int r;
 973
 974         r = radeon_ring_lock(rdev, ring, 2);
 975         if (r) {
 976                 return;
 977         }
 978         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 979         radeon_ring_write(ring,
 980                           RADEON_ISYNC_ANY2D_IDLE3D |
 981                           RADEON_ISYNC_ANY3D_IDLE2D |
 982                           RADEON_ISYNC_WAIT_IDLEGUI |
 983                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 984         radeon_ring_unlock_commit(rdev, ring, false);
 985 }
 986
 987
 988 /* Load the microcode for the CP */
 989 static int r100_cp_init_microcode(struct radeon_device *rdev)
 990 {
 991         const char *fw_name = NULL;
 992         int err;
 993
 994         DRM_DEBUG_KMS("\n");
 995
 996         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 997             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 998             (rdev->family == CHIP_RS200)) {
 999                 DRM_INFO("Loading R100 Microcode\n");
1000                 fw_name = FIRMWARE_R100;
1001         } else if ((rdev->family == CHIP_R200) ||
1002                    (rdev->family == CHIP_RV250) ||
1003                    (rdev->family == CHIP_RV280) ||
1004                    (rdev->family == CHIP_RS300)) {
1005                 DRM_INFO("Loading R200 Microcode\n");
1006                 fw_name = FIRMWARE_R200;
1007         } else if ((rdev->family == CHIP_R300) ||
1008                    (rdev->family == CHIP_R350) ||
1009                    (rdev->family == CHIP_RV350) ||
1010                    (rdev->family == CHIP_RV380) ||
1011                    (rdev->family == CHIP_RS400) ||
1012                    (rdev->family == CHIP_RS480)) {
1013                 DRM_INFO("Loading R300 Microcode\n");
1014                 fw_name = FIRMWARE_R300;
1015         } else if ((rdev->family == CHIP_R420) ||
1016                    (rdev->family == CHIP_R423) ||
1017                    (rdev->family == CHIP_RV410)) {
1018                 DRM_INFO("Loading R400 Microcode\n");
1019                 fw_name = FIRMWARE_R420;
1020         } else if ((rdev->family == CHIP_RS690) ||
1021                    (rdev->family == CHIP_RS740)) {
1022                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1023                 fw_name = FIRMWARE_RS690;
1024         } else if (rdev->family == CHIP_RS600) {
1025                 DRM_INFO("Loading RS600 Microcode\n");
1026                 fw_name = FIRMWARE_RS600;
1027         } else if ((rdev->family == CHIP_RV515) ||
1028                    (rdev->family == CHIP_R520) ||
1029                    (rdev->family == CHIP_RV530) ||
1030                    (rdev->family == CHIP_R580) ||
1031                    (rdev->family == CHIP_RV560) ||
1032                    (rdev->family == CHIP_RV570)) {
1033                 DRM_INFO("Loading R500 Microcode\n");
1034                 fw_name = FIRMWARE_R520;
1035         }
1036
1037         err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
1038         if (err) {
1039                 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
1040         } else if (rdev->me_fw->size % 8) {
1041                 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1042                        rdev->me_fw->size, fw_name);
1043                 err = -EINVAL;
1044                 release_firmware(rdev->me_fw);
1045                 rdev->me_fw = NULL;
1046         }
1047         return err;
1048 }
1049
1050 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1051                       struct radeon_ring *ring)
1052 {
1053         u32 rptr;
1054
1055         if (rdev->wb.enabled)
1056                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1057         else
1058                 rptr = RREG32(RADEON_CP_RB_RPTR);
1059
1060         return rptr;
1061 }
1062
1063 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1064                       struct radeon_ring *ring)
1065 {
1066         return RREG32(RADEON_CP_RB_WPTR);
1067 }
1068
1069 void r100_gfx_set_wptr(struct radeon_device *rdev,
1070                        struct radeon_ring *ring)
1071 {
1072         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1073         (void)RREG32(RADEON_CP_RB_WPTR);
1074 }
1075
1076 static void r100_cp_load_microcode(struct radeon_device *rdev)
1077 {
1078         const __be32 *fw_data;
1079         int i, size;
1080
1081         if (r100_gui_wait_for_idle(rdev)) {
1082                 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1083         }
1084
1085         if (rdev->me_fw) {
1086                 size = rdev->me_fw->size / 4;
1087                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1088                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1089                 for (i = 0; i < size; i += 2) {
1090                         WREG32(RADEON_CP_ME_RAM_DATAH,
1091                                be32_to_cpup(&fw_data[i]));
1092                         WREG32(RADEON_CP_ME_RAM_DATAL,
1093                                be32_to_cpup(&fw_data[i + 1]));
1094                 }
1095         }
1096 }
1097
1098 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1099 {
1100         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1101         unsigned rb_bufsz;
1102         unsigned rb_blksz;
1103         unsigned max_fetch;
1104         unsigned pre_write_timer;
1105         unsigned pre_write_limit;
1106         unsigned indirect2_start;
1107         unsigned indirect1_start;
1108         uint32_t tmp;
1109         int r;
1110
1111         if (r100_debugfs_cp_init(rdev)) {
1112                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1113         }
1114         if (!rdev->me_fw) {
1115                 r = r100_cp_init_microcode(rdev);
1116                 if (r) {
1117                         DRM_ERROR("Failed to load firmware!\n");
1118                         return r;
1119                 }
1120         }
1121
1122         /* Align ring size */
1123         rb_bufsz = order_base_2(ring_size / 8);
1124         ring_size = (1 << (rb_bufsz + 1)) * 4;
1125         r100_cp_load_microcode(rdev);
1126         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1127                              RADEON_CP_PACKET2);
1128         if (r) {
1129                 return r;
1130         }
1131         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1132          * the rptr copy in system ram */
1133         rb_blksz = 9;
1134         /* cp will read 128bytes at a time (4 dwords) */
1135         max_fetch = 1;
1136         ring->align_mask = 16 - 1;
1137         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1138         pre_write_timer = 64;
1139         /* Force CP_RB_WPTR write if written more than one time before the
1140          * delay expire
1141          */
1142         pre_write_limit = 0;
1143         /* Setup the cp cache like this (cache size is 96 dwords) :
1144          *      RING            0  to 15
1145          *      INDIRECT1       16 to 79
1146          *      INDIRECT2       80 to 95
1147          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1148          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1149          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1150          * Idea being that most of the gpu cmd will be through indirect1 buffer
1151          * so it gets the bigger cache.
1152          */
1153         indirect2_start = 80;
1154         indirect1_start = 16;
1155         /* cp setup */
1156         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1157         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1158                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1159                REG_SET(RADEON_MAX_FETCH, max_fetch));
1160 #ifdef __BIG_ENDIAN
1161         tmp |= RADEON_BUF_SWAP_32BIT;
1162 #endif
1163         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1164
1165         /* Set ring address */
1166         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1167         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1168         /* Force read & write ptr to 0 */
1169         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1170         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1171         ring->wptr = 0;
1172         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1173
1174         /* set the wb address whether it's enabled or not */
1175         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1176                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1177         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1178
1179         if (rdev->wb.enabled)
1180                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1181         else {
1182                 tmp |= RADEON_RB_NO_UPDATE;
1183                 WREG32(R_000770_SCRATCH_UMSK, 0);
1184         }
1185
1186         WREG32(RADEON_CP_RB_CNTL, tmp);
1187         udelay(10);
1188         /* Set cp mode to bus mastering & enable cp*/
1189         WREG32(RADEON_CP_CSQ_MODE,
1190                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1191                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1192         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1193         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1194         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1195
1196         /* at this point everything should be setup correctly to enable master */
1197         pci_set_master(rdev->pdev);
1198
1199         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1200         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1201         if (r) {
1202                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1203                 return r;
1204         }
1205         ring->ready = true;
1206         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1207
1208         if (!ring->rptr_save_reg /* not resuming from suspend */
1209             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1210                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1211                 if (r) {
1212                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1213                         ring->rptr_save_reg = 0;
1214                 }
1215         }
1216         return 0;
1217 }
1218
1219 void r100_cp_fini(struct radeon_device *rdev)
1220 {
1221         if (r100_cp_wait_for_idle(rdev)) {
1222                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1223         }
1224         /* Disable ring */
1225         r100_cp_disable(rdev);
1226         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1227         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1228         DRM_INFO("radeon: cp finalized\n");
1229 }
1230
1231 void r100_cp_disable(struct radeon_device *rdev)
1232 {
1233         /* Disable ring */
1234         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1235         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1236         WREG32(RADEON_CP_CSQ_MODE, 0);
1237         WREG32(RADEON_CP_CSQ_CNTL, 0);
1238         WREG32(R_000770_SCRATCH_UMSK, 0);
1239         if (r100_gui_wait_for_idle(rdev)) {
1240                 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1241         }
1242 }
1243
1244 /*
1245  * CS functions
1246  */
1247 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1248                             struct radeon_cs_packet *pkt,
1249                             unsigned idx,
1250                             unsigned reg)
1251 {
1252         int r;
1253         u32 tile_flags = 0;
1254         u32 tmp;
1255         struct radeon_bo_list *reloc;
1256         u32 value;
1257
1258         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1259         if (r) {
1260                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1261                           idx, reg);
1262                 radeon_cs_dump_packet(p, pkt);
1263                 return r;
1264         }
1265
1266         value = radeon_get_ib_value(p, idx);
1267         tmp = value & 0x003fffff;
1268         tmp += (((u32)reloc->gpu_offset) >> 10);
1269
1270         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1271                 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1272                         tile_flags |= RADEON_DST_TILE_MACRO;
1273                 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1274                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1275                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1276                                 radeon_cs_dump_packet(p, pkt);
1277                                 return -EINVAL;
1278                         }
1279                         tile_flags |= RADEON_DST_TILE_MICRO;
1280                 }
1281
1282                 tmp |= tile_flags;
1283                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1284         } else
1285                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1286         return 0;
1287 }
1288
1289 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1290                              struct radeon_cs_packet *pkt,
1291                              int idx)
1292 {
1293         unsigned c, i;
1294         struct radeon_bo_list *reloc;
1295         struct r100_cs_track *track;
1296         int r = 0;
1297         volatile uint32_t *ib;
1298         u32 idx_value;
1299
1300         ib = p->ib.ptr;
1301         track = (struct r100_cs_track *)p->track;
1302         c = radeon_get_ib_value(p, idx++) & 0x1F;
1303         if (c > 16) {
1304             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1305                       pkt->opcode);
1306             radeon_cs_dump_packet(p, pkt);
1307             return -EINVAL;
1308         }
1309         track->num_arrays = c;
1310         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1311                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1312                 if (r) {
1313                         DRM_ERROR("No reloc for packet3 %d\n",
1314                                   pkt->opcode);
1315                         radeon_cs_dump_packet(p, pkt);
1316                         return r;
1317                 }
1318                 idx_value = radeon_get_ib_value(p, idx);
1319                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1320
1321                 track->arrays[i + 0].esize = idx_value >> 8;
1322                 track->arrays[i + 0].robj = reloc->robj;
1323                 track->arrays[i + 0].esize &= 0x7F;
1324                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1325                 if (r) {
1326                         DRM_ERROR("No reloc for packet3 %d\n",
1327                                   pkt->opcode);
1328                         radeon_cs_dump_packet(p, pkt);
1329                         return r;
1330                 }
1331                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1332                 track->arrays[i + 1].robj = reloc->robj;
1333                 track->arrays[i + 1].esize = idx_value >> 24;
1334                 track->arrays[i + 1].esize &= 0x7F;
1335         }
1336         if (c & 1) {
1337                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1338                 if (r) {
1339                         DRM_ERROR("No reloc for packet3 %d\n",
1340                                           pkt->opcode);
1341                         radeon_cs_dump_packet(p, pkt);
1342                         return r;
1343                 }
1344                 idx_value = radeon_get_ib_value(p, idx);
1345                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1346                 track->arrays[i + 0].robj = reloc->robj;
1347                 track->arrays[i + 0].esize = idx_value >> 8;
1348                 track->arrays[i + 0].esize &= 0x7F;
1349         }
1350         return r;
1351 }
1352
1353 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1354                           struct radeon_cs_packet *pkt,
1355                           const unsigned *auth, unsigned n,
1356                           radeon_packet0_check_t check)
1357 {
1358         unsigned reg;
1359         unsigned i, j, m;
1360         unsigned idx;
1361         int r;
1362
1363         idx = pkt->idx + 1;
1364         reg = pkt->reg;
1365         /* Check that register fall into register range
1366          * determined by the number of entry (n) in the
1367          * safe register bitmap.
1368          */
1369         if (pkt->one_reg_wr) {
1370                 if ((reg >> 7) > n) {
1371                         return -EINVAL;
1372                 }
1373         } else {
1374                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1375                         return -EINVAL;
1376                 }
1377         }
1378         for (i = 0; i <= pkt->count; i++, idx++) {
1379                 j = (reg >> 7);
1380                 m = 1 << ((reg >> 2) & 31);
1381                 if (auth[j] & m) {
1382                         r = check(p, pkt, idx, reg);
1383                         if (r) {
1384                                 return r;
1385                         }
1386                 }
1387                 if (pkt->one_reg_wr) {
1388                         if (!(auth[j] & m)) {
1389                                 break;
1390                         }
1391                 } else {
1392                         reg += 4;
1393                 }
1394         }
1395         return 0;
1396 }
1397
1398 /**
1399  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1400  * @parser:             parser structure holding parsing context.
1401  *
1402  * Userspace sends a special sequence for VLINE waits.
1403  * PACKET0 - VLINE_START_END + value
1404  * PACKET0 - WAIT_UNTIL +_value
1405  * RELOC (P3) - crtc_id in reloc.
1406  *
1407  * This function parses this and relocates the VLINE START END
1408  * and WAIT UNTIL packets to the correct crtc.
1409  * It also detects a switched off crtc and nulls out the
1410  * wait in that case.
1411  */
1412 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1413 {
1414         struct drm_crtc *crtc;
1415         struct radeon_crtc *radeon_crtc;
1416         struct radeon_cs_packet p3reloc, waitreloc;
1417         int crtc_id;
1418         int r;
1419         uint32_t header, h_idx, reg;
1420         volatile uint32_t *ib;
1421
1422         ib = p->ib.ptr;
1423
1424         /* parse the wait until */
1425         r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1426         if (r)
1427                 return r;
1428
1429         /* check its a wait until and only 1 count */
1430         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1431             waitreloc.count != 0) {
1432                 DRM_ERROR("vline wait had illegal wait until segment\n");
1433                 return -EINVAL;
1434         }
1435
1436         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1437                 DRM_ERROR("vline wait had illegal wait until\n");
1438                 return -EINVAL;
1439         }
1440
1441         /* jump over the NOP */
1442         r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1443         if (r)
1444                 return r;
1445
1446         h_idx = p->idx - 2;
1447         p->idx += waitreloc.count + 2;
1448         p->idx += p3reloc.count + 2;
1449
1450         header = radeon_get_ib_value(p, h_idx);
1451         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1452         reg = R100_CP_PACKET0_GET_REG(header);
1453         crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1454         if (!crtc) {
1455                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1456                 return -ENOENT;
1457         }
1458         radeon_crtc = to_radeon_crtc(crtc);
1459         crtc_id = radeon_crtc->crtc_id;
1460
1461         if (!crtc->enabled) {
1462                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1463                 ib[h_idx + 2] = PACKET2(0);
1464                 ib[h_idx + 3] = PACKET2(0);
1465         } else if (crtc_id == 1) {
1466                 switch (reg) {
1467                 case AVIVO_D1MODE_VLINE_START_END:
1468                         header &= ~R300_CP_PACKET0_REG_MASK;
1469                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1470                         break;
1471                 case RADEON_CRTC_GUI_TRIG_VLINE:
1472                         header &= ~R300_CP_PACKET0_REG_MASK;
1473                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1474                         break;
1475                 default:
1476                         DRM_ERROR("unknown crtc reloc\n");
1477                         return -EINVAL;
1478                 }
1479                 ib[h_idx] = header;
1480                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int r100_get_vtx_size(uint32_t vtx_fmt)
1487 {
1488         int vtx_size;
1489         vtx_size = 2;
1490         /* ordered according to bits in spec */
1491         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1492                 vtx_size++;
1493         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1494                 vtx_size += 3;
1495         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1496                 vtx_size++;
1497         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1498                 vtx_size++;
1499         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1500                 vtx_size += 3;
1501         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1502                 vtx_size++;
1503         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1504                 vtx_size++;
1505         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1506                 vtx_size += 2;
1507         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1508                 vtx_size += 2;
1509         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1510                 vtx_size++;
1511         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1512                 vtx_size += 2;
1513         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1514                 vtx_size++;
1515         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1516                 vtx_size += 2;
1517         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1518                 vtx_size++;
1519         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1520                 vtx_size++;
1521         /* blend weight */
1522         if (vtx_fmt & (0x7 << 15))
1523                 vtx_size += (vtx_fmt >> 15) & 0x7;
1524         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1525                 vtx_size += 3;
1526         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1527                 vtx_size += 2;
1528         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1529                 vtx_size++;
1530         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1531                 vtx_size++;
1532         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1533                 vtx_size++;
1534         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1535                 vtx_size++;
1536         return vtx_size;
1537 }
1538
1539 static int r100_packet0_check(struct radeon_cs_parser *p,
1540                               struct radeon_cs_packet *pkt,
1541                               unsigned idx, unsigned reg)
1542 {
1543         struct radeon_bo_list *reloc;
1544         struct r100_cs_track *track;
1545         volatile uint32_t *ib;
1546         uint32_t tmp;
1547         int r;
1548         int i, face;
1549         u32 tile_flags = 0;
1550         u32 idx_value;
1551
1552         ib = p->ib.ptr;
1553         track = (struct r100_cs_track *)p->track;
1554
1555         idx_value = radeon_get_ib_value(p, idx);
1556
1557         switch (reg) {
1558         case RADEON_CRTC_GUI_TRIG_VLINE:
1559                 r = r100_cs_packet_parse_vline(p);
1560                 if (r) {
1561                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1562                                   idx, reg);
1563                         radeon_cs_dump_packet(p, pkt);
1564                         return r;
1565                 }
1566                 break;
1567                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1568                  * range access */
1569         case RADEON_DST_PITCH_OFFSET:
1570         case RADEON_SRC_PITCH_OFFSET:
1571                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1572                 if (r)
1573                         return r;
1574                 break;
1575         case RADEON_RB3D_DEPTHOFFSET:
1576                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1577                 if (r) {
1578                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1579                                   idx, reg);
1580                         radeon_cs_dump_packet(p, pkt);
1581                         return r;
1582                 }
1583                 track->zb.robj = reloc->robj;
1584                 track->zb.offset = idx_value;
1585                 track->zb_dirty = true;
1586                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1587                 break;
1588         case RADEON_RB3D_COLOROFFSET:
1589                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1590                 if (r) {
1591                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1592                                   idx, reg);
1593                         radeon_cs_dump_packet(p, pkt);
1594                         return r;
1595                 }
1596                 track->cb[0].robj = reloc->robj;
1597                 track->cb[0].offset = idx_value;
1598                 track->cb_dirty = true;
1599                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1600                 break;
1601         case RADEON_PP_TXOFFSET_0:
1602         case RADEON_PP_TXOFFSET_1:
1603         case RADEON_PP_TXOFFSET_2:
1604                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1605                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1606                 if (r) {
1607                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1608                                   idx, reg);
1609                         radeon_cs_dump_packet(p, pkt);
1610                         return r;
1611                 }
1612                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1613                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1614                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1615                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1616                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1617
1618                         tmp = idx_value & ~(0x7 << 2);
1619                         tmp |= tile_flags;
1620                         ib[idx] = tmp + ((u32)reloc->gpu_offset);
1621                 } else
1622                         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1623                 track->textures[i].robj = reloc->robj;
1624                 track->tex_dirty = true;
1625                 break;
1626         case RADEON_PP_CUBIC_OFFSET_T0_0:
1627         case RADEON_PP_CUBIC_OFFSET_T0_1:
1628         case RADEON_PP_CUBIC_OFFSET_T0_2:
1629         case RADEON_PP_CUBIC_OFFSET_T0_3:
1630         case RADEON_PP_CUBIC_OFFSET_T0_4:
1631                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1632                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1633                 if (r) {
1634                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1635                                   idx, reg);
1636                         radeon_cs_dump_packet(p, pkt);
1637                         return r;
1638                 }
1639                 track->textures[0].cube_info[i].offset = idx_value;
1640                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1641                 track->textures[0].cube_info[i].robj = reloc->robj;
1642                 track->tex_dirty = true;
1643                 break;
1644         case RADEON_PP_CUBIC_OFFSET_T1_0:
1645         case RADEON_PP_CUBIC_OFFSET_T1_1:
1646         case RADEON_PP_CUBIC_OFFSET_T1_2:
1647         case RADEON_PP_CUBIC_OFFSET_T1_3:
1648         case RADEON_PP_CUBIC_OFFSET_T1_4:
1649                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1650                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1651                 if (r) {
1652                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1653                                   idx, reg);
1654                         radeon_cs_dump_packet(p, pkt);
1655                         return r;
1656                 }
1657                 track->textures[1].cube_info[i].offset = idx_value;
1658                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1659                 track->textures[1].cube_info[i].robj = reloc->robj;
1660                 track->tex_dirty = true;
1661                 break;
1662         case RADEON_PP_CUBIC_OFFSET_T2_0:
1663         case RADEON_PP_CUBIC_OFFSET_T2_1:
1664         case RADEON_PP_CUBIC_OFFSET_T2_2:
1665         case RADEON_PP_CUBIC_OFFSET_T2_3:
1666         case RADEON_PP_CUBIC_OFFSET_T2_4:
1667                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1668                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1669                 if (r) {
1670                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1671                                   idx, reg);
1672                         radeon_cs_dump_packet(p, pkt);
1673                         return r;
1674                 }
1675                 track->textures[2].cube_info[i].offset = idx_value;
1676                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1677                 track->textures[2].cube_info[i].robj = reloc->robj;
1678                 track->tex_dirty = true;
1679                 break;
1680         case RADEON_RE_WIDTH_HEIGHT:
1681                 track->maxy = ((idx_value >> 16) & 0x7FF);
1682                 track->cb_dirty = true;
1683                 track->zb_dirty = true;
1684                 break;
1685         case RADEON_RB3D_COLORPITCH:
1686                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1687                 if (r) {
1688                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1689                                   idx, reg);
1690                         radeon_cs_dump_packet(p, pkt);
1691                         return r;
1692                 }
1693                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1694                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1695                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1696                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1697                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1698
1699                         tmp = idx_value & ~(0x7 << 16);
1700                         tmp |= tile_flags;
1701                         ib[idx] = tmp;
1702                 } else
1703                         ib[idx] = idx_value;
1704
1705                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1706                 track->cb_dirty = true;
1707                 break;
1708         case RADEON_RB3D_DEPTHPITCH:
1709                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1710                 track->zb_dirty = true;
1711                 break;
1712         case RADEON_RB3D_CNTL:
1713                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1714                 case 7:
1715                 case 8:
1716                 case 9:
1717                 case 11:
1718                 case 12:
1719                         track->cb[0].cpp = 1;
1720                         break;
1721                 case 3:
1722                 case 4:
1723                 case 15:
1724                         track->cb[0].cpp = 2;
1725                         break;
1726                 case 6:
1727                         track->cb[0].cpp = 4;
1728                         break;
1729                 default:
1730                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1731                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1732                         return -EINVAL;
1733                 }
1734                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1735                 track->cb_dirty = true;
1736                 track->zb_dirty = true;
1737                 break;
1738         case RADEON_RB3D_ZSTENCILCNTL:
1739                 switch (idx_value & 0xf) {
1740                 case 0:
1741                         track->zb.cpp = 2;
1742                         break;
1743                 case 2:
1744                 case 3:
1745                 case 4:
1746                 case 5:
1747                 case 9:
1748                 case 11:
1749                         track->zb.cpp = 4;
1750                         break;
1751                 default:
1752                         break;
1753                 }
1754                 track->zb_dirty = true;
1755                 break;
1756         case RADEON_RB3D_ZPASS_ADDR:
1757                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1758                 if (r) {
1759                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1760                                   idx, reg);
1761                         radeon_cs_dump_packet(p, pkt);
1762                         return r;
1763                 }
1764                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1765                 break;
1766         case RADEON_PP_CNTL:
1767                 {
1768                         uint32_t temp = idx_value >> 4;
1769                         for (i = 0; i < track->num_texture; i++)
1770                                 track->textures[i].enabled = !!(temp & (1 << i));
1771                         track->tex_dirty = true;
1772                 }
1773                 break;
1774         case RADEON_SE_VF_CNTL:
1775                 track->vap_vf_cntl = idx_value;
1776                 break;
1777         case RADEON_SE_VTX_FMT:
1778                 track->vtx_size = r100_get_vtx_size(idx_value);
1779                 break;
1780         case RADEON_PP_TEX_SIZE_0:
1781         case RADEON_PP_TEX_SIZE_1:
1782         case RADEON_PP_TEX_SIZE_2:
1783                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1784                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1785                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1786                 track->tex_dirty = true;
1787                 break;
1788         case RADEON_PP_TEX_PITCH_0:
1789         case RADEON_PP_TEX_PITCH_1:
1790         case RADEON_PP_TEX_PITCH_2:
1791                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1792                 track->textures[i].pitch = idx_value + 32;
1793                 track->tex_dirty = true;
1794                 break;
1795         case RADEON_PP_TXFILTER_0:
1796         case RADEON_PP_TXFILTER_1:
1797         case RADEON_PP_TXFILTER_2:
1798                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1799                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1800                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1801                 tmp = (idx_value >> 23) & 0x7;
1802                 if (tmp == 2 || tmp == 6)
1803                         track->textures[i].roundup_w = false;
1804                 tmp = (idx_value >> 27) & 0x7;
1805                 if (tmp == 2 || tmp == 6)
1806                         track->textures[i].roundup_h = false;
1807                 track->tex_dirty = true;
1808                 break;
1809         case RADEON_PP_TXFORMAT_0:
1810         case RADEON_PP_TXFORMAT_1:
1811         case RADEON_PP_TXFORMAT_2:
1812                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1813                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1814                         track->textures[i].use_pitch = 1;
1815                 } else {
1816                         track->textures[i].use_pitch = 0;
1817                         track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1818                         track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1819                 }
1820                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1821                         track->textures[i].tex_coord_type = 2;
1822                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1823                 case RADEON_TXFORMAT_I8:
1824                 case RADEON_TXFORMAT_RGB332:
1825                 case RADEON_TXFORMAT_Y8:
1826                         track->textures[i].cpp = 1;
1827                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1828                         break;
1829                 case RADEON_TXFORMAT_AI88:
1830                 case RADEON_TXFORMAT_ARGB1555:
1831                 case RADEON_TXFORMAT_RGB565:
1832                 case RADEON_TXFORMAT_ARGB4444:
1833                 case RADEON_TXFORMAT_VYUY422:
1834                 case RADEON_TXFORMAT_YVYU422:
1835                 case RADEON_TXFORMAT_SHADOW16:
1836                 case RADEON_TXFORMAT_LDUDV655:
1837                 case RADEON_TXFORMAT_DUDV88:
1838                         track->textures[i].cpp = 2;
1839                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1840                         break;
1841                 case RADEON_TXFORMAT_ARGB8888:
1842                 case RADEON_TXFORMAT_RGBA8888:
1843                 case RADEON_TXFORMAT_SHADOW32:
1844                 case RADEON_TXFORMAT_LDUDUV8888:
1845                         track->textures[i].cpp = 4;
1846                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1847                         break;
1848                 case RADEON_TXFORMAT_DXT1:
1849                         track->textures[i].cpp = 1;
1850                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1851                         break;
1852                 case RADEON_TXFORMAT_DXT23:
1853                 case RADEON_TXFORMAT_DXT45:
1854                         track->textures[i].cpp = 1;
1855                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1856                         break;
1857                 }
1858                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1859                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1860                 track->tex_dirty = true;
1861                 break;
1862         case RADEON_PP_CUBIC_FACES_0:
1863         case RADEON_PP_CUBIC_FACES_1:
1864         case RADEON_PP_CUBIC_FACES_2:
1865                 tmp = idx_value;
1866                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1867                 for (face = 0; face < 4; face++) {
1868                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1869                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1870                 }
1871                 track->tex_dirty = true;
1872                 break;
1873         default:
1874                 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1875                 return -EINVAL;
1876         }
1877         return 0;
1878 }
1879
1880 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1881                                          struct radeon_cs_packet *pkt,
1882                                          struct radeon_bo *robj)
1883 {
1884         unsigned idx;
1885         u32 value;
1886         idx = pkt->idx + 1;
1887         value = radeon_get_ib_value(p, idx + 2);
1888         if ((value + 1) > radeon_bo_size(robj)) {
1889                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1890                           "(need %u have %lu) !\n",
1891                           value + 1,
1892                           radeon_bo_size(robj));
1893                 return -EINVAL;
1894         }
1895         return 0;
1896 }
1897
1898 static int r100_packet3_check(struct radeon_cs_parser *p,
1899                               struct radeon_cs_packet *pkt)
1900 {
1901         struct radeon_bo_list *reloc;
1902         struct r100_cs_track *track;
1903         unsigned idx;
1904         volatile uint32_t *ib;
1905         int r;
1906
1907         ib = p->ib.ptr;
1908         idx = pkt->idx + 1;
1909         track = (struct r100_cs_track *)p->track;
1910         switch (pkt->opcode) {
1911         case PACKET3_3D_LOAD_VBPNTR:
1912                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1913                 if (r)
1914                         return r;
1915                 break;
1916         case PACKET3_INDX_BUFFER:
1917                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1918                 if (r) {
1919                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1920                         radeon_cs_dump_packet(p, pkt);
1921                         return r;
1922                 }
1923                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1924                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1925                 if (r) {
1926                         return r;
1927                 }
1928                 break;
1929         case 0x23:
1930                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1931                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1932                 if (r) {
1933                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1934                         radeon_cs_dump_packet(p, pkt);
1935                         return r;
1936                 }
1937                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1938                 track->num_arrays = 1;
1939                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1940
1941                 track->arrays[0].robj = reloc->robj;
1942                 track->arrays[0].esize = track->vtx_size;
1943
1944                 track->max_indx = radeon_get_ib_value(p, idx+1);
1945
1946                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1947                 track->immd_dwords = pkt->count - 1;
1948                 r = r100_cs_track_check(p->rdev, track);
1949                 if (r)
1950                         return r;
1951                 break;
1952         case PACKET3_3D_DRAW_IMMD:
1953                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1954                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1955                         return -EINVAL;
1956                 }
1957                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1958                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1959                 track->immd_dwords = pkt->count - 1;
1960                 r = r100_cs_track_check(p->rdev, track);
1961                 if (r)
1962                         return r;
1963                 break;
1964                 /* triggers drawing using in-packet vertex data */
1965         case PACKET3_3D_DRAW_IMMD_2:
1966                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1967                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1968                         return -EINVAL;
1969                 }
1970                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1971                 track->immd_dwords = pkt->count;
1972                 r = r100_cs_track_check(p->rdev, track);
1973                 if (r)
1974                         return r;
1975                 break;
1976                 /* triggers drawing using in-packet vertex data */
1977         case PACKET3_3D_DRAW_VBUF_2:
1978                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1979                 r = r100_cs_track_check(p->rdev, track);
1980                 if (r)
1981                         return r;
1982                 break;
1983                 /* triggers drawing of vertex buffers setup elsewhere */
1984         case PACKET3_3D_DRAW_INDX_2:
1985                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1986                 r = r100_cs_track_check(p->rdev, track);
1987                 if (r)
1988                         return r;
1989                 break;
1990                 /* triggers drawing using indices to vertex buffer */
1991         case PACKET3_3D_DRAW_VBUF:
1992                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1993                 r = r100_cs_track_check(p->rdev, track);
1994                 if (r)
1995                         return r;
1996                 break;
1997                 /* triggers drawing of vertex buffers setup elsewhere */
1998         case PACKET3_3D_DRAW_INDX:
1999                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2000                 r = r100_cs_track_check(p->rdev, track);
2001                 if (r)
2002                         return r;
2003                 break;
2004                 /* triggers drawing using indices to vertex buffer */
2005         case PACKET3_3D_CLEAR_HIZ:
2006         case PACKET3_3D_CLEAR_ZMASK:
2007                 if (p->rdev->hyperz_filp != p->filp)
2008                         return -EINVAL;
2009                 break;
2010         case PACKET3_NOP:
2011                 break;
2012         default:
2013                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2014                 return -EINVAL;
2015         }
2016         return 0;
2017 }
2018
2019 int r100_cs_parse(struct radeon_cs_parser *p)
2020 {
2021         struct radeon_cs_packet pkt;
2022         struct r100_cs_track *track;
2023         int r;
2024
2025         track = kzalloc(sizeof(*track), GFP_KERNEL);
2026         if (!track)
2027                 return -ENOMEM;
2028         r100_cs_track_clear(p->rdev, track);
2029         p->track = track;
2030         do {
2031                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2032                 if (r) {
2033                         return r;
2034                 }
2035                 p->idx += pkt.count + 2;
2036                 switch (pkt.type) {
2037                 case RADEON_PACKET_TYPE0:
2038                         if (p->rdev->family >= CHIP_R200)
2039                                 r = r100_cs_parse_packet0(p, &pkt,
2040                                         p->rdev->config.r100.reg_safe_bm,
2041                                         p->rdev->config.r100.reg_safe_bm_size,
2042                                         &r200_packet0_check);
2043                         else
2044                                 r = r100_cs_parse_packet0(p, &pkt,
2045                                         p->rdev->config.r100.reg_safe_bm,
2046                                         p->rdev->config.r100.reg_safe_bm_size,
2047                                         &r100_packet0_check);
2048                         break;
2049                 case RADEON_PACKET_TYPE2:
2050                         break;
2051                 case RADEON_PACKET_TYPE3:
2052                         r = r100_packet3_check(p, &pkt);
2053                         break;
2054                 default:
2055                         DRM_ERROR("Unknown packet type %d !\n",
2056                                   pkt.type);
2057                         return -EINVAL;
2058                 }
2059                 if (r)
2060                         return r;
2061         } while (p->idx < p->chunk_ib->length_dw);
2062         return 0;
2063 }
2064
2065 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2066 {
2067         DRM_ERROR("pitch                      %d\n", t->pitch);
2068         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2069         DRM_ERROR("width                      %d\n", t->width);
2070         DRM_ERROR("width_11                   %d\n", t->width_11);
2071         DRM_ERROR("height                     %d\n", t->height);
2072         DRM_ERROR("height_11                  %d\n", t->height_11);
2073         DRM_ERROR("num levels                 %d\n", t->num_levels);
2074         DRM_ERROR("depth                      %d\n", t->txdepth);
2075         DRM_ERROR("bpp                        %d\n", t->cpp);
2076         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2077         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2078         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2079         DRM_ERROR("compress format            %d\n", t->compress_format);
2080 }
2081
2082 static int r100_track_compress_size(int compress_format, int w, int h)
2083 {
2084         int block_width, block_height, block_bytes;
2085         int wblocks, hblocks;
2086         int min_wblocks;
2087         int sz;
2088
2089         block_width = 4;
2090         block_height = 4;
2091
2092         switch (compress_format) {
2093         case R100_TRACK_COMP_DXT1:
2094                 block_bytes = 8;
2095                 min_wblocks = 4;
2096                 break;
2097         default:
2098         case R100_TRACK_COMP_DXT35:
2099                 block_bytes = 16;
2100                 min_wblocks = 2;
2101                 break;
2102         }
2103
2104         hblocks = (h + block_height - 1) / block_height;
2105         wblocks = (w + block_width - 1) / block_width;
2106         if (wblocks < min_wblocks)
2107                 wblocks = min_wblocks;
2108         sz = wblocks * hblocks * block_bytes;
2109         return sz;
2110 }
2111
2112 static int r100_cs_track_cube(struct radeon_device *rdev,
2113                               struct r100_cs_track *track, unsigned idx)
2114 {
2115         unsigned face, w, h;
2116         struct radeon_bo *cube_robj;
2117         unsigned long size;
2118         unsigned compress_format = track->textures[idx].compress_format;
2119
2120         for (face = 0; face < 5; face++) {
2121                 cube_robj = track->textures[idx].cube_info[face].robj;
2122                 w = track->textures[idx].cube_info[face].width;
2123                 h = track->textures[idx].cube_info[face].height;
2124
2125                 if (compress_format) {
2126                         size = r100_track_compress_size(compress_format, w, h);
2127                 } else
2128                         size = w * h;
2129                 size *= track->textures[idx].cpp;
2130
2131                 size += track->textures[idx].cube_info[face].offset;
2132
2133                 if (size > radeon_bo_size(cube_robj)) {
2134                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2135                                   size, radeon_bo_size(cube_robj));
2136                         r100_cs_track_texture_print(&track->textures[idx]);
2137                         return -1;
2138                 }
2139         }
2140         return 0;
2141 }
2142
2143 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2144                                        struct r100_cs_track *track)
2145 {
2146         struct radeon_bo *robj;
2147         unsigned long size;
2148         unsigned u, i, w, h, d;
2149         int ret;
2150
2151         for (u = 0; u < track->num_texture; u++) {
2152                 if (!track->textures[u].enabled)
2153                         continue;
2154                 if (track->textures[u].lookup_disable)
2155                         continue;
2156                 robj = track->textures[u].robj;
2157                 if (robj == NULL) {
2158                         DRM_ERROR("No texture bound to unit %u\n", u);
2159                         return -EINVAL;
2160                 }
2161                 size = 0;
2162                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2163                         if (track->textures[u].use_pitch) {
2164                                 if (rdev->family < CHIP_R300)
2165                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2166                                 else
2167                                         w = track->textures[u].pitch / (1 << i);
2168                         } else {
2169                                 w = track->textures[u].width;
2170                                 if (rdev->family >= CHIP_RV515)
2171                                         w |= track->textures[u].width_11;
2172                                 w = w / (1 << i);
2173                                 if (track->textures[u].roundup_w)
2174                                         w = roundup_pow_of_two(w);
2175                         }
2176                         h = track->textures[u].height;
2177                         if (rdev->family >= CHIP_RV515)
2178                                 h |= track->textures[u].height_11;
2179                         h = h / (1 << i);
2180                         if (track->textures[u].roundup_h)
2181                                 h = roundup_pow_of_two(h);
2182                         if (track->textures[u].tex_coord_type == 1) {
2183                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2184                                 if (!d)
2185                                         d = 1;
2186                         } else {
2187                                 d = 1;
2188                         }
2189                         if (track->textures[u].compress_format) {
2190
2191                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2192                                 /* compressed textures are block based */
2193                         } else
2194                                 size += w * h * d;
2195                 }
2196                 size *= track->textures[u].cpp;
2197
2198                 switch (track->textures[u].tex_coord_type) {
2199                 case 0:
2200                 case 1:
2201                         break;
2202                 case 2:
2203                         if (track->separate_cube) {
2204                                 ret = r100_cs_track_cube(rdev, track, u);
2205                                 if (ret)
2206                                         return ret;
2207                         } else
2208                                 size *= 6;
2209                         break;
2210                 default:
2211                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2212                                   "%u\n", track->textures[u].tex_coord_type, u);
2213                         return -EINVAL;
2214                 }
2215                 if (size > radeon_bo_size(robj)) {
2216                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2217                                   "%lu\n", u, size, radeon_bo_size(robj));
2218                         r100_cs_track_texture_print(&track->textures[u]);
2219                         return -EINVAL;
2220                 }
2221         }
2222         return 0;
2223 }
2224
2225 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2226 {
2227         unsigned i;
2228         unsigned long size;
2229         unsigned prim_walk;
2230         unsigned nverts;
2231         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2232
2233         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2234             !track->blend_read_enable)
2235                 num_cb = 0;
2236
2237         for (i = 0; i < num_cb; i++) {
2238                 if (track->cb[i].robj == NULL) {
2239                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2240                         return -EINVAL;
2241                 }
2242                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2243                 size += track->cb[i].offset;
2244                 if (size > radeon_bo_size(track->cb[i].robj)) {
2245                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2246                                   "(need %lu have %lu) !\n", i, size,
2247                                   radeon_bo_size(track->cb[i].robj));
2248                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2249                                   i, track->cb[i].pitch, track->cb[i].cpp,
2250                                   track->cb[i].offset, track->maxy);
2251                         return -EINVAL;
2252                 }
2253         }
2254         track->cb_dirty = false;
2255
2256         if (track->zb_dirty && track->z_enabled) {
2257                 if (track->zb.robj == NULL) {
2258                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2259                         return -EINVAL;
2260                 }
2261                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2262                 size += track->zb.offset;
2263                 if (size > radeon_bo_size(track->zb.robj)) {
2264                         DRM_ERROR("[drm] Buffer too small for z buffer "
2265                                   "(need %lu have %lu) !\n", size,
2266                                   radeon_bo_size(track->zb.robj));
2267                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2268                                   track->zb.pitch, track->zb.cpp,
2269                                   track->zb.offset, track->maxy);
2270                         return -EINVAL;
2271                 }
2272         }
2273         track->zb_dirty = false;
2274
2275         if (track->aa_dirty && track->aaresolve) {
2276                 if (track->aa.robj == NULL) {
2277                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2278                         return -EINVAL;
2279                 }
2280                 /* I believe the format comes from colorbuffer0. */
2281                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2282                 size += track->aa.offset;
2283                 if (size > radeon_bo_size(track->aa.robj)) {
2284                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2285                                   "(need %lu have %lu) !\n", i, size,
2286                                   radeon_bo_size(track->aa.robj));
2287                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2288                                   i, track->aa.pitch, track->cb[0].cpp,
2289                                   track->aa.offset, track->maxy);
2290                         return -EINVAL;
2291                 }
2292         }
2293         track->aa_dirty = false;
2294
2295         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2296         if (track->vap_vf_cntl & (1 << 14)) {
2297                 nverts = track->vap_alt_nverts;
2298         } else {
2299                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2300         }
2301         switch (prim_walk) {
2302         case 1:
2303                 for (i = 0; i < track->num_arrays; i++) {
2304                         size = track->arrays[i].esize * track->max_indx * 4;
2305                         if (track->arrays[i].robj == NULL) {
2306                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2307                                           "bound\n", prim_walk, i);
2308                                 return -EINVAL;
2309                         }
2310                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2311                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2312                                         "need %lu dwords have %lu dwords\n",
2313                                         prim_walk, i, size >> 2,
2314                                         radeon_bo_size(track->arrays[i].robj)
2315                                         >> 2);
2316                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2317                                 return -EINVAL;
2318                         }
2319                 }
2320                 break;
2321         case 2:
2322                 for (i = 0; i < track->num_arrays; i++) {
2323                         size = track->arrays[i].esize * (nverts - 1) * 4;
2324                         if (track->arrays[i].robj == NULL) {
2325                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2326                                           "bound\n", prim_walk, i);
2327                                 return -EINVAL;
2328                         }
2329                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2330                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2331                                         "need %lu dwords have %lu dwords\n",
2332                                         prim_walk, i, size >> 2,
2333                                         radeon_bo_size(track->arrays[i].robj)
2334                                         >> 2);
2335                                 return -EINVAL;
2336                         }
2337                 }
2338                 break;
2339         case 3:
2340                 size = track->vtx_size * nverts;
2341                 if (size != track->immd_dwords) {
2342                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2343                                   track->immd_dwords, size);
2344                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2345                                   nverts, track->vtx_size);
2346                         return -EINVAL;
2347                 }
2348                 break;
2349         default:
2350                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2351                           prim_walk);
2352                 return -EINVAL;
2353         }
2354
2355         if (track->tex_dirty) {
2356                 track->tex_dirty = false;
2357                 return r100_cs_track_texture_check(rdev, track);
2358         }
2359         return 0;
2360 }
2361
2362 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2363 {
2364         unsigned i, face;
2365
2366         track->cb_dirty = true;
2367         track->zb_dirty = true;
2368         track->tex_dirty = true;
2369         track->aa_dirty = true;
2370
2371         if (rdev->family < CHIP_R300) {
2372                 track->num_cb = 1;
2373                 if (rdev->family <= CHIP_RS200)
2374                         track->num_texture = 3;
2375                 else
2376                         track->num_texture = 6;
2377                 track->maxy = 2048;
2378                 track->separate_cube = 1;
2379         } else {
2380                 track->num_cb = 4;
2381                 track->num_texture = 16;
2382                 track->maxy = 4096;
2383                 track->separate_cube = 0;
2384                 track->aaresolve = false;
2385                 track->aa.robj = NULL;
2386         }
2387
2388         for (i = 0; i < track->num_cb; i++) {
2389                 track->cb[i].robj = NULL;
2390                 track->cb[i].pitch = 8192;
2391                 track->cb[i].cpp = 16;
2392                 track->cb[i].offset = 0;
2393         }
2394         track->z_enabled = true;
2395         track->zb.robj = NULL;
2396         track->zb.pitch = 8192;
2397         track->zb.cpp = 4;
2398         track->zb.offset = 0;
2399         track->vtx_size = 0x7F;
2400         track->immd_dwords = 0xFFFFFFFFUL;
2401         track->num_arrays = 11;
2402         track->max_indx = 0x00FFFFFFUL;
2403         for (i = 0; i < track->num_arrays; i++) {
2404                 track->arrays[i].robj = NULL;
2405                 track->arrays[i].esize = 0x7F;
2406         }
2407         for (i = 0; i < track->num_texture; i++) {
2408                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2409                 track->textures[i].pitch = 16536;
2410                 track->textures[i].width = 16536;
2411                 track->textures[i].height = 16536;
2412                 track->textures[i].width_11 = 1 << 11;
2413                 track->textures[i].height_11 = 1 << 11;
2414                 track->textures[i].num_levels = 12;
2415                 if (rdev->family <= CHIP_RS200) {
2416                         track->textures[i].tex_coord_type = 0;
2417                         track->textures[i].txdepth = 0;
2418                 } else {
2419                         track->textures[i].txdepth = 16;
2420                         track->textures[i].tex_coord_type = 1;
2421                 }
2422                 track->textures[i].cpp = 64;
2423                 track->textures[i].robj = NULL;
2424                 /* CS IB emission code makes sure texture unit are disabled */
2425                 track->textures[i].enabled = false;
2426                 track->textures[i].lookup_disable = false;
2427                 track->textures[i].roundup_w = true;
2428                 track->textures[i].roundup_h = true;
2429                 if (track->separate_cube)
2430                         for (face = 0; face < 5; face++) {
2431                                 track->textures[i].cube_info[face].robj = NULL;
2432                                 track->textures[i].cube_info[face].width = 16536;
2433                                 track->textures[i].cube_info[face].height = 16536;
2434                                 track->textures[i].cube_info[face].offset = 0;
2435                         }
2436         }
2437 }
2438
2439 /*
2440  * Global GPU functions
2441  */
2442 static void r100_errata(struct radeon_device *rdev)
2443 {
2444         rdev->pll_errata = 0;
2445
2446         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2447                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2448         }
2449
2450         if (rdev->family == CHIP_RV100 ||
2451             rdev->family == CHIP_RS100 ||
2452             rdev->family == CHIP_RS200) {
2453                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2454         }
2455 }
2456
2457 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2458 {
2459         unsigned i;
2460         uint32_t tmp;
2461
2462         for (i = 0; i < rdev->usec_timeout; i++) {
2463                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2464                 if (tmp >= n) {
2465                         return 0;
2466                 }
2467                 DRM_UDELAY(1);
2468         }
2469         return -1;
2470 }
2471
2472 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2473 {
2474         unsigned i;
2475         uint32_t tmp;
2476
2477         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2478                 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2479         }
2480         for (i = 0; i < rdev->usec_timeout; i++) {
2481                 tmp = RREG32(RADEON_RBBM_STATUS);
2482                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2483                         return 0;
2484                 }
2485                 DRM_UDELAY(1);
2486         }
2487         return -1;
2488 }
2489
2490 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2491 {
2492         unsigned i;
2493         uint32_t tmp;
2494
2495         for (i = 0; i < rdev->usec_timeout; i++) {
2496                 /* read MC_STATUS */
2497                 tmp = RREG32(RADEON_MC_STATUS);
2498                 if (tmp & RADEON_MC_IDLE) {
2499                         return 0;
2500                 }
2501                 DRM_UDELAY(1);
2502         }
2503         return -1;
2504 }
2505
2506 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2507 {
2508         u32 rbbm_status;
2509
2510         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2511         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2512                 radeon_ring_lockup_update(rdev, ring);
2513                 return false;
2514         }
2515         return radeon_ring_test_lockup(rdev, ring);
2516 }
2517
2518 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2519 void r100_enable_bm(struct radeon_device *rdev)
2520 {
2521         uint32_t tmp;
2522         /* Enable bus mastering */
2523         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2524         WREG32(RADEON_BUS_CNTL, tmp);
2525 }
2526
2527 void r100_bm_disable(struct radeon_device *rdev)
2528 {
2529         u32 tmp;
2530
2531         /* disable bus mastering */
2532         tmp = RREG32(R_000030_BUS_CNTL);
2533         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2534         mdelay(1);
2535         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2536         mdelay(1);
2537         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2538         tmp = RREG32(RADEON_BUS_CNTL);
2539         mdelay(1);
2540         pci_clear_master(rdev->pdev);
2541         mdelay(1);
2542 }
2543
2544 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2545 {
2546         struct r100_mc_save save;
2547         u32 status, tmp;
2548         int ret = 0;
2549
2550         status = RREG32(R_000E40_RBBM_STATUS);
2551         if (!G_000E40_GUI_ACTIVE(status)) {
2552                 return 0;
2553         }
2554         r100_mc_stop(rdev, &save);
2555         status = RREG32(R_000E40_RBBM_STATUS);
2556         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2557         /* stop CP */
2558         WREG32(RADEON_CP_CSQ_CNTL, 0);
2559         tmp = RREG32(RADEON_CP_RB_CNTL);
2560         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2561         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2562         WREG32(RADEON_CP_RB_WPTR, 0);
2563         WREG32(RADEON_CP_RB_CNTL, tmp);
2564         /* save PCI state */
2565         pci_save_state(rdev->pdev);
2566         /* disable bus mastering */
2567         r100_bm_disable(rdev);
2568         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2569                                         S_0000F0_SOFT_RESET_RE(1) |
2570                                         S_0000F0_SOFT_RESET_PP(1) |
2571                                         S_0000F0_SOFT_RESET_RB(1));
2572         RREG32(R_0000F0_RBBM_SOFT_RESET);
2573         mdelay(500);
2574         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2575         mdelay(1);
2576         status = RREG32(R_000E40_RBBM_STATUS);
2577         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2578         /* reset CP */
2579         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2580         RREG32(R_0000F0_RBBM_SOFT_RESET);
2581         mdelay(500);
2582         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2583         mdelay(1);
2584         status = RREG32(R_000E40_RBBM_STATUS);
2585         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2586         /* restore PCI & busmastering */
2587         pci_restore_state(rdev->pdev);
2588         r100_enable_bm(rdev);
2589         /* Check if GPU is idle */
2590         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2591                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2592                 dev_err(rdev->dev, "failed to reset GPU\n");
2593                 ret = -1;
2594         } else
2595                 dev_info(rdev->dev, "GPU reset succeed\n");
2596         r100_mc_resume(rdev, &save);
2597         return ret;
2598 }
2599
2600 void r100_set_common_regs(struct radeon_device *rdev)
2601 {
2602         struct drm_device *dev = rdev->ddev;
2603         bool force_dac2 = false;
2604         u32 tmp;
2605
2606         /* set these so they don't interfere with anything */
2607         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2608         WREG32(RADEON_SUBPIC_CNTL, 0);
2609         WREG32(RADEON_VIPH_CONTROL, 0);
2610         WREG32(RADEON_I2C_CNTL_1, 0);
2611         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2612         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2613         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2614
2615         /* always set up dac2 on rn50 and some rv100 as lots
2616          * of servers seem to wire it up to a VGA port but
2617          * don't report it in the bios connector
2618          * table.
2619          */
2620         switch (dev->pdev->device) {
2621                 /* RN50 */
2622         case 0x515e:
2623         case 0x5969:
2624                 force_dac2 = true;
2625                 break;
2626                 /* RV100*/
2627         case 0x5159:
2628         case 0x515a:
2629                 /* DELL triple head servers */
2630                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2631                     ((dev->pdev->subsystem_device == 0x016c) ||
2632                      (dev->pdev->subsystem_device == 0x016d) ||
2633                      (dev->pdev->subsystem_device == 0x016e) ||
2634                      (dev->pdev->subsystem_device == 0x016f) ||
2635                      (dev->pdev->subsystem_device == 0x0170) ||
2636                      (dev->pdev->subsystem_device == 0x017d) ||
2637                      (dev->pdev->subsystem_device == 0x017e) ||
2638                      (dev->pdev->subsystem_device == 0x0183) ||
2639                      (dev->pdev->subsystem_device == 0x018a) ||
2640                      (dev->pdev->subsystem_device == 0x019a)))
2641                         force_dac2 = true;
2642                 break;
2643         }
2644
2645         if (force_dac2) {
2646                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2647                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2648                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2649
2650                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2651                    enable it, even it's detected.
2652                 */
2653
2654                 /* force it to crtc0 */
2655                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2656                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2657                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2658
2659                 /* set up the TV DAC */
2660                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2661                                  RADEON_TV_DAC_STD_MASK |
2662                                  RADEON_TV_DAC_RDACPD |
2663                                  RADEON_TV_DAC_GDACPD |
2664                                  RADEON_TV_DAC_BDACPD |
2665                                  RADEON_TV_DAC_BGADJ_MASK |
2666                                  RADEON_TV_DAC_DACADJ_MASK);
2667                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2668                                 RADEON_TV_DAC_NHOLD |
2669                                 RADEON_TV_DAC_STD_PS2 |
2670                                 (0x58 << 16));
2671
2672                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2673                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2674                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2675         }
2676
2677         /* switch PM block to ACPI mode */
2678         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2679         tmp &= ~RADEON_PM_MODE_SEL;
2680         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2681
2682 }
2683
2684 /*
2685  * VRAM info
2686  */
2687 static void r100_vram_get_type(struct radeon_device *rdev)
2688 {
2689         uint32_t tmp;
2690
2691         rdev->mc.vram_is_ddr = false;
2692         if (rdev->flags & RADEON_IS_IGP)
2693                 rdev->mc.vram_is_ddr = true;
2694         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2695                 rdev->mc.vram_is_ddr = true;
2696         if ((rdev->family == CHIP_RV100) ||
2697             (rdev->family == CHIP_RS100) ||
2698             (rdev->family == CHIP_RS200)) {
2699                 tmp = RREG32(RADEON_MEM_CNTL);
2700                 if (tmp & RV100_HALF_MODE) {
2701                         rdev->mc.vram_width = 32;
2702                 } else {
2703                         rdev->mc.vram_width = 64;
2704                 }
2705                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2706                         rdev->mc.vram_width /= 4;
2707                         rdev->mc.vram_is_ddr = true;
2708                 }
2709         } else if (rdev->family <= CHIP_RV280) {
2710                 tmp = RREG32(RADEON_MEM_CNTL);
2711                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2712                         rdev->mc.vram_width = 128;
2713                 } else {
2714                         rdev->mc.vram_width = 64;
2715                 }
2716         } else {
2717                 /* newer IGPs */
2718                 rdev->mc.vram_width = 128;
2719         }
2720 }
2721
2722 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2723 {
2724         u32 aper_size;
2725         u8 byte;
2726
2727         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2728
2729         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2730          * that is has the 2nd generation multifunction PCI interface
2731          */
2732         if (rdev->family == CHIP_RV280 ||
2733             rdev->family >= CHIP_RV350) {
2734                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2735                        ~RADEON_HDP_APER_CNTL);
2736                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2737                 return aper_size * 2;
2738         }
2739
2740         /* Older cards have all sorts of funny issues to deal with. First
2741          * check if it's a multifunction card by reading the PCI config
2742          * header type... Limit those to one aperture size
2743          */
2744         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2745         if (byte & 0x80) {
2746                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2747                 DRM_INFO("Limiting VRAM to one aperture\n");
2748                 return aper_size;
2749         }
2750
2751         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2752          * have set it up. We don't write this as it's broken on some ASICs but
2753          * we expect the BIOS to have done the right thing (might be too optimistic...)
2754          */
2755         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2756                 return aper_size * 2;
2757         return aper_size;
2758 }
2759
2760 void r100_vram_init_sizes(struct radeon_device *rdev)
2761 {
2762         u64 config_aper_size;
2763
2764         /* work out accessible VRAM */
2765         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2766         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2767         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2768         /* FIXME we don't use the second aperture yet when we could use it */
2769         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2770                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2771         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2772         if (rdev->flags & RADEON_IS_IGP) {
2773                 uint32_t tom;
2774                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2775                 tom = RREG32(RADEON_NB_TOM);
2776                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2777                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2778                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2779         } else {
2780                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2781                 /* Some production boards of m6 will report 0
2782                  * if it's 8 MB
2783                  */
2784                 if (rdev->mc.real_vram_size == 0) {
2785                         rdev->mc.real_vram_size = 8192 * 1024;
2786                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2787                 }
2788                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2789                  * Novell bug 204882 + along with lots of ubuntu ones
2790                  */
2791                 if (rdev->mc.aper_size > config_aper_size)
2792                         config_aper_size = rdev->mc.aper_size;
2793
2794                 if (config_aper_size > rdev->mc.real_vram_size)
2795                         rdev->mc.mc_vram_size = config_aper_size;
2796                 else
2797                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2798         }
2799 }
2800
2801 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2802 {
2803         uint32_t temp;
2804
2805         temp = RREG32(RADEON_CONFIG_CNTL);
2806         if (state == false) {
2807                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2808                 temp |= RADEON_CFG_VGA_IO_DIS;
2809         } else {
2810                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2811         }
2812         WREG32(RADEON_CONFIG_CNTL, temp);
2813 }
2814
2815 static void r100_mc_init(struct radeon_device *rdev)
2816 {
2817         u64 base;
2818
2819         r100_vram_get_type(rdev);
2820         r100_vram_init_sizes(rdev);
2821         base = rdev->mc.aper_base;
2822         if (rdev->flags & RADEON_IS_IGP)
2823                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2824         radeon_vram_location(rdev, &rdev->mc, base);
2825         rdev->mc.gtt_base_align = 0;
2826         if (!(rdev->flags & RADEON_IS_AGP))
2827                 radeon_gtt_location(rdev, &rdev->mc);
2828         radeon_update_bandwidth_info(rdev);
2829 }
2830
2831
2832 /*
2833  * Indirect registers accessor
2834  */
2835 void r100_pll_errata_after_index(struct radeon_device *rdev)
2836 {
2837         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2838                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2839                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2840         }
2841 }
2842
2843 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2844 {
2845         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2846          * or the chip could hang on a subsequent access
2847          */
2848         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2849                 mdelay(5);
2850         }
2851
2852         /* This function is required to workaround a hardware bug in some (all?)
2853          * revisions of the R300.  This workaround should be called after every
2854          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2855          * may not be correct.
2856          */
2857         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2858                 uint32_t save, tmp;
2859
2860                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2861                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2862                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2863                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2864                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2865         }
2866 }
2867
2868 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2869 {
2870         unsigned long flags;
2871         uint32_t data;
2872
2873         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2874         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2875         r100_pll_errata_after_index(rdev);
2876         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2877         r100_pll_errata_after_data(rdev);
2878         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2879         return data;
2880 }
2881
2882 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2883 {
2884         unsigned long flags;
2885
2886         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2887         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2888         r100_pll_errata_after_index(rdev);
2889         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2890         r100_pll_errata_after_data(rdev);
2891         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2892 }
2893
2894 static void r100_set_safe_registers(struct radeon_device *rdev)
2895 {
2896         if (ASIC_IS_RN50(rdev)) {
2897                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2898                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2899         } else if (rdev->family < CHIP_R200) {
2900                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2901                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2902         } else {
2903                 r200_set_safe_registers(rdev);
2904         }
2905 }
2906
2907 /*
2908  * Debugfs info
2909  */
2910 #if defined(CONFIG_DEBUG_FS)
2911 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2912 {
2913         struct drm_info_node *node = (struct drm_info_node *) m->private;
2914         struct drm_device *dev = node->minor->dev;
2915         struct radeon_device *rdev = dev->dev_private;
2916         uint32_t reg, value;
2917         unsigned i;
2918
2919         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2920         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2921         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2922         for (i = 0; i < 64; i++) {
2923                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2924                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2925                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2926                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2927                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2928         }
2929         return 0;
2930 }
2931
2932 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2933 {
2934         struct drm_info_node *node = (struct drm_info_node *) m->private;
2935         struct drm_device *dev = node->minor->dev;
2936         struct radeon_device *rdev = dev->dev_private;
2937         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2938         uint32_t rdp, wdp;
2939         unsigned count, i, j;
2940
2941         radeon_ring_free_size(rdev, ring);
2942         rdp = RREG32(RADEON_CP_RB_RPTR);
2943         wdp = RREG32(RADEON_CP_RB_WPTR);
2944         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2945         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2946         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2947         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2948         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2949         seq_printf(m, "%u dwords in ring\n", count);
2950         if (ring->ready) {
2951                 for (j = 0; j <= count; j++) {
2952                         i = (rdp + j) & ring->ptr_mask;
2953                         seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2954                 }
2955         }
2956         return 0;
2957 }
2958
2959
2960 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2961 {
2962         struct drm_info_node *node = (struct drm_info_node *) m->private;
2963         struct drm_device *dev = node->minor->dev;
2964         struct radeon_device *rdev = dev->dev_private;
2965         uint32_t csq_stat, csq2_stat, tmp;
2966         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2967         unsigned i;
2968
2969         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2970         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2971         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2972         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2973         r_rptr = (csq_stat >> 0) & 0x3ff;
2974         r_wptr = (csq_stat >> 10) & 0x3ff;
2975         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2976         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2977         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2978         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2979         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2980         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2981         seq_printf(m, "Ring rptr %u\n", r_rptr);
2982         seq_printf(m, "Ring wptr %u\n", r_wptr);
2983         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2984         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2985         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2986         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2987         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2988          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2989         seq_printf(m, "Ring fifo:\n");
2990         for (i = 0; i < 256; i++) {
2991                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2992                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2993                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2994         }
2995         seq_printf(m, "Indirect1 fifo:\n");
2996         for (i = 256; i <= 512; i++) {
2997                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2998                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2999                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3000         }
3001         seq_printf(m, "Indirect2 fifo:\n");
3002         for (i = 640; i < ib1_wptr; i++) {
3003                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3004                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3005                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3006         }
3007         return 0;
3008 }
3009
3010 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3011 {
3012         struct drm_info_node *node = (struct drm_info_node *) m->private;
3013         struct drm_device *dev = node->minor->dev;
3014         struct radeon_device *rdev = dev->dev_private;
3015         uint32_t tmp;
3016
3017         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3018         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3019         tmp = RREG32(RADEON_MC_FB_LOCATION);
3020         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3021         tmp = RREG32(RADEON_BUS_CNTL);
3022         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3023         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3024         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3025         tmp = RREG32(RADEON_AGP_BASE);
3026         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3027         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3028         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3029         tmp = RREG32(0x01D0);
3030         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3031         tmp = RREG32(RADEON_AIC_LO_ADDR);
3032         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3033         tmp = RREG32(RADEON_AIC_HI_ADDR);
3034         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3035         tmp = RREG32(0x01E4);
3036         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3037         return 0;
3038 }
3039
3040 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3041         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3042 };
3043
3044 static struct drm_info_list r100_debugfs_cp_list[] = {
3045         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3046         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3047 };
3048
3049 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3050         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3051 };
3052 #endif
3053
3054 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3055 {
3056 #if defined(CONFIG_DEBUG_FS)
3057         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3058 #else
3059         return 0;
3060 #endif
3061 }
3062
3063 int r100_debugfs_cp_init(struct radeon_device *rdev)
3064 {
3065 #if defined(CONFIG_DEBUG_FS)
3066         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3067 #else
3068         return 0;
3069 #endif
3070 }
3071
3072 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3073 {
3074 #if defined(CONFIG_DEBUG_FS)
3075         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3076 #else
3077         return 0;
3078 #endif
3079 }
3080
3081 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3082                          uint32_t tiling_flags, uint32_t pitch,
3083                          uint32_t offset, uint32_t obj_size)
3084 {
3085         int surf_index = reg * 16;
3086         int flags = 0;
3087
3088         if (rdev->family <= CHIP_RS200) {
3089                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3090                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3091                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3092                 if (tiling_flags & RADEON_TILING_MACRO)
3093                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3094                 /* setting pitch to 0 disables tiling */
3095                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3096                                 == 0)
3097                         pitch = 0;
3098         } else if (rdev->family <= CHIP_RV280) {
3099                 if (tiling_flags & (RADEON_TILING_MACRO))
3100                         flags |= R200_SURF_TILE_COLOR_MACRO;
3101                 if (tiling_flags & RADEON_TILING_MICRO)
3102                         flags |= R200_SURF_TILE_COLOR_MICRO;
3103         } else {
3104                 if (tiling_flags & RADEON_TILING_MACRO)
3105                         flags |= R300_SURF_TILE_MACRO;
3106                 if (tiling_flags & RADEON_TILING_MICRO)
3107                         flags |= R300_SURF_TILE_MICRO;
3108         }
3109
3110         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3111                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3112         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3113                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3114
3115         /* r100/r200 divide by 16 */
3116         if (rdev->family < CHIP_R300)
3117                 flags |= pitch / 16;
3118         else
3119                 flags |= pitch / 8;
3120
3121
3122         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3123         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3124         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3125         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3126         return 0;
3127 }
3128
3129 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3130 {
3131         int surf_index = reg * 16;
3132         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3133 }
3134
3135 void r100_bandwidth_update(struct radeon_device *rdev)
3136 {
3137         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3138         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3139         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3140         fixed20_12 crit_point_ff = {0};
3141         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3142         fixed20_12 memtcas_ff[8] = {
3143                 dfixed_init(1),
3144                 dfixed_init(2),
3145                 dfixed_init(3),
3146                 dfixed_init(0),
3147                 dfixed_init_half(1),
3148                 dfixed_init_half(2),
3149                 dfixed_init(0),
3150         };
3151         fixed20_12 memtcas_rs480_ff[8] = {
3152                 dfixed_init(0),
3153                 dfixed_init(1),
3154                 dfixed_init(2),
3155                 dfixed_init(3),
3156                 dfixed_init(0),
3157                 dfixed_init_half(1),
3158                 dfixed_init_half(2),
3159                 dfixed_init_half(3),
3160         };
3161         fixed20_12 memtcas2_ff[8] = {
3162                 dfixed_init(0),
3163                 dfixed_init(1),
3164                 dfixed_init(2),
3165                 dfixed_init(3),
3166                 dfixed_init(4),
3167                 dfixed_init(5),
3168                 dfixed_init(6),
3169                 dfixed_init(7),
3170         };
3171         fixed20_12 memtrbs[8] = {
3172                 dfixed_init(1),
3173                 dfixed_init_half(1),
3174                 dfixed_init(2),
3175                 dfixed_init_half(2),
3176                 dfixed_init(3),
3177                 dfixed_init_half(3),
3178                 dfixed_init(4),
3179                 dfixed_init_half(4)
3180         };
3181         fixed20_12 memtrbs_r4xx[8] = {
3182                 dfixed_init(4),
3183                 dfixed_init(5),
3184                 dfixed_init(6),
3185                 dfixed_init(7),
3186                 dfixed_init(8),
3187                 dfixed_init(9),
3188                 dfixed_init(10),
3189                 dfixed_init(11)
3190         };
3191         fixed20_12 min_mem_eff;
3192         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3193         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3194         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3195                 disp_drain_rate2, read_return_rate;
3196         fixed20_12 time_disp1_drop_priority;
3197         int c;
3198         int cur_size = 16;       /* in octawords */
3199         int critical_point = 0, critical_point2;
3200 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3201         int stop_req, max_stop_req;
3202         struct drm_display_mode *mode1 = NULL;
3203         struct drm_display_mode *mode2 = NULL;
3204         uint32_t pixel_bytes1 = 0;
3205         uint32_t pixel_bytes2 = 0;
3206
3207         /* Guess line buffer size to be 8192 pixels */
3208         u32 lb_size = 8192;
3209
3210         if (!rdev->mode_info.mode_config_initialized)
3211                 return;
3212
3213         radeon_update_display_priority(rdev);
3214
3215         if (rdev->mode_info.crtcs[0]->base.enabled) {
3216                 const struct drm_framebuffer *fb =
3217                         rdev->mode_info.crtcs[0]->base.primary->fb;
3218
3219                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3220                 pixel_bytes1 = fb->format->cpp[0];
3221         }
3222         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3223                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3224                         const struct drm_framebuffer *fb =
3225                                 rdev->mode_info.crtcs[1]->base.primary->fb;
3226
3227                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3228                         pixel_bytes2 = fb->format->cpp[0];
3229                 }
3230         }
3231
3232         min_mem_eff.full = dfixed_const_8(0);
3233         /* get modes */
3234         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3235                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3236                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3237                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3238                 /* check crtc enables */
3239                 if (mode2)
3240                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3241                 if (mode1)
3242                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3243                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3244         }
3245
3246         /*
3247          * determine is there is enough bw for current mode
3248          */
3249         sclk_ff = rdev->pm.sclk;
3250         mclk_ff = rdev->pm.mclk;
3251
3252         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3253         temp_ff.full = dfixed_const(temp);
3254         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3255
3256         pix_clk.full = 0;
3257         pix_clk2.full = 0;
3258         peak_disp_bw.full = 0;
3259         if (mode1) {
3260                 temp_ff.full = dfixed_const(1000);
3261                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3262                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3263                 temp_ff.full = dfixed_const(pixel_bytes1);
3264                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3265         }
3266         if (mode2) {
3267                 temp_ff.full = dfixed_const(1000);
3268                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3269                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3270                 temp_ff.full = dfixed_const(pixel_bytes2);
3271                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3272         }
3273
3274         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3275         if (peak_disp_bw.full >= mem_bw.full) {
3276                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3277                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3278         }
3279
3280         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3281         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3282         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3283                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3284                 mem_trp  = ((temp & 0x3)) + 1;
3285                 mem_tras = ((temp & 0x70) >> 4) + 1;
3286         } else if (rdev->family == CHIP_R300 ||
3287                    rdev->family == CHIP_R350) { /* r300, r350 */
3288                 mem_trcd = (temp & 0x7) + 1;
3289                 mem_trp = ((temp >> 8) & 0x7) + 1;
3290                 mem_tras = ((temp >> 11) & 0xf) + 4;
3291         } else if (rdev->family == CHIP_RV350 ||
3292                    rdev->family == CHIP_RV380) {
3293                 /* rv3x0 */
3294                 mem_trcd = (temp & 0x7) + 3;
3295                 mem_trp = ((temp >> 8) & 0x7) + 3;
3296                 mem_tras = ((temp >> 11) & 0xf) + 6;
3297         } else if (rdev->family == CHIP_R420 ||
3298                    rdev->family == CHIP_R423 ||
3299                    rdev->family == CHIP_RV410) {
3300                 /* r4xx */
3301                 mem_trcd = (temp & 0xf) + 3;
3302                 if (mem_trcd > 15)
3303                         mem_trcd = 15;
3304                 mem_trp = ((temp >> 8) & 0xf) + 3;
3305                 if (mem_trp > 15)
3306                         mem_trp = 15;
3307                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3308                 if (mem_tras > 31)
3309                         mem_tras = 31;
3310         } else { /* RV200, R200 */
3311                 mem_trcd = (temp & 0x7) + 1;
3312                 mem_trp = ((temp >> 8) & 0x7) + 1;
3313                 mem_tras = ((temp >> 12) & 0xf) + 4;
3314         }
3315         /* convert to FF */
3316         trcd_ff.full = dfixed_const(mem_trcd);
3317         trp_ff.full = dfixed_const(mem_trp);
3318         tras_ff.full = dfixed_const(mem_tras);
3319
3320         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3321         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3322         data = (temp & (7 << 20)) >> 20;
3323         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3324                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3325                         tcas_ff = memtcas_rs480_ff[data];
3326                 else
3327                         tcas_ff = memtcas_ff[data];
3328         } else
3329                 tcas_ff = memtcas2_ff[data];
3330
3331         if (rdev->family == CHIP_RS400 ||
3332             rdev->family == CHIP_RS480) {
3333                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3334                 data = (temp >> 23) & 0x7;
3335                 if (data < 5)
3336                         tcas_ff.full += dfixed_const(data);
3337         }
3338
3339         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3340                 /* on the R300, Tcas is included in Trbs.
3341                  */
3342                 temp = RREG32(RADEON_MEM_CNTL);
3343                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3344                 if (data == 1) {
3345                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3346                                 temp = RREG32(R300_MC_IND_INDEX);
3347                                 temp &= ~R300_MC_IND_ADDR_MASK;
3348                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3349                                 WREG32(R300_MC_IND_INDEX, temp);
3350                                 temp = RREG32(R300_MC_IND_DATA);
3351                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3352                         } else {
3353                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3354                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3355                         }
3356                 } else {
3357                         temp = RREG32(R300_MC_READ_CNTL_AB);
3358                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3359                 }
3360                 if (rdev->family == CHIP_RV410 ||
3361                     rdev->family == CHIP_R420 ||
3362                     rdev->family == CHIP_R423)
3363                         trbs_ff = memtrbs_r4xx[data];
3364                 else
3365                         trbs_ff = memtrbs[data];
3366                 tcas_ff.full += trbs_ff.full;
3367         }
3368
3369         sclk_eff_ff.full = sclk_ff.full;
3370
3371         if (rdev->flags & RADEON_IS_AGP) {
3372                 fixed20_12 agpmode_ff;
3373                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3374                 temp_ff.full = dfixed_const_666(16);
3375                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3376         }
3377         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3378
3379         if (ASIC_IS_R300(rdev)) {
3380                 sclk_delay_ff.full = dfixed_const(250);
3381         } else {
3382                 if ((rdev->family == CHIP_RV100) ||
3383                     rdev->flags & RADEON_IS_IGP) {
3384                         if (rdev->mc.vram_is_ddr)
3385                                 sclk_delay_ff.full = dfixed_const(41);
3386                         else
3387                                 sclk_delay_ff.full = dfixed_const(33);
3388                 } else {
3389                         if (rdev->mc.vram_width == 128)
3390                                 sclk_delay_ff.full = dfixed_const(57);
3391                         else
3392                                 sclk_delay_ff.full = dfixed_const(41);
3393                 }
3394         }
3395
3396         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3397
3398         if (rdev->mc.vram_is_ddr) {
3399                 if (rdev->mc.vram_width == 32) {
3400                         k1.full = dfixed_const(40);
3401                         c  = 3;
3402                 } else {
3403                         k1.full = dfixed_const(20);
3404                         c  = 1;
3405                 }
3406         } else {
3407                 k1.full = dfixed_const(40);
3408                 c  = 3;
3409         }
3410
3411         temp_ff.full = dfixed_const(2);
3412         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3413         temp_ff.full = dfixed_const(c);
3414         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3415         temp_ff.full = dfixed_const(4);
3416         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3417         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3418         mc_latency_mclk.full += k1.full;
3419
3420         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3421         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3422
3423         /*
3424           HW cursor time assuming worst case of full size colour cursor.
3425         */
3426         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3427         temp_ff.full += trcd_ff.full;
3428         if (temp_ff.full < tras_ff.full)
3429                 temp_ff.full = tras_ff.full;
3430         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3431
3432         temp_ff.full = dfixed_const(cur_size);
3433         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3434         /*
3435           Find the total latency for the display data.
3436         */
3437         disp_latency_overhead.full = dfixed_const(8);
3438         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3439         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3440         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3441
3442         if (mc_latency_mclk.full > mc_latency_sclk.full)
3443                 disp_latency.full = mc_latency_mclk.full;
3444         else
3445                 disp_latency.full = mc_latency_sclk.full;
3446
3447         /* setup Max GRPH_STOP_REQ default value */
3448         if (ASIC_IS_RV100(rdev))
3449                 max_stop_req = 0x5c;
3450         else
3451                 max_stop_req = 0x7c;
3452
3453         if (mode1) {
3454                 /*  CRTC1
3455                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3456                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3457                 */
3458                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3459
3460                 if (stop_req > max_stop_req)
3461                         stop_req = max_stop_req;
3462
3463                 /*
3464                   Find the drain rate of the display buffer.
3465                 */
3466                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3467                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3468
3469                 /*
3470                   Find the critical point of the display buffer.
3471                 */
3472                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3473                 crit_point_ff.full += dfixed_const_half(0);
3474
3475                 critical_point = dfixed_trunc(crit_point_ff);
3476
3477                 if (rdev->disp_priority == 2) {
3478                         critical_point = 0;
3479                 }
3480
3481                 /*
3482                   The critical point should never be above max_stop_req-4.  Setting
3483                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3484                 */
3485                 if (max_stop_req - critical_point < 4)
3486                         critical_point = 0;
3487
3488                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3489                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3490                         critical_point = 0x10;
3491                 }
3492
3493                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3494                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3495                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3496                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3497                 if ((rdev->family == CHIP_R350) &&
3498                     (stop_req > 0x15)) {
3499                         stop_req -= 0x10;
3500                 }
3501                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3502                 temp |= RADEON_GRPH_BUFFER_SIZE;
3503                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3504                           RADEON_GRPH_CRITICAL_AT_SOF |
3505                           RADEON_GRPH_STOP_CNTL);
3506                 /*
3507                   Write the result into the register.
3508                 */
3509                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3510                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3511
3512 #if 0
3513                 if ((rdev->family == CHIP_RS400) ||
3514                     (rdev->family == CHIP_RS480)) {
3515                         /* attempt to program RS400 disp regs correctly ??? */
3516                         temp = RREG32(RS400_DISP1_REG_CNTL);
3517                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3518                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3519                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3520                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3521                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3522                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3523                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3524                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3525                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3526                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3527                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3528                 }
3529 #endif
3530
3531                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3532                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3533                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3534         }
3535
3536         if (mode2) {
3537                 u32 grph2_cntl;
3538                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3539
3540                 if (stop_req > max_stop_req)
3541                         stop_req = max_stop_req;
3542
3543                 /*
3544                   Find the drain rate of the display buffer.
3545                 */
3546                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3547                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3548
3549                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3550                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3551                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3552                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3553                 if ((rdev->family == CHIP_R350) &&
3554                     (stop_req > 0x15)) {
3555                         stop_req -= 0x10;
3556                 }
3557                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3558                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3559                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3560                           RADEON_GRPH_CRITICAL_AT_SOF |
3561                           RADEON_GRPH_STOP_CNTL);
3562
3563                 if ((rdev->family == CHIP_RS100) ||
3564                     (rdev->family == CHIP_RS200))
3565                         critical_point2 = 0;
3566                 else {
3567                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3568                         temp_ff.full = dfixed_const(temp);
3569                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3570                         if (sclk_ff.full < temp_ff.full)
3571                                 temp_ff.full = sclk_ff.full;
3572
3573                         read_return_rate.full = temp_ff.full;
3574
3575                         if (mode1) {
3576                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3577                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3578                         } else {
3579                                 time_disp1_drop_priority.full = 0;
3580                         }
3581                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3582                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3583                         crit_point_ff.full += dfixed_const_half(0);
3584
3585                         critical_point2 = dfixed_trunc(crit_point_ff);
3586
3587                         if (rdev->disp_priority == 2) {
3588                                 critical_point2 = 0;
3589                         }
3590
3591                         if (max_stop_req - critical_point2 < 4)
3592                                 critical_point2 = 0;
3593
3594                 }
3595
3596                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3597                         /* some R300 cards have problem with this set to 0 */
3598                         critical_point2 = 0x10;
3599                 }
3600
3601                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3602                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3603
3604                 if ((rdev->family == CHIP_RS400) ||
3605                     (rdev->family == CHIP_RS480)) {
3606 #if 0
3607                         /* attempt to program RS400 disp2 regs correctly ??? */
3608                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3609                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3610                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3611                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3612                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3613                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3614                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3615                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3616                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3617                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3618                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3619                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3620 #endif
3621                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3622                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3623                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3624                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3625                 }
3626
3627                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3628                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3629         }
3630
3631         /* Save number of lines the linebuffer leads before the scanout */
3632         if (mode1)
3633             rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3634
3635         if (mode2)
3636             rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3637 }
3638
3639 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3640 {
3641         uint32_t scratch;
3642         uint32_t tmp = 0;
3643         unsigned i;
3644         int r;
3645
3646         r = radeon_scratch_get(rdev, &scratch);
3647         if (r) {
3648                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3649                 return r;
3650         }
3651         WREG32(scratch, 0xCAFEDEAD);
3652         r = radeon_ring_lock(rdev, ring, 2);
3653         if (r) {
3654                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3655                 radeon_scratch_free(rdev, scratch);
3656                 return r;
3657         }
3658         radeon_ring_write(ring, PACKET0(scratch, 0));
3659         radeon_ring_write(ring, 0xDEADBEEF);
3660         radeon_ring_unlock_commit(rdev, ring, false);
3661         for (i = 0; i < rdev->usec_timeout; i++) {
3662                 tmp = RREG32(scratch);
3663                 if (tmp == 0xDEADBEEF) {
3664                         break;
3665                 }
3666                 DRM_UDELAY(1);
3667         }
3668         if (i < rdev->usec_timeout) {
3669                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3670         } else {
3671                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3672                           scratch, tmp);
3673                 r = -EINVAL;
3674         }
3675         radeon_scratch_free(rdev, scratch);
3676         return r;
3677 }
3678
3679 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3680 {
3681         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3682
3683         if (ring->rptr_save_reg) {
3684                 u32 next_rptr = ring->wptr + 2 + 3;
3685                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3686                 radeon_ring_write(ring, next_rptr);
3687         }
3688
3689         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3690         radeon_ring_write(ring, ib->gpu_addr);
3691         radeon_ring_write(ring, ib->length_dw);
3692 }
3693
3694 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3695 {
3696         struct radeon_ib ib;
3697         uint32_t scratch;
3698         uint32_t tmp = 0;
3699         unsigned i;
3700         int r;
3701
3702         r = radeon_scratch_get(rdev, &scratch);
3703         if (r) {
3704                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3705                 return r;
3706         }
3707         WREG32(scratch, 0xCAFEDEAD);
3708         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3709         if (r) {
3710                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3711                 goto free_scratch;
3712         }
3713         ib.ptr[0] = PACKET0(scratch, 0);
3714         ib.ptr[1] = 0xDEADBEEF;
3715         ib.ptr[2] = PACKET2(0);
3716         ib.ptr[3] = PACKET2(0);
3717         ib.ptr[4] = PACKET2(0);
3718         ib.ptr[5] = PACKET2(0);
3719         ib.ptr[6] = PACKET2(0);
3720         ib.ptr[7] = PACKET2(0);
3721         ib.length_dw = 8;
3722         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3723         if (r) {
3724                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3725                 goto free_ib;
3726         }
3727         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3728                 RADEON_USEC_IB_TEST_TIMEOUT));
3729         if (r < 0) {
3730                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3731                 goto free_ib;
3732         } else if (r == 0) {
3733                 DRM_ERROR("radeon: fence wait timed out.\n");
3734                 r = -ETIMEDOUT;
3735                 goto free_ib;
3736         }
3737         r = 0;
3738         for (i = 0; i < rdev->usec_timeout; i++) {
3739                 tmp = RREG32(scratch);
3740                 if (tmp == 0xDEADBEEF) {
3741                         break;
3742                 }
3743                 DRM_UDELAY(1);
3744         }
3745         if (i < rdev->usec_timeout) {
3746                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3747         } else {
3748                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3749                           scratch, tmp);
3750                 r = -EINVAL;
3751         }
3752 free_ib:
3753         radeon_ib_free(rdev, &ib);
3754 free_scratch:
3755         radeon_scratch_free(rdev, scratch);
3756         return r;
3757 }
3758
3759 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3760 {
3761         /* Shutdown CP we shouldn't need to do that but better be safe than
3762          * sorry
3763          */
3764         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3765         WREG32(R_000740_CP_CSQ_CNTL, 0);
3766
3767         /* Save few CRTC registers */
3768         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3769         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3770         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3771         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3772         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3773                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3774                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3775         }
3776
3777         /* Disable VGA aperture access */
3778         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3779         /* Disable cursor, overlay, crtc */
3780         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3781         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3782                                         S_000054_CRTC_DISPLAY_DIS(1));
3783         WREG32(R_000050_CRTC_GEN_CNTL,
3784                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3785                         S_000050_CRTC_DISP_REQ_EN_B(1));
3786         WREG32(R_000420_OV0_SCALE_CNTL,
3787                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3788         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3789         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3790                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3791                                                 S_000360_CUR2_LOCK(1));
3792                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3793                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3794                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3795                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3796                 WREG32(R_000360_CUR2_OFFSET,
3797                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3798         }
3799 }
3800
3801 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3802 {
3803         /* Update base address for crtc */
3804         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3805         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3806                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3807         }
3808         /* Restore CRTC registers */
3809         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3810         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3811         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3812         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3813                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3814         }
3815 }
3816
3817 void r100_vga_render_disable(struct radeon_device *rdev)
3818 {
3819         u32 tmp;
3820
3821         tmp = RREG8(R_0003C2_GENMO_WT);
3822         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3823 }
3824
3825 static void r100_debugfs(struct radeon_device *rdev)
3826 {
3827         int r;
3828
3829         r = r100_debugfs_mc_info_init(rdev);
3830         if (r)
3831                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3832 }
3833
3834 static void r100_mc_program(struct radeon_device *rdev)
3835 {
3836         struct r100_mc_save save;
3837
3838         /* Stops all mc clients */
3839         r100_mc_stop(rdev, &save);
3840         if (rdev->flags & RADEON_IS_AGP) {
3841                 WREG32(R_00014C_MC_AGP_LOCATION,
3842                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3843                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3844                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3845                 if (rdev->family > CHIP_RV200)
3846                         WREG32(R_00015C_AGP_BASE_2,
3847                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3848         } else {
3849                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3850                 WREG32(R_000170_AGP_BASE, 0);
3851                 if (rdev->family > CHIP_RV200)
3852                         WREG32(R_00015C_AGP_BASE_2, 0);
3853         }
3854         /* Wait for mc idle */
3855         if (r100_mc_wait_for_idle(rdev))
3856                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3857         /* Program MC, should be a 32bits limited address space */
3858         WREG32(R_000148_MC_FB_LOCATION,
3859                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3860                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3861         r100_mc_resume(rdev, &save);
3862 }
3863
3864 static void r100_clock_startup(struct radeon_device *rdev)
3865 {
3866         u32 tmp;
3867
3868         if (radeon_dynclks != -1 && radeon_dynclks)
3869                 radeon_legacy_set_clock_gating(rdev, 1);
3870         /* We need to force on some of the block */
3871         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3872         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3873         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3874                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3875         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3876 }
3877
3878 static int r100_startup(struct radeon_device *rdev)
3879 {
3880         int r;
3881
3882         /* set common regs */
3883         r100_set_common_regs(rdev);
3884         /* program mc */
3885         r100_mc_program(rdev);
3886         /* Resume clock */
3887         r100_clock_startup(rdev);
3888         /* Initialize GART (initialize after TTM so we can allocate
3889          * memory through TTM but finalize after TTM) */
3890         r100_enable_bm(rdev);
3891         if (rdev->flags & RADEON_IS_PCI) {
3892                 r = r100_pci_gart_enable(rdev);
3893                 if (r)
3894                         return r;
3895         }
3896
3897         /* allocate wb buffer */
3898         r = radeon_wb_init(rdev);
3899         if (r)
3900                 return r;
3901
3902         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3903         if (r) {
3904                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3905                 return r;
3906         }
3907
3908         /* Enable IRQ */
3909         if (!rdev->irq.installed) {
3910                 r = radeon_irq_kms_init(rdev);
3911                 if (r)
3912                         return r;
3913         }
3914
3915         r100_irq_set(rdev);
3916         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3917         /* 1M ring buffer */
3918         r = r100_cp_init(rdev, 1024 * 1024);
3919         if (r) {
3920                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3921                 return r;
3922         }
3923
3924         r = radeon_ib_pool_init(rdev);
3925         if (r) {
3926                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3927                 return r;
3928         }
3929
3930         return 0;
3931 }
3932
3933 int r100_resume(struct radeon_device *rdev)
3934 {
3935         int r;
3936
3937         /* Make sur GART are not working */
3938         if (rdev->flags & RADEON_IS_PCI)
3939                 r100_pci_gart_disable(rdev);
3940         /* Resume clock before doing reset */
3941         r100_clock_startup(rdev);
3942         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3943         if (radeon_asic_reset(rdev)) {
3944                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3945                         RREG32(R_000E40_RBBM_STATUS),
3946                         RREG32(R_0007C0_CP_STAT));
3947         }
3948         /* post */
3949         radeon_combios_asic_init(rdev->ddev);
3950         /* Resume clock after posting */
3951         r100_clock_startup(rdev);
3952         /* Initialize surface registers */
3953         radeon_surface_init(rdev);
3954
3955         rdev->accel_working = true;
3956         r = r100_startup(rdev);
3957         if (r) {
3958                 rdev->accel_working = false;
3959         }
3960         return r;
3961 }
3962
3963 int r100_suspend(struct radeon_device *rdev)
3964 {
3965         radeon_pm_suspend(rdev);
3966         r100_cp_disable(rdev);
3967         radeon_wb_disable(rdev);
3968         r100_irq_disable(rdev);
3969         if (rdev->flags & RADEON_IS_PCI)
3970                 r100_pci_gart_disable(rdev);
3971         return 0;
3972 }
3973
3974 void r100_fini(struct radeon_device *rdev)
3975 {
3976         radeon_pm_fini(rdev);
3977         r100_cp_fini(rdev);
3978         radeon_wb_fini(rdev);
3979         radeon_ib_pool_fini(rdev);
3980         radeon_gem_fini(rdev);
3981         if (rdev->flags & RADEON_IS_PCI)
3982                 r100_pci_gart_fini(rdev);
3983         radeon_agp_fini(rdev);
3984         radeon_irq_kms_fini(rdev);
3985         radeon_fence_driver_fini(rdev);
3986         radeon_bo_fini(rdev);
3987         radeon_atombios_fini(rdev);
3988         kfree(rdev->bios);
3989         rdev->bios = NULL;
3990 }
3991
3992 /*
3993  * Due to how kexec works, it can leave the hw fully initialised when it
3994  * boots the new kernel. However doing our init sequence with the CP and
3995  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3996  * do some quick sanity checks and restore sane values to avoid this
3997  * problem.
3998  */
3999 void r100_restore_sanity(struct radeon_device *rdev)
4000 {
4001         u32 tmp;
4002
4003         tmp = RREG32(RADEON_CP_CSQ_CNTL);
4004         if (tmp) {
4005                 WREG32(RADEON_CP_CSQ_CNTL, 0);
4006         }
4007         tmp = RREG32(RADEON_CP_RB_CNTL);
4008         if (tmp) {
4009                 WREG32(RADEON_CP_RB_CNTL, 0);
4010         }
4011         tmp = RREG32(RADEON_SCRATCH_UMSK);
4012         if (tmp) {
4013                 WREG32(RADEON_SCRATCH_UMSK, 0);
4014         }
4015 }
4016
4017 int r100_init(struct radeon_device *rdev)
4018 {
4019         int r;
4020
4021         /* Register debugfs file specific to this group of asics */
4022         r100_debugfs(rdev);
4023         /* Disable VGA */
4024         r100_vga_render_disable(rdev);
4025         /* Initialize scratch registers */
4026         radeon_scratch_init(rdev);
4027         /* Initialize surface registers */
4028         radeon_surface_init(rdev);
4029         /* sanity check some register to avoid hangs like after kexec */
4030         r100_restore_sanity(rdev);
4031         /* TODO: disable VGA need to use VGA request */
4032         /* BIOS*/
4033         if (!radeon_get_bios(rdev)) {
4034                 if (ASIC_IS_AVIVO(rdev))
4035                         return -EINVAL;
4036         }
4037         if (rdev->is_atom_bios) {
4038                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4039                 return -EINVAL;
4040         } else {
4041                 r = radeon_combios_init(rdev);
4042                 if (r)
4043                         return r;
4044         }
4045         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4046         if (radeon_asic_reset(rdev)) {
4047                 dev_warn(rdev->dev,
4048                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4049                         RREG32(R_000E40_RBBM_STATUS),
4050                         RREG32(R_0007C0_CP_STAT));
4051         }
4052         /* check if cards are posted or not */
4053         if (radeon_boot_test_post_card(rdev) == false)
4054                 return -EINVAL;
4055         /* Set asic errata */
4056         r100_errata(rdev);
4057         /* Initialize clocks */
4058         radeon_get_clock_info(rdev->ddev);
4059         /* initialize AGP */
4060         if (rdev->flags & RADEON_IS_AGP) {
4061                 r = radeon_agp_init(rdev);
4062                 if (r) {
4063                         radeon_agp_disable(rdev);
4064                 }
4065         }
4066         /* initialize VRAM */
4067         r100_mc_init(rdev);
4068         /* Fence driver */
4069         r = radeon_fence_driver_init(rdev);
4070         if (r)
4071                 return r;
4072         /* Memory manager */
4073         r = radeon_bo_init(rdev);
4074         if (r)
4075                 return r;
4076         if (rdev->flags & RADEON_IS_PCI) {
4077                 r = r100_pci_gart_init(rdev);
4078                 if (r)
4079                         return r;
4080         }
4081         r100_set_safe_registers(rdev);
4082
4083         /* Initialize power management */
4084         radeon_pm_init(rdev);
4085
4086         rdev->accel_working = true;
4087         r = r100_startup(rdev);
4088         if (r) {
4089                 /* Somethings want wront with the accel init stop accel */
4090                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4091                 r100_cp_fini(rdev);
4092                 radeon_wb_fini(rdev);
4093                 radeon_ib_pool_fini(rdev);
4094                 radeon_irq_kms_fini(rdev);
4095                 if (rdev->flags & RADEON_IS_PCI)
4096                         r100_pci_gart_fini(rdev);
4097                 rdev->accel_working = false;
4098         }
4099         return 0;
4100 }
4101
4102 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4103 {
4104         unsigned long flags;
4105         uint32_t ret;
4106
4107         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4108         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4109         ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4110         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4111         return ret;
4112 }
4113
4114 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4115 {
4116         unsigned long flags;
4117
4118         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4119         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4120         writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4121         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4122 }
4123
4124 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4125 {
4126         if (reg < rdev->rio_mem_size)
4127                 return ioread32(rdev->rio_mem + reg);
4128         else {
4129                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4130                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4131         }
4132 }
4133
4134 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4135 {
4136         if (reg < rdev->rio_mem_size)
4137                 iowrite32(v, rdev->rio_mem + reg);
4138         else {
4139                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4140                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4141         }
4142 }