drivers/gpu/drm/radeon/cypress_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "radeon.h"
  27 #include "radeon_asic.h"
  28 #include "evergreend.h"
  29 #include "r600_dpm.h"
  30 #include "cypress_dpm.h"
  31 #include "atom.h"
  32
  33 #define SMC_RAM_END 0x8000
  34
  35 #define MC_CG_ARB_FREQ_F0           0x0a
  36 #define MC_CG_ARB_FREQ_F1           0x0b
  37 #define MC_CG_ARB_FREQ_F2           0x0c
  38 #define MC_CG_ARB_FREQ_F3           0x0d
  39
  40 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  41 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  42 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  43 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  44
  45 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
  46 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
  47 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
  48
  49 static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
  50                                                  bool enable)
  51 {
  52         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  53         u32 tmp, bif;
  54
  55         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  56         if (enable) {
  57                 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  58                     (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  59                         if (!pi->boot_in_gen2) {
  60                                 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
  61                                 bif |= CG_CLIENT_REQ(0xd);
  62                                 WREG32(CG_BIF_REQ_AND_RSP, bif);
  63
  64                                 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
  65                                 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
  66                                 tmp |= LC_GEN2_EN_STRAP;
  67
  68                                 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
  69                                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  70                                 udelay(10);
  71                                 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
  72                                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  73                         }
  74                 }
  75         } else {
  76                 if (!pi->boot_in_gen2) {
  77                         tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
  78                         tmp &= ~LC_GEN2_EN_STRAP;
  79                 }
  80                 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
  81                     (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
  82                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  83         }
  84 }
  85
  86 static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
  87                                              bool enable)
  88 {
  89         cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
  90
  91         if (enable)
  92                 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
  93         else
  94                 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
  95 }
  96
  97 #if 0
  98 static int cypress_enter_ulp_state(struct radeon_device *rdev)
  99 {
 100         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 101
 102         if (pi->gfx_clock_gating) {
 103                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
 104                 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
 105                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
 106
 107                 RREG32(GB_ADDR_CONFIG);
 108         }
 109
 110         WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
 111                  ~HOST_SMC_MSG_MASK);
 112
 113         udelay(7000);
 114
 115         return 0;
 116 }
 117 #endif
 118
 119 static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
 120                                             bool enable)
 121 {
 122         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 123
 124         if (enable) {
 125                 if (eg_pi->light_sleep) {
 126                         WREG32(GRBM_GFX_INDEX, 0xC0000000);
 127
 128                         WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF);
 129                         WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF);
 130                         WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF);
 131                         WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF);
 132                         WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF);
 133                         WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF);
 134                         WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF);
 135                         WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF);
 136                         WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF);
 137                         WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF);
 138                         WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF);
 139                         WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF);
 140
 141                         WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
 142                 }
 143                 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
 144         } else {
 145                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
 146                 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
 147                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
 148                 RREG32(GB_ADDR_CONFIG);
 149
 150                 if (eg_pi->light_sleep) {
 151                         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
 152
 153                         WREG32(GRBM_GFX_INDEX, 0xC0000000);
 154
 155                         WREG32_CG(CG_CGLS_TILE_0, 0);
 156                         WREG32_CG(CG_CGLS_TILE_1, 0);
 157                         WREG32_CG(CG_CGLS_TILE_2, 0);
 158                         WREG32_CG(CG_CGLS_TILE_3, 0);
 159                         WREG32_CG(CG_CGLS_TILE_4, 0);
 160                         WREG32_CG(CG_CGLS_TILE_5, 0);
 161                         WREG32_CG(CG_CGLS_TILE_6, 0);
 162                         WREG32_CG(CG_CGLS_TILE_7, 0);
 163                         WREG32_CG(CG_CGLS_TILE_8, 0);
 164                         WREG32_CG(CG_CGLS_TILE_9, 0);
 165                         WREG32_CG(CG_CGLS_TILE_10, 0);
 166                         WREG32_CG(CG_CGLS_TILE_11, 0);
 167                 }
 168         }
 169 }
 170
 171 static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
 172                                            bool enable)
 173 {
 174         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 175         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 176
 177         if (enable) {
 178                 u32 cgts_sm_ctrl_reg;
 179
 180                 if (rdev->family == CHIP_CEDAR)
 181                         cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT;
 182                 else if (rdev->family == CHIP_REDWOOD)
 183                         cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT;
 184                 else
 185                         cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT;
 186
 187                 WREG32(GRBM_GFX_INDEX, 0xC0000000);
 188
 189                 WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT);
 190                 WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF);
 191                 WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT);
 192                 WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT);
 193
 194                 if (pi->mgcgtssm)
 195                         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 196
 197                 if (eg_pi->mcls) {
 198                         WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 199                         WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 200                         WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 201                         WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 202                         WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 203                         WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 204                         WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 205                         WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
 206                 }
 207         } else {
 208                 WREG32(GRBM_GFX_INDEX, 0xC0000000);
 209
 210                 WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
 211                 WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF);
 212                 WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF);
 213                 WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF);
 214
 215                 if (pi->mgcgtssm)
 216                         WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
 217         }
 218 }
 219
 220 void cypress_enable_spread_spectrum(struct radeon_device *rdev,
 221                                     bool enable)
 222 {
 223         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 224
 225         if (enable) {
 226                 if (pi->sclk_ss)
 227                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
 228
 229                 if (pi->mclk_ss)
 230                         WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
 231         } else {
 232                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
 233                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
 234                 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
 235                 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
 236         }
 237 }
 238
 239 void cypress_start_dpm(struct radeon_device *rdev)
 240 {
 241         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
 242 }
 243
 244 void cypress_enable_sclk_control(struct radeon_device *rdev,
 245                                  bool enable)
 246 {
 247         if (enable)
 248                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
 249         else
 250                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
 251 }
 252
 253 void cypress_enable_mclk_control(struct radeon_device *rdev,
 254                                  bool enable)
 255 {
 256         if (enable)
 257                 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
 258         else
 259                 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
 260 }
 261
 262 int cypress_notify_smc_display_change(struct radeon_device *rdev,
 263                                       bool has_display)
 264 {
 265         PPSMC_Msg msg = has_display ?
 266                 (PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay;
 267
 268         if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
 269                 return -EINVAL;
 270
 271         return 0;
 272 }
 273
 274 void cypress_program_response_times(struct radeon_device *rdev)
 275 {
 276         u32 reference_clock;
 277         u32 mclk_switch_limit;
 278
 279         reference_clock = radeon_get_xclk(rdev);
 280         mclk_switch_limit = (460 * reference_clock) / 100;
 281
 282         rv770_write_smc_soft_register(rdev,
 283                                       RV770_SMC_SOFT_REGISTER_mclk_switch_lim,
 284                                       mclk_switch_limit);
 285
 286         rv770_write_smc_soft_register(rdev,
 287                                       RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
 288
 289         rv770_write_smc_soft_register(rdev,
 290                                       RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
 291
 292         rv770_program_response_times(rdev);
 293
 294         if (ASIC_IS_LOMBOK(rdev))
 295                 rv770_write_smc_soft_register(rdev,
 296                                               RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1);
 297
 298 }
 299
 300 static int cypress_pcie_performance_request(struct radeon_device *rdev,
 301                                             u8 perf_req, bool advertise)
 302 {
 303 #if defined(CONFIG_ACPI)
 304         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 305 #endif
 306         u32 tmp;
 307
 308         udelay(10);
 309         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 310         if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
 311                 return 0;
 312
 313 #if defined(CONFIG_ACPI)
 314         if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
 315             (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
 316                 eg_pi->pcie_performance_request_registered = true;
 317                 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
 318         } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
 319                    eg_pi->pcie_performance_request_registered) {
 320                 eg_pi->pcie_performance_request_registered = false;
 321                 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
 322         }
 323 #endif
 324
 325         return 0;
 326 }
 327
 328 void cypress_advertise_gen2_capability(struct radeon_device *rdev)
 329 {
 330         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 331         u32 tmp;
 332
 333 #if defined(CONFIG_ACPI)
 334         radeon_acpi_pcie_notify_device_ready(rdev);
 335 #endif
 336
 337         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 338
 339         if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
 340             (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
 341                 pi->pcie_gen2 = true;
 342         else
 343                 pi->pcie_gen2 = false;
 344
 345         if (!pi->pcie_gen2)
 346                 cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
 347
 348 }
 349
 350 static enum radeon_pcie_gen cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
 351 {
 352         struct rv7xx_ps *state = rv770_get_ps(radeon_state);
 353
 354         if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
 355                 return 1;
 356         return 0;
 357 }
 358
 359 void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
 360                                                          struct radeon_ps *radeon_new_state,
 361                                                          struct radeon_ps *radeon_current_state)
 362 {
 363         enum radeon_pcie_gen pcie_link_speed_target =
 364                 cypress_get_maximum_link_speed(radeon_new_state);
 365         enum radeon_pcie_gen pcie_link_speed_current =
 366                 cypress_get_maximum_link_speed(radeon_current_state);
 367         u8 request;
 368
 369         if (pcie_link_speed_target < pcie_link_speed_current) {
 370                 if (pcie_link_speed_target == RADEON_PCIE_GEN1)
 371                         request = PCIE_PERF_REQ_PECI_GEN1;
 372                 else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
 373                         request = PCIE_PERF_REQ_PECI_GEN2;
 374                 else
 375                         request = PCIE_PERF_REQ_PECI_GEN3;
 376
 377                 cypress_pcie_performance_request(rdev, request, false);
 378         }
 379 }
 380
 381 void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
 382                                                           struct radeon_ps *radeon_new_state,
 383                                                           struct radeon_ps *radeon_current_state)
 384 {
 385         enum radeon_pcie_gen pcie_link_speed_target =
 386                 cypress_get_maximum_link_speed(radeon_new_state);
 387         enum radeon_pcie_gen pcie_link_speed_current =
 388                 cypress_get_maximum_link_speed(radeon_current_state);
 389         u8 request;
 390
 391         if (pcie_link_speed_target > pcie_link_speed_current) {
 392                 if (pcie_link_speed_target == RADEON_PCIE_GEN1)
 393                         request = PCIE_PERF_REQ_PECI_GEN1;
 394                 else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
 395                         request = PCIE_PERF_REQ_PECI_GEN2;
 396                 else
 397                         request = PCIE_PERF_REQ_PECI_GEN3;
 398
 399                 cypress_pcie_performance_request(rdev, request, false);
 400         }
 401 }
 402
 403 static int cypress_populate_voltage_value(struct radeon_device *rdev,
 404                                           struct atom_voltage_table *table,
 405                                           u16 value, RV770_SMC_VOLTAGE_VALUE *voltage)
 406 {
 407         unsigned int i;
 408
 409         for (i = 0; i < table->count; i++) {
 410                 if (value <= table->entries[i].value) {
 411                         voltage->index = (u8)i;
 412                         voltage->value = cpu_to_be16(table->entries[i].value);
 413                         break;
 414                 }
 415         }
 416
 417         if (i == table->count)
 418                 return -EINVAL;
 419
 420         return 0;
 421 }
 422
 423 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
 424 {
 425         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 426         u8 result = 0;
 427         bool strobe_mode = false;
 428
 429         if (pi->mem_gddr5) {
 430                 if (mclk <= pi->mclk_strobe_mode_threshold)
 431                         strobe_mode = true;
 432                 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
 433
 434                 if (strobe_mode)
 435                         result |= SMC_STROBE_ENABLE;
 436         }
 437
 438         return result;
 439 }
 440
 441 u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
 442 {
 443         u32 ref_clk = rdev->clock.mpll.reference_freq;
 444         u32 vco = clkf * ref_clk;
 445
 446         /* 100 Mhz ref clk */
 447         if (ref_clk == 10000) {
 448                 if (vco > 500000)
 449                         return 0xC6;
 450                 if (vco > 400000)
 451                         return 0x9D;
 452                 if (vco > 330000)
 453                         return 0x6C;
 454                 if (vco > 250000)
 455                         return 0x2B;
 456                 if (vco >  160000)
 457                         return 0x5B;
 458                 if (vco > 120000)
 459                         return 0x0A;
 460                 return 0x4B;
 461         }
 462
 463         /* 27 Mhz ref clk */
 464         if (vco > 250000)
 465                 return 0x8B;
 466         if (vco > 200000)
 467                 return 0xCC;
 468         if (vco > 150000)
 469                 return 0x9B;
 470         return 0x6B;
 471 }
 472
 473 static int cypress_populate_mclk_value(struct radeon_device *rdev,
 474                                        u32 engine_clock, u32 memory_clock,
 475                                        RV7XX_SMC_MCLK_VALUE *mclk,
 476                                        bool strobe_mode, bool dll_state_on)
 477 {
 478         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 479
 480         u32 mpll_ad_func_cntl =
 481                 pi->clk_regs.rv770.mpll_ad_func_cntl;
 482         u32 mpll_ad_func_cntl_2 =
 483                 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
 484         u32 mpll_dq_func_cntl =
 485                 pi->clk_regs.rv770.mpll_dq_func_cntl;
 486         u32 mpll_dq_func_cntl_2 =
 487                 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
 488         u32 mclk_pwrmgt_cntl =
 489                 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
 490         u32 dll_cntl =
 491                 pi->clk_regs.rv770.dll_cntl;
 492         u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
 493         u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
 494         struct atom_clock_dividers dividers;
 495         u32 ibias;
 496         u32 dll_speed;
 497         int ret;
 498         u32 mc_seq_misc7;
 499
 500         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
 501                                              memory_clock, strobe_mode, &dividers);
 502         if (ret)
 503                 return ret;
 504
 505         if (!strobe_mode) {
 506                 mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
 507
 508                 if(mc_seq_misc7 & 0x8000000)
 509                         dividers.post_div = 1;
 510         }
 511
 512         ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
 513
 514         mpll_ad_func_cntl &= ~(CLKR_MASK |
 515                                YCLK_POST_DIV_MASK |
 516                                CLKF_MASK |
 517                                CLKFRAC_MASK |
 518                                IBIAS_MASK);
 519         mpll_ad_func_cntl |= CLKR(dividers.ref_div);
 520         mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
 521         mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
 522         mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
 523         mpll_ad_func_cntl |= IBIAS(ibias);
 524
 525         if (dividers.vco_mode)
 526                 mpll_ad_func_cntl_2 |= VCO_MODE;
 527         else
 528                 mpll_ad_func_cntl_2 &= ~VCO_MODE;
 529
 530         if (pi->mem_gddr5) {
 531                 mpll_dq_func_cntl &= ~(CLKR_MASK |
 532                                        YCLK_POST_DIV_MASK |
 533                                        CLKF_MASK |
 534                                        CLKFRAC_MASK |
 535                                        IBIAS_MASK);
 536                 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
 537                 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
 538                 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
 539                 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
 540                 mpll_dq_func_cntl |= IBIAS(ibias);
 541
 542                 if (strobe_mode)
 543                         mpll_dq_func_cntl &= ~PDNB;
 544                 else
 545                         mpll_dq_func_cntl |= PDNB;
 546
 547                 if (dividers.vco_mode)
 548                         mpll_dq_func_cntl_2 |= VCO_MODE;
 549                 else
 550                         mpll_dq_func_cntl_2 &= ~VCO_MODE;
 551         }
 552
 553         if (pi->mclk_ss) {
 554                 struct radeon_atom_ss ss;
 555                 u32 vco_freq = memory_clock * dividers.post_div;
 556
 557                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 558                                                      ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
 559                         u32 reference_clock = rdev->clock.mpll.reference_freq;
 560                         u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
 561                         u32 clk_s, clk_v;
 562
 563                         if (!decoded_ref)
 564                                 return -EINVAL;
 565                         clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
 566                         clk_v = ss.percentage *
 567                                 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
 568
 569                         mpll_ss1 &= ~CLKV_MASK;
 570                         mpll_ss1 |= CLKV(clk_v);
 571
 572                         mpll_ss2 &= ~CLKS_MASK;
 573                         mpll_ss2 |= CLKS(clk_s);
 574                 }
 575         }
 576
 577         dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
 578                                         memory_clock);
 579
 580         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
 581         mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
 582         if (dll_state_on)
 583                 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
 584                                      MRDCKA1_PDNB |
 585                                      MRDCKB0_PDNB |
 586                                      MRDCKB1_PDNB |
 587                                      MRDCKC0_PDNB |
 588                                      MRDCKC1_PDNB |
 589                                      MRDCKD0_PDNB |
 590                                      MRDCKD1_PDNB);
 591         else
 592                 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
 593                                       MRDCKA1_PDNB |
 594                                       MRDCKB0_PDNB |
 595                                       MRDCKB1_PDNB |
 596                                       MRDCKC0_PDNB |
 597                                       MRDCKC1_PDNB |
 598                                       MRDCKD0_PDNB |
 599                                       MRDCKD1_PDNB);
 600
 601         mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
 602         mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
 603         mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
 604         mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
 605         mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
 606         mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
 607         mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
 608         mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
 609         mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
 610
 611         return 0;
 612 }
 613
 614 u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
 615                                     u32 memory_clock, bool strobe_mode)
 616 {
 617         u8 mc_para_index;
 618
 619         if (rdev->family >= CHIP_BARTS) {
 620                 if (strobe_mode) {
 621                         if (memory_clock < 10000)
 622                                 mc_para_index = 0x00;
 623                         else if (memory_clock > 47500)
 624                                 mc_para_index = 0x0f;
 625                         else
 626                                 mc_para_index = (u8)((memory_clock - 10000) / 2500);
 627                 } else {
 628                         if (memory_clock < 65000)
 629                                 mc_para_index = 0x00;
 630                         else if (memory_clock > 135000)
 631                                 mc_para_index = 0x0f;
 632                         else
 633                                 mc_para_index = (u8)((memory_clock - 60000) / 5000);
 634                 }
 635         } else {
 636                 if (strobe_mode) {
 637                         if (memory_clock < 10000)
 638                                 mc_para_index = 0x00;
 639                         else if (memory_clock > 47500)
 640                                 mc_para_index = 0x0f;
 641                         else
 642                                 mc_para_index = (u8)((memory_clock - 10000) / 2500);
 643                 } else {
 644                         if (memory_clock < 40000)
 645                                 mc_para_index = 0x00;
 646                         else if (memory_clock > 115000)
 647                                 mc_para_index = 0x0f;
 648                         else
 649                                 mc_para_index = (u8)((memory_clock - 40000) / 5000);
 650                 }
 651         }
 652         return mc_para_index;
 653 }
 654
 655 static int cypress_populate_mvdd_value(struct radeon_device *rdev,
 656                                        u32 mclk,
 657                                        RV770_SMC_VOLTAGE_VALUE *voltage)
 658 {
 659         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 660         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 661
 662         if (!pi->mvdd_control) {
 663                 voltage->index = eg_pi->mvdd_high_index;
 664                 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
 665                 return 0;
 666         }
 667
 668         if (mclk <= pi->mvdd_split_frequency) {
 669                 voltage->index = eg_pi->mvdd_low_index;
 670                 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
 671         } else {
 672                 voltage->index = eg_pi->mvdd_high_index;
 673                 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
 674         }
 675
 676         return 0;
 677 }
 678
 679 int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
 680                                        struct rv7xx_pl *pl,
 681                                        RV770_SMC_HW_PERFORMANCE_LEVEL *level,
 682                                        u8 watermark_level)
 683 {
 684         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 685         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 686         int ret;
 687         bool dll_state_on;
 688
 689         level->gen2PCIE = pi->pcie_gen2 ?
 690                 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
 691         level->gen2XSP  = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
 692         level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
 693         level->displayWatermark = watermark_level;
 694
 695         ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
 696         if (ret)
 697                 return ret;
 698
 699         level->mcFlags =  0;
 700         if (pi->mclk_stutter_mode_threshold &&
 701             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
 702             !eg_pi->uvd_enabled) {
 703                 level->mcFlags |= SMC_MC_STUTTER_EN;
 704                 if (eg_pi->sclk_deep_sleep)
 705                         level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
 706                 else
 707                         level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
 708         }
 709
 710         if (pi->mem_gddr5) {
 711                 if (pl->mclk > pi->mclk_edc_enable_threshold)
 712                         level->mcFlags |= SMC_MC_EDC_RD_FLAG;
 713
 714                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
 715                         level->mcFlags |= SMC_MC_EDC_WR_FLAG;
 716
 717                 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
 718
 719                 if (level->strobeMode & SMC_STROBE_ENABLE) {
 720                         if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
 721                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
 722                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
 723                         else
 724                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
 725                 } else
 726                         dll_state_on = eg_pi->dll_default_on;
 727
 728                 ret = cypress_populate_mclk_value(rdev,
 729                                                   pl->sclk,
 730                                                   pl->mclk,
 731                                                   &level->mclk,
 732                                                   (level->strobeMode & SMC_STROBE_ENABLE) != 0,
 733                                                   dll_state_on);
 734         } else {
 735                 ret = cypress_populate_mclk_value(rdev,
 736                                                   pl->sclk,
 737                                                   pl->mclk,
 738                                                   &level->mclk,
 739                                                   true,
 740                                                   true);
 741         }
 742         if (ret)
 743                 return ret;
 744
 745         ret = cypress_populate_voltage_value(rdev,
 746                                              &eg_pi->vddc_voltage_table,
 747                                              pl->vddc,
 748                                              &level->vddc);
 749         if (ret)
 750                 return ret;
 751
 752         if (eg_pi->vddci_control) {
 753                 ret = cypress_populate_voltage_value(rdev,
 754                                                      &eg_pi->vddci_voltage_table,
 755                                                      pl->vddci,
 756                                                      &level->vddci);
 757                 if (ret)
 758                         return ret;
 759         }
 760
 761         ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
 762
 763         return ret;
 764 }
 765
 766 static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
 767                                               struct radeon_ps *radeon_state,
 768                                               RV770_SMC_SWSTATE *smc_state)
 769 {
 770         struct rv7xx_ps *state = rv770_get_ps(radeon_state);
 771         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 772         int ret;
 773
 774         if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
 775                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
 776
 777         ret = cypress_convert_power_level_to_smc(rdev,
 778                                                  &state->low,
 779                                                  &smc_state->levels[0],
 780                                                  PPSMC_DISPLAY_WATERMARK_LOW);
 781         if (ret)
 782                 return ret;
 783
 784         ret = cypress_convert_power_level_to_smc(rdev,
 785                                                  &state->medium,
 786                                                  &smc_state->levels[1],
 787                                                  PPSMC_DISPLAY_WATERMARK_LOW);
 788         if (ret)
 789                 return ret;
 790
 791         ret = cypress_convert_power_level_to_smc(rdev,
 792                                                  &state->high,
 793                                                  &smc_state->levels[2],
 794                                                  PPSMC_DISPLAY_WATERMARK_HIGH);
 795         if (ret)
 796                 return ret;
 797
 798         smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
 799         smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
 800         smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
 801
 802         if (eg_pi->dynamic_ac_timing) {
 803                 smc_state->levels[0].ACIndex = 2;
 804                 smc_state->levels[1].ACIndex = 3;
 805                 smc_state->levels[2].ACIndex = 4;
 806         } else {
 807                 smc_state->levels[0].ACIndex = 0;
 808                 smc_state->levels[1].ACIndex = 0;
 809                 smc_state->levels[2].ACIndex = 0;
 810         }
 811
 812         rv770_populate_smc_sp(rdev, radeon_state, smc_state);
 813
 814         return rv770_populate_smc_t(rdev, radeon_state, smc_state);
 815 }
 816
 817 static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry,
 818                                          SMC_Evergreen_MCRegisterSet *data,
 819                                          u32 num_entries, u32 valid_flag)
 820 {
 821         u32 i, j;
 822
 823         for (i = 0, j = 0; j < num_entries; j++) {
 824                 if (valid_flag & (1 << j)) {
 825                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
 826                         i++;
 827                 }
 828         }
 829 }
 830
 831 static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
 832                                                       struct rv7xx_pl *pl,
 833                                                       SMC_Evergreen_MCRegisterSet *mc_reg_table_data)
 834 {
 835         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 836         u32 i = 0;
 837
 838         for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
 839                 if (pl->mclk <=
 840                     eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
 841                         break;
 842         }
 843
 844         if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
 845                 --i;
 846
 847         cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
 848                                      mc_reg_table_data,
 849                                      eg_pi->mc_reg_table.last,
 850                                      eg_pi->mc_reg_table.valid_flag);
 851 }
 852
 853 static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
 854                                                 struct radeon_ps *radeon_state,
 855                                                 SMC_Evergreen_MCRegisters *mc_reg_table)
 856 {
 857         struct rv7xx_ps *state = rv770_get_ps(radeon_state);
 858
 859         cypress_convert_mc_reg_table_entry_to_smc(rdev,
 860                                                   &state->low,
 861                                                   &mc_reg_table->data[2]);
 862         cypress_convert_mc_reg_table_entry_to_smc(rdev,
 863                                                   &state->medium,
 864                                                   &mc_reg_table->data[3]);
 865         cypress_convert_mc_reg_table_entry_to_smc(rdev,
 866                                                   &state->high,
 867                                                   &mc_reg_table->data[4]);
 868 }
 869
 870 int cypress_upload_sw_state(struct radeon_device *rdev,
 871                             struct radeon_ps *radeon_new_state)
 872 {
 873         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 874         u16 address = pi->state_table_start +
 875                 offsetof(RV770_SMC_STATETABLE, driverState);
 876         RV770_SMC_SWSTATE state = { 0 };
 877         int ret;
 878
 879         ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
 880         if (ret)
 881                 return ret;
 882
 883         return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
 884                                     sizeof(RV770_SMC_SWSTATE),
 885                                     pi->sram_end);
 886 }
 887
 888 int cypress_upload_mc_reg_table(struct radeon_device *rdev,
 889                                 struct radeon_ps *radeon_new_state)
 890 {
 891         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 892         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 893         SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
 894         u16 address;
 895
 896         cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
 897
 898         address = eg_pi->mc_reg_table_start +
 899                 (u16)offsetof(SMC_Evergreen_MCRegisters, data[2]);
 900
 901         return rv770_copy_bytes_to_smc(rdev, address,
 902                                        (u8 *)&mc_reg_table.data[2],
 903                                        sizeof(SMC_Evergreen_MCRegisterSet) * 3,
 904                                        pi->sram_end);
 905 }
 906
 907 u32 cypress_calculate_burst_time(struct radeon_device *rdev,
 908                                  u32 engine_clock, u32 memory_clock)
 909 {
 910         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 911         u32 multiplier = pi->mem_gddr5 ? 1 : 2;
 912         u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
 913         u32 burst_time;
 914
 915         if (result <= 4)
 916                 burst_time = 0;
 917         else if (result < 8)
 918                 burst_time = result - 4;
 919         else {
 920                 burst_time = result / 2 ;
 921                 if (burst_time > 18)
 922                         burst_time = 18;
 923         }
 924
 925         return burst_time;
 926 }
 927
 928 void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
 929                                               struct radeon_ps *radeon_new_state)
 930 {
 931         struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
 932         u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
 933
 934         mc_arb_burst_time &= ~(STATE1_MASK | STATE2_MASK | STATE3_MASK);
 935
 936         mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev,
 937                                                                  new_state->low.sclk,
 938                                                                  new_state->low.mclk));
 939         mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev,
 940                                                                  new_state->medium.sclk,
 941                                                                  new_state->medium.mclk));
 942         mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev,
 943                                                                  new_state->high.sclk,
 944                                                                  new_state->high.mclk));
 945
 946         rv730_program_memory_timing_parameters(rdev, radeon_new_state);
 947
 948         WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
 949 }
 950
 951 static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
 952                                               SMC_Evergreen_MCRegisters *mc_reg_table)
 953 {
 954         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 955         u32 i, j;
 956
 957         for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
 958                 if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
 959                         mc_reg_table->address[i].s0 =
 960                                 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
 961                         mc_reg_table->address[i].s1 =
 962                                 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
 963                         i++;
 964                 }
 965         }
 966
 967         mc_reg_table->last = (u8)i;
 968 }
 969
 970 static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
 971 {
 972         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 973         u32 i = 0;
 974
 975         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
 976         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
 977         i++;
 978
 979         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
 980         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
 981         i++;
 982
 983         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
 984         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
 985         i++;
 986
 987         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
 988         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
 989         i++;
 990
 991         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
 992         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
 993         i++;
 994
 995         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
 996         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
 997         i++;
 998
 999         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
1000         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
1001         i++;
1002
1003         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
1004         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
1005         i++;
1006
1007         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1008         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
1009         i++;
1010
1011         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1012         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
1013         i++;
1014
1015         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1016         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
1017         i++;
1018
1019         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
1020         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
1021         i++;
1022
1023         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
1024         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
1025         i++;
1026
1027         eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
1028         eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
1029         i++;
1030
1031         eg_pi->mc_reg_table.last = (u8)i;
1032 }
1033
1034 static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
1035                                                      struct evergreen_mc_reg_entry *entry)
1036 {
1037         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1038         u32 i;
1039
1040         for (i = 0; i < eg_pi->mc_reg_table.last; i++)
1041                 entry->mc_data[i] =
1042                         RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1043
1044 }
1045
1046 static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
1047                                                       struct atom_memory_clock_range_table *range_table)
1048 {
1049         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1050         u32 i, j;
1051
1052         for (i = 0; i < range_table->num_entries; i++) {
1053                 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
1054                         range_table->mclk[i];
1055                 radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
1056                 cypress_retrieve_ac_timing_for_one_entry(rdev,
1057                                                          &eg_pi->mc_reg_table.mc_reg_table_entry[i]);
1058         }
1059
1060         eg_pi->mc_reg_table.num_entries = range_table->num_entries;
1061         eg_pi->mc_reg_table.valid_flag = 0;
1062
1063         for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1064                 for (j = 1; j < range_table->num_entries; j++) {
1065                         if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
1066                             eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
1067                                 eg_pi->mc_reg_table.valid_flag |= (1 << i);
1068                                 break;
1069                         }
1070                 }
1071         }
1072 }
1073
1074 static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
1075 {
1076         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1077         u8 module_index = rv770_get_memory_module_index(rdev);
1078         struct atom_memory_clock_range_table range_table = { 0 };
1079         int ret;
1080
1081         ret = radeon_atom_get_mclk_range_table(rdev,
1082                                                pi->mem_gddr5,
1083                                                module_index, &range_table);
1084         if (ret)
1085                 return ret;
1086
1087         cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
1088
1089         return 0;
1090 }
1091
1092 static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
1093 {
1094         u32 i, j;
1095         u32 channels = 2;
1096
1097         if ((rdev->family == CHIP_CYPRESS) ||
1098             (rdev->family == CHIP_HEMLOCK))
1099                 channels = 4;
1100         else if (rdev->family == CHIP_CEDAR)
1101                 channels = 1;
1102
1103         for (i = 0; i < channels; i++) {
1104                 if ((rdev->family == CHIP_CYPRESS) ||
1105                     (rdev->family == CHIP_HEMLOCK)) {
1106                         WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1107                         WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1108                 } else {
1109                         WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1110                         WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1111                 }
1112                 for (j = 0; j < rdev->usec_timeout; j++) {
1113                         if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
1114                                 break;
1115                         udelay(1);
1116                 }
1117         }
1118 }
1119
1120 static void cypress_force_mc_use_s1(struct radeon_device *rdev,
1121                                     struct radeon_ps *radeon_boot_state)
1122 {
1123         struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1124         u32 strobe_mode;
1125         u32 mc_seq_cg;
1126         int i;
1127
1128         if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1129                 return;
1130
1131         radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
1132         radeon_mc_wait_for_idle(rdev);
1133
1134         if ((rdev->family == CHIP_CYPRESS) ||
1135             (rdev->family == CHIP_HEMLOCK)) {
1136                 WREG32(MC_CONFIG_MCD, 0xf);
1137                 WREG32(MC_CG_CONFIG_MCD, 0xf);
1138         } else {
1139                 WREG32(MC_CONFIG, 0xf);
1140                 WREG32(MC_CG_CONFIG, 0xf);
1141         }
1142
1143         for (i = 0; i < rdev->num_crtc; i++)
1144                 radeon_wait_for_vblank(rdev, i);
1145
1146         WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1147         cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1148
1149         strobe_mode = cypress_get_strobe_mode_settings(rdev,
1150                                                        boot_state->low.mclk);
1151
1152         mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1);
1153         mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1154         WREG32(MC_SEQ_CG, mc_seq_cg);
1155
1156         for (i = 0; i < rdev->usec_timeout; i++) {
1157                 if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1158                         break;
1159                 udelay(1);
1160         }
1161
1162         mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1163         mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1164         WREG32(MC_SEQ_CG, mc_seq_cg);
1165
1166         cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1167 }
1168
1169 static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
1170 {
1171         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1172         u32 value;
1173         u32 i;
1174
1175         for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1176                 value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1177                 WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
1178         }
1179 }
1180
1181 static void cypress_force_mc_use_s0(struct radeon_device *rdev,
1182                                     struct radeon_ps *radeon_boot_state)
1183 {
1184         struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1185         u32 strobe_mode;
1186         u32 mc_seq_cg;
1187         int i;
1188
1189         cypress_copy_ac_timing_from_s1_to_s0(rdev);
1190         radeon_mc_wait_for_idle(rdev);
1191
1192         if ((rdev->family == CHIP_CYPRESS) ||
1193             (rdev->family == CHIP_HEMLOCK)) {
1194                 WREG32(MC_CONFIG_MCD, 0xf);
1195                 WREG32(MC_CG_CONFIG_MCD, 0xf);
1196         } else {
1197                 WREG32(MC_CONFIG, 0xf);
1198                 WREG32(MC_CG_CONFIG, 0xf);
1199         }
1200
1201         for (i = 0; i < rdev->num_crtc; i++)
1202                 radeon_wait_for_vblank(rdev, i);
1203
1204         WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1205         cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1206
1207         strobe_mode = cypress_get_strobe_mode_settings(rdev,
1208                                                        boot_state->low.mclk);
1209
1210         mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0);
1211         mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1212         WREG32(MC_SEQ_CG, mc_seq_cg);
1213
1214         for (i = 0; i < rdev->usec_timeout; i++) {
1215                 if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
1216                         break;
1217                 udelay(1);
1218         }
1219
1220         mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1221         mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1222         WREG32(MC_SEQ_CG, mc_seq_cg);
1223
1224         cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1225 }
1226
1227 static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
1228                                                RV770_SMC_VOLTAGE_VALUE *voltage)
1229 {
1230         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1231
1232         voltage->index = eg_pi->mvdd_high_index;
1233         voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1234
1235         return 0;
1236 }
1237
1238 int cypress_populate_smc_initial_state(struct radeon_device *rdev,
1239                                        struct radeon_ps *radeon_initial_state,
1240                                        RV770_SMC_STATETABLE *table)
1241 {
1242         struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state);
1243         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1244         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1245         u32 a_t;
1246
1247         table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1248                 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1249         table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1250                 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1251         table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1252                 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1253         table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1254                 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1255         table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1256                 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1257         table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1258                 cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1259
1260         table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1261                 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1262         table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1263                 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1264
1265         table->initialState.levels[0].mclk.mclk770.mclk_value =
1266                 cpu_to_be32(initial_state->low.mclk);
1267
1268         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1269                 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1270         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1271                 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1272         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1273                 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1274         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1275                 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1276         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1277                 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1278
1279         table->initialState.levels[0].sclk.sclk_value =
1280                 cpu_to_be32(initial_state->low.sclk);
1281
1282         table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1283
1284         table->initialState.levels[0].ACIndex = 0;
1285
1286         cypress_populate_voltage_value(rdev,
1287                                        &eg_pi->vddc_voltage_table,
1288                                        initial_state->low.vddc,
1289                                        &table->initialState.levels[0].vddc);
1290
1291         if (eg_pi->vddci_control)
1292                 cypress_populate_voltage_value(rdev,
1293                                                &eg_pi->vddci_voltage_table,
1294                                                initial_state->low.vddci,
1295                                                &table->initialState.levels[0].vddci);
1296
1297         cypress_populate_initial_mvdd_value(rdev,
1298                                             &table->initialState.levels[0].mvdd);
1299
1300         a_t = CG_R(0xffff) | CG_L(0);
1301         table->initialState.levels[0].aT = cpu_to_be32(a_t);
1302
1303         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1304
1305
1306         if (pi->boot_in_gen2)
1307                 table->initialState.levels[0].gen2PCIE = 1;
1308         else
1309                 table->initialState.levels[0].gen2PCIE = 0;
1310         if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1311                 table->initialState.levels[0].gen2XSP = 1;
1312         else
1313                 table->initialState.levels[0].gen2XSP = 0;
1314
1315         if (pi->mem_gddr5) {
1316                 table->initialState.levels[0].strobeMode =
1317                         cypress_get_strobe_mode_settings(rdev,
1318                                                          initial_state->low.mclk);
1319
1320                 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
1321                         table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1322                 else
1323                         table->initialState.levels[0].mcFlags =  0;
1324         }
1325
1326         table->initialState.levels[1] = table->initialState.levels[0];
1327         table->initialState.levels[2] = table->initialState.levels[0];
1328
1329         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1330
1331         return 0;
1332 }
1333
1334 int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
1335                                     RV770_SMC_STATETABLE *table)
1336 {
1337         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1338         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1339         u32 mpll_ad_func_cntl =
1340                 pi->clk_regs.rv770.mpll_ad_func_cntl;
1341         u32 mpll_ad_func_cntl_2 =
1342                 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
1343         u32 mpll_dq_func_cntl =
1344                 pi->clk_regs.rv770.mpll_dq_func_cntl;
1345         u32 mpll_dq_func_cntl_2 =
1346                 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
1347         u32 spll_func_cntl =
1348                 pi->clk_regs.rv770.cg_spll_func_cntl;
1349         u32 spll_func_cntl_2 =
1350                 pi->clk_regs.rv770.cg_spll_func_cntl_2;
1351         u32 spll_func_cntl_3 =
1352                 pi->clk_regs.rv770.cg_spll_func_cntl_3;
1353         u32 mclk_pwrmgt_cntl =
1354                 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
1355         u32 dll_cntl =
1356                 pi->clk_regs.rv770.dll_cntl;
1357
1358         table->ACPIState = table->initialState;
1359
1360         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1361
1362         if (pi->acpi_vddc) {
1363                 cypress_populate_voltage_value(rdev,
1364                                                &eg_pi->vddc_voltage_table,
1365                                                pi->acpi_vddc,
1366                                                &table->ACPIState.levels[0].vddc);
1367                 if (pi->pcie_gen2) {
1368                         if (pi->acpi_pcie_gen2)
1369                                 table->ACPIState.levels[0].gen2PCIE = 1;
1370                         else
1371                                 table->ACPIState.levels[0].gen2PCIE = 0;
1372                 } else
1373                         table->ACPIState.levels[0].gen2PCIE = 0;
1374                 if (pi->acpi_pcie_gen2)
1375                         table->ACPIState.levels[0].gen2XSP = 1;
1376                 else
1377                         table->ACPIState.levels[0].gen2XSP = 0;
1378         } else {
1379                 cypress_populate_voltage_value(rdev,
1380                                                &eg_pi->vddc_voltage_table,
1381                                                pi->min_vddc_in_table,
1382                                                &table->ACPIState.levels[0].vddc);
1383                 table->ACPIState.levels[0].gen2PCIE = 0;
1384         }
1385
1386         if (eg_pi->acpi_vddci) {
1387                 if (eg_pi->vddci_control) {
1388                         cypress_populate_voltage_value(rdev,
1389                                                        &eg_pi->vddci_voltage_table,
1390                                                        eg_pi->acpi_vddci,
1391                                                        &table->ACPIState.levels[0].vddci);
1392                 }
1393         }
1394
1395         mpll_ad_func_cntl &= ~PDNB;
1396
1397         mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1398
1399         if (pi->mem_gddr5)
1400                 mpll_dq_func_cntl &= ~PDNB;
1401         mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1402
1403         mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1404                              MRDCKA1_RESET |
1405                              MRDCKB0_RESET |
1406                              MRDCKB1_RESET |
1407                              MRDCKC0_RESET |
1408                              MRDCKC1_RESET |
1409                              MRDCKD0_RESET |
1410                              MRDCKD1_RESET);
1411
1412         mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1413                               MRDCKA1_PDNB |
1414                               MRDCKB0_PDNB |
1415                               MRDCKB1_PDNB |
1416                               MRDCKC0_PDNB |
1417                               MRDCKC1_PDNB |
1418                               MRDCKD0_PDNB |
1419                               MRDCKD1_PDNB);
1420
1421         dll_cntl |= (MRDCKA0_BYPASS |
1422                      MRDCKA1_BYPASS |
1423                      MRDCKB0_BYPASS |
1424                      MRDCKB1_BYPASS |
1425                      MRDCKC0_BYPASS |
1426                      MRDCKC1_BYPASS |
1427                      MRDCKD0_BYPASS |
1428                      MRDCKD1_BYPASS);
1429
1430         /* evergreen only */
1431         if (rdev->family <= CHIP_HEMLOCK)
1432                 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
1433
1434         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1435         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1436
1437         table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1438                 cpu_to_be32(mpll_ad_func_cntl);
1439         table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1440                 cpu_to_be32(mpll_ad_func_cntl_2);
1441         table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1442                 cpu_to_be32(mpll_dq_func_cntl);
1443         table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1444                 cpu_to_be32(mpll_dq_func_cntl_2);
1445         table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1446                 cpu_to_be32(mclk_pwrmgt_cntl);
1447         table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1448
1449         table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
1450
1451         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1452                 cpu_to_be32(spll_func_cntl);
1453         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1454                 cpu_to_be32(spll_func_cntl_2);
1455         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1456                 cpu_to_be32(spll_func_cntl_3);
1457
1458         table->ACPIState.levels[0].sclk.sclk_value = 0;
1459
1460         cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1461
1462         if (eg_pi->dynamic_ac_timing)
1463                 table->ACPIState.levels[0].ACIndex = 1;
1464
1465         table->ACPIState.levels[1] = table->ACPIState.levels[0];
1466         table->ACPIState.levels[2] = table->ACPIState.levels[0];
1467
1468         return 0;
1469 }
1470
1471 static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
1472                                                           struct atom_voltage_table *voltage_table)
1473 {
1474         unsigned int i, diff;
1475
1476         if (voltage_table->count <= MAX_NO_VREG_STEPS)
1477                 return;
1478
1479         diff = voltage_table->count - MAX_NO_VREG_STEPS;
1480
1481         for (i= 0; i < MAX_NO_VREG_STEPS; i++)
1482                 voltage_table->entries[i] = voltage_table->entries[i + diff];
1483
1484         voltage_table->count = MAX_NO_VREG_STEPS;
1485 }
1486
1487 int cypress_construct_voltage_tables(struct radeon_device *rdev)
1488 {
1489         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1490         int ret;
1491
1492         ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0,
1493                                             &eg_pi->vddc_voltage_table);
1494         if (ret)
1495                 return ret;
1496
1497         if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
1498                 cypress_trim_voltage_table_to_fit_state_table(rdev,
1499                                                               &eg_pi->vddc_voltage_table);
1500
1501         if (eg_pi->vddci_control) {
1502                 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0,
1503                                                     &eg_pi->vddci_voltage_table);
1504                 if (ret)
1505                         return ret;
1506
1507                 if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
1508                         cypress_trim_voltage_table_to_fit_state_table(rdev,
1509                                                                       &eg_pi->vddci_voltage_table);
1510         }
1511
1512         return 0;
1513 }
1514
1515 static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
1516                                                struct atom_voltage_table *voltage_table,
1517                                                RV770_SMC_STATETABLE *table)
1518 {
1519         unsigned int i;
1520
1521         for (i = 0; i < voltage_table->count; i++) {
1522                 table->highSMIO[i] = 0;
1523                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1524         }
1525 }
1526
1527 int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
1528                                         RV770_SMC_STATETABLE *table)
1529 {
1530         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1531         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1532         unsigned char i;
1533
1534         if (eg_pi->vddc_voltage_table.count) {
1535                 cypress_populate_smc_voltage_table(rdev,
1536                                                    &eg_pi->vddc_voltage_table,
1537                                                    table);
1538
1539                 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
1540                 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
1541                         cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1542
1543                 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1544                         if (pi->max_vddc_in_table <=
1545                             eg_pi->vddc_voltage_table.entries[i].value) {
1546                                 table->maxVDDCIndexInPPTable = i;
1547                                 break;
1548                         }
1549                 }
1550         }
1551
1552         if (eg_pi->vddci_voltage_table.count) {
1553                 cypress_populate_smc_voltage_table(rdev,
1554                                                    &eg_pi->vddci_voltage_table,
1555                                                    table);
1556
1557                 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
1558                 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
1559                         cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
1560         }
1561
1562         return 0;
1563 }
1564
1565 static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)
1566 {
1567         if ((memory_info->mem_type == MEM_TYPE_GDDR3) ||
1568             (memory_info->mem_type == MEM_TYPE_DDR3))
1569                 return 30000;
1570
1571         return 0;
1572 }
1573
1574 int cypress_get_mvdd_configuration(struct radeon_device *rdev)
1575 {
1576         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1577         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1578         u8 module_index;
1579         struct atom_memory_info memory_info;
1580         u32 tmp = RREG32(GENERAL_PWRMGT);
1581
1582         if (!(tmp & BACKBIAS_PAD_EN)) {
1583                 eg_pi->mvdd_high_index = 0;
1584                 eg_pi->mvdd_low_index = 1;
1585                 pi->mvdd_control = false;
1586                 return 0;
1587         }
1588
1589         if (tmp & BACKBIAS_VALUE)
1590                 eg_pi->mvdd_high_index = 1;
1591         else
1592                 eg_pi->mvdd_high_index = 0;
1593
1594         eg_pi->mvdd_low_index =
1595                 (eg_pi->mvdd_high_index == 0) ? 1 : 0;
1596
1597         module_index = rv770_get_memory_module_index(rdev);
1598
1599         if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
1600                 pi->mvdd_control = false;
1601                 return 0;
1602         }
1603
1604         pi->mvdd_split_frequency =
1605                 cypress_get_mclk_split_point(&memory_info);
1606
1607         if (pi->mvdd_split_frequency == 0) {
1608                 pi->mvdd_control = false;
1609                 return 0;
1610         }
1611
1612         return 0;
1613 }
1614
1615 static int cypress_init_smc_table(struct radeon_device *rdev,
1616                                   struct radeon_ps *radeon_boot_state)
1617 {
1618         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1619         RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1620         int ret;
1621
1622         memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1623
1624         cypress_populate_smc_voltage_tables(rdev, table);
1625
1626         switch (rdev->pm.int_thermal_type) {
1627         case THERMAL_TYPE_EVERGREEN:
1628         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1629                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1630                 break;
1631         case THERMAL_TYPE_NONE:
1632                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1633                 break;
1634         default:
1635                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1636                 break;
1637         }
1638
1639         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1640                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1641
1642         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1643                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1644
1645         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1646                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1647
1648         if (pi->mem_gddr5)
1649                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1650
1651         ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1652         if (ret)
1653                 return ret;
1654
1655         ret = cypress_populate_smc_acpi_state(rdev, table);
1656         if (ret)
1657                 return ret;
1658
1659         table->driverState = table->initialState;
1660
1661         return rv770_copy_bytes_to_smc(rdev,
1662                                        pi->state_table_start,
1663                                        (u8 *)table, sizeof(RV770_SMC_STATETABLE),
1664                                        pi->sram_end);
1665 }
1666
1667 int cypress_populate_mc_reg_table(struct radeon_device *rdev,
1668                                   struct radeon_ps *radeon_boot_state)
1669 {
1670         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1671         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1672         struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1673         SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
1674
1675         rv770_write_smc_soft_register(rdev,
1676                                       RV770_SMC_SOFT_REGISTER_seq_index, 1);
1677
1678         cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
1679
1680         cypress_convert_mc_reg_table_entry_to_smc(rdev,
1681                                                   &boot_state->low,
1682                                                   &mc_reg_table.data[0]);
1683
1684         cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
1685                                      &mc_reg_table.data[1], eg_pi->mc_reg_table.last,
1686                                      eg_pi->mc_reg_table.valid_flag);
1687
1688         cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
1689
1690         return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
1691                                        (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),
1692                                        pi->sram_end);
1693 }
1694
1695 int cypress_get_table_locations(struct radeon_device *rdev)
1696 {
1697         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1698         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1699         u32 tmp;
1700         int ret;
1701
1702         ret = rv770_read_smc_sram_dword(rdev,
1703                                         EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1704                                         EVERGREEN_SMC_FIRMWARE_HEADER_stateTable,
1705                                         &tmp, pi->sram_end);
1706         if (ret)
1707                 return ret;
1708
1709         pi->state_table_start = (u16)tmp;
1710
1711         ret = rv770_read_smc_sram_dword(rdev,
1712                                         EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1713                                         EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters,
1714                                         &tmp, pi->sram_end);
1715         if (ret)
1716                 return ret;
1717
1718         pi->soft_regs_start = (u16)tmp;
1719
1720         ret = rv770_read_smc_sram_dword(rdev,
1721                                         EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1722                                         EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable,
1723                                         &tmp, pi->sram_end);
1724         if (ret)
1725                 return ret;
1726
1727         eg_pi->mc_reg_table_start = (u16)tmp;
1728
1729         return 0;
1730 }
1731
1732 void cypress_enable_display_gap(struct radeon_device *rdev)
1733 {
1734         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1735
1736         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1737         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1738                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
1739
1740         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1741         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
1742                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
1743         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1744 }
1745
1746 static void cypress_program_display_gap(struct radeon_device *rdev)
1747 {
1748         u32 tmp, pipe;
1749         int i;
1750
1751         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1752         if (rdev->pm.dpm.new_active_crtc_count > 0)
1753                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1754         else
1755                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1756
1757         if (rdev->pm.dpm.new_active_crtc_count > 1)
1758                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1759         else
1760                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1761
1762         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1763
1764         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
1765         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
1766
1767         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1768             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1769                 /* find the first active crtc */
1770                 for (i = 0; i < rdev->num_crtc; i++) {
1771                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1772                                 break;
1773                 }
1774                 if (i == rdev->num_crtc)
1775                         pipe = 0;
1776                 else
1777                         pipe = i;
1778
1779                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
1780                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
1781                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
1782         }
1783
1784         cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1785 }
1786
1787 void cypress_dpm_setup_asic(struct radeon_device *rdev)
1788 {
1789         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1790
1791         rv740_read_clock_registers(rdev);
1792         rv770_read_voltage_smio_registers(rdev);
1793         rv770_get_max_vddc(rdev);
1794         rv770_get_memory_type(rdev);
1795
1796         if (eg_pi->pcie_performance_request)
1797                 eg_pi->pcie_performance_request_registered = false;
1798
1799         if (eg_pi->pcie_performance_request)
1800                 cypress_advertise_gen2_capability(rdev);
1801
1802         rv770_get_pcie_gen2_status(rdev);
1803
1804         rv770_enable_acpi_pm(rdev);
1805 }
1806
1807 int cypress_dpm_enable(struct radeon_device *rdev)
1808 {
1809         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1810         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1811         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1812         int ret;
1813
1814         if (pi->gfx_clock_gating)
1815                 rv770_restore_cgcg(rdev);
1816
1817         if (rv770_dpm_enabled(rdev))
1818                 return -EINVAL;
1819
1820         if (pi->voltage_control) {
1821                 rv770_enable_voltage_control(rdev, true);
1822                 ret = cypress_construct_voltage_tables(rdev);
1823                 if (ret) {
1824                         DRM_ERROR("cypress_construct_voltage_tables failed\n");
1825                         return ret;
1826                 }
1827         }
1828
1829         if (pi->mvdd_control) {
1830                 ret = cypress_get_mvdd_configuration(rdev);
1831                 if (ret) {
1832                         DRM_ERROR("cypress_get_mvdd_configuration failed\n");
1833                         return ret;
1834                 }
1835         }
1836
1837         if (eg_pi->dynamic_ac_timing) {
1838                 cypress_set_mc_reg_address_table(rdev);
1839                 cypress_force_mc_use_s0(rdev, boot_ps);
1840                 ret = cypress_initialize_mc_reg_table(rdev);
1841                 if (ret)
1842                         eg_pi->dynamic_ac_timing = false;
1843                 cypress_force_mc_use_s1(rdev, boot_ps);
1844         }
1845
1846         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1847                 rv770_enable_backbias(rdev, true);
1848
1849         if (pi->dynamic_ss)
1850                 cypress_enable_spread_spectrum(rdev, true);
1851
1852         if (pi->thermal_protection)
1853                 rv770_enable_thermal_protection(rdev, true);
1854
1855         rv770_setup_bsp(rdev);
1856         rv770_program_git(rdev);
1857         rv770_program_tp(rdev);
1858         rv770_program_tpp(rdev);
1859         rv770_program_sstp(rdev);
1860         rv770_program_engine_speed_parameters(rdev);
1861         cypress_enable_display_gap(rdev);
1862         rv770_program_vc(rdev);
1863
1864         if (pi->dynamic_pcie_gen2)
1865                 cypress_enable_dynamic_pcie_gen2(rdev, true);
1866
1867         ret = rv770_upload_firmware(rdev);
1868         if (ret) {
1869                 DRM_ERROR("rv770_upload_firmware failed\n");
1870                 return ret;
1871         }
1872
1873         ret = cypress_get_table_locations(rdev);
1874         if (ret) {
1875                 DRM_ERROR("cypress_get_table_locations failed\n");
1876                 return ret;
1877         }
1878         ret = cypress_init_smc_table(rdev, boot_ps);
1879         if (ret) {
1880                 DRM_ERROR("cypress_init_smc_table failed\n");
1881                 return ret;
1882         }
1883         if (eg_pi->dynamic_ac_timing) {
1884                 ret = cypress_populate_mc_reg_table(rdev, boot_ps);
1885                 if (ret) {
1886                         DRM_ERROR("cypress_populate_mc_reg_table failed\n");
1887                         return ret;
1888                 }
1889         }
1890
1891         cypress_program_response_times(rdev);
1892
1893         r7xx_start_smc(rdev);
1894
1895         ret = cypress_notify_smc_display_change(rdev, false);
1896         if (ret) {
1897                 DRM_ERROR("cypress_notify_smc_display_change failed\n");
1898                 return ret;
1899         }
1900         cypress_enable_sclk_control(rdev, true);
1901
1902         if (eg_pi->memory_transition)
1903                 cypress_enable_mclk_control(rdev, true);
1904
1905         cypress_start_dpm(rdev);
1906
1907         if (pi->gfx_clock_gating)
1908                 cypress_gfx_clock_gating_enable(rdev, true);
1909
1910         if (pi->mg_clock_gating)
1911                 cypress_mg_clock_gating_enable(rdev, true);
1912
1913         rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1914
1915         return 0;
1916 }
1917
1918 void cypress_dpm_disable(struct radeon_device *rdev)
1919 {
1920         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1921         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1922         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1923
1924         if (!rv770_dpm_enabled(rdev))
1925                 return;
1926
1927         rv770_clear_vc(rdev);
1928
1929         if (pi->thermal_protection)
1930                 rv770_enable_thermal_protection(rdev, false);
1931
1932         if (pi->dynamic_pcie_gen2)
1933                 cypress_enable_dynamic_pcie_gen2(rdev, false);
1934
1935         if (rdev->irq.installed &&
1936             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1937                 rdev->irq.dpm_thermal = false;
1938                 radeon_irq_set(rdev);
1939         }
1940
1941         if (pi->gfx_clock_gating)
1942                 cypress_gfx_clock_gating_enable(rdev, false);
1943
1944         if (pi->mg_clock_gating)
1945                 cypress_mg_clock_gating_enable(rdev, false);
1946
1947         rv770_stop_dpm(rdev);
1948         r7xx_stop_smc(rdev);
1949
1950         cypress_enable_spread_spectrum(rdev, false);
1951
1952         if (eg_pi->dynamic_ac_timing)
1953                 cypress_force_mc_use_s1(rdev, boot_ps);
1954
1955         rv770_reset_smio_status(rdev);
1956 }
1957
1958 int cypress_dpm_set_power_state(struct radeon_device *rdev)
1959 {
1960         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1961         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1962         struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1963         int ret;
1964
1965         ret = rv770_restrict_performance_levels_before_switch(rdev);
1966         if (ret) {
1967                 DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n");
1968                 return ret;
1969         }
1970         if (eg_pi->pcie_performance_request)
1971                 cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
1972
1973         rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1974         ret = rv770_halt_smc(rdev);
1975         if (ret) {
1976                 DRM_ERROR("rv770_halt_smc failed\n");
1977                 return ret;
1978         }
1979         ret = cypress_upload_sw_state(rdev, new_ps);
1980         if (ret) {
1981                 DRM_ERROR("cypress_upload_sw_state failed\n");
1982                 return ret;
1983         }
1984         if (eg_pi->dynamic_ac_timing) {
1985                 ret = cypress_upload_mc_reg_table(rdev, new_ps);
1986                 if (ret) {
1987                         DRM_ERROR("cypress_upload_mc_reg_table failed\n");
1988                         return ret;
1989                 }
1990         }
1991
1992         cypress_program_memory_timing_parameters(rdev, new_ps);
1993
1994         ret = rv770_resume_smc(rdev);
1995         if (ret) {
1996                 DRM_ERROR("rv770_resume_smc failed\n");
1997                 return ret;
1998         }
1999         ret = rv770_set_sw_state(rdev);
2000         if (ret) {
2001                 DRM_ERROR("rv770_set_sw_state failed\n");
2002                 return ret;
2003         }
2004         rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2005
2006         if (eg_pi->pcie_performance_request)
2007                 cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2008
2009         return 0;
2010 }
2011
2012 #if 0
2013 void cypress_dpm_reset_asic(struct radeon_device *rdev)
2014 {
2015         rv770_restrict_performance_levels_before_switch(rdev);
2016         rv770_set_boot_state(rdev);
2017 }
2018 #endif
2019
2020 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev)
2021 {
2022         cypress_program_display_gap(rdev);
2023 }
2024
2025 int cypress_dpm_init(struct radeon_device *rdev)
2026 {
2027         struct rv7xx_power_info *pi;
2028         struct evergreen_power_info *eg_pi;
2029         struct atom_clock_dividers dividers;
2030         int ret;
2031
2032         eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
2033         if (eg_pi == NULL)
2034                 return -ENOMEM;
2035         rdev->pm.dpm.priv = eg_pi;
2036         pi = &eg_pi->rv7xx;
2037
2038         rv770_get_max_vddc(rdev);
2039
2040         eg_pi->ulv.supported = false;
2041         pi->acpi_vddc = 0;
2042         eg_pi->acpi_vddci = 0;
2043         pi->min_vddc_in_table = 0;
2044         pi->max_vddc_in_table = 0;
2045
2046         ret = r600_get_platform_caps(rdev);
2047         if (ret)
2048                 return ret;
2049
2050         ret = rv7xx_parse_power_table(rdev);
2051         if (ret)
2052                 return ret;
2053
2054         if (rdev->pm.dpm.voltage_response_time == 0)
2055                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2056         if (rdev->pm.dpm.backbias_response_time == 0)
2057                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2058
2059         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2060                                              0, false, &dividers);
2061         if (ret)
2062                 pi->ref_div = dividers.ref_div + 1;
2063         else
2064                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2065
2066         pi->mclk_strobe_mode_threshold = 40000;
2067         pi->mclk_edc_enable_threshold = 40000;
2068         eg_pi->mclk_edc_wr_enable_threshold = 40000;
2069
2070         pi->rlp = RV770_RLP_DFLT;
2071         pi->rmp = RV770_RMP_DFLT;
2072         pi->lhp = RV770_LHP_DFLT;
2073         pi->lmp = RV770_LMP_DFLT;
2074
2075         pi->voltage_control =
2076                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2077
2078         pi->mvdd_control =
2079                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2080
2081         eg_pi->vddci_control =
2082                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2083
2084         rv770_get_engine_memory_ss(rdev);
2085
2086         pi->asi = RV770_ASI_DFLT;
2087         pi->pasi = CYPRESS_HASI_DFLT;
2088         pi->vrc = CYPRESS_VRC_DFLT;
2089
2090         pi->power_gating = false;
2091
2092         if ((rdev->family == CHIP_CYPRESS) ||
2093             (rdev->family == CHIP_HEMLOCK))
2094                 pi->gfx_clock_gating = false;
2095         else
2096                 pi->gfx_clock_gating = true;
2097
2098         pi->mg_clock_gating = true;
2099         pi->mgcgtssm = true;
2100         eg_pi->ls_clock_gating = false;
2101         eg_pi->sclk_deep_sleep = false;
2102
2103         pi->dynamic_pcie_gen2 = true;
2104
2105         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2106                 pi->thermal_protection = true;
2107         else
2108                 pi->thermal_protection = false;
2109
2110         pi->display_gap = true;
2111
2112         if (rdev->flags & RADEON_IS_MOBILITY)
2113                 pi->dcodt = true;
2114         else
2115                 pi->dcodt = false;
2116
2117         pi->ulps = true;
2118
2119         eg_pi->dynamic_ac_timing = true;
2120         eg_pi->abm = true;
2121         eg_pi->mcls = true;
2122         eg_pi->light_sleep = true;
2123         eg_pi->memory_transition = true;
2124 #if defined(CONFIG_ACPI)
2125         eg_pi->pcie_performance_request =
2126                 radeon_acpi_is_pcie_performance_request_supported(rdev);
2127 #else
2128         eg_pi->pcie_performance_request = false;
2129 #endif
2130
2131         if ((rdev->family == CHIP_CYPRESS) ||
2132             (rdev->family == CHIP_HEMLOCK) ||
2133             (rdev->family == CHIP_JUNIPER))
2134                 eg_pi->dll_default_on = true;
2135         else
2136                 eg_pi->dll_default_on = false;
2137
2138         eg_pi->sclk_deep_sleep = false;
2139         pi->mclk_stutter_mode_threshold = 0;
2140
2141         pi->sram_end = SMC_RAM_END;
2142
2143         return 0;
2144 }
2145
2146 void cypress_dpm_fini(struct radeon_device *rdev)
2147 {
2148         int i;
2149
2150         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2151                 kfree(rdev->pm.dpm.ps[i].ps_priv);
2152         }
2153         kfree(rdev->pm.dpm.ps);
2154         kfree(rdev->pm.dpm.priv);
2155 }
2156
2157 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev)
2158 {
2159         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2160         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2161         /* we never hit the non-gddr5 limit so disable it */
2162         u32 switch_limit = pi->mem_gddr5 ? 450 : 0;
2163
2164         if (vblank_time < switch_limit)
2165                 return true;
2166         else
2167                 return false;
2168
2169 }