2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
33 #include <linux/seq_file.h>
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
40 #define SMC_RAM_END 0x40000
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
46 static const struct ci_pt_defaults defaults_hawaii_xt =
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
53 static const struct ci_pt_defaults defaults_hawaii_pro =
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
60 static const struct ci_pt_defaults defaults_bonaire_xt =
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
67 static const struct ci_pt_defaults defaults_bonaire_pro =
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
74 static const struct ci_pt_defaults defaults_saturn_xt =
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
81 static const struct ci_pt_defaults defaults_saturn_pro =
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
88 static const struct ci_pt_config_reg didt_config_ci[] =
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
187 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
188 PPSMC_Msg msg, u32 parameter);
190 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
191 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
193 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
195 struct ci_power_info *pi = rdev->pm.dpm.priv;
200 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
202 struct ci_ps *ps = rps->ps_priv;
207 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
209 struct ci_power_info *pi = ci_get_pi(rdev);
211 switch (rdev->pdev->device) {
219 pi->powertune_defaults = &defaults_bonaire_xt;
225 pi->powertune_defaults = &defaults_saturn_xt;
229 pi->powertune_defaults = &defaults_hawaii_xt;
233 pi->powertune_defaults = &defaults_hawaii_pro;
243 pi->powertune_defaults = &defaults_bonaire_xt;
247 pi->dte_tj_offset = 0;
249 pi->caps_power_containment = true;
250 pi->caps_cac = false;
251 pi->caps_sq_ramping = false;
252 pi->caps_db_ramping = false;
253 pi->caps_td_ramping = false;
254 pi->caps_tcp_ramping = false;
256 if (pi->caps_power_containment) {
258 if (rdev->family == CHIP_HAWAII)
259 pi->enable_bapm_feature = false;
261 pi->enable_bapm_feature = true;
262 pi->enable_tdc_limit_feature = true;
263 pi->enable_pkg_pwr_tracking_feature = true;
267 static u8 ci_convert_to_vid(u16 vddc)
269 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
272 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
274 struct ci_power_info *pi = ci_get_pi(rdev);
275 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
276 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
277 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
280 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
282 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
284 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
285 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
288 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
289 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
290 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
291 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
292 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
294 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
295 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
301 static int ci_populate_vddc_vid(struct radeon_device *rdev)
303 struct ci_power_info *pi = ci_get_pi(rdev);
304 u8 *vid = pi->smc_powertune_table.VddCVid;
307 if (pi->vddc_voltage_table.count > 8)
310 for (i = 0; i < pi->vddc_voltage_table.count; i++)
311 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
316 static int ci_populate_svi_load_line(struct radeon_device *rdev)
318 struct ci_power_info *pi = ci_get_pi(rdev);
319 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
321 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
322 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
323 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
324 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
329 static int ci_populate_tdc_limit(struct radeon_device *rdev)
331 struct ci_power_info *pi = ci_get_pi(rdev);
332 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
335 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
336 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
337 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
338 pt_defaults->tdc_vddc_throttle_release_limit_perc;
339 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
344 static int ci_populate_dw8(struct radeon_device *rdev)
346 struct ci_power_info *pi = ci_get_pi(rdev);
347 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
350 ret = ci_read_smc_sram_dword(rdev,
351 SMU7_FIRMWARE_HEADER_LOCATION +
352 offsetof(SMU7_Firmware_Header, PmFuseTable) +
353 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
354 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
359 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
364 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
366 struct ci_power_info *pi = ci_get_pi(rdev);
368 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
369 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
370 rdev->pm.dpm.fan.fan_output_sensitivity =
371 rdev->pm.dpm.fan.default_fan_output_sensitivity;
373 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
374 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
379 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
381 struct ci_power_info *pi = ci_get_pi(rdev);
382 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
383 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
386 min = max = hi_vid[0];
387 for (i = 0; i < 8; i++) {
388 if (0 != hi_vid[i]) {
395 if (0 != lo_vid[i]) {
403 if ((min == 0) || (max == 0))
405 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
406 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
411 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
413 struct ci_power_info *pi = ci_get_pi(rdev);
414 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
415 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
416 struct radeon_cac_tdp_table *cac_tdp_table =
417 rdev->pm.dpm.dyn_state.cac_tdp_table;
419 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
420 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
422 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
423 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
428 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
430 struct ci_power_info *pi = ci_get_pi(rdev);
431 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
433 struct radeon_cac_tdp_table *cac_tdp_table =
434 rdev->pm.dpm.dyn_state.cac_tdp_table;
435 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
440 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
441 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
444 dpm_table->GpuTjMax =
445 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
446 dpm_table->GpuTjHyst = 8;
448 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
451 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
452 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
454 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
455 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
458 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
459 def1 = pt_defaults->bapmti_r;
460 def2 = pt_defaults->bapmti_rc;
462 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
463 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
464 for (k = 0; k < SMU7_DTE_SINKS; k++) {
465 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
466 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
476 static int ci_populate_pm_base(struct radeon_device *rdev)
478 struct ci_power_info *pi = ci_get_pi(rdev);
479 u32 pm_fuse_table_offset;
482 if (pi->caps_power_containment) {
483 ret = ci_read_smc_sram_dword(rdev,
484 SMU7_FIRMWARE_HEADER_LOCATION +
485 offsetof(SMU7_Firmware_Header, PmFuseTable),
486 &pm_fuse_table_offset, pi->sram_end);
489 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
492 ret = ci_populate_vddc_vid(rdev);
495 ret = ci_populate_svi_load_line(rdev);
498 ret = ci_populate_tdc_limit(rdev);
501 ret = ci_populate_dw8(rdev);
504 ret = ci_populate_fuzzy_fan(rdev);
507 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
510 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
513 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
514 (u8 *)&pi->smc_powertune_table,
515 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
523 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
525 struct ci_power_info *pi = ci_get_pi(rdev);
528 if (pi->caps_sq_ramping) {
529 data = RREG32_DIDT(DIDT_SQ_CTRL0);
531 data |= DIDT_CTRL_EN;
533 data &= ~DIDT_CTRL_EN;
534 WREG32_DIDT(DIDT_SQ_CTRL0, data);
537 if (pi->caps_db_ramping) {
538 data = RREG32_DIDT(DIDT_DB_CTRL0);
540 data |= DIDT_CTRL_EN;
542 data &= ~DIDT_CTRL_EN;
543 WREG32_DIDT(DIDT_DB_CTRL0, data);
546 if (pi->caps_td_ramping) {
547 data = RREG32_DIDT(DIDT_TD_CTRL0);
549 data |= DIDT_CTRL_EN;
551 data &= ~DIDT_CTRL_EN;
552 WREG32_DIDT(DIDT_TD_CTRL0, data);
555 if (pi->caps_tcp_ramping) {
556 data = RREG32_DIDT(DIDT_TCP_CTRL0);
558 data |= DIDT_CTRL_EN;
560 data &= ~DIDT_CTRL_EN;
561 WREG32_DIDT(DIDT_TCP_CTRL0, data);
565 static int ci_program_pt_config_registers(struct radeon_device *rdev,
566 const struct ci_pt_config_reg *cac_config_regs)
568 const struct ci_pt_config_reg *config_regs = cac_config_regs;
572 if (config_regs == NULL)
575 while (config_regs->offset != 0xFFFFFFFF) {
576 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
577 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
579 switch (config_regs->type) {
580 case CISLANDS_CONFIGREG_SMC_IND:
581 data = RREG32_SMC(config_regs->offset);
583 case CISLANDS_CONFIGREG_DIDT_IND:
584 data = RREG32_DIDT(config_regs->offset);
587 data = RREG32(config_regs->offset << 2);
591 data &= ~config_regs->mask;
592 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
595 switch (config_regs->type) {
596 case CISLANDS_CONFIGREG_SMC_IND:
597 WREG32_SMC(config_regs->offset, data);
599 case CISLANDS_CONFIGREG_DIDT_IND:
600 WREG32_DIDT(config_regs->offset, data);
603 WREG32(config_regs->offset << 2, data);
613 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
615 struct ci_power_info *pi = ci_get_pi(rdev);
618 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
619 pi->caps_td_ramping || pi->caps_tcp_ramping) {
620 cik_enter_rlc_safe_mode(rdev);
623 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
625 cik_exit_rlc_safe_mode(rdev);
630 ci_do_enable_didt(rdev, enable);
632 cik_exit_rlc_safe_mode(rdev);
638 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
640 struct ci_power_info *pi = ci_get_pi(rdev);
641 PPSMC_Result smc_result;
645 pi->power_containment_features = 0;
646 if (pi->caps_power_containment) {
647 if (pi->enable_bapm_feature) {
648 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
649 if (smc_result != PPSMC_Result_OK)
652 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
655 if (pi->enable_tdc_limit_feature) {
656 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
657 if (smc_result != PPSMC_Result_OK)
660 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
663 if (pi->enable_pkg_pwr_tracking_feature) {
664 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
665 if (smc_result != PPSMC_Result_OK) {
668 struct radeon_cac_tdp_table *cac_tdp_table =
669 rdev->pm.dpm.dyn_state.cac_tdp_table;
670 u32 default_pwr_limit =
671 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
673 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
675 ci_set_power_limit(rdev, default_pwr_limit);
680 if (pi->caps_power_containment && pi->power_containment_features) {
681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
682 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
687 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
688 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
689 pi->power_containment_features = 0;
696 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
698 struct ci_power_info *pi = ci_get_pi(rdev);
699 PPSMC_Result smc_result;
704 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
705 if (smc_result != PPSMC_Result_OK) {
707 pi->cac_enabled = false;
709 pi->cac_enabled = true;
711 } else if (pi->cac_enabled) {
712 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
713 pi->cac_enabled = false;
720 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
723 struct ci_power_info *pi = ci_get_pi(rdev);
724 PPSMC_Result smc_result = PPSMC_Result_OK;
726 if (pi->thermal_sclk_dpm_enabled) {
728 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
730 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
733 if (smc_result == PPSMC_Result_OK)
739 static int ci_power_control_set_level(struct radeon_device *rdev)
741 struct ci_power_info *pi = ci_get_pi(rdev);
742 struct radeon_cac_tdp_table *cac_tdp_table =
743 rdev->pm.dpm.dyn_state.cac_tdp_table;
747 bool adjust_polarity = false; /* ??? */
749 if (pi->caps_power_containment) {
750 adjust_percent = adjust_polarity ?
751 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
752 target_tdp = ((100 + adjust_percent) *
753 (s32)cac_tdp_table->configurable_tdp) / 100;
755 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
761 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
763 struct ci_power_info *pi = ci_get_pi(rdev);
765 if (pi->uvd_power_gated == gate)
768 pi->uvd_power_gated = gate;
770 ci_update_uvd_dpm(rdev, gate);
773 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
775 struct ci_power_info *pi = ci_get_pi(rdev);
776 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
777 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
779 /* disable mclk switching if the refresh is >120Hz, even if the
780 * blanking period would allow it
782 if (r600_dpm_get_vrefresh(rdev) > 120)
785 /* disable mclk switching if the refresh is >120Hz, even if the
786 * blanking period would allow it
788 if (r600_dpm_get_vrefresh(rdev) > 120)
791 if (vblank_time < switch_limit)
798 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
799 struct radeon_ps *rps)
801 struct ci_ps *ps = ci_get_ps(rps);
802 struct ci_power_info *pi = ci_get_pi(rdev);
803 struct radeon_clock_and_voltage_limits *max_limits;
804 bool disable_mclk_switching;
808 if (rps->vce_active) {
809 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
810 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
816 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
817 ci_dpm_vblank_too_short(rdev))
818 disable_mclk_switching = true;
820 disable_mclk_switching = false;
822 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
823 pi->battery_state = true;
825 pi->battery_state = false;
827 if (rdev->pm.dpm.ac_power)
828 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
830 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
832 if (rdev->pm.dpm.ac_power == false) {
833 for (i = 0; i < ps->performance_level_count; i++) {
834 if (ps->performance_levels[i].mclk > max_limits->mclk)
835 ps->performance_levels[i].mclk = max_limits->mclk;
836 if (ps->performance_levels[i].sclk > max_limits->sclk)
837 ps->performance_levels[i].sclk = max_limits->sclk;
841 /* XXX validate the min clocks required for display */
843 if (disable_mclk_switching) {
844 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
845 sclk = ps->performance_levels[0].sclk;
847 mclk = ps->performance_levels[0].mclk;
848 sclk = ps->performance_levels[0].sclk;
851 if (rps->vce_active) {
852 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
853 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
854 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
855 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
858 ps->performance_levels[0].sclk = sclk;
859 ps->performance_levels[0].mclk = mclk;
861 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
862 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
864 if (disable_mclk_switching) {
865 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
866 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
868 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
869 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
873 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
874 int min_temp, int max_temp)
876 int low_temp = 0 * 1000;
877 int high_temp = 255 * 1000;
880 if (low_temp < min_temp)
882 if (high_temp > max_temp)
883 high_temp = max_temp;
884 if (high_temp < low_temp) {
885 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
889 tmp = RREG32_SMC(CG_THERMAL_INT);
890 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
891 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
892 CI_DIG_THERM_INTL(low_temp / 1000);
893 WREG32_SMC(CG_THERMAL_INT, tmp);
896 /* XXX: need to figure out how to handle this properly */
897 tmp = RREG32_SMC(CG_THERMAL_CTRL);
898 tmp &= DIG_THERM_DPM_MASK;
899 tmp |= DIG_THERM_DPM(high_temp / 1000);
900 WREG32_SMC(CG_THERMAL_CTRL, tmp);
903 rdev->pm.dpm.thermal.min_temp = low_temp;
904 rdev->pm.dpm.thermal.max_temp = high_temp;
909 static int ci_thermal_enable_alert(struct radeon_device *rdev,
912 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
916 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
917 WREG32_SMC(CG_THERMAL_INT, thermal_int);
918 rdev->irq.dpm_thermal = false;
919 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
920 if (result != PPSMC_Result_OK) {
921 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
925 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
926 WREG32_SMC(CG_THERMAL_INT, thermal_int);
927 rdev->irq.dpm_thermal = true;
928 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
929 if (result != PPSMC_Result_OK) {
930 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
938 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
940 struct ci_power_info *pi = ci_get_pi(rdev);
943 if (pi->fan_ctrl_is_in_default_mode) {
944 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
945 pi->fan_ctrl_default_mode = tmp;
946 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
948 pi->fan_ctrl_is_in_default_mode = false;
951 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
953 WREG32_SMC(CG_FDO_CTRL2, tmp);
955 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
956 tmp |= FDO_PWM_MODE(mode);
957 WREG32_SMC(CG_FDO_CTRL2, tmp);
960 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
962 struct ci_power_info *pi = ci_get_pi(rdev);
963 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
965 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
966 u16 fdo_min, slope1, slope2;
967 u32 reference_clock, tmp;
971 if (!pi->fan_table_start) {
972 rdev->pm.dpm.fan.ucode_fan_control = false;
976 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
979 rdev->pm.dpm.fan.ucode_fan_control = false;
983 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
984 do_div(tmp64, 10000);
985 fdo_min = (u16)tmp64;
987 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
988 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
990 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
991 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
993 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
994 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
996 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
997 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
998 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
1000 fan_table.Slope1 = cpu_to_be16(slope1);
1001 fan_table.Slope2 = cpu_to_be16(slope2);
1003 fan_table.FdoMin = cpu_to_be16(fdo_min);
1005 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
1007 fan_table.HystUp = cpu_to_be16(1);
1009 fan_table.HystSlope = cpu_to_be16(1);
1011 fan_table.TempRespLim = cpu_to_be16(5);
1013 reference_clock = radeon_get_xclk(rdev);
1015 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1016 reference_clock) / 1600);
1018 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1020 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1021 fan_table.TempSrc = (uint8_t)tmp;
1023 ret = ci_copy_bytes_to_smc(rdev,
1024 pi->fan_table_start,
1030 DRM_ERROR("Failed to load fan table to the SMC.");
1031 rdev->pm.dpm.fan.ucode_fan_control = false;
1037 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1039 struct ci_power_info *pi = ci_get_pi(rdev);
1042 if (pi->caps_od_fuzzy_fan_control_support) {
1043 ret = ci_send_msg_to_smc_with_parameter(rdev,
1044 PPSMC_StartFanControl,
1046 if (ret != PPSMC_Result_OK)
1048 ret = ci_send_msg_to_smc_with_parameter(rdev,
1049 PPSMC_MSG_SetFanPwmMax,
1050 rdev->pm.dpm.fan.default_max_fan_pwm);
1051 if (ret != PPSMC_Result_OK)
1054 ret = ci_send_msg_to_smc_with_parameter(rdev,
1055 PPSMC_StartFanControl,
1057 if (ret != PPSMC_Result_OK)
1061 pi->fan_is_controlled_by_smc = true;
1065 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1068 struct ci_power_info *pi = ci_get_pi(rdev);
1070 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1071 if (ret == PPSMC_Result_OK) {
1072 pi->fan_is_controlled_by_smc = false;
1078 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1084 if (rdev->pm.no_fan)
1087 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1088 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1093 tmp64 = (u64)duty * 100;
1094 do_div(tmp64, duty100);
1095 *speed = (u32)tmp64;
1103 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1109 struct ci_power_info *pi = ci_get_pi(rdev);
1111 if (rdev->pm.no_fan)
1114 if (pi->fan_is_controlled_by_smc)
1120 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1125 tmp64 = (u64)speed * duty100;
1129 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1130 tmp |= FDO_STATIC_DUTY(duty);
1131 WREG32_SMC(CG_FDO_CTRL0, tmp);
1136 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1139 /* stop auto-manage */
1140 if (rdev->pm.dpm.fan.ucode_fan_control)
1141 ci_fan_ctrl_stop_smc_fan_control(rdev);
1142 ci_fan_ctrl_set_static_mode(rdev, mode);
1144 /* restart auto-manage */
1145 if (rdev->pm.dpm.fan.ucode_fan_control)
1146 ci_thermal_start_smc_fan_control(rdev);
1148 ci_fan_ctrl_set_default_mode(rdev);
1152 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1154 struct ci_power_info *pi = ci_get_pi(rdev);
1157 if (pi->fan_is_controlled_by_smc)
1160 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1161 return (tmp >> FDO_PWM_MODE_SHIFT);
1165 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1169 u32 xclk = radeon_get_xclk(rdev);
1171 if (rdev->pm.no_fan)
1174 if (rdev->pm.fan_pulses_per_revolution == 0)
1177 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1178 if (tach_period == 0)
1181 *speed = 60 * xclk * 10000 / tach_period;
1186 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1189 u32 tach_period, tmp;
1190 u32 xclk = radeon_get_xclk(rdev);
1192 if (rdev->pm.no_fan)
1195 if (rdev->pm.fan_pulses_per_revolution == 0)
1198 if ((speed < rdev->pm.fan_min_rpm) ||
1199 (speed > rdev->pm.fan_max_rpm))
1202 if (rdev->pm.dpm.fan.ucode_fan_control)
1203 ci_fan_ctrl_stop_smc_fan_control(rdev);
1205 tach_period = 60 * xclk * 10000 / (8 * speed);
1206 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1207 tmp |= TARGET_PERIOD(tach_period);
1208 WREG32_SMC(CG_TACH_CTRL, tmp);
1210 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1216 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1218 struct ci_power_info *pi = ci_get_pi(rdev);
1221 if (!pi->fan_ctrl_is_in_default_mode) {
1222 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1223 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1224 WREG32_SMC(CG_FDO_CTRL2, tmp);
1226 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1227 tmp |= TMIN(pi->t_min);
1228 WREG32_SMC(CG_FDO_CTRL2, tmp);
1229 pi->fan_ctrl_is_in_default_mode = true;
1233 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1235 if (rdev->pm.dpm.fan.ucode_fan_control) {
1236 ci_fan_ctrl_start_smc_fan_control(rdev);
1237 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1241 static void ci_thermal_initialize(struct radeon_device *rdev)
1245 if (rdev->pm.fan_pulses_per_revolution) {
1246 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1247 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1248 WREG32_SMC(CG_TACH_CTRL, tmp);
1251 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1252 tmp |= TACH_PWM_RESP_RATE(0x28);
1253 WREG32_SMC(CG_FDO_CTRL2, tmp);
1256 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1260 ci_thermal_initialize(rdev);
1261 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1264 ret = ci_thermal_enable_alert(rdev, true);
1267 if (rdev->pm.dpm.fan.ucode_fan_control) {
1268 ret = ci_thermal_setup_fan_table(rdev);
1271 ci_thermal_start_smc_fan_control(rdev);
1277 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1279 if (!rdev->pm.no_fan)
1280 ci_fan_ctrl_set_default_mode(rdev);
1284 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1285 u16 reg_offset, u32 *value)
1287 struct ci_power_info *pi = ci_get_pi(rdev);
1289 return ci_read_smc_sram_dword(rdev,
1290 pi->soft_regs_start + reg_offset,
1291 value, pi->sram_end);
1295 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1296 u16 reg_offset, u32 value)
1298 struct ci_power_info *pi = ci_get_pi(rdev);
1300 return ci_write_smc_sram_dword(rdev,
1301 pi->soft_regs_start + reg_offset,
1302 value, pi->sram_end);
1305 static void ci_init_fps_limits(struct radeon_device *rdev)
1307 struct ci_power_info *pi = ci_get_pi(rdev);
1308 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1314 table->FpsHighT = cpu_to_be16(tmp);
1317 table->FpsLowT = cpu_to_be16(tmp);
1321 static int ci_update_sclk_t(struct radeon_device *rdev)
1323 struct ci_power_info *pi = ci_get_pi(rdev);
1325 u32 low_sclk_interrupt_t = 0;
1327 if (pi->caps_sclk_throttle_low_notification) {
1328 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1330 ret = ci_copy_bytes_to_smc(rdev,
1331 pi->dpm_table_start +
1332 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1333 (u8 *)&low_sclk_interrupt_t,
1334 sizeof(u32), pi->sram_end);
1341 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1343 struct ci_power_info *pi = ci_get_pi(rdev);
1344 u16 leakage_id, virtual_voltage_id;
1348 pi->vddc_leakage.count = 0;
1349 pi->vddci_leakage.count = 0;
1351 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1352 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1353 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1354 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1356 if (vddc != 0 && vddc != virtual_voltage_id) {
1357 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1358 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1359 pi->vddc_leakage.count++;
1362 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1363 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1364 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1365 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1368 if (vddc != 0 && vddc != virtual_voltage_id) {
1369 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1370 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1371 pi->vddc_leakage.count++;
1373 if (vddci != 0 && vddci != virtual_voltage_id) {
1374 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1375 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1376 pi->vddci_leakage.count++;
1383 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1385 struct ci_power_info *pi = ci_get_pi(rdev);
1386 bool want_thermal_protection;
1387 enum radeon_dpm_event_src dpm_event_src;
1393 want_thermal_protection = false;
1395 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1396 want_thermal_protection = true;
1397 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1399 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1400 want_thermal_protection = true;
1401 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1403 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1404 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1405 want_thermal_protection = true;
1406 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1410 if (want_thermal_protection) {
1412 /* XXX: need to figure out how to handle this properly */
1413 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1414 tmp &= DPM_EVENT_SRC_MASK;
1415 tmp |= DPM_EVENT_SRC(dpm_event_src);
1416 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1419 tmp = RREG32_SMC(GENERAL_PWRMGT);
1420 if (pi->thermal_protection)
1421 tmp &= ~THERMAL_PROTECTION_DIS;
1423 tmp |= THERMAL_PROTECTION_DIS;
1424 WREG32_SMC(GENERAL_PWRMGT, tmp);
1426 tmp = RREG32_SMC(GENERAL_PWRMGT);
1427 tmp |= THERMAL_PROTECTION_DIS;
1428 WREG32_SMC(GENERAL_PWRMGT, tmp);
1432 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1433 enum radeon_dpm_auto_throttle_src source,
1436 struct ci_power_info *pi = ci_get_pi(rdev);
1439 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1440 pi->active_auto_throttle_sources |= 1 << source;
1441 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1444 if (pi->active_auto_throttle_sources & (1 << source)) {
1445 pi->active_auto_throttle_sources &= ~(1 << source);
1446 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1451 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1453 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1454 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1457 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1459 struct ci_power_info *pi = ci_get_pi(rdev);
1460 PPSMC_Result smc_result;
1462 if (!pi->need_update_smu7_dpm_table)
1465 if ((!pi->sclk_dpm_key_disabled) &&
1466 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1467 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1468 if (smc_result != PPSMC_Result_OK)
1472 if ((!pi->mclk_dpm_key_disabled) &&
1473 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1474 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1475 if (smc_result != PPSMC_Result_OK)
1479 pi->need_update_smu7_dpm_table = 0;
1483 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1485 struct ci_power_info *pi = ci_get_pi(rdev);
1486 PPSMC_Result smc_result;
1489 if (!pi->sclk_dpm_key_disabled) {
1490 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1491 if (smc_result != PPSMC_Result_OK)
1495 if (!pi->mclk_dpm_key_disabled) {
1496 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1497 if (smc_result != PPSMC_Result_OK)
1500 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1502 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1503 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1504 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1508 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1509 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1510 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1513 if (!pi->sclk_dpm_key_disabled) {
1514 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1515 if (smc_result != PPSMC_Result_OK)
1519 if (!pi->mclk_dpm_key_disabled) {
1520 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1521 if (smc_result != PPSMC_Result_OK)
1529 static int ci_start_dpm(struct radeon_device *rdev)
1531 struct ci_power_info *pi = ci_get_pi(rdev);
1532 PPSMC_Result smc_result;
1536 tmp = RREG32_SMC(GENERAL_PWRMGT);
1537 tmp |= GLOBAL_PWRMGT_EN;
1538 WREG32_SMC(GENERAL_PWRMGT, tmp);
1540 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1541 tmp |= DYNAMIC_PM_EN;
1542 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1544 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1546 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1548 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1549 if (smc_result != PPSMC_Result_OK)
1552 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1556 if (!pi->pcie_dpm_key_disabled) {
1557 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1558 if (smc_result != PPSMC_Result_OK)
1565 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1567 struct ci_power_info *pi = ci_get_pi(rdev);
1568 PPSMC_Result smc_result;
1570 if (!pi->need_update_smu7_dpm_table)
1573 if ((!pi->sclk_dpm_key_disabled) &&
1574 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1575 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1576 if (smc_result != PPSMC_Result_OK)
1580 if ((!pi->mclk_dpm_key_disabled) &&
1581 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1582 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1583 if (smc_result != PPSMC_Result_OK)
1590 static int ci_stop_dpm(struct radeon_device *rdev)
1592 struct ci_power_info *pi = ci_get_pi(rdev);
1593 PPSMC_Result smc_result;
1597 tmp = RREG32_SMC(GENERAL_PWRMGT);
1598 tmp &= ~GLOBAL_PWRMGT_EN;
1599 WREG32_SMC(GENERAL_PWRMGT, tmp);
1601 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1602 tmp &= ~DYNAMIC_PM_EN;
1603 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1605 if (!pi->pcie_dpm_key_disabled) {
1606 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1607 if (smc_result != PPSMC_Result_OK)
1611 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1615 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1616 if (smc_result != PPSMC_Result_OK)
1622 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1624 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1627 tmp &= ~SCLK_PWRMGT_OFF;
1629 tmp |= SCLK_PWRMGT_OFF;
1630 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1634 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1637 struct ci_power_info *pi = ci_get_pi(rdev);
1638 struct radeon_cac_tdp_table *cac_tdp_table =
1639 rdev->pm.dpm.dyn_state.cac_tdp_table;
1643 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1645 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1647 ci_set_power_limit(rdev, power_limit);
1649 if (pi->caps_automatic_dc_transition) {
1651 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1653 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1660 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1661 PPSMC_Msg msg, u32 parameter)
1663 WREG32(SMC_MSG_ARG_0, parameter);
1664 return ci_send_msg_to_smc(rdev, msg);
1667 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1668 PPSMC_Msg msg, u32 *parameter)
1670 PPSMC_Result smc_result;
1672 smc_result = ci_send_msg_to_smc(rdev, msg);
1674 if ((smc_result == PPSMC_Result_OK) && parameter)
1675 *parameter = RREG32(SMC_MSG_ARG_0);
1680 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1682 struct ci_power_info *pi = ci_get_pi(rdev);
1684 if (!pi->sclk_dpm_key_disabled) {
1685 PPSMC_Result smc_result =
1686 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1687 if (smc_result != PPSMC_Result_OK)
1694 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1696 struct ci_power_info *pi = ci_get_pi(rdev);
1698 if (!pi->mclk_dpm_key_disabled) {
1699 PPSMC_Result smc_result =
1700 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1701 if (smc_result != PPSMC_Result_OK)
1708 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1710 struct ci_power_info *pi = ci_get_pi(rdev);
1712 if (!pi->pcie_dpm_key_disabled) {
1713 PPSMC_Result smc_result =
1714 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1715 if (smc_result != PPSMC_Result_OK)
1722 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1724 struct ci_power_info *pi = ci_get_pi(rdev);
1726 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1727 PPSMC_Result smc_result =
1728 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1729 if (smc_result != PPSMC_Result_OK)
1736 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1739 PPSMC_Result smc_result =
1740 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1741 if (smc_result != PPSMC_Result_OK)
1747 static int ci_set_boot_state(struct radeon_device *rdev)
1749 return ci_enable_sclk_mclk_dpm(rdev, false);
1753 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1756 PPSMC_Result smc_result =
1757 ci_send_msg_to_smc_return_parameter(rdev,
1758 PPSMC_MSG_API_GetSclkFrequency,
1760 if (smc_result != PPSMC_Result_OK)
1766 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1769 PPSMC_Result smc_result =
1770 ci_send_msg_to_smc_return_parameter(rdev,
1771 PPSMC_MSG_API_GetMclkFrequency,
1773 if (smc_result != PPSMC_Result_OK)
1779 static void ci_dpm_start_smc(struct radeon_device *rdev)
1783 ci_program_jump_on_start(rdev);
1784 ci_start_smc_clock(rdev);
1786 for (i = 0; i < rdev->usec_timeout; i++) {
1787 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1792 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1795 ci_stop_smc_clock(rdev);
1798 static int ci_process_firmware_header(struct radeon_device *rdev)
1800 struct ci_power_info *pi = ci_get_pi(rdev);
1804 ret = ci_read_smc_sram_dword(rdev,
1805 SMU7_FIRMWARE_HEADER_LOCATION +
1806 offsetof(SMU7_Firmware_Header, DpmTable),
1807 &tmp, pi->sram_end);
1811 pi->dpm_table_start = tmp;
1813 ret = ci_read_smc_sram_dword(rdev,
1814 SMU7_FIRMWARE_HEADER_LOCATION +
1815 offsetof(SMU7_Firmware_Header, SoftRegisters),
1816 &tmp, pi->sram_end);
1820 pi->soft_regs_start = tmp;
1822 ret = ci_read_smc_sram_dword(rdev,
1823 SMU7_FIRMWARE_HEADER_LOCATION +
1824 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1825 &tmp, pi->sram_end);
1829 pi->mc_reg_table_start = tmp;
1831 ret = ci_read_smc_sram_dword(rdev,
1832 SMU7_FIRMWARE_HEADER_LOCATION +
1833 offsetof(SMU7_Firmware_Header, FanTable),
1834 &tmp, pi->sram_end);
1838 pi->fan_table_start = tmp;
1840 ret = ci_read_smc_sram_dword(rdev,
1841 SMU7_FIRMWARE_HEADER_LOCATION +
1842 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1843 &tmp, pi->sram_end);
1847 pi->arb_table_start = tmp;
1852 static void ci_read_clock_registers(struct radeon_device *rdev)
1854 struct ci_power_info *pi = ci_get_pi(rdev);
1856 pi->clock_registers.cg_spll_func_cntl =
1857 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1858 pi->clock_registers.cg_spll_func_cntl_2 =
1859 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1860 pi->clock_registers.cg_spll_func_cntl_3 =
1861 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1862 pi->clock_registers.cg_spll_func_cntl_4 =
1863 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1864 pi->clock_registers.cg_spll_spread_spectrum =
1865 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1866 pi->clock_registers.cg_spll_spread_spectrum_2 =
1867 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1868 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1869 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1870 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1871 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1872 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1873 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1874 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1875 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1876 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1879 static void ci_init_sclk_t(struct radeon_device *rdev)
1881 struct ci_power_info *pi = ci_get_pi(rdev);
1883 pi->low_sclk_interrupt_t = 0;
1886 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1889 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1892 tmp &= ~THERMAL_PROTECTION_DIS;
1894 tmp |= THERMAL_PROTECTION_DIS;
1895 WREG32_SMC(GENERAL_PWRMGT, tmp);
1898 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1900 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1902 tmp |= STATIC_PM_EN;
1904 WREG32_SMC(GENERAL_PWRMGT, tmp);
1908 static int ci_enter_ulp_state(struct radeon_device *rdev)
1911 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1918 static int ci_exit_ulp_state(struct radeon_device *rdev)
1922 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1926 for (i = 0; i < rdev->usec_timeout; i++) {
1927 if (RREG32(SMC_RESP_0) == 1)
1936 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1939 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1941 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1944 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1947 struct ci_power_info *pi = ci_get_pi(rdev);
1950 if (pi->caps_sclk_ds) {
1951 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1954 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1958 if (pi->caps_sclk_ds) {
1959 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1967 static void ci_program_display_gap(struct radeon_device *rdev)
1969 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1970 u32 pre_vbi_time_in_us;
1971 u32 frame_time_in_us;
1972 u32 ref_clock = rdev->clock.spll.reference_freq;
1973 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1974 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1976 tmp &= ~DISP_GAP_MASK;
1977 if (rdev->pm.dpm.new_active_crtc_count > 0)
1978 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1980 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1981 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1983 if (refresh_rate == 0)
1985 if (vblank_time == 0xffffffff)
1987 frame_time_in_us = 1000000 / refresh_rate;
1988 pre_vbi_time_in_us =
1989 frame_time_in_us - 200 - vblank_time;
1990 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1992 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1993 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1994 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1997 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
2001 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
2003 struct ci_power_info *pi = ci_get_pi(rdev);
2007 if (pi->caps_sclk_ss_support) {
2008 tmp = RREG32_SMC(GENERAL_PWRMGT);
2009 tmp |= DYN_SPREAD_SPECTRUM_EN;
2010 WREG32_SMC(GENERAL_PWRMGT, tmp);
2013 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2015 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2017 tmp = RREG32_SMC(GENERAL_PWRMGT);
2018 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2019 WREG32_SMC(GENERAL_PWRMGT, tmp);
2023 static void ci_program_sstp(struct radeon_device *rdev)
2025 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2028 static void ci_enable_display_gap(struct radeon_device *rdev)
2030 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2032 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2033 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2034 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2036 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2039 static void ci_program_vc(struct radeon_device *rdev)
2043 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2044 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2045 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2047 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2048 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2049 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2050 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2051 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2052 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2053 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2054 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2057 static void ci_clear_vc(struct radeon_device *rdev)
2061 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2062 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2063 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2065 WREG32_SMC(CG_FTV_0, 0);
2066 WREG32_SMC(CG_FTV_1, 0);
2067 WREG32_SMC(CG_FTV_2, 0);
2068 WREG32_SMC(CG_FTV_3, 0);
2069 WREG32_SMC(CG_FTV_4, 0);
2070 WREG32_SMC(CG_FTV_5, 0);
2071 WREG32_SMC(CG_FTV_6, 0);
2072 WREG32_SMC(CG_FTV_7, 0);
2075 static int ci_upload_firmware(struct radeon_device *rdev)
2077 struct ci_power_info *pi = ci_get_pi(rdev);
2080 for (i = 0; i < rdev->usec_timeout; i++) {
2081 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2084 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2086 ci_stop_smc_clock(rdev);
2089 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2095 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2096 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2097 struct atom_voltage_table *voltage_table)
2101 if (voltage_dependency_table == NULL)
2104 voltage_table->mask_low = 0;
2105 voltage_table->phase_delay = 0;
2107 voltage_table->count = voltage_dependency_table->count;
2108 for (i = 0; i < voltage_table->count; i++) {
2109 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2110 voltage_table->entries[i].smio_low = 0;
2116 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2118 struct ci_power_info *pi = ci_get_pi(rdev);
2121 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2122 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2123 VOLTAGE_OBJ_GPIO_LUT,
2124 &pi->vddc_voltage_table);
2127 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2128 ret = ci_get_svi2_voltage_table(rdev,
2129 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2130 &pi->vddc_voltage_table);
2135 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2136 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2137 &pi->vddc_voltage_table);
2139 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2140 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2141 VOLTAGE_OBJ_GPIO_LUT,
2142 &pi->vddci_voltage_table);
2145 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2146 ret = ci_get_svi2_voltage_table(rdev,
2147 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2148 &pi->vddci_voltage_table);
2153 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2154 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2155 &pi->vddci_voltage_table);
2157 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2158 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2159 VOLTAGE_OBJ_GPIO_LUT,
2160 &pi->mvdd_voltage_table);
2163 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2164 ret = ci_get_svi2_voltage_table(rdev,
2165 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2166 &pi->mvdd_voltage_table);
2171 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2172 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2173 &pi->mvdd_voltage_table);
2178 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2179 struct atom_voltage_table_entry *voltage_table,
2180 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2184 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2185 &smc_voltage_table->StdVoltageHiSidd,
2186 &smc_voltage_table->StdVoltageLoSidd);
2189 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2190 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2193 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2194 smc_voltage_table->StdVoltageHiSidd =
2195 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2196 smc_voltage_table->StdVoltageLoSidd =
2197 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2200 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2201 SMU7_Discrete_DpmTable *table)
2203 struct ci_power_info *pi = ci_get_pi(rdev);
2206 table->VddcLevelCount = pi->vddc_voltage_table.count;
2207 for (count = 0; count < table->VddcLevelCount; count++) {
2208 ci_populate_smc_voltage_table(rdev,
2209 &pi->vddc_voltage_table.entries[count],
2210 &table->VddcLevel[count]);
2212 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2213 table->VddcLevel[count].Smio |=
2214 pi->vddc_voltage_table.entries[count].smio_low;
2216 table->VddcLevel[count].Smio = 0;
2218 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2223 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2224 SMU7_Discrete_DpmTable *table)
2227 struct ci_power_info *pi = ci_get_pi(rdev);
2229 table->VddciLevelCount = pi->vddci_voltage_table.count;
2230 for (count = 0; count < table->VddciLevelCount; count++) {
2231 ci_populate_smc_voltage_table(rdev,
2232 &pi->vddci_voltage_table.entries[count],
2233 &table->VddciLevel[count]);
2235 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2236 table->VddciLevel[count].Smio |=
2237 pi->vddci_voltage_table.entries[count].smio_low;
2239 table->VddciLevel[count].Smio = 0;
2241 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2246 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2247 SMU7_Discrete_DpmTable *table)
2249 struct ci_power_info *pi = ci_get_pi(rdev);
2252 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2253 for (count = 0; count < table->MvddLevelCount; count++) {
2254 ci_populate_smc_voltage_table(rdev,
2255 &pi->mvdd_voltage_table.entries[count],
2256 &table->MvddLevel[count]);
2258 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2259 table->MvddLevel[count].Smio |=
2260 pi->mvdd_voltage_table.entries[count].smio_low;
2262 table->MvddLevel[count].Smio = 0;
2264 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2269 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2270 SMU7_Discrete_DpmTable *table)
2274 ret = ci_populate_smc_vddc_table(rdev, table);
2278 ret = ci_populate_smc_vddci_table(rdev, table);
2282 ret = ci_populate_smc_mvdd_table(rdev, table);
2289 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2290 SMU7_Discrete_VoltageLevel *voltage)
2292 struct ci_power_info *pi = ci_get_pi(rdev);
2295 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2296 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2297 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2298 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2303 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2310 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2311 struct atom_voltage_table_entry *voltage_table,
2312 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2315 bool voltage_found = false;
2316 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2317 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2319 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2322 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2323 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2324 if (voltage_table->value ==
2325 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2326 voltage_found = true;
2327 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2330 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2331 *std_voltage_lo_sidd =
2332 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2333 *std_voltage_hi_sidd =
2334 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2339 if (!voltage_found) {
2340 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2341 if (voltage_table->value <=
2342 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2343 voltage_found = true;
2344 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2347 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2348 *std_voltage_lo_sidd =
2349 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2350 *std_voltage_hi_sidd =
2351 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2361 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2362 const struct radeon_phase_shedding_limits_table *limits,
2364 u32 *phase_shedding)
2368 *phase_shedding = 1;
2370 for (i = 0; i < limits->count; i++) {
2371 if (sclk < limits->entries[i].sclk) {
2372 *phase_shedding = i;
2378 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2379 const struct radeon_phase_shedding_limits_table *limits,
2381 u32 *phase_shedding)
2385 *phase_shedding = 1;
2387 for (i = 0; i < limits->count; i++) {
2388 if (mclk < limits->entries[i].mclk) {
2389 *phase_shedding = i;
2395 static int ci_init_arb_table_index(struct radeon_device *rdev)
2397 struct ci_power_info *pi = ci_get_pi(rdev);
2401 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2402 &tmp, pi->sram_end);
2407 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2409 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2413 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2414 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2415 u32 clock, u32 *voltage)
2419 if (allowed_clock_voltage_table->count == 0)
2422 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2423 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2424 *voltage = allowed_clock_voltage_table->entries[i].v;
2429 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2434 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2435 u32 sclk, u32 min_sclk_in_sr)
2439 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2440 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2445 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2446 tmp = sclk / (1 << i);
2447 if (tmp >= min || i == 0)
2454 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2456 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2459 static int ci_reset_to_default(struct radeon_device *rdev)
2461 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2465 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2469 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2471 if (tmp == MC_CG_ARB_FREQ_F0)
2474 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2477 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2478 const u32 engine_clock,
2479 const u32 memory_clock,
2485 tmp = RREG32(MC_SEQ_MISC0);
2486 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2489 ((rdev->pdev->device == 0x67B0) ||
2490 (rdev->pdev->device == 0x67B1))) {
2491 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2492 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2493 *dram_timimg2 &= ~0x00ff0000;
2494 *dram_timimg2 |= tmp2 << 16;
2495 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2496 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2497 *dram_timimg2 &= ~0x00ff0000;
2498 *dram_timimg2 |= tmp2 << 16;
2504 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2507 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2513 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2515 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2516 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2517 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2519 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2521 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2522 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2523 arb_regs->McArbBurstTime = (u8)burst_time;
2528 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2530 struct ci_power_info *pi = ci_get_pi(rdev);
2531 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2535 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2537 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2538 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2539 ret = ci_populate_memory_timing_parameters(rdev,
2540 pi->dpm_table.sclk_table.dpm_levels[i].value,
2541 pi->dpm_table.mclk_table.dpm_levels[j].value,
2542 &arb_regs.entries[i][j]);
2549 ret = ci_copy_bytes_to_smc(rdev,
2550 pi->arb_table_start,
2552 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2558 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2560 struct ci_power_info *pi = ci_get_pi(rdev);
2562 if (pi->need_update_smu7_dpm_table == 0)
2565 return ci_do_program_memory_timing_parameters(rdev);
2568 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2569 struct radeon_ps *radeon_boot_state)
2571 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2572 struct ci_power_info *pi = ci_get_pi(rdev);
2575 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2576 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2577 boot_state->performance_levels[0].sclk) {
2578 pi->smc_state_table.GraphicsBootLevel = level;
2583 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2584 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2585 boot_state->performance_levels[0].mclk) {
2586 pi->smc_state_table.MemoryBootLevel = level;
2592 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2597 for (i = dpm_table->count; i > 0; i--) {
2598 mask_value = mask_value << 1;
2599 if (dpm_table->dpm_levels[i-1].enabled)
2602 mask_value &= 0xFFFFFFFE;
2608 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2609 SMU7_Discrete_DpmTable *table)
2611 struct ci_power_info *pi = ci_get_pi(rdev);
2612 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2615 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2616 table->LinkLevel[i].PcieGenSpeed =
2617 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2618 table->LinkLevel[i].PcieLaneCount =
2619 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2620 table->LinkLevel[i].EnabledForActivity = 1;
2621 table->LinkLevel[i].DownT = cpu_to_be32(5);
2622 table->LinkLevel[i].UpT = cpu_to_be32(30);
2625 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2626 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2627 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2630 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2631 SMU7_Discrete_DpmTable *table)
2634 struct atom_clock_dividers dividers;
2637 table->UvdLevelCount =
2638 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2640 for (count = 0; count < table->UvdLevelCount; count++) {
2641 table->UvdLevel[count].VclkFrequency =
2642 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2643 table->UvdLevel[count].DclkFrequency =
2644 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2645 table->UvdLevel[count].MinVddc =
2646 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2647 table->UvdLevel[count].MinVddcPhases = 1;
2649 ret = radeon_atom_get_clock_dividers(rdev,
2650 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2651 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2655 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2657 ret = radeon_atom_get_clock_dividers(rdev,
2658 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2659 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2663 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2665 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2666 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2667 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2673 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2674 SMU7_Discrete_DpmTable *table)
2677 struct atom_clock_dividers dividers;
2680 table->VceLevelCount =
2681 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2683 for (count = 0; count < table->VceLevelCount; count++) {
2684 table->VceLevel[count].Frequency =
2685 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2686 table->VceLevel[count].MinVoltage =
2687 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2688 table->VceLevel[count].MinPhases = 1;
2690 ret = radeon_atom_get_clock_dividers(rdev,
2691 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2692 table->VceLevel[count].Frequency, false, ÷rs);
2696 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2698 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2699 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2706 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2707 SMU7_Discrete_DpmTable *table)
2710 struct atom_clock_dividers dividers;
2713 table->AcpLevelCount = (u8)
2714 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2716 for (count = 0; count < table->AcpLevelCount; count++) {
2717 table->AcpLevel[count].Frequency =
2718 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2719 table->AcpLevel[count].MinVoltage =
2720 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2721 table->AcpLevel[count].MinPhases = 1;
2723 ret = radeon_atom_get_clock_dividers(rdev,
2724 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2725 table->AcpLevel[count].Frequency, false, ÷rs);
2729 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2731 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2732 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2738 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2739 SMU7_Discrete_DpmTable *table)
2742 struct atom_clock_dividers dividers;
2745 table->SamuLevelCount =
2746 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2748 for (count = 0; count < table->SamuLevelCount; count++) {
2749 table->SamuLevel[count].Frequency =
2750 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2751 table->SamuLevel[count].MinVoltage =
2752 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2753 table->SamuLevel[count].MinPhases = 1;
2755 ret = radeon_atom_get_clock_dividers(rdev,
2756 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2757 table->SamuLevel[count].Frequency, false, ÷rs);
2761 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2763 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2764 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2770 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2772 SMU7_Discrete_MemoryLevel *mclk,
2776 struct ci_power_info *pi = ci_get_pi(rdev);
2777 u32 dll_cntl = pi->clock_registers.dll_cntl;
2778 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2779 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2780 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2781 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2782 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2783 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2784 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2785 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2786 struct atom_mpll_param mpll_param;
2789 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2793 mpll_func_cntl &= ~BWCTRL_MASK;
2794 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2796 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2797 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2798 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2800 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2801 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2803 if (pi->mem_gddr5) {
2804 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2805 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2806 YCLK_POST_DIV(mpll_param.post_div);
2809 if (pi->caps_mclk_ss_support) {
2810 struct radeon_atom_ss ss;
2813 u32 reference_clock = rdev->clock.mpll.reference_freq;
2815 if (mpll_param.qdr == 1)
2816 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2818 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2820 tmp = (freq_nom / reference_clock);
2822 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2823 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2824 u32 clks = reference_clock * 5 / ss.rate;
2825 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2827 mpll_ss1 &= ~CLKV_MASK;
2828 mpll_ss1 |= CLKV(clkv);
2830 mpll_ss2 &= ~CLKS_MASK;
2831 mpll_ss2 |= CLKS(clks);
2835 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2836 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2839 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2841 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2843 mclk->MclkFrequency = memory_clock;
2844 mclk->MpllFuncCntl = mpll_func_cntl;
2845 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2846 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2847 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2848 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2849 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2850 mclk->DllCntl = dll_cntl;
2851 mclk->MpllSs1 = mpll_ss1;
2852 mclk->MpllSs2 = mpll_ss2;
2857 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2859 SMU7_Discrete_MemoryLevel *memory_level)
2861 struct ci_power_info *pi = ci_get_pi(rdev);
2865 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2866 ret = ci_get_dependency_volt_by_clk(rdev,
2867 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2868 memory_clock, &memory_level->MinVddc);
2873 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2874 ret = ci_get_dependency_volt_by_clk(rdev,
2875 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2876 memory_clock, &memory_level->MinVddci);
2881 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2882 ret = ci_get_dependency_volt_by_clk(rdev,
2883 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2884 memory_clock, &memory_level->MinMvdd);
2889 memory_level->MinVddcPhases = 1;
2891 if (pi->vddc_phase_shed_control)
2892 ci_populate_phase_value_based_on_mclk(rdev,
2893 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2895 &memory_level->MinVddcPhases);
2897 memory_level->EnabledForThrottle = 1;
2898 memory_level->UpH = 0;
2899 memory_level->DownH = 100;
2900 memory_level->VoltageDownH = 0;
2901 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2903 memory_level->StutterEnable = false;
2904 memory_level->StrobeEnable = false;
2905 memory_level->EdcReadEnable = false;
2906 memory_level->EdcWriteEnable = false;
2907 memory_level->RttEnable = false;
2909 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2911 if (pi->mclk_stutter_mode_threshold &&
2912 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2913 (pi->uvd_enabled == false) &&
2914 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2915 (rdev->pm.dpm.new_active_crtc_count <= 2))
2916 memory_level->StutterEnable = true;
2918 if (pi->mclk_strobe_mode_threshold &&
2919 (memory_clock <= pi->mclk_strobe_mode_threshold))
2920 memory_level->StrobeEnable = 1;
2922 if (pi->mem_gddr5) {
2923 memory_level->StrobeRatio =
2924 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2925 if (pi->mclk_edc_enable_threshold &&
2926 (memory_clock > pi->mclk_edc_enable_threshold))
2927 memory_level->EdcReadEnable = true;
2929 if (pi->mclk_edc_wr_enable_threshold &&
2930 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2931 memory_level->EdcWriteEnable = true;
2933 if (memory_level->StrobeEnable) {
2934 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2935 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2936 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2938 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2940 dll_state_on = pi->dll_default_on;
2943 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2944 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2947 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2951 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2952 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2953 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2954 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2956 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2957 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2958 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2959 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2960 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2961 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2962 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2963 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2964 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2965 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2966 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2971 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2972 SMU7_Discrete_DpmTable *table)
2974 struct ci_power_info *pi = ci_get_pi(rdev);
2975 struct atom_clock_dividers dividers;
2976 SMU7_Discrete_VoltageLevel voltage_level;
2977 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2978 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2979 u32 dll_cntl = pi->clock_registers.dll_cntl;
2980 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2983 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2986 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2988 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2990 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2992 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2994 ret = radeon_atom_get_clock_dividers(rdev,
2995 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2996 table->ACPILevel.SclkFrequency, false, ÷rs);
3000 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3001 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3002 table->ACPILevel.DeepSleepDivId = 0;
3004 spll_func_cntl &= ~SPLL_PWRON;
3005 spll_func_cntl |= SPLL_RESET;
3007 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3008 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3010 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3011 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3012 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3013 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3014 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3015 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3016 table->ACPILevel.CcPwrDynRm = 0;
3017 table->ACPILevel.CcPwrDynRm1 = 0;
3019 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3020 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3021 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3022 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3023 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3024 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3025 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3026 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3027 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3028 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3029 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3031 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3032 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3034 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3036 table->MemoryACPILevel.MinVddci =
3037 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3039 table->MemoryACPILevel.MinVddci =
3040 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3043 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3044 table->MemoryACPILevel.MinMvdd = 0;
3046 table->MemoryACPILevel.MinMvdd =
3047 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3049 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3050 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3052 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3054 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3055 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3056 table->MemoryACPILevel.MpllAdFuncCntl =
3057 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3058 table->MemoryACPILevel.MpllDqFuncCntl =
3059 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3060 table->MemoryACPILevel.MpllFuncCntl =
3061 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3062 table->MemoryACPILevel.MpllFuncCntl_1 =
3063 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3064 table->MemoryACPILevel.MpllFuncCntl_2 =
3065 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3066 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3067 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3069 table->MemoryACPILevel.EnabledForThrottle = 0;
3070 table->MemoryACPILevel.EnabledForActivity = 0;
3071 table->MemoryACPILevel.UpH = 0;
3072 table->MemoryACPILevel.DownH = 100;
3073 table->MemoryACPILevel.VoltageDownH = 0;
3074 table->MemoryACPILevel.ActivityLevel =
3075 cpu_to_be16((u16)pi->mclk_activity_target);
3077 table->MemoryACPILevel.StutterEnable = false;
3078 table->MemoryACPILevel.StrobeEnable = false;
3079 table->MemoryACPILevel.EdcReadEnable = false;
3080 table->MemoryACPILevel.EdcWriteEnable = false;
3081 table->MemoryACPILevel.RttEnable = false;
3087 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3089 struct ci_power_info *pi = ci_get_pi(rdev);
3090 struct ci_ulv_parm *ulv = &pi->ulv;
3092 if (ulv->supported) {
3094 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3097 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3104 static int ci_populate_ulv_level(struct radeon_device *rdev,
3105 SMU7_Discrete_Ulv *state)
3107 struct ci_power_info *pi = ci_get_pi(rdev);
3108 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3110 state->CcPwrDynRm = 0;
3111 state->CcPwrDynRm1 = 0;
3113 if (ulv_voltage == 0) {
3114 pi->ulv.supported = false;
3118 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3119 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3120 state->VddcOffset = 0;
3123 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3125 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3126 state->VddcOffsetVid = 0;
3128 state->VddcOffsetVid = (u8)
3129 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3130 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3132 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3134 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3135 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3136 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3141 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3143 SMU7_Discrete_GraphicsLevel *sclk)
3145 struct ci_power_info *pi = ci_get_pi(rdev);
3146 struct atom_clock_dividers dividers;
3147 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3148 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3149 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3150 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3151 u32 reference_clock = rdev->clock.spll.reference_freq;
3152 u32 reference_divider;
3156 ret = radeon_atom_get_clock_dividers(rdev,
3157 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3158 engine_clock, false, ÷rs);
3162 reference_divider = 1 + dividers.ref_div;
3163 fbdiv = dividers.fb_div & 0x3FFFFFF;
3165 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3166 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3167 spll_func_cntl_3 |= SPLL_DITHEN;
3169 if (pi->caps_sclk_ss_support) {
3170 struct radeon_atom_ss ss;
3171 u32 vco_freq = engine_clock * dividers.post_div;
3173 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3174 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3175 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3176 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3178 cg_spll_spread_spectrum &= ~CLK_S_MASK;
3179 cg_spll_spread_spectrum |= CLK_S(clk_s);
3180 cg_spll_spread_spectrum |= SSEN;
3182 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3183 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3187 sclk->SclkFrequency = engine_clock;
3188 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3189 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3190 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3191 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3192 sclk->SclkDid = (u8)dividers.post_divider;
3197 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3199 u16 sclk_activity_level_t,
3200 SMU7_Discrete_GraphicsLevel *graphic_level)
3202 struct ci_power_info *pi = ci_get_pi(rdev);
3205 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3209 ret = ci_get_dependency_volt_by_clk(rdev,
3210 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3211 engine_clock, &graphic_level->MinVddc);
3215 graphic_level->SclkFrequency = engine_clock;
3217 graphic_level->Flags = 0;
3218 graphic_level->MinVddcPhases = 1;
3220 if (pi->vddc_phase_shed_control)
3221 ci_populate_phase_value_based_on_sclk(rdev,
3222 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3224 &graphic_level->MinVddcPhases);
3226 graphic_level->ActivityLevel = sclk_activity_level_t;
3228 graphic_level->CcPwrDynRm = 0;
3229 graphic_level->CcPwrDynRm1 = 0;
3230 graphic_level->EnabledForThrottle = 1;
3231 graphic_level->UpH = 0;
3232 graphic_level->DownH = 0;
3233 graphic_level->VoltageDownH = 0;
3234 graphic_level->PowerThrottle = 0;
3236 if (pi->caps_sclk_ds)
3237 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3239 CISLAND_MINIMUM_ENGINE_CLOCK);
3241 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3243 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3244 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3245 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3246 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3247 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3248 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3249 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3250 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3251 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3252 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3253 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3258 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3260 struct ci_power_info *pi = ci_get_pi(rdev);
3261 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3262 u32 level_array_address = pi->dpm_table_start +
3263 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3264 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3265 SMU7_MAX_LEVELS_GRAPHICS;
3266 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3269 memset(levels, 0, level_array_size);
3271 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3272 ret = ci_populate_single_graphic_level(rdev,
3273 dpm_table->sclk_table.dpm_levels[i].value,
3274 (u16)pi->activity_target[i],
3275 &pi->smc_state_table.GraphicsLevel[i]);
3279 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3280 if (i == (dpm_table->sclk_table.count - 1))
3281 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3282 PPSMC_DISPLAY_WATERMARK_HIGH;
3284 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3286 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3287 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3288 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3290 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3291 (u8 *)levels, level_array_size,
3299 static int ci_populate_ulv_state(struct radeon_device *rdev,
3300 SMU7_Discrete_Ulv *ulv_level)
3302 return ci_populate_ulv_level(rdev, ulv_level);
3305 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3307 struct ci_power_info *pi = ci_get_pi(rdev);
3308 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3309 u32 level_array_address = pi->dpm_table_start +
3310 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3311 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3312 SMU7_MAX_LEVELS_MEMORY;
3313 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3316 memset(levels, 0, level_array_size);
3318 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3319 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3321 ret = ci_populate_single_memory_level(rdev,
3322 dpm_table->mclk_table.dpm_levels[i].value,
3323 &pi->smc_state_table.MemoryLevel[i]);
3328 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3330 if ((dpm_table->mclk_table.count >= 2) &&
3331 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3332 pi->smc_state_table.MemoryLevel[1].MinVddc =
3333 pi->smc_state_table.MemoryLevel[0].MinVddc;
3334 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3335 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3338 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3340 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3341 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3342 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3344 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3345 PPSMC_DISPLAY_WATERMARK_HIGH;
3347 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3348 (u8 *)levels, level_array_size,
3356 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3357 struct ci_single_dpm_table* dpm_table,
3362 dpm_table->count = count;
3363 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3364 dpm_table->dpm_levels[i].enabled = false;
3367 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3368 u32 index, u32 pcie_gen, u32 pcie_lanes)
3370 dpm_table->dpm_levels[index].value = pcie_gen;
3371 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3372 dpm_table->dpm_levels[index].enabled = true;
3375 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3377 struct ci_power_info *pi = ci_get_pi(rdev);
3379 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3382 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3383 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3384 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3385 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3386 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3387 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3390 ci_reset_single_dpm_table(rdev,
3391 &pi->dpm_table.pcie_speed_table,
3392 SMU7_MAX_LEVELS_LINK);
3394 if (rdev->family == CHIP_BONAIRE)
3395 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3396 pi->pcie_gen_powersaving.min,
3397 pi->pcie_lane_powersaving.max);
3399 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3400 pi->pcie_gen_powersaving.min,
3401 pi->pcie_lane_powersaving.min);
3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3403 pi->pcie_gen_performance.min,
3404 pi->pcie_lane_performance.min);
3405 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3406 pi->pcie_gen_powersaving.min,
3407 pi->pcie_lane_powersaving.max);
3408 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3409 pi->pcie_gen_performance.min,
3410 pi->pcie_lane_performance.max);
3411 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3412 pi->pcie_gen_powersaving.max,
3413 pi->pcie_lane_powersaving.max);
3414 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3415 pi->pcie_gen_performance.max,
3416 pi->pcie_lane_performance.max);
3418 pi->dpm_table.pcie_speed_table.count = 6;
3423 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3425 struct ci_power_info *pi = ci_get_pi(rdev);
3426 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3427 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3428 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3429 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3430 struct radeon_cac_leakage_table *std_voltage_table =
3431 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3434 if (allowed_sclk_vddc_table == NULL)
3436 if (allowed_sclk_vddc_table->count < 1)
3438 if (allowed_mclk_table == NULL)
3440 if (allowed_mclk_table->count < 1)
3443 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3445 ci_reset_single_dpm_table(rdev,
3446 &pi->dpm_table.sclk_table,
3447 SMU7_MAX_LEVELS_GRAPHICS);
3448 ci_reset_single_dpm_table(rdev,
3449 &pi->dpm_table.mclk_table,
3450 SMU7_MAX_LEVELS_MEMORY);
3451 ci_reset_single_dpm_table(rdev,
3452 &pi->dpm_table.vddc_table,
3453 SMU7_MAX_LEVELS_VDDC);
3454 ci_reset_single_dpm_table(rdev,
3455 &pi->dpm_table.vddci_table,
3456 SMU7_MAX_LEVELS_VDDCI);
3457 ci_reset_single_dpm_table(rdev,
3458 &pi->dpm_table.mvdd_table,
3459 SMU7_MAX_LEVELS_MVDD);
3461 pi->dpm_table.sclk_table.count = 0;
3462 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3464 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3465 allowed_sclk_vddc_table->entries[i].clk)) {
3466 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3467 allowed_sclk_vddc_table->entries[i].clk;
3468 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3469 (i == 0) ? true : false;
3470 pi->dpm_table.sclk_table.count++;
3474 pi->dpm_table.mclk_table.count = 0;
3475 for (i = 0; i < allowed_mclk_table->count; i++) {
3477 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3478 allowed_mclk_table->entries[i].clk)) {
3479 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3480 allowed_mclk_table->entries[i].clk;
3481 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3482 (i == 0) ? true : false;
3483 pi->dpm_table.mclk_table.count++;
3487 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3488 pi->dpm_table.vddc_table.dpm_levels[i].value =
3489 allowed_sclk_vddc_table->entries[i].v;
3490 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3491 std_voltage_table->entries[i].leakage;
3492 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3494 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3496 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3497 if (allowed_mclk_table) {
3498 for (i = 0; i < allowed_mclk_table->count; i++) {
3499 pi->dpm_table.vddci_table.dpm_levels[i].value =
3500 allowed_mclk_table->entries[i].v;
3501 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3503 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3506 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3507 if (allowed_mclk_table) {
3508 for (i = 0; i < allowed_mclk_table->count; i++) {
3509 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3510 allowed_mclk_table->entries[i].v;
3511 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3513 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3516 ci_setup_default_pcie_tables(rdev);
3521 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3522 u32 value, u32 *boot_level)
3527 for(i = 0; i < table->count; i++) {
3528 if (value == table->dpm_levels[i].value) {
3537 static int ci_init_smc_table(struct radeon_device *rdev)
3539 struct ci_power_info *pi = ci_get_pi(rdev);
3540 struct ci_ulv_parm *ulv = &pi->ulv;
3541 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3542 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3545 ret = ci_setup_default_dpm_tables(rdev);
3549 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3550 ci_populate_smc_voltage_tables(rdev, table);
3552 ci_init_fps_limits(rdev);
3554 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3555 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3557 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3558 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3561 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3563 if (ulv->supported) {
3564 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3567 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3570 ret = ci_populate_all_graphic_levels(rdev);
3574 ret = ci_populate_all_memory_levels(rdev);
3578 ci_populate_smc_link_level(rdev, table);
3580 ret = ci_populate_smc_acpi_level(rdev, table);
3584 ret = ci_populate_smc_vce_level(rdev, table);
3588 ret = ci_populate_smc_acp_level(rdev, table);
3592 ret = ci_populate_smc_samu_level(rdev, table);
3596 ret = ci_do_program_memory_timing_parameters(rdev);
3600 ret = ci_populate_smc_uvd_level(rdev, table);
3604 table->UvdBootLevel = 0;
3605 table->VceBootLevel = 0;
3606 table->AcpBootLevel = 0;
3607 table->SamuBootLevel = 0;
3608 table->GraphicsBootLevel = 0;
3609 table->MemoryBootLevel = 0;
3611 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3612 pi->vbios_boot_state.sclk_bootup_value,
3613 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3615 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3616 pi->vbios_boot_state.mclk_bootup_value,
3617 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3619 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3620 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3621 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3623 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3625 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3629 table->UVDInterval = 1;
3630 table->VCEInterval = 1;
3631 table->ACPInterval = 1;
3632 table->SAMUInterval = 1;
3633 table->GraphicsVoltageChangeEnable = 1;
3634 table->GraphicsThermThrottleEnable = 1;
3635 table->GraphicsInterval = 1;
3636 table->VoltageInterval = 1;
3637 table->ThermalInterval = 1;
3638 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3639 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3640 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3641 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3642 table->MemoryVoltageChangeEnable = 1;
3643 table->MemoryInterval = 1;
3644 table->VoltageResponseTime = 0;
3645 table->VddcVddciDelta = 4000;
3646 table->PhaseResponseTime = 0;
3647 table->MemoryThermThrottleEnable = 1;
3648 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3649 table->PCIeGenInterval = 1;
3650 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3651 table->SVI2Enable = 1;
3653 table->SVI2Enable = 0;
3655 table->ThermGpio = 17;
3656 table->SclkStepSize = 0x4000;
3658 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3659 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3660 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3661 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3662 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3663 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3664 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3665 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3666 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3667 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3668 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3669 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3670 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3671 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3673 ret = ci_copy_bytes_to_smc(rdev,
3674 pi->dpm_table_start +
3675 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3676 (u8 *)&table->SystemFlags,
3677 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3685 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3686 struct ci_single_dpm_table *dpm_table,
3687 u32 low_limit, u32 high_limit)
3691 for (i = 0; i < dpm_table->count; i++) {
3692 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3693 (dpm_table->dpm_levels[i].value > high_limit))
3694 dpm_table->dpm_levels[i].enabled = false;
3696 dpm_table->dpm_levels[i].enabled = true;
3700 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3701 u32 speed_low, u32 lanes_low,
3702 u32 speed_high, u32 lanes_high)
3704 struct ci_power_info *pi = ci_get_pi(rdev);
3705 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3708 for (i = 0; i < pcie_table->count; i++) {
3709 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3710 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3711 (pcie_table->dpm_levels[i].value > speed_high) ||
3712 (pcie_table->dpm_levels[i].param1 > lanes_high))
3713 pcie_table->dpm_levels[i].enabled = false;
3715 pcie_table->dpm_levels[i].enabled = true;
3718 for (i = 0; i < pcie_table->count; i++) {
3719 if (pcie_table->dpm_levels[i].enabled) {
3720 for (j = i + 1; j < pcie_table->count; j++) {
3721 if (pcie_table->dpm_levels[j].enabled) {
3722 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3723 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3724 pcie_table->dpm_levels[j].enabled = false;
3731 static int ci_trim_dpm_states(struct radeon_device *rdev,
3732 struct radeon_ps *radeon_state)
3734 struct ci_ps *state = ci_get_ps(radeon_state);
3735 struct ci_power_info *pi = ci_get_pi(rdev);
3736 u32 high_limit_count;
3738 if (state->performance_level_count < 1)
3741 if (state->performance_level_count == 1)
3742 high_limit_count = 0;
3744 high_limit_count = 1;
3746 ci_trim_single_dpm_states(rdev,
3747 &pi->dpm_table.sclk_table,
3748 state->performance_levels[0].sclk,
3749 state->performance_levels[high_limit_count].sclk);
3751 ci_trim_single_dpm_states(rdev,
3752 &pi->dpm_table.mclk_table,
3753 state->performance_levels[0].mclk,
3754 state->performance_levels[high_limit_count].mclk);
3756 ci_trim_pcie_dpm_states(rdev,
3757 state->performance_levels[0].pcie_gen,
3758 state->performance_levels[0].pcie_lane,
3759 state->performance_levels[high_limit_count].pcie_gen,
3760 state->performance_levels[high_limit_count].pcie_lane);
3765 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3767 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3768 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3769 struct radeon_clock_voltage_dependency_table *vddc_table =
3770 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3771 u32 requested_voltage = 0;
3774 if (disp_voltage_table == NULL)
3776 if (!disp_voltage_table->count)
3779 for (i = 0; i < disp_voltage_table->count; i++) {
3780 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3781 requested_voltage = disp_voltage_table->entries[i].v;
3784 for (i = 0; i < vddc_table->count; i++) {
3785 if (requested_voltage <= vddc_table->entries[i].v) {
3786 requested_voltage = vddc_table->entries[i].v;
3787 return (ci_send_msg_to_smc_with_parameter(rdev,
3788 PPSMC_MSG_VddC_Request,
3789 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3797 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3799 struct ci_power_info *pi = ci_get_pi(rdev);
3800 PPSMC_Result result;
3802 ci_apply_disp_minimum_voltage_request(rdev);
3804 if (!pi->sclk_dpm_key_disabled) {
3805 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3806 result = ci_send_msg_to_smc_with_parameter(rdev,
3807 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3808 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3809 if (result != PPSMC_Result_OK)
3814 if (!pi->mclk_dpm_key_disabled) {
3815 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3816 result = ci_send_msg_to_smc_with_parameter(rdev,
3817 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3818 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3819 if (result != PPSMC_Result_OK)
3824 if (!pi->pcie_dpm_key_disabled) {
3825 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3826 result = ci_send_msg_to_smc_with_parameter(rdev,
3827 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3828 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3829 if (result != PPSMC_Result_OK)
3837 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3838 struct radeon_ps *radeon_state)
3840 struct ci_power_info *pi = ci_get_pi(rdev);
3841 struct ci_ps *state = ci_get_ps(radeon_state);
3842 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3843 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3844 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3845 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3848 pi->need_update_smu7_dpm_table = 0;
3850 for (i = 0; i < sclk_table->count; i++) {
3851 if (sclk == sclk_table->dpm_levels[i].value)
3855 if (i >= sclk_table->count) {
3856 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3858 /* XXX check display min clock requirements */
3859 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3860 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3863 for (i = 0; i < mclk_table->count; i++) {
3864 if (mclk == mclk_table->dpm_levels[i].value)
3868 if (i >= mclk_table->count)
3869 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3871 if (rdev->pm.dpm.current_active_crtc_count !=
3872 rdev->pm.dpm.new_active_crtc_count)
3873 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3876 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3877 struct radeon_ps *radeon_state)
3879 struct ci_power_info *pi = ci_get_pi(rdev);
3880 struct ci_ps *state = ci_get_ps(radeon_state);
3881 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3882 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3883 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3886 if (!pi->need_update_smu7_dpm_table)
3889 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3890 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3892 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3893 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3895 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3896 ret = ci_populate_all_graphic_levels(rdev);
3901 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3902 ret = ci_populate_all_memory_levels(rdev);
3910 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3912 struct ci_power_info *pi = ci_get_pi(rdev);
3913 const struct radeon_clock_and_voltage_limits *max_limits;
3916 if (rdev->pm.dpm.ac_power)
3917 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3919 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3922 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3924 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3925 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3926 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3928 if (!pi->caps_uvd_dpm)
3933 ci_send_msg_to_smc_with_parameter(rdev,
3934 PPSMC_MSG_UVDDPM_SetEnabledMask,
3935 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3937 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3938 pi->uvd_enabled = true;
3939 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3940 ci_send_msg_to_smc_with_parameter(rdev,
3941 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3942 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3945 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3946 pi->uvd_enabled = false;
3947 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3948 ci_send_msg_to_smc_with_parameter(rdev,
3949 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3950 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3954 return (ci_send_msg_to_smc(rdev, enable ?
3955 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3959 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3961 struct ci_power_info *pi = ci_get_pi(rdev);
3962 const struct radeon_clock_and_voltage_limits *max_limits;
3965 if (rdev->pm.dpm.ac_power)
3966 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3968 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3971 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3972 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3973 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3974 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3976 if (!pi->caps_vce_dpm)
3981 ci_send_msg_to_smc_with_parameter(rdev,
3982 PPSMC_MSG_VCEDPM_SetEnabledMask,
3983 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3986 return (ci_send_msg_to_smc(rdev, enable ?
3987 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3992 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3994 struct ci_power_info *pi = ci_get_pi(rdev);
3995 const struct radeon_clock_and_voltage_limits *max_limits;
3998 if (rdev->pm.dpm.ac_power)
3999 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4001 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4004 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4005 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4006 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4007 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4009 if (!pi->caps_samu_dpm)
4014 ci_send_msg_to_smc_with_parameter(rdev,
4015 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4016 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4018 return (ci_send_msg_to_smc(rdev, enable ?
4019 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4023 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4025 struct ci_power_info *pi = ci_get_pi(rdev);
4026 const struct radeon_clock_and_voltage_limits *max_limits;
4029 if (rdev->pm.dpm.ac_power)
4030 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4032 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4035 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4036 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4037 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4038 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4040 if (!pi->caps_acp_dpm)
4045 ci_send_msg_to_smc_with_parameter(rdev,
4046 PPSMC_MSG_ACPDPM_SetEnabledMask,
4047 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4050 return (ci_send_msg_to_smc(rdev, enable ?
4051 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4056 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4058 struct ci_power_info *pi = ci_get_pi(rdev);
4062 if (pi->caps_uvd_dpm ||
4063 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4064 pi->smc_state_table.UvdBootLevel = 0;
4066 pi->smc_state_table.UvdBootLevel =
4067 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4069 tmp = RREG32_SMC(DPM_TABLE_475);
4070 tmp &= ~UvdBootLevel_MASK;
4071 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4072 WREG32_SMC(DPM_TABLE_475, tmp);
4075 return ci_enable_uvd_dpm(rdev, !gate);
4078 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4081 u32 min_evclk = 30000; /* ??? */
4082 struct radeon_vce_clock_voltage_dependency_table *table =
4083 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4085 for (i = 0; i < table->count; i++) {
4086 if (table->entries[i].evclk >= min_evclk)
4090 return table->count - 1;
4093 static int ci_update_vce_dpm(struct radeon_device *rdev,
4094 struct radeon_ps *radeon_new_state,
4095 struct radeon_ps *radeon_current_state)
4097 struct ci_power_info *pi = ci_get_pi(rdev);
4101 if (radeon_current_state->evclk != radeon_new_state->evclk) {
4102 if (radeon_new_state->evclk) {
4103 /* turn the clocks on when encoding */
4104 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4106 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4107 tmp = RREG32_SMC(DPM_TABLE_475);
4108 tmp &= ~VceBootLevel_MASK;
4109 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4110 WREG32_SMC(DPM_TABLE_475, tmp);
4112 ret = ci_enable_vce_dpm(rdev, true);
4114 /* turn the clocks off when not encoding */
4115 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4117 ret = ci_enable_vce_dpm(rdev, false);
4124 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4126 return ci_enable_samu_dpm(rdev, gate);
4129 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4131 struct ci_power_info *pi = ci_get_pi(rdev);
4135 pi->smc_state_table.AcpBootLevel = 0;
4137 tmp = RREG32_SMC(DPM_TABLE_475);
4138 tmp &= ~AcpBootLevel_MASK;
4139 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4140 WREG32_SMC(DPM_TABLE_475, tmp);
4143 return ci_enable_acp_dpm(rdev, !gate);
4147 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4148 struct radeon_ps *radeon_state)
4150 struct ci_power_info *pi = ci_get_pi(rdev);
4153 ret = ci_trim_dpm_states(rdev, radeon_state);
4157 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4158 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4159 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4160 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4161 pi->last_mclk_dpm_enable_mask =
4162 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4163 if (pi->uvd_enabled) {
4164 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4165 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4167 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4168 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4173 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4178 while ((level_mask & (1 << level)) == 0)
4185 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4186 enum radeon_dpm_forced_level level)
4188 struct ci_power_info *pi = ci_get_pi(rdev);
4192 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4193 if ((!pi->pcie_dpm_key_disabled) &&
4194 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4196 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4200 ret = ci_dpm_force_state_pcie(rdev, level);
4203 for (i = 0; i < rdev->usec_timeout; i++) {
4204 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4205 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4212 if ((!pi->sclk_dpm_key_disabled) &&
4213 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4215 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4219 ret = ci_dpm_force_state_sclk(rdev, levels);
4222 for (i = 0; i < rdev->usec_timeout; i++) {
4223 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4224 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4231 if ((!pi->mclk_dpm_key_disabled) &&
4232 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4234 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4238 ret = ci_dpm_force_state_mclk(rdev, levels);
4241 for (i = 0; i < rdev->usec_timeout; i++) {
4242 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4243 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4250 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4251 if ((!pi->sclk_dpm_key_disabled) &&
4252 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4253 levels = ci_get_lowest_enabled_level(rdev,
4254 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4255 ret = ci_dpm_force_state_sclk(rdev, levels);
4258 for (i = 0; i < rdev->usec_timeout; i++) {
4259 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4260 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4266 if ((!pi->mclk_dpm_key_disabled) &&
4267 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4268 levels = ci_get_lowest_enabled_level(rdev,
4269 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4270 ret = ci_dpm_force_state_mclk(rdev, levels);
4273 for (i = 0; i < rdev->usec_timeout; i++) {
4274 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4275 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4281 if ((!pi->pcie_dpm_key_disabled) &&
4282 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4283 levels = ci_get_lowest_enabled_level(rdev,
4284 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4285 ret = ci_dpm_force_state_pcie(rdev, levels);
4288 for (i = 0; i < rdev->usec_timeout; i++) {
4289 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4290 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4296 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4297 if (!pi->pcie_dpm_key_disabled) {
4298 PPSMC_Result smc_result;
4300 smc_result = ci_send_msg_to_smc(rdev,
4301 PPSMC_MSG_PCIeDPM_UnForceLevel);
4302 if (smc_result != PPSMC_Result_OK)
4305 ret = ci_upload_dpm_level_enable_mask(rdev);
4310 rdev->pm.dpm.forced_level = level;
4315 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4316 struct ci_mc_reg_table *table)
4318 struct ci_power_info *pi = ci_get_pi(rdev);
4322 for (i = 0, j = table->last; i < table->last; i++) {
4323 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4325 switch(table->mc_reg_address[i].s1 << 2) {
4327 temp_reg = RREG32(MC_PMG_CMD_EMRS);
4328 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4329 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4330 for (k = 0; k < table->num_entries; k++) {
4331 table->mc_reg_table_entry[k].mc_data[j] =
4332 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4335 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4338 temp_reg = RREG32(MC_PMG_CMD_MRS);
4339 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4340 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4341 for (k = 0; k < table->num_entries; k++) {
4342 table->mc_reg_table_entry[k].mc_data[j] =
4343 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4345 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4348 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4351 if (!pi->mem_gddr5) {
4352 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4353 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4354 for (k = 0; k < table->num_entries; k++) {
4355 table->mc_reg_table_entry[k].mc_data[j] =
4356 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4359 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4363 case MC_SEQ_RESERVE_M:
4364 temp_reg = RREG32(MC_PMG_CMD_MRS1);
4365 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4366 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4367 for (k = 0; k < table->num_entries; k++) {
4368 table->mc_reg_table_entry[k].mc_data[j] =
4369 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4372 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4386 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4391 case MC_SEQ_RAS_TIMING >> 2:
4392 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4394 case MC_SEQ_DLL_STBY >> 2:
4395 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4397 case MC_SEQ_G5PDX_CMD0 >> 2:
4398 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4400 case MC_SEQ_G5PDX_CMD1 >> 2:
4401 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4403 case MC_SEQ_G5PDX_CTRL >> 2:
4404 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4406 case MC_SEQ_CAS_TIMING >> 2:
4407 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4409 case MC_SEQ_MISC_TIMING >> 2:
4410 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4412 case MC_SEQ_MISC_TIMING2 >> 2:
4413 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4415 case MC_SEQ_PMG_DVS_CMD >> 2:
4416 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4418 case MC_SEQ_PMG_DVS_CTL >> 2:
4419 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4421 case MC_SEQ_RD_CTL_D0 >> 2:
4422 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4424 case MC_SEQ_RD_CTL_D1 >> 2:
4425 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4427 case MC_SEQ_WR_CTL_D0 >> 2:
4428 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4430 case MC_SEQ_WR_CTL_D1 >> 2:
4431 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4433 case MC_PMG_CMD_EMRS >> 2:
4434 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4436 case MC_PMG_CMD_MRS >> 2:
4437 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4439 case MC_PMG_CMD_MRS1 >> 2:
4440 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4442 case MC_SEQ_PMG_TIMING >> 2:
4443 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4445 case MC_PMG_CMD_MRS2 >> 2:
4446 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4448 case MC_SEQ_WR_CTL_2 >> 2:
4449 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4459 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4463 for (i = 0; i < table->last; i++) {
4464 for (j = 1; j < table->num_entries; j++) {
4465 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4466 table->mc_reg_table_entry[j].mc_data[i]) {
4467 table->valid_flag |= 1 << i;
4474 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4479 for (i = 0; i < table->last; i++) {
4480 table->mc_reg_address[i].s0 =
4481 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4482 address : table->mc_reg_address[i].s1;
4486 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4487 struct ci_mc_reg_table *ci_table)
4491 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4493 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4496 for (i = 0; i < table->last; i++)
4497 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4499 ci_table->last = table->last;
4501 for (i = 0; i < table->num_entries; i++) {
4502 ci_table->mc_reg_table_entry[i].mclk_max =
4503 table->mc_reg_table_entry[i].mclk_max;
4504 for (j = 0; j < table->last; j++)
4505 ci_table->mc_reg_table_entry[i].mc_data[j] =
4506 table->mc_reg_table_entry[i].mc_data[j];
4508 ci_table->num_entries = table->num_entries;
4513 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4514 struct ci_mc_reg_table *table)
4520 tmp = RREG32(MC_SEQ_MISC0);
4521 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4524 ((rdev->pdev->device == 0x67B0) ||
4525 (rdev->pdev->device == 0x67B1))) {
4526 for (i = 0; i < table->last; i++) {
4527 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4529 switch(table->mc_reg_address[i].s1 >> 2) {
4531 for (k = 0; k < table->num_entries; k++) {
4532 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4533 (table->mc_reg_table_entry[k].mclk_max == 137500))
4534 table->mc_reg_table_entry[k].mc_data[i] =
4535 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4539 case MC_SEQ_WR_CTL_D0:
4540 for (k = 0; k < table->num_entries; k++) {
4541 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4542 (table->mc_reg_table_entry[k].mclk_max == 137500))
4543 table->mc_reg_table_entry[k].mc_data[i] =
4544 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4548 case MC_SEQ_WR_CTL_D1:
4549 for (k = 0; k < table->num_entries; k++) {
4550 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4551 (table->mc_reg_table_entry[k].mclk_max == 137500))
4552 table->mc_reg_table_entry[k].mc_data[i] =
4553 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4557 case MC_SEQ_WR_CTL_2:
4558 for (k = 0; k < table->num_entries; k++) {
4559 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4560 (table->mc_reg_table_entry[k].mclk_max == 137500))
4561 table->mc_reg_table_entry[k].mc_data[i] = 0;
4564 case MC_SEQ_CAS_TIMING:
4565 for (k = 0; k < table->num_entries; k++) {
4566 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4567 table->mc_reg_table_entry[k].mc_data[i] =
4568 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4570 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4571 table->mc_reg_table_entry[k].mc_data[i] =
4572 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4576 case MC_SEQ_MISC_TIMING:
4577 for (k = 0; k < table->num_entries; k++) {
4578 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4579 table->mc_reg_table_entry[k].mc_data[i] =
4580 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4582 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4583 table->mc_reg_table_entry[k].mc_data[i] =
4584 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4593 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4594 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4595 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4596 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4597 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4603 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4605 struct ci_power_info *pi = ci_get_pi(rdev);
4606 struct atom_mc_reg_table *table;
4607 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4608 u8 module_index = rv770_get_memory_module_index(rdev);
4611 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4615 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4616 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4617 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4618 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4619 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4620 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4621 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4622 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4623 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4624 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4625 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4626 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4627 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4628 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4629 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4630 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4631 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4632 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4633 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4634 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4636 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4640 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4644 ci_set_s0_mc_reg_index(ci_table);
4646 ret = ci_register_patching_mc_seq(rdev, ci_table);
4650 ret = ci_set_mc_special_registers(rdev, ci_table);
4654 ci_set_valid_flag(ci_table);
4662 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4663 SMU7_Discrete_MCRegisters *mc_reg_table)
4665 struct ci_power_info *pi = ci_get_pi(rdev);
4668 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4669 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4670 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4672 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4673 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4678 mc_reg_table->last = (u8)i;
4683 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4684 SMU7_Discrete_MCRegisterSet *data,
4685 u32 num_entries, u32 valid_flag)
4689 for (i = 0, j = 0; j < num_entries; j++) {
4690 if (valid_flag & (1 << j)) {
4691 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4697 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4698 const u32 memory_clock,
4699 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4701 struct ci_power_info *pi = ci_get_pi(rdev);
4704 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4705 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4709 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4712 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4713 mc_reg_table_data, pi->mc_reg_table.last,
4714 pi->mc_reg_table.valid_flag);
4717 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4718 SMU7_Discrete_MCRegisters *mc_reg_table)
4720 struct ci_power_info *pi = ci_get_pi(rdev);
4723 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4724 ci_convert_mc_reg_table_entry_to_smc(rdev,
4725 pi->dpm_table.mclk_table.dpm_levels[i].value,
4726 &mc_reg_table->data[i]);
4729 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4731 struct ci_power_info *pi = ci_get_pi(rdev);
4734 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4736 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4739 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4741 return ci_copy_bytes_to_smc(rdev,
4742 pi->mc_reg_table_start,
4743 (u8 *)&pi->smc_mc_reg_table,
4744 sizeof(SMU7_Discrete_MCRegisters),
4748 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4750 struct ci_power_info *pi = ci_get_pi(rdev);
4752 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4755 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4757 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4759 return ci_copy_bytes_to_smc(rdev,
4760 pi->mc_reg_table_start +
4761 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4762 (u8 *)&pi->smc_mc_reg_table.data[0],
4763 sizeof(SMU7_Discrete_MCRegisterSet) *
4764 pi->dpm_table.mclk_table.count,
4768 static void ci_enable_voltage_control(struct radeon_device *rdev)
4770 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4772 tmp |= VOLT_PWRMGT_EN;
4773 WREG32_SMC(GENERAL_PWRMGT, tmp);
4776 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4777 struct radeon_ps *radeon_state)
4779 struct ci_ps *state = ci_get_ps(radeon_state);
4781 u16 pcie_speed, max_speed = 0;
4783 for (i = 0; i < state->performance_level_count; i++) {
4784 pcie_speed = state->performance_levels[i].pcie_gen;
4785 if (max_speed < pcie_speed)
4786 max_speed = pcie_speed;
4792 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4796 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4797 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4799 return (u16)speed_cntl;
4802 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4806 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4807 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4809 switch (link_width) {
4810 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4812 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4814 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4816 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4818 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4819 /* not actually supported */
4821 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4822 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4828 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4829 struct radeon_ps *radeon_new_state,
4830 struct radeon_ps *radeon_current_state)
4832 struct ci_power_info *pi = ci_get_pi(rdev);
4833 enum radeon_pcie_gen target_link_speed =
4834 ci_get_maximum_link_speed(rdev, radeon_new_state);
4835 enum radeon_pcie_gen current_link_speed;
4837 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4838 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4840 current_link_speed = pi->force_pcie_gen;
4842 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4843 pi->pspp_notify_required = false;
4844 if (target_link_speed > current_link_speed) {
4845 switch (target_link_speed) {
4847 case RADEON_PCIE_GEN3:
4848 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4850 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4851 if (current_link_speed == RADEON_PCIE_GEN2)
4853 case RADEON_PCIE_GEN2:
4854 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4858 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4862 if (target_link_speed < current_link_speed)
4863 pi->pspp_notify_required = true;
4867 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4868 struct radeon_ps *radeon_new_state,
4869 struct radeon_ps *radeon_current_state)
4871 struct ci_power_info *pi = ci_get_pi(rdev);
4872 enum radeon_pcie_gen target_link_speed =
4873 ci_get_maximum_link_speed(rdev, radeon_new_state);
4876 if (pi->pspp_notify_required) {
4877 if (target_link_speed == RADEON_PCIE_GEN3)
4878 request = PCIE_PERF_REQ_PECI_GEN3;
4879 else if (target_link_speed == RADEON_PCIE_GEN2)
4880 request = PCIE_PERF_REQ_PECI_GEN2;
4882 request = PCIE_PERF_REQ_PECI_GEN1;
4884 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4885 (ci_get_current_pcie_speed(rdev) > 0))
4889 radeon_acpi_pcie_performance_request(rdev, request, false);
4894 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4896 struct ci_power_info *pi = ci_get_pi(rdev);
4897 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4898 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4899 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4900 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4901 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4902 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4904 if (allowed_sclk_vddc_table == NULL)
4906 if (allowed_sclk_vddc_table->count < 1)
4908 if (allowed_mclk_vddc_table == NULL)
4910 if (allowed_mclk_vddc_table->count < 1)
4912 if (allowed_mclk_vddci_table == NULL)
4914 if (allowed_mclk_vddci_table->count < 1)
4917 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4918 pi->max_vddc_in_pp_table =
4919 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4921 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4922 pi->max_vddci_in_pp_table =
4923 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4925 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4926 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4927 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4928 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4929 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4930 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4931 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4932 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4937 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4939 struct ci_power_info *pi = ci_get_pi(rdev);
4940 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4943 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4944 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4945 *vddc = leakage_table->actual_voltage[leakage_index];
4951 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4953 struct ci_power_info *pi = ci_get_pi(rdev);
4954 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4957 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4958 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4959 *vddci = leakage_table->actual_voltage[leakage_index];
4965 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4966 struct radeon_clock_voltage_dependency_table *table)
4971 for (i = 0; i < table->count; i++)
4972 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4976 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4977 struct radeon_clock_voltage_dependency_table *table)
4982 for (i = 0; i < table->count; i++)
4983 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4987 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4988 struct radeon_vce_clock_voltage_dependency_table *table)
4993 for (i = 0; i < table->count; i++)
4994 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4998 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4999 struct radeon_uvd_clock_voltage_dependency_table *table)
5004 for (i = 0; i < table->count; i++)
5005 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5009 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5010 struct radeon_phase_shedding_limits_table *table)
5015 for (i = 0; i < table->count; i++)
5016 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5020 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5021 struct radeon_clock_and_voltage_limits *table)
5024 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5025 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5029 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5030 struct radeon_cac_leakage_table *table)
5035 for (i = 0; i < table->count; i++)
5036 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5040 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5043 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5044 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5045 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5046 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5047 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5048 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5049 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5050 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5051 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5052 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5053 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5054 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5055 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5056 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5057 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5058 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5059 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5060 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5061 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5062 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5063 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5064 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5065 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5066 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5070 static void ci_get_memory_type(struct radeon_device *rdev)
5072 struct ci_power_info *pi = ci_get_pi(rdev);
5075 tmp = RREG32(MC_SEQ_MISC0);
5077 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5078 MC_SEQ_MISC0_GDDR5_VALUE)
5079 pi->mem_gddr5 = true;
5081 pi->mem_gddr5 = false;
5085 static void ci_update_current_ps(struct radeon_device *rdev,
5086 struct radeon_ps *rps)
5088 struct ci_ps *new_ps = ci_get_ps(rps);
5089 struct ci_power_info *pi = ci_get_pi(rdev);
5091 pi->current_rps = *rps;
5092 pi->current_ps = *new_ps;
5093 pi->current_rps.ps_priv = &pi->current_ps;
5096 static void ci_update_requested_ps(struct radeon_device *rdev,
5097 struct radeon_ps *rps)
5099 struct ci_ps *new_ps = ci_get_ps(rps);
5100 struct ci_power_info *pi = ci_get_pi(rdev);
5102 pi->requested_rps = *rps;
5103 pi->requested_ps = *new_ps;
5104 pi->requested_rps.ps_priv = &pi->requested_ps;
5107 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5109 struct ci_power_info *pi = ci_get_pi(rdev);
5110 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5111 struct radeon_ps *new_ps = &requested_ps;
5113 ci_update_requested_ps(rdev, new_ps);
5115 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5120 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5122 struct ci_power_info *pi = ci_get_pi(rdev);
5123 struct radeon_ps *new_ps = &pi->requested_rps;
5125 ci_update_current_ps(rdev, new_ps);
5129 void ci_dpm_setup_asic(struct radeon_device *rdev)
5133 r = ci_mc_load_microcode(rdev);
5135 DRM_ERROR("Failed to load MC firmware!\n");
5136 ci_read_clock_registers(rdev);
5137 ci_get_memory_type(rdev);
5138 ci_enable_acpi_power_management(rdev);
5139 ci_init_sclk_t(rdev);
5142 int ci_dpm_enable(struct radeon_device *rdev)
5144 struct ci_power_info *pi = ci_get_pi(rdev);
5145 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5148 if (ci_is_smc_running(rdev))
5150 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5151 ci_enable_voltage_control(rdev);
5152 ret = ci_construct_voltage_tables(rdev);
5154 DRM_ERROR("ci_construct_voltage_tables failed\n");
5158 if (pi->caps_dynamic_ac_timing) {
5159 ret = ci_initialize_mc_reg_table(rdev);
5161 pi->caps_dynamic_ac_timing = false;
5164 ci_enable_spread_spectrum(rdev, true);
5165 if (pi->thermal_protection)
5166 ci_enable_thermal_protection(rdev, true);
5167 ci_program_sstp(rdev);
5168 ci_enable_display_gap(rdev);
5169 ci_program_vc(rdev);
5170 ret = ci_upload_firmware(rdev);
5172 DRM_ERROR("ci_upload_firmware failed\n");
5175 ret = ci_process_firmware_header(rdev);
5177 DRM_ERROR("ci_process_firmware_header failed\n");
5180 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5182 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5185 ret = ci_init_smc_table(rdev);
5187 DRM_ERROR("ci_init_smc_table failed\n");
5190 ret = ci_init_arb_table_index(rdev);
5192 DRM_ERROR("ci_init_arb_table_index failed\n");
5195 if (pi->caps_dynamic_ac_timing) {
5196 ret = ci_populate_initial_mc_reg_table(rdev);
5198 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5202 ret = ci_populate_pm_base(rdev);
5204 DRM_ERROR("ci_populate_pm_base failed\n");
5207 ci_dpm_start_smc(rdev);
5208 ci_enable_vr_hot_gpio_interrupt(rdev);
5209 ret = ci_notify_smc_display_change(rdev, false);
5211 DRM_ERROR("ci_notify_smc_display_change failed\n");
5214 ci_enable_sclk_control(rdev, true);
5215 ret = ci_enable_ulv(rdev, true);
5217 DRM_ERROR("ci_enable_ulv failed\n");
5220 ret = ci_enable_ds_master_switch(rdev, true);
5222 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5225 ret = ci_start_dpm(rdev);
5227 DRM_ERROR("ci_start_dpm failed\n");
5230 ret = ci_enable_didt(rdev, true);
5232 DRM_ERROR("ci_enable_didt failed\n");
5235 ret = ci_enable_smc_cac(rdev, true);
5237 DRM_ERROR("ci_enable_smc_cac failed\n");
5240 ret = ci_enable_power_containment(rdev, true);
5242 DRM_ERROR("ci_enable_power_containment failed\n");
5246 ret = ci_power_control_set_level(rdev);
5248 DRM_ERROR("ci_power_control_set_level failed\n");
5252 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5254 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5256 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5260 ci_thermal_start_thermal_controller(rdev);
5262 ci_update_current_ps(rdev, boot_ps);
5267 static int ci_set_temperature_range(struct radeon_device *rdev)
5271 ret = ci_thermal_enable_alert(rdev, false);
5274 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5277 ret = ci_thermal_enable_alert(rdev, true);
5284 int ci_dpm_late_enable(struct radeon_device *rdev)
5288 ret = ci_set_temperature_range(rdev);
5292 ci_dpm_powergate_uvd(rdev, true);
5297 void ci_dpm_disable(struct radeon_device *rdev)
5299 struct ci_power_info *pi = ci_get_pi(rdev);
5300 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5302 ci_dpm_powergate_uvd(rdev, false);
5304 if (!ci_is_smc_running(rdev))
5307 ci_thermal_stop_thermal_controller(rdev);
5309 if (pi->thermal_protection)
5310 ci_enable_thermal_protection(rdev, false);
5311 ci_enable_power_containment(rdev, false);
5312 ci_enable_smc_cac(rdev, false);
5313 ci_enable_didt(rdev, false);
5314 ci_enable_spread_spectrum(rdev, false);
5315 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5317 ci_enable_ds_master_switch(rdev, false);
5318 ci_enable_ulv(rdev, false);
5320 ci_reset_to_default(rdev);
5321 ci_dpm_stop_smc(rdev);
5322 ci_force_switch_to_arb_f0(rdev);
5323 ci_enable_thermal_based_sclk_dpm(rdev, false);
5325 ci_update_current_ps(rdev, boot_ps);
5328 int ci_dpm_set_power_state(struct radeon_device *rdev)
5330 struct ci_power_info *pi = ci_get_pi(rdev);
5331 struct radeon_ps *new_ps = &pi->requested_rps;
5332 struct radeon_ps *old_ps = &pi->current_rps;
5335 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5336 if (pi->pcie_performance_request)
5337 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5338 ret = ci_freeze_sclk_mclk_dpm(rdev);
5340 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5343 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5345 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5348 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5350 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5354 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5356 DRM_ERROR("ci_update_vce_dpm failed\n");
5360 ret = ci_update_sclk_t(rdev);
5362 DRM_ERROR("ci_update_sclk_t failed\n");
5365 if (pi->caps_dynamic_ac_timing) {
5366 ret = ci_update_and_upload_mc_reg_table(rdev);
5368 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5372 ret = ci_program_memory_timing_parameters(rdev);
5374 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5377 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5379 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5382 ret = ci_upload_dpm_level_enable_mask(rdev);
5384 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5387 if (pi->pcie_performance_request)
5388 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5394 void ci_dpm_reset_asic(struct radeon_device *rdev)
5396 ci_set_boot_state(rdev);
5400 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5402 ci_program_display_gap(rdev);
5406 struct _ATOM_POWERPLAY_INFO info;
5407 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5408 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5409 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5410 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5411 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5414 union pplib_clock_info {
5415 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5416 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5417 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5418 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5419 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5420 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5423 union pplib_power_state {
5424 struct _ATOM_PPLIB_STATE v1;
5425 struct _ATOM_PPLIB_STATE_V2 v2;
5428 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5429 struct radeon_ps *rps,
5430 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5433 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5434 rps->class = le16_to_cpu(non_clock_info->usClassification);
5435 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5437 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5438 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5439 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5445 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5446 rdev->pm.dpm.boot_ps = rps;
5447 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5448 rdev->pm.dpm.uvd_ps = rps;
5451 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5452 struct radeon_ps *rps, int index,
5453 union pplib_clock_info *clock_info)
5455 struct ci_power_info *pi = ci_get_pi(rdev);
5456 struct ci_ps *ps = ci_get_ps(rps);
5457 struct ci_pl *pl = &ps->performance_levels[index];
5459 ps->performance_level_count = index + 1;
5461 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5462 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5463 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5464 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5466 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5468 pi->vbios_boot_state.pcie_gen_bootup_value,
5469 clock_info->ci.ucPCIEGen);
5470 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5471 pi->vbios_boot_state.pcie_lane_bootup_value,
5472 le16_to_cpu(clock_info->ci.usPCIELane));
5474 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5475 pi->acpi_pcie_gen = pl->pcie_gen;
5478 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5479 pi->ulv.supported = true;
5481 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5484 /* patch up boot state */
5485 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5486 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5487 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5488 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5489 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5492 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5493 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5494 pi->use_pcie_powersaving_levels = true;
5495 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5496 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5497 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5498 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5499 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5500 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5501 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5502 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5504 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5505 pi->use_pcie_performance_levels = true;
5506 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5507 pi->pcie_gen_performance.max = pl->pcie_gen;
5508 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5509 pi->pcie_gen_performance.min = pl->pcie_gen;
5510 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5511 pi->pcie_lane_performance.max = pl->pcie_lane;
5512 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5513 pi->pcie_lane_performance.min = pl->pcie_lane;
5520 static int ci_parse_power_table(struct radeon_device *rdev)
5522 struct radeon_mode_info *mode_info = &rdev->mode_info;
5523 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5524 union pplib_power_state *power_state;
5525 int i, j, k, non_clock_array_index, clock_array_index;
5526 union pplib_clock_info *clock_info;
5527 struct _StateArray *state_array;
5528 struct _ClockInfoArray *clock_info_array;
5529 struct _NonClockInfoArray *non_clock_info_array;
5530 union power_info *power_info;
5531 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5534 u8 *power_state_offset;
5537 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5538 &frev, &crev, &data_offset))
5540 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5542 state_array = (struct _StateArray *)
5543 (mode_info->atom_context->bios + data_offset +
5544 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5545 clock_info_array = (struct _ClockInfoArray *)
5546 (mode_info->atom_context->bios + data_offset +
5547 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5548 non_clock_info_array = (struct _NonClockInfoArray *)
5549 (mode_info->atom_context->bios + data_offset +
5550 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5552 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5553 state_array->ucNumEntries, GFP_KERNEL);
5554 if (!rdev->pm.dpm.ps)
5556 power_state_offset = (u8 *)state_array->states;
5557 rdev->pm.dpm.num_ps = 0;
5558 for (i = 0; i < state_array->ucNumEntries; i++) {
5560 power_state = (union pplib_power_state *)power_state_offset;
5561 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5562 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5563 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5564 if (!rdev->pm.power_state[i].clock_info)
5566 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5569 rdev->pm.dpm.ps[i].ps_priv = ps;
5570 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5572 non_clock_info_array->ucEntrySize);
5574 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5575 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5576 clock_array_index = idx[j];
5577 if (clock_array_index >= clock_info_array->ucNumEntries)
5579 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5581 clock_info = (union pplib_clock_info *)
5582 ((u8 *)&clock_info_array->clockInfo[0] +
5583 (clock_array_index * clock_info_array->ucEntrySize));
5584 ci_parse_pplib_clock_info(rdev,
5585 &rdev->pm.dpm.ps[i], k,
5589 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5590 rdev->pm.dpm.num_ps = i + 1;
5593 /* fill in the vce power states */
5594 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5596 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5597 clock_info = (union pplib_clock_info *)
5598 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5599 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5600 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5601 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5602 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5603 rdev->pm.dpm.vce_states[i].sclk = sclk;
5604 rdev->pm.dpm.vce_states[i].mclk = mclk;
5610 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5611 struct ci_vbios_boot_state *boot_state)
5613 struct radeon_mode_info *mode_info = &rdev->mode_info;
5614 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5615 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5619 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5620 &frev, &crev, &data_offset)) {
5622 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5624 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5625 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5626 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5627 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5628 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5629 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5630 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5637 void ci_dpm_fini(struct radeon_device *rdev)
5641 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5642 kfree(rdev->pm.dpm.ps[i].ps_priv);
5644 kfree(rdev->pm.dpm.ps);
5645 kfree(rdev->pm.dpm.priv);
5646 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5647 r600_free_extended_power_table(rdev);
5650 int ci_dpm_init(struct radeon_device *rdev)
5652 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5653 SMU7_Discrete_DpmTable *dpm_table;
5654 struct radeon_gpio_rec gpio;
5655 u16 data_offset, size;
5657 struct ci_power_info *pi;
5661 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5664 rdev->pm.dpm.priv = pi;
5666 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5668 pi->sys_pcie_mask = 0;
5670 pi->sys_pcie_mask = mask;
5671 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5673 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5674 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5675 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5676 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5678 pi->pcie_lane_performance.max = 0;
5679 pi->pcie_lane_performance.min = 16;
5680 pi->pcie_lane_powersaving.max = 0;
5681 pi->pcie_lane_powersaving.min = 16;
5683 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5689 ret = r600_get_platform_caps(rdev);
5695 ret = r600_parse_extended_power_table(rdev);
5701 ret = ci_parse_power_table(rdev);
5707 pi->dll_default_on = false;
5708 pi->sram_end = SMC_RAM_END;
5710 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5711 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5712 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5713 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5714 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5715 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5716 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5717 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5719 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5721 pi->sclk_dpm_key_disabled = 0;
5722 pi->mclk_dpm_key_disabled = 0;
5723 pi->pcie_dpm_key_disabled = 0;
5724 pi->thermal_sclk_dpm_enabled = 0;
5726 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5727 if ((rdev->pdev->device == 0x6658) &&
5728 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5729 pi->mclk_dpm_key_disabled = 1;
5732 pi->caps_sclk_ds = true;
5734 pi->mclk_strobe_mode_threshold = 40000;
5735 pi->mclk_stutter_mode_threshold = 40000;
5736 pi->mclk_edc_enable_threshold = 40000;
5737 pi->mclk_edc_wr_enable_threshold = 40000;
5739 ci_initialize_powertune_defaults(rdev);
5741 pi->caps_fps = false;
5743 pi->caps_sclk_throttle_low_notification = false;
5745 pi->caps_uvd_dpm = true;
5746 pi->caps_vce_dpm = true;
5748 ci_get_leakage_voltages(rdev);
5749 ci_patch_dependency_tables_with_leakage(rdev);
5750 ci_set_private_data_variables_based_on_pptable(rdev);
5752 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5753 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5754 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5758 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5759 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5760 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5761 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5762 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5763 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5764 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5765 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5766 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5768 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5769 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5770 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5772 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5773 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5774 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5775 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5777 if (rdev->family == CHIP_HAWAII) {
5778 pi->thermal_temp_setting.temperature_low = 94500;
5779 pi->thermal_temp_setting.temperature_high = 95000;
5780 pi->thermal_temp_setting.temperature_shutdown = 104000;
5782 pi->thermal_temp_setting.temperature_low = 99500;
5783 pi->thermal_temp_setting.temperature_high = 100000;
5784 pi->thermal_temp_setting.temperature_shutdown = 104000;
5787 pi->uvd_enabled = false;
5789 dpm_table = &pi->smc_state_table;
5791 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5793 dpm_table->VRHotGpio = gpio.shift;
5794 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5796 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5797 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5800 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5802 dpm_table->AcDcGpio = gpio.shift;
5803 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5805 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5806 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5809 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5811 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5813 switch (gpio.shift) {
5815 tmp &= ~GNB_SLOW_MODE_MASK;
5816 tmp |= GNB_SLOW_MODE(1);
5819 tmp &= ~GNB_SLOW_MODE_MASK;
5820 tmp |= GNB_SLOW_MODE(2);
5826 tmp |= FORCE_NB_PS1;
5832 DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift);
5835 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5838 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5839 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5840 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5841 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5842 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5843 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5844 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5846 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5847 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5848 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5849 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5850 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5852 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5855 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5856 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5857 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5858 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5859 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5861 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5864 pi->vddc_phase_shed_control = true;
5866 #if defined(CONFIG_ACPI)
5867 pi->pcie_performance_request =
5868 radeon_acpi_is_pcie_performance_request_supported(rdev);
5870 pi->pcie_performance_request = false;
5873 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5874 &frev, &crev, &data_offset)) {
5875 pi->caps_sclk_ss_support = true;
5876 pi->caps_mclk_ss_support = true;
5877 pi->dynamic_ss = true;
5879 pi->caps_sclk_ss_support = false;
5880 pi->caps_mclk_ss_support = false;
5881 pi->dynamic_ss = true;
5884 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5885 pi->thermal_protection = true;
5887 pi->thermal_protection = false;
5889 pi->caps_dynamic_ac_timing = true;
5891 pi->uvd_power_gated = false;
5893 /* make sure dc limits are valid */
5894 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5895 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5896 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5897 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5899 pi->fan_ctrl_is_in_default_mode = true;
5904 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5907 struct ci_power_info *pi = ci_get_pi(rdev);
5908 struct radeon_ps *rps = &pi->current_rps;
5909 u32 sclk = ci_get_average_sclk_freq(rdev);
5910 u32 mclk = ci_get_average_mclk_freq(rdev);
5912 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5913 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5914 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5918 void ci_dpm_print_power_state(struct radeon_device *rdev,
5919 struct radeon_ps *rps)
5921 struct ci_ps *ps = ci_get_ps(rps);
5925 r600_dpm_print_class_info(rps->class, rps->class2);
5926 r600_dpm_print_cap_info(rps->caps);
5927 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5928 for (i = 0; i < ps->performance_level_count; i++) {
5929 pl = &ps->performance_levels[i];
5930 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5931 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5933 r600_dpm_print_ps_status(rdev, rps);
5936 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5938 u32 sclk = ci_get_average_sclk_freq(rdev);
5943 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5945 u32 mclk = ci_get_average_mclk_freq(rdev);
5950 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5952 struct ci_power_info *pi = ci_get_pi(rdev);
5953 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5956 return requested_state->performance_levels[0].sclk;
5958 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5961 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5963 struct ci_power_info *pi = ci_get_pi(rdev);
5964 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5967 return requested_state->performance_levels[0].mclk;
5969 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;