drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "radeon_asic.h"
  28 #include "radeon_ucode.h"
  29 #include "cikd.h"
  30 #include "r600_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "atom.h"
  33 #include <linux/seq_file.h>
  34
  35 #define MC_CG_ARB_FREQ_F0           0x0a
  36 #define MC_CG_ARB_FREQ_F1           0x0b
  37 #define MC_CG_ARB_FREQ_F2           0x0c
  38 #define MC_CG_ARB_FREQ_F3           0x0d
  39
  40 #define SMC_RAM_END 0x40000
  41
  42 #define VOLTAGE_SCALE               4
  43 #define VOLTAGE_VID_OFFSET_SCALE1    625
  44 #define VOLTAGE_VID_OFFSET_SCALE2    100
  45
  46 static const struct ci_pt_defaults defaults_hawaii_xt =
  47 {
  48         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  49         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  50         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  51 };
  52
  53 static const struct ci_pt_defaults defaults_hawaii_pro =
  54 {
  55         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  56         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  57         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  58 };
  59
  60 static const struct ci_pt_defaults defaults_bonaire_xt =
  61 {
  62         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  63         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  64         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  65 };
  66
  67 static const struct ci_pt_defaults defaults_bonaire_pro =
  68 {
  69         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  70         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  71         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  72 };
  73
  74 static const struct ci_pt_defaults defaults_saturn_xt =
  75 {
  76         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  77         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  78         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  79 };
  80
  81 static const struct ci_pt_defaults defaults_saturn_pro =
  82 {
  83         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  84         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  85         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  86 };
  87
  88 static const struct ci_pt_config_reg didt_config_ci[] =
  89 {
  90         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0xFFFFFFFF }
 163 };
 164
 165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 167                                        u32 arb_freq_src, u32 arb_freq_dest);
 168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 171                                                      u32 max_voltage_steps,
 172                                                      struct atom_voltage_table *voltage_table);
 173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
 176 extern void cik_update_cg(struct radeon_device *rdev,
 177                           u32 block, bool enable);
 178
 179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 180                                          struct atom_voltage_table_entry *voltage_table,
 181                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 184                                        u32 target_tdp);
 185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 186
 187 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
 188                                                       PPSMC_Msg msg, u32 parameter);
 189
 190 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
 191 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
 192
 193 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 194 {
 195         struct ci_power_info *pi = rdev->pm.dpm.priv;
 196
 197         return pi;
 198 }
 199
 200 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 201 {
 202         struct ci_ps *ps = rps->ps_priv;
 203
 204         return ps;
 205 }
 206
 207 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 208 {
 209         struct ci_power_info *pi = ci_get_pi(rdev);
 210
 211         switch (rdev->pdev->device) {
 212         case 0x6649:
 213         case 0x6650:
 214         case 0x6651:
 215         case 0x6658:
 216         case 0x665C:
 217         case 0x665D:
 218         default:
 219                 pi->powertune_defaults = &defaults_bonaire_xt;
 220                 break;
 221         case 0x6640:
 222         case 0x6641:
 223         case 0x6646:
 224         case 0x6647:
 225                 pi->powertune_defaults = &defaults_saturn_xt;
 226                 break;
 227         case 0x67B8:
 228         case 0x67B0:
 229                 pi->powertune_defaults = &defaults_hawaii_xt;
 230                 break;
 231         case 0x67BA:
 232         case 0x67B1:
 233                 pi->powertune_defaults = &defaults_hawaii_pro;
 234                 break;
 235         case 0x67A0:
 236         case 0x67A1:
 237         case 0x67A2:
 238         case 0x67A8:
 239         case 0x67A9:
 240         case 0x67AA:
 241         case 0x67B9:
 242         case 0x67BE:
 243                 pi->powertune_defaults = &defaults_bonaire_xt;
 244                 break;
 245         }
 246
 247         pi->dte_tj_offset = 0;
 248
 249         pi->caps_power_containment = true;
 250         pi->caps_cac = false;
 251         pi->caps_sq_ramping = false;
 252         pi->caps_db_ramping = false;
 253         pi->caps_td_ramping = false;
 254         pi->caps_tcp_ramping = false;
 255
 256         if (pi->caps_power_containment) {
 257                 pi->caps_cac = true;
 258                 if (rdev->family == CHIP_HAWAII)
 259                         pi->enable_bapm_feature = false;
 260                 else
 261                         pi->enable_bapm_feature = true;
 262                 pi->enable_tdc_limit_feature = true;
 263                 pi->enable_pkg_pwr_tracking_feature = true;
 264         }
 265 }
 266
 267 static u8 ci_convert_to_vid(u16 vddc)
 268 {
 269         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 270 }
 271
 272 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 273 {
 274         struct ci_power_info *pi = ci_get_pi(rdev);
 275         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 276         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 277         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 278         u32 i;
 279
 280         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 281                 return -EINVAL;
 282         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 283                 return -EINVAL;
 284         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 285             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 286                 return -EINVAL;
 287
 288         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 289                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 290                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 291                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 292                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 293                 } else {
 294                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 295                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 296                 }
 297         }
 298         return 0;
 299 }
 300
 301 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 302 {
 303         struct ci_power_info *pi = ci_get_pi(rdev);
 304         u8 *vid = pi->smc_powertune_table.VddCVid;
 305         u32 i;
 306
 307         if (pi->vddc_voltage_table.count > 8)
 308                 return -EINVAL;
 309
 310         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 311                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 312
 313         return 0;
 314 }
 315
 316 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 317 {
 318         struct ci_power_info *pi = ci_get_pi(rdev);
 319         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 320
 321         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 322         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 323         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 324         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 325
 326         return 0;
 327 }
 328
 329 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 330 {
 331         struct ci_power_info *pi = ci_get_pi(rdev);
 332         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 333         u16 tdc_limit;
 334
 335         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 336         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 337         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 338                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 339         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 340
 341         return 0;
 342 }
 343
 344 static int ci_populate_dw8(struct radeon_device *rdev)
 345 {
 346         struct ci_power_info *pi = ci_get_pi(rdev);
 347         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 348         int ret;
 349
 350         ret = ci_read_smc_sram_dword(rdev,
 351                                      SMU7_FIRMWARE_HEADER_LOCATION +
 352                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 353                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 354                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 355                                      pi->sram_end);
 356         if (ret)
 357                 return -EINVAL;
 358         else
 359                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 360
 361         return 0;
 362 }
 363
 364 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
 365 {
 366         struct ci_power_info *pi = ci_get_pi(rdev);
 367
 368         if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
 369             (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
 370                 rdev->pm.dpm.fan.fan_output_sensitivity =
 371                         rdev->pm.dpm.fan.default_fan_output_sensitivity;
 372
 373         pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
 374                 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
 375
 376         return 0;
 377 }
 378
 379 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 380 {
 381         struct ci_power_info *pi = ci_get_pi(rdev);
 382         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 383         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 384         int i, min, max;
 385
 386         min = max = hi_vid[0];
 387         for (i = 0; i < 8; i++) {
 388                 if (0 != hi_vid[i]) {
 389                         if (min > hi_vid[i])
 390                                 min = hi_vid[i];
 391                         if (max < hi_vid[i])
 392                                 max = hi_vid[i];
 393                 }
 394
 395                 if (0 != lo_vid[i]) {
 396                         if (min > lo_vid[i])
 397                                 min = lo_vid[i];
 398                         if (max < lo_vid[i])
 399                                 max = lo_vid[i];
 400                 }
 401         }
 402
 403         if ((min == 0) || (max == 0))
 404                 return -EINVAL;
 405         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 406         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 407
 408         return 0;
 409 }
 410
 411 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 412 {
 413         struct ci_power_info *pi = ci_get_pi(rdev);
 414         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 415         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 416         struct radeon_cac_tdp_table *cac_tdp_table =
 417                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 418
 419         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 420         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 421
 422         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 423         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 424
 425         return 0;
 426 }
 427
 428 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 429 {
 430         struct ci_power_info *pi = ci_get_pi(rdev);
 431         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 432         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 433         struct radeon_cac_tdp_table *cac_tdp_table =
 434                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 435         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 436         int i, j, k;
 437         const u16 *def1;
 438         const u16 *def2;
 439
 440         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 441         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 442
 443         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 444         dpm_table->GpuTjMax =
 445                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 446         dpm_table->GpuTjHyst = 8;
 447
 448         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 449
 450         if (ppm) {
 451                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 452                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 453         } else {
 454                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 455                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 456         }
 457
 458         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 459         def1 = pt_defaults->bapmti_r;
 460         def2 = pt_defaults->bapmti_rc;
 461
 462         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 463                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 464                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 465                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 466                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 467                                 def1++;
 468                                 def2++;
 469                         }
 470                 }
 471         }
 472
 473         return 0;
 474 }
 475
 476 static int ci_populate_pm_base(struct radeon_device *rdev)
 477 {
 478         struct ci_power_info *pi = ci_get_pi(rdev);
 479         u32 pm_fuse_table_offset;
 480         int ret;
 481
 482         if (pi->caps_power_containment) {
 483                 ret = ci_read_smc_sram_dword(rdev,
 484                                              SMU7_FIRMWARE_HEADER_LOCATION +
 485                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 486                                              &pm_fuse_table_offset, pi->sram_end);
 487                 if (ret)
 488                         return ret;
 489                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 490                 if (ret)
 491                         return ret;
 492                 ret = ci_populate_vddc_vid(rdev);
 493                 if (ret)
 494                         return ret;
 495                 ret = ci_populate_svi_load_line(rdev);
 496                 if (ret)
 497                         return ret;
 498                 ret = ci_populate_tdc_limit(rdev);
 499                 if (ret)
 500                         return ret;
 501                 ret = ci_populate_dw8(rdev);
 502                 if (ret)
 503                         return ret;
 504                 ret = ci_populate_fuzzy_fan(rdev);
 505                 if (ret)
 506                         return ret;
 507                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 508                 if (ret)
 509                         return ret;
 510                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 511                 if (ret)
 512                         return ret;
 513                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 514                                            (u8 *)&pi->smc_powertune_table,
 515                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 516                 if (ret)
 517                         return ret;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 524 {
 525         struct ci_power_info *pi = ci_get_pi(rdev);
 526         u32 data;
 527
 528         if (pi->caps_sq_ramping) {
 529                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 530                 if (enable)
 531                         data |= DIDT_CTRL_EN;
 532                 else
 533                         data &= ~DIDT_CTRL_EN;
 534                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 535         }
 536
 537         if (pi->caps_db_ramping) {
 538                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 539                 if (enable)
 540                         data |= DIDT_CTRL_EN;
 541                 else
 542                         data &= ~DIDT_CTRL_EN;
 543                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 544         }
 545
 546         if (pi->caps_td_ramping) {
 547                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 548                 if (enable)
 549                         data |= DIDT_CTRL_EN;
 550                 else
 551                         data &= ~DIDT_CTRL_EN;
 552                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 553         }
 554
 555         if (pi->caps_tcp_ramping) {
 556                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 557                 if (enable)
 558                         data |= DIDT_CTRL_EN;
 559                 else
 560                         data &= ~DIDT_CTRL_EN;
 561                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 562         }
 563 }
 564
 565 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 566                                           const struct ci_pt_config_reg *cac_config_regs)
 567 {
 568         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 569         u32 data;
 570         u32 cache = 0;
 571
 572         if (config_regs == NULL)
 573                 return -EINVAL;
 574
 575         while (config_regs->offset != 0xFFFFFFFF) {
 576                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 577                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 578                 } else {
 579                         switch (config_regs->type) {
 580                         case CISLANDS_CONFIGREG_SMC_IND:
 581                                 data = RREG32_SMC(config_regs->offset);
 582                                 break;
 583                         case CISLANDS_CONFIGREG_DIDT_IND:
 584                                 data = RREG32_DIDT(config_regs->offset);
 585                                 break;
 586                         default:
 587                                 data = RREG32(config_regs->offset << 2);
 588                                 break;
 589                         }
 590
 591                         data &= ~config_regs->mask;
 592                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 593                         data |= cache;
 594
 595                         switch (config_regs->type) {
 596                         case CISLANDS_CONFIGREG_SMC_IND:
 597                                 WREG32_SMC(config_regs->offset, data);
 598                                 break;
 599                         case CISLANDS_CONFIGREG_DIDT_IND:
 600                                 WREG32_DIDT(config_regs->offset, data);
 601                                 break;
 602                         default:
 603                                 WREG32(config_regs->offset << 2, data);
 604                                 break;
 605                         }
 606                         cache = 0;
 607                 }
 608                 config_regs++;
 609         }
 610         return 0;
 611 }
 612
 613 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 614 {
 615         struct ci_power_info *pi = ci_get_pi(rdev);
 616         int ret;
 617
 618         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 619             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 620                 cik_enter_rlc_safe_mode(rdev);
 621
 622                 if (enable) {
 623                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 624                         if (ret) {
 625                                 cik_exit_rlc_safe_mode(rdev);
 626                                 return ret;
 627                         }
 628                 }
 629
 630                 ci_do_enable_didt(rdev, enable);
 631
 632                 cik_exit_rlc_safe_mode(rdev);
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 639 {
 640         struct ci_power_info *pi = ci_get_pi(rdev);
 641         PPSMC_Result smc_result;
 642         int ret = 0;
 643
 644         if (enable) {
 645                 pi->power_containment_features = 0;
 646                 if (pi->caps_power_containment) {
 647                         if (pi->enable_bapm_feature) {
 648                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 649                                 if (smc_result != PPSMC_Result_OK)
 650                                         ret = -EINVAL;
 651                                 else
 652                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 653                         }
 654
 655                         if (pi->enable_tdc_limit_feature) {
 656                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 657                                 if (smc_result != PPSMC_Result_OK)
 658                                         ret = -EINVAL;
 659                                 else
 660                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 661                         }
 662
 663                         if (pi->enable_pkg_pwr_tracking_feature) {
 664                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 665                                 if (smc_result != PPSMC_Result_OK) {
 666                                         ret = -EINVAL;
 667                                 } else {
 668                                         struct radeon_cac_tdp_table *cac_tdp_table =
 669                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 670                                         u32 default_pwr_limit =
 671                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 672
 673                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 674
 675                                         ci_set_power_limit(rdev, default_pwr_limit);
 676                                 }
 677                         }
 678                 }
 679         } else {
 680                 if (pi->caps_power_containment && pi->power_containment_features) {
 681                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 682                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 683
 684                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 685                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 686
 687                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 688                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 689                         pi->power_containment_features = 0;
 690                 }
 691         }
 692
 693         return ret;
 694 }
 695
 696 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 697 {
 698         struct ci_power_info *pi = ci_get_pi(rdev);
 699         PPSMC_Result smc_result;
 700         int ret = 0;
 701
 702         if (pi->caps_cac) {
 703                 if (enable) {
 704                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 705                         if (smc_result != PPSMC_Result_OK) {
 706                                 ret = -EINVAL;
 707                                 pi->cac_enabled = false;
 708                         } else {
 709                                 pi->cac_enabled = true;
 710                         }
 711                 } else if (pi->cac_enabled) {
 712                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 713                         pi->cac_enabled = false;
 714                 }
 715         }
 716
 717         return ret;
 718 }
 719
 720 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
 721                                             bool enable)
 722 {
 723         struct ci_power_info *pi = ci_get_pi(rdev);
 724         PPSMC_Result smc_result = PPSMC_Result_OK;
 725
 726         if (pi->thermal_sclk_dpm_enabled) {
 727                 if (enable)
 728                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
 729                 else
 730                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
 731         }
 732
 733         if (smc_result == PPSMC_Result_OK)
 734                 return 0;
 735         else
 736                 return -EINVAL;
 737 }
 738
 739 static int ci_power_control_set_level(struct radeon_device *rdev)
 740 {
 741         struct ci_power_info *pi = ci_get_pi(rdev);
 742         struct radeon_cac_tdp_table *cac_tdp_table =
 743                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 744         s32 adjust_percent;
 745         s32 target_tdp;
 746         int ret = 0;
 747         bool adjust_polarity = false; /* ??? */
 748
 749         if (pi->caps_power_containment) {
 750                 adjust_percent = adjust_polarity ?
 751                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 752                 target_tdp = ((100 + adjust_percent) *
 753                               (s32)cac_tdp_table->configurable_tdp) / 100;
 754
 755                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 756         }
 757
 758         return ret;
 759 }
 760
 761 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 762 {
 763         struct ci_power_info *pi = ci_get_pi(rdev);
 764
 765         if (pi->uvd_power_gated == gate)
 766                 return;
 767
 768         pi->uvd_power_gated = gate;
 769
 770         ci_update_uvd_dpm(rdev, gate);
 771 }
 772
 773 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 774 {
 775         struct ci_power_info *pi = ci_get_pi(rdev);
 776         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 777         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 778
 779         /* disable mclk switching if the refresh is >120Hz, even if the
 780         * blanking period would allow it
 781         */
 782         if (r600_dpm_get_vrefresh(rdev) > 120)
 783                 return true;
 784
 785         /* disable mclk switching if the refresh is >120Hz, even if the
 786         * blanking period would allow it
 787         */
 788         if (r600_dpm_get_vrefresh(rdev) > 120)
 789                 return true;
 790
 791         if (vblank_time < switch_limit)
 792                 return true;
 793         else
 794                 return false;
 795
 796 }
 797
 798 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 799                                         struct radeon_ps *rps)
 800 {
 801         struct ci_ps *ps = ci_get_ps(rps);
 802         struct ci_power_info *pi = ci_get_pi(rdev);
 803         struct radeon_clock_and_voltage_limits *max_limits;
 804         bool disable_mclk_switching;
 805         u32 sclk, mclk;
 806         int i;
 807
 808         if (rps->vce_active) {
 809                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
 810                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
 811         } else {
 812                 rps->evclk = 0;
 813                 rps->ecclk = 0;
 814         }
 815
 816         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 817             ci_dpm_vblank_too_short(rdev))
 818                 disable_mclk_switching = true;
 819         else
 820                 disable_mclk_switching = false;
 821
 822         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 823                 pi->battery_state = true;
 824         else
 825                 pi->battery_state = false;
 826
 827         if (rdev->pm.dpm.ac_power)
 828                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 829         else
 830                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 831
 832         if (rdev->pm.dpm.ac_power == false) {
 833                 for (i = 0; i < ps->performance_level_count; i++) {
 834                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 835                                 ps->performance_levels[i].mclk = max_limits->mclk;
 836                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 837                                 ps->performance_levels[i].sclk = max_limits->sclk;
 838                 }
 839         }
 840
 841         /* XXX validate the min clocks required for display */
 842
 843         if (disable_mclk_switching) {
 844                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 845                 sclk = ps->performance_levels[0].sclk;
 846         } else {
 847                 mclk = ps->performance_levels[0].mclk;
 848                 sclk = ps->performance_levels[0].sclk;
 849         }
 850
 851         if (rps->vce_active) {
 852                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
 853                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
 854                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
 855                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
 856         }
 857
 858         ps->performance_levels[0].sclk = sclk;
 859         ps->performance_levels[0].mclk = mclk;
 860
 861         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 862                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 863
 864         if (disable_mclk_switching) {
 865                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 866                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 867         } else {
 868                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 869                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 870         }
 871 }
 872
 873 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
 874                                             int min_temp, int max_temp)
 875 {
 876         int low_temp = 0 * 1000;
 877         int high_temp = 255 * 1000;
 878         u32 tmp;
 879
 880         if (low_temp < min_temp)
 881                 low_temp = min_temp;
 882         if (high_temp > max_temp)
 883                 high_temp = max_temp;
 884         if (high_temp < low_temp) {
 885                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 886                 return -EINVAL;
 887         }
 888
 889         tmp = RREG32_SMC(CG_THERMAL_INT);
 890         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 891         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 892                 CI_DIG_THERM_INTL(low_temp / 1000);
 893         WREG32_SMC(CG_THERMAL_INT, tmp);
 894
 895 #if 0
 896         /* XXX: need to figure out how to handle this properly */
 897         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 898         tmp &= DIG_THERM_DPM_MASK;
 899         tmp |= DIG_THERM_DPM(high_temp / 1000);
 900         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 901 #endif
 902
 903         rdev->pm.dpm.thermal.min_temp = low_temp;
 904         rdev->pm.dpm.thermal.max_temp = high_temp;
 905
 906         return 0;
 907 }
 908
 909 static int ci_thermal_enable_alert(struct radeon_device *rdev,
 910                                    bool enable)
 911 {
 912         u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
 913         PPSMC_Result result;
 914
 915         if (enable) {
 916                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
 917                 WREG32_SMC(CG_THERMAL_INT, thermal_int);
 918                 rdev->irq.dpm_thermal = false;
 919                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
 920                 if (result != PPSMC_Result_OK) {
 921                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
 922                         return -EINVAL;
 923                 }
 924         } else {
 925                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
 926                 WREG32_SMC(CG_THERMAL_INT, thermal_int);
 927                 rdev->irq.dpm_thermal = true;
 928                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
 929                 if (result != PPSMC_Result_OK) {
 930                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
 931                         return -EINVAL;
 932                 }
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
 939 {
 940         struct ci_power_info *pi = ci_get_pi(rdev);
 941         u32 tmp;
 942
 943         if (pi->fan_ctrl_is_in_default_mode) {
 944                 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
 945                 pi->fan_ctrl_default_mode = tmp;
 946                 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
 947                 pi->t_min = tmp;
 948                 pi->fan_ctrl_is_in_default_mode = false;
 949         }
 950
 951         tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
 952         tmp |= TMIN(0);
 953         WREG32_SMC(CG_FDO_CTRL2, tmp);
 954
 955         tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
 956         tmp |= FDO_PWM_MODE(mode);
 957         WREG32_SMC(CG_FDO_CTRL2, tmp);
 958 }
 959
 960 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
 961 {
 962         struct ci_power_info *pi = ci_get_pi(rdev);
 963         SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
 964         u32 duty100;
 965         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
 966         u16 fdo_min, slope1, slope2;
 967         u32 reference_clock, tmp;
 968         int ret;
 969         u64 tmp64;
 970
 971         if (!pi->fan_table_start) {
 972                 rdev->pm.dpm.fan.ucode_fan_control = false;
 973                 return 0;
 974         }
 975
 976         duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
 977
 978         if (duty100 == 0) {
 979                 rdev->pm.dpm.fan.ucode_fan_control = false;
 980                 return 0;
 981         }
 982
 983         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
 984         do_div(tmp64, 10000);
 985         fdo_min = (u16)tmp64;
 986
 987         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
 988         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
 989
 990         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
 991         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
 992
 993         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
 994         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
 995
 996         fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
 997         fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
 998         fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
 999
1000         fan_table.Slope1 = cpu_to_be16(slope1);
1001         fan_table.Slope2 = cpu_to_be16(slope2);
1002
1003         fan_table.FdoMin = cpu_to_be16(fdo_min);
1004
1005         fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
1006
1007         fan_table.HystUp = cpu_to_be16(1);
1008
1009         fan_table.HystSlope = cpu_to_be16(1);
1010
1011         fan_table.TempRespLim = cpu_to_be16(5);
1012
1013         reference_clock = radeon_get_xclk(rdev);
1014
1015         fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1016                                                reference_clock) / 1600);
1017
1018         fan_table.FdoMax = cpu_to_be16((u16)duty100);
1019
1020         tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1021         fan_table.TempSrc = (uint8_t)tmp;
1022
1023         ret = ci_copy_bytes_to_smc(rdev,
1024                                    pi->fan_table_start,
1025                                    (u8 *)(&fan_table),
1026                                    sizeof(fan_table),
1027                                    pi->sram_end);
1028
1029         if (ret) {
1030                 DRM_ERROR("Failed to load fan table to the SMC.");
1031                 rdev->pm.dpm.fan.ucode_fan_control = false;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1038 {
1039         struct ci_power_info *pi = ci_get_pi(rdev);
1040         PPSMC_Result ret;
1041
1042         if (pi->caps_od_fuzzy_fan_control_support) {
1043                 ret = ci_send_msg_to_smc_with_parameter(rdev,
1044                                                         PPSMC_StartFanControl,
1045                                                         FAN_CONTROL_FUZZY);
1046                 if (ret != PPSMC_Result_OK)
1047                         return -EINVAL;
1048                 ret = ci_send_msg_to_smc_with_parameter(rdev,
1049                                                         PPSMC_MSG_SetFanPwmMax,
1050                                                         rdev->pm.dpm.fan.default_max_fan_pwm);
1051                 if (ret != PPSMC_Result_OK)
1052                         return -EINVAL;
1053         } else {
1054                 ret = ci_send_msg_to_smc_with_parameter(rdev,
1055                                                         PPSMC_StartFanControl,
1056                                                         FAN_CONTROL_TABLE);
1057                 if (ret != PPSMC_Result_OK)
1058                         return -EINVAL;
1059         }
1060
1061         pi->fan_is_controlled_by_smc = true;
1062         return 0;
1063 }
1064
1065 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1066 {
1067         PPSMC_Result ret;
1068         struct ci_power_info *pi = ci_get_pi(rdev);
1069
1070         ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1071         if (ret == PPSMC_Result_OK) {
1072                 pi->fan_is_controlled_by_smc = false;
1073                 return 0;
1074         } else
1075                 return -EINVAL;
1076 }
1077
1078 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1079                                              u32 *speed)
1080 {
1081         u32 duty, duty100;
1082         u64 tmp64;
1083
1084         if (rdev->pm.no_fan)
1085                 return -ENOENT;
1086
1087         duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1088         duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1089
1090         if (duty100 == 0)
1091                 return -EINVAL;
1092
1093         tmp64 = (u64)duty * 100;
1094         do_div(tmp64, duty100);
1095         *speed = (u32)tmp64;
1096
1097         if (*speed > 100)
1098                 *speed = 100;
1099
1100         return 0;
1101 }
1102
1103 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1104                                              u32 speed)
1105 {
1106         u32 tmp;
1107         u32 duty, duty100;
1108         u64 tmp64;
1109         struct ci_power_info *pi = ci_get_pi(rdev);
1110
1111         if (rdev->pm.no_fan)
1112                 return -ENOENT;
1113
1114         if (pi->fan_is_controlled_by_smc)
1115                 return -EINVAL;
1116
1117         if (speed > 100)
1118                 return -EINVAL;
1119
1120         duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1121
1122         if (duty100 == 0)
1123                 return -EINVAL;
1124
1125         tmp64 = (u64)speed * duty100;
1126         do_div(tmp64, 100);
1127         duty = (u32)tmp64;
1128
1129         tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1130         tmp |= FDO_STATIC_DUTY(duty);
1131         WREG32_SMC(CG_FDO_CTRL0, tmp);
1132
1133         return 0;
1134 }
1135
1136 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1137 {
1138         if (mode) {
1139                 /* stop auto-manage */
1140                 if (rdev->pm.dpm.fan.ucode_fan_control)
1141                         ci_fan_ctrl_stop_smc_fan_control(rdev);
1142                 ci_fan_ctrl_set_static_mode(rdev, mode);
1143         } else {
1144                 /* restart auto-manage */
1145                 if (rdev->pm.dpm.fan.ucode_fan_control)
1146                         ci_thermal_start_smc_fan_control(rdev);
1147                 else
1148                         ci_fan_ctrl_set_default_mode(rdev);
1149         }
1150 }
1151
1152 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1153 {
1154         struct ci_power_info *pi = ci_get_pi(rdev);
1155         u32 tmp;
1156
1157         if (pi->fan_is_controlled_by_smc)
1158                 return 0;
1159
1160         tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1161         return (tmp >> FDO_PWM_MODE_SHIFT);
1162 }
1163
1164 #if 0
1165 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1166                                          u32 *speed)
1167 {
1168         u32 tach_period;
1169         u32 xclk = radeon_get_xclk(rdev);
1170
1171         if (rdev->pm.no_fan)
1172                 return -ENOENT;
1173
1174         if (rdev->pm.fan_pulses_per_revolution == 0)
1175                 return -ENOENT;
1176
1177         tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1178         if (tach_period == 0)
1179                 return -ENOENT;
1180
1181         *speed = 60 * xclk * 10000 / tach_period;
1182
1183         return 0;
1184 }
1185
1186 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1187                                          u32 speed)
1188 {
1189         u32 tach_period, tmp;
1190         u32 xclk = radeon_get_xclk(rdev);
1191
1192         if (rdev->pm.no_fan)
1193                 return -ENOENT;
1194
1195         if (rdev->pm.fan_pulses_per_revolution == 0)
1196                 return -ENOENT;
1197
1198         if ((speed < rdev->pm.fan_min_rpm) ||
1199             (speed > rdev->pm.fan_max_rpm))
1200                 return -EINVAL;
1201
1202         if (rdev->pm.dpm.fan.ucode_fan_control)
1203                 ci_fan_ctrl_stop_smc_fan_control(rdev);
1204
1205         tach_period = 60 * xclk * 10000 / (8 * speed);
1206         tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1207         tmp |= TARGET_PERIOD(tach_period);
1208         WREG32_SMC(CG_TACH_CTRL, tmp);
1209
1210         ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1211
1212         return 0;
1213 }
1214 #endif
1215
1216 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1217 {
1218         struct ci_power_info *pi = ci_get_pi(rdev);
1219         u32 tmp;
1220
1221         if (!pi->fan_ctrl_is_in_default_mode) {
1222                 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1223                 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1224                 WREG32_SMC(CG_FDO_CTRL2, tmp);
1225
1226                 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1227                 tmp |= TMIN(pi->t_min);
1228                 WREG32_SMC(CG_FDO_CTRL2, tmp);
1229                 pi->fan_ctrl_is_in_default_mode = true;
1230         }
1231 }
1232
1233 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1234 {
1235         if (rdev->pm.dpm.fan.ucode_fan_control) {
1236                 ci_fan_ctrl_start_smc_fan_control(rdev);
1237                 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1238         }
1239 }
1240
1241 static void ci_thermal_initialize(struct radeon_device *rdev)
1242 {
1243         u32 tmp;
1244
1245         if (rdev->pm.fan_pulses_per_revolution) {
1246                 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1247                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1248                 WREG32_SMC(CG_TACH_CTRL, tmp);
1249         }
1250
1251         tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1252         tmp |= TACH_PWM_RESP_RATE(0x28);
1253         WREG32_SMC(CG_FDO_CTRL2, tmp);
1254 }
1255
1256 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1257 {
1258         int ret;
1259
1260         ci_thermal_initialize(rdev);
1261         ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1262         if (ret)
1263                 return ret;
1264         ret = ci_thermal_enable_alert(rdev, true);
1265         if (ret)
1266                 return ret;
1267         if (rdev->pm.dpm.fan.ucode_fan_control) {
1268                 ret = ci_thermal_setup_fan_table(rdev);
1269                 if (ret)
1270                         return ret;
1271                 ci_thermal_start_smc_fan_control(rdev);
1272         }
1273
1274         return 0;
1275 }
1276
1277 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1278 {
1279         if (!rdev->pm.no_fan)
1280                 ci_fan_ctrl_set_default_mode(rdev);
1281 }
1282
1283 #if 0
1284 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1285                                      u16 reg_offset, u32 *value)
1286 {
1287         struct ci_power_info *pi = ci_get_pi(rdev);
1288
1289         return ci_read_smc_sram_dword(rdev,
1290                                       pi->soft_regs_start + reg_offset,
1291                                       value, pi->sram_end);
1292 }
1293 #endif
1294
1295 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1296                                       u16 reg_offset, u32 value)
1297 {
1298         struct ci_power_info *pi = ci_get_pi(rdev);
1299
1300         return ci_write_smc_sram_dword(rdev,
1301                                        pi->soft_regs_start + reg_offset,
1302                                        value, pi->sram_end);
1303 }
1304
1305 static void ci_init_fps_limits(struct radeon_device *rdev)
1306 {
1307         struct ci_power_info *pi = ci_get_pi(rdev);
1308         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1309
1310         if (pi->caps_fps) {
1311                 u16 tmp;
1312
1313                 tmp = 45;
1314                 table->FpsHighT = cpu_to_be16(tmp);
1315
1316                 tmp = 30;
1317                 table->FpsLowT = cpu_to_be16(tmp);
1318         }
1319 }
1320
1321 static int ci_update_sclk_t(struct radeon_device *rdev)
1322 {
1323         struct ci_power_info *pi = ci_get_pi(rdev);
1324         int ret = 0;
1325         u32 low_sclk_interrupt_t = 0;
1326
1327         if (pi->caps_sclk_throttle_low_notification) {
1328                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1329
1330                 ret = ci_copy_bytes_to_smc(rdev,
1331                                            pi->dpm_table_start +
1332                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1333                                            (u8 *)&low_sclk_interrupt_t,
1334                                            sizeof(u32), pi->sram_end);
1335
1336         }
1337
1338         return ret;
1339 }
1340
1341 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1342 {
1343         struct ci_power_info *pi = ci_get_pi(rdev);
1344         u16 leakage_id, virtual_voltage_id;
1345         u16 vddc, vddci;
1346         int i;
1347
1348         pi->vddc_leakage.count = 0;
1349         pi->vddci_leakage.count = 0;
1350
1351         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1352                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1353                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1354                         if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1355                                 continue;
1356                         if (vddc != 0 && vddc != virtual_voltage_id) {
1357                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1358                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1359                                 pi->vddc_leakage.count++;
1360                         }
1361                 }
1362         } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1363                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1364                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1365                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1366                                                                                  virtual_voltage_id,
1367                                                                                  leakage_id) == 0) {
1368                                 if (vddc != 0 && vddc != virtual_voltage_id) {
1369                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1370                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1371                                         pi->vddc_leakage.count++;
1372                                 }
1373                                 if (vddci != 0 && vddci != virtual_voltage_id) {
1374                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1375                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1376                                         pi->vddci_leakage.count++;
1377                                 }
1378                         }
1379                 }
1380         }
1381 }
1382
1383 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1384 {
1385         struct ci_power_info *pi = ci_get_pi(rdev);
1386         bool want_thermal_protection;
1387         enum radeon_dpm_event_src dpm_event_src;
1388         u32 tmp;
1389
1390         switch (sources) {
1391         case 0:
1392         default:
1393                 want_thermal_protection = false;
1394                 break;
1395         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1396                 want_thermal_protection = true;
1397                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1398                 break;
1399         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1400                 want_thermal_protection = true;
1401                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1402                 break;
1403         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1404               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1405                 want_thermal_protection = true;
1406                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1407                 break;
1408         }
1409
1410         if (want_thermal_protection) {
1411 #if 0
1412                 /* XXX: need to figure out how to handle this properly */
1413                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1414                 tmp &= DPM_EVENT_SRC_MASK;
1415                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1416                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1417 #endif
1418
1419                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1420                 if (pi->thermal_protection)
1421                         tmp &= ~THERMAL_PROTECTION_DIS;
1422                 else
1423                         tmp |= THERMAL_PROTECTION_DIS;
1424                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1425         } else {
1426                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1427                 tmp |= THERMAL_PROTECTION_DIS;
1428                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1429         }
1430 }
1431
1432 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1433                                            enum radeon_dpm_auto_throttle_src source,
1434                                            bool enable)
1435 {
1436         struct ci_power_info *pi = ci_get_pi(rdev);
1437
1438         if (enable) {
1439                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1440                         pi->active_auto_throttle_sources |= 1 << source;
1441                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1442                 }
1443         } else {
1444                 if (pi->active_auto_throttle_sources & (1 << source)) {
1445                         pi->active_auto_throttle_sources &= ~(1 << source);
1446                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1447                 }
1448         }
1449 }
1450
1451 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1452 {
1453         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1454                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1455 }
1456
1457 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1458 {
1459         struct ci_power_info *pi = ci_get_pi(rdev);
1460         PPSMC_Result smc_result;
1461
1462         if (!pi->need_update_smu7_dpm_table)
1463                 return 0;
1464
1465         if ((!pi->sclk_dpm_key_disabled) &&
1466             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1467                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1468                 if (smc_result != PPSMC_Result_OK)
1469                         return -EINVAL;
1470         }
1471
1472         if ((!pi->mclk_dpm_key_disabled) &&
1473             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1474                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1475                 if (smc_result != PPSMC_Result_OK)
1476                         return -EINVAL;
1477         }
1478
1479         pi->need_update_smu7_dpm_table = 0;
1480         return 0;
1481 }
1482
1483 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1484 {
1485         struct ci_power_info *pi = ci_get_pi(rdev);
1486         PPSMC_Result smc_result;
1487
1488         if (enable) {
1489                 if (!pi->sclk_dpm_key_disabled) {
1490                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1491                         if (smc_result != PPSMC_Result_OK)
1492                                 return -EINVAL;
1493                 }
1494
1495                 if (!pi->mclk_dpm_key_disabled) {
1496                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1497                         if (smc_result != PPSMC_Result_OK)
1498                                 return -EINVAL;
1499
1500                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1501
1502                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1503                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1504                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1505
1506                         udelay(10);
1507
1508                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1509                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1510                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1511                 }
1512         } else {
1513                 if (!pi->sclk_dpm_key_disabled) {
1514                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1515                         if (smc_result != PPSMC_Result_OK)
1516                                 return -EINVAL;
1517                 }
1518
1519                 if (!pi->mclk_dpm_key_disabled) {
1520                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1521                         if (smc_result != PPSMC_Result_OK)
1522                                 return -EINVAL;
1523                 }
1524         }
1525
1526         return 0;
1527 }
1528
1529 static int ci_start_dpm(struct radeon_device *rdev)
1530 {
1531         struct ci_power_info *pi = ci_get_pi(rdev);
1532         PPSMC_Result smc_result;
1533         int ret;
1534         u32 tmp;
1535
1536         tmp = RREG32_SMC(GENERAL_PWRMGT);
1537         tmp |= GLOBAL_PWRMGT_EN;
1538         WREG32_SMC(GENERAL_PWRMGT, tmp);
1539
1540         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1541         tmp |= DYNAMIC_PM_EN;
1542         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1543
1544         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1545
1546         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1547
1548         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1549         if (smc_result != PPSMC_Result_OK)
1550                 return -EINVAL;
1551
1552         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1553         if (ret)
1554                 return ret;
1555
1556         if (!pi->pcie_dpm_key_disabled) {
1557                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1558                 if (smc_result != PPSMC_Result_OK)
1559                         return -EINVAL;
1560         }
1561
1562         return 0;
1563 }
1564
1565 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1566 {
1567         struct ci_power_info *pi = ci_get_pi(rdev);
1568         PPSMC_Result smc_result;
1569
1570         if (!pi->need_update_smu7_dpm_table)
1571                 return 0;
1572
1573         if ((!pi->sclk_dpm_key_disabled) &&
1574             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1575                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1576                 if (smc_result != PPSMC_Result_OK)
1577                         return -EINVAL;
1578         }
1579
1580         if ((!pi->mclk_dpm_key_disabled) &&
1581             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1582                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1583                 if (smc_result != PPSMC_Result_OK)
1584                         return -EINVAL;
1585         }
1586
1587         return 0;
1588 }
1589
1590 static int ci_stop_dpm(struct radeon_device *rdev)
1591 {
1592         struct ci_power_info *pi = ci_get_pi(rdev);
1593         PPSMC_Result smc_result;
1594         int ret;
1595         u32 tmp;
1596
1597         tmp = RREG32_SMC(GENERAL_PWRMGT);
1598         tmp &= ~GLOBAL_PWRMGT_EN;
1599         WREG32_SMC(GENERAL_PWRMGT, tmp);
1600
1601         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1602         tmp &= ~DYNAMIC_PM_EN;
1603         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1604
1605         if (!pi->pcie_dpm_key_disabled) {
1606                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1607                 if (smc_result != PPSMC_Result_OK)
1608                         return -EINVAL;
1609         }
1610
1611         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1612         if (ret)
1613                 return ret;
1614
1615         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1616         if (smc_result != PPSMC_Result_OK)
1617                 return -EINVAL;
1618
1619         return 0;
1620 }
1621
1622 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1623 {
1624         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1625
1626         if (enable)
1627                 tmp &= ~SCLK_PWRMGT_OFF;
1628         else
1629                 tmp |= SCLK_PWRMGT_OFF;
1630         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1631 }
1632
1633 #if 0
1634 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1635                                         bool ac_power)
1636 {
1637         struct ci_power_info *pi = ci_get_pi(rdev);
1638         struct radeon_cac_tdp_table *cac_tdp_table =
1639                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1640         u32 power_limit;
1641
1642         if (ac_power)
1643                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1644         else
1645                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1646
1647         ci_set_power_limit(rdev, power_limit);
1648
1649         if (pi->caps_automatic_dc_transition) {
1650                 if (ac_power)
1651                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1652                 else
1653                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1654         }
1655
1656         return 0;
1657 }
1658 #endif
1659
1660 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1661                                                       PPSMC_Msg msg, u32 parameter)
1662 {
1663         WREG32(SMC_MSG_ARG_0, parameter);
1664         return ci_send_msg_to_smc(rdev, msg);
1665 }
1666
1667 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1668                                                         PPSMC_Msg msg, u32 *parameter)
1669 {
1670         PPSMC_Result smc_result;
1671
1672         smc_result = ci_send_msg_to_smc(rdev, msg);
1673
1674         if ((smc_result == PPSMC_Result_OK) && parameter)
1675                 *parameter = RREG32(SMC_MSG_ARG_0);
1676
1677         return smc_result;
1678 }
1679
1680 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1681 {
1682         struct ci_power_info *pi = ci_get_pi(rdev);
1683
1684         if (!pi->sclk_dpm_key_disabled) {
1685                 PPSMC_Result smc_result =
1686                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1687                 if (smc_result != PPSMC_Result_OK)
1688                         return -EINVAL;
1689         }
1690
1691         return 0;
1692 }
1693
1694 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1695 {
1696         struct ci_power_info *pi = ci_get_pi(rdev);
1697
1698         if (!pi->mclk_dpm_key_disabled) {
1699                 PPSMC_Result smc_result =
1700                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1701                 if (smc_result != PPSMC_Result_OK)
1702                         return -EINVAL;
1703         }
1704
1705         return 0;
1706 }
1707
1708 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1709 {
1710         struct ci_power_info *pi = ci_get_pi(rdev);
1711
1712         if (!pi->pcie_dpm_key_disabled) {
1713                 PPSMC_Result smc_result =
1714                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1715                 if (smc_result != PPSMC_Result_OK)
1716                         return -EINVAL;
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1723 {
1724         struct ci_power_info *pi = ci_get_pi(rdev);
1725
1726         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1727                 PPSMC_Result smc_result =
1728                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1729                 if (smc_result != PPSMC_Result_OK)
1730                         return -EINVAL;
1731         }
1732
1733         return 0;
1734 }
1735
1736 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1737                                        u32 target_tdp)
1738 {
1739         PPSMC_Result smc_result =
1740                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1741         if (smc_result != PPSMC_Result_OK)
1742                 return -EINVAL;
1743         return 0;
1744 }
1745
1746 #if 0
1747 static int ci_set_boot_state(struct radeon_device *rdev)
1748 {
1749         return ci_enable_sclk_mclk_dpm(rdev, false);
1750 }
1751 #endif
1752
1753 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1754 {
1755         u32 sclk_freq;
1756         PPSMC_Result smc_result =
1757                 ci_send_msg_to_smc_return_parameter(rdev,
1758                                                     PPSMC_MSG_API_GetSclkFrequency,
1759                                                     &sclk_freq);
1760         if (smc_result != PPSMC_Result_OK)
1761                 sclk_freq = 0;
1762
1763         return sclk_freq;
1764 }
1765
1766 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1767 {
1768         u32 mclk_freq;
1769         PPSMC_Result smc_result =
1770                 ci_send_msg_to_smc_return_parameter(rdev,
1771                                                     PPSMC_MSG_API_GetMclkFrequency,
1772                                                     &mclk_freq);
1773         if (smc_result != PPSMC_Result_OK)
1774                 mclk_freq = 0;
1775
1776         return mclk_freq;
1777 }
1778
1779 static void ci_dpm_start_smc(struct radeon_device *rdev)
1780 {
1781         int i;
1782
1783         ci_program_jump_on_start(rdev);
1784         ci_start_smc_clock(rdev);
1785         ci_start_smc(rdev);
1786         for (i = 0; i < rdev->usec_timeout; i++) {
1787                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1788                         break;
1789         }
1790 }
1791
1792 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1793 {
1794         ci_reset_smc(rdev);
1795         ci_stop_smc_clock(rdev);
1796 }
1797
1798 static int ci_process_firmware_header(struct radeon_device *rdev)
1799 {
1800         struct ci_power_info *pi = ci_get_pi(rdev);
1801         u32 tmp;
1802         int ret;
1803
1804         ret = ci_read_smc_sram_dword(rdev,
1805                                      SMU7_FIRMWARE_HEADER_LOCATION +
1806                                      offsetof(SMU7_Firmware_Header, DpmTable),
1807                                      &tmp, pi->sram_end);
1808         if (ret)
1809                 return ret;
1810
1811         pi->dpm_table_start = tmp;
1812
1813         ret = ci_read_smc_sram_dword(rdev,
1814                                      SMU7_FIRMWARE_HEADER_LOCATION +
1815                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1816                                      &tmp, pi->sram_end);
1817         if (ret)
1818                 return ret;
1819
1820         pi->soft_regs_start = tmp;
1821
1822         ret = ci_read_smc_sram_dword(rdev,
1823                                      SMU7_FIRMWARE_HEADER_LOCATION +
1824                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1825                                      &tmp, pi->sram_end);
1826         if (ret)
1827                 return ret;
1828
1829         pi->mc_reg_table_start = tmp;
1830
1831         ret = ci_read_smc_sram_dword(rdev,
1832                                      SMU7_FIRMWARE_HEADER_LOCATION +
1833                                      offsetof(SMU7_Firmware_Header, FanTable),
1834                                      &tmp, pi->sram_end);
1835         if (ret)
1836                 return ret;
1837
1838         pi->fan_table_start = tmp;
1839
1840         ret = ci_read_smc_sram_dword(rdev,
1841                                      SMU7_FIRMWARE_HEADER_LOCATION +
1842                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1843                                      &tmp, pi->sram_end);
1844         if (ret)
1845                 return ret;
1846
1847         pi->arb_table_start = tmp;
1848
1849         return 0;
1850 }
1851
1852 static void ci_read_clock_registers(struct radeon_device *rdev)
1853 {
1854         struct ci_power_info *pi = ci_get_pi(rdev);
1855
1856         pi->clock_registers.cg_spll_func_cntl =
1857                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1858         pi->clock_registers.cg_spll_func_cntl_2 =
1859                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1860         pi->clock_registers.cg_spll_func_cntl_3 =
1861                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1862         pi->clock_registers.cg_spll_func_cntl_4 =
1863                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1864         pi->clock_registers.cg_spll_spread_spectrum =
1865                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1866         pi->clock_registers.cg_spll_spread_spectrum_2 =
1867                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1868         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1869         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1870         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1871         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1872         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1873         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1874         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1875         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1876         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1877 }
1878
1879 static void ci_init_sclk_t(struct radeon_device *rdev)
1880 {
1881         struct ci_power_info *pi = ci_get_pi(rdev);
1882
1883         pi->low_sclk_interrupt_t = 0;
1884 }
1885
1886 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1887                                          bool enable)
1888 {
1889         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1890
1891         if (enable)
1892                 tmp &= ~THERMAL_PROTECTION_DIS;
1893         else
1894                 tmp |= THERMAL_PROTECTION_DIS;
1895         WREG32_SMC(GENERAL_PWRMGT, tmp);
1896 }
1897
1898 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1899 {
1900         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1901
1902         tmp |= STATIC_PM_EN;
1903
1904         WREG32_SMC(GENERAL_PWRMGT, tmp);
1905 }
1906
1907 #if 0
1908 static int ci_enter_ulp_state(struct radeon_device *rdev)
1909 {
1910
1911         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1912
1913         udelay(25000);
1914
1915         return 0;
1916 }
1917
1918 static int ci_exit_ulp_state(struct radeon_device *rdev)
1919 {
1920         int i;
1921
1922         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1923
1924         udelay(7000);
1925
1926         for (i = 0; i < rdev->usec_timeout; i++) {
1927                 if (RREG32(SMC_RESP_0) == 1)
1928                         break;
1929                 udelay(1000);
1930         }
1931
1932         return 0;
1933 }
1934 #endif
1935
1936 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1937                                         bool has_display)
1938 {
1939         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1940
1941         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1942 }
1943
1944 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1945                                       bool enable)
1946 {
1947         struct ci_power_info *pi = ci_get_pi(rdev);
1948
1949         if (enable) {
1950                 if (pi->caps_sclk_ds) {
1951                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1952                                 return -EINVAL;
1953                 } else {
1954                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1955                                 return -EINVAL;
1956                 }
1957         } else {
1958                 if (pi->caps_sclk_ds) {
1959                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1960                                 return -EINVAL;
1961                 }
1962         }
1963
1964         return 0;
1965 }
1966
1967 static void ci_program_display_gap(struct radeon_device *rdev)
1968 {
1969         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1970         u32 pre_vbi_time_in_us;
1971         u32 frame_time_in_us;
1972         u32 ref_clock = rdev->clock.spll.reference_freq;
1973         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1974         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1975
1976         tmp &= ~DISP_GAP_MASK;
1977         if (rdev->pm.dpm.new_active_crtc_count > 0)
1978                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1979         else
1980                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1981         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1982
1983         if (refresh_rate == 0)
1984                 refresh_rate = 60;
1985         if (vblank_time == 0xffffffff)
1986                 vblank_time = 500;
1987         frame_time_in_us = 1000000 / refresh_rate;
1988         pre_vbi_time_in_us =
1989                 frame_time_in_us - 200 - vblank_time;
1990         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1991
1992         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1993         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1994         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1995
1996
1997         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1998
1999 }
2000
2001 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
2002 {
2003         struct ci_power_info *pi = ci_get_pi(rdev);
2004         u32 tmp;
2005
2006         if (enable) {
2007                 if (pi->caps_sclk_ss_support) {
2008                         tmp = RREG32_SMC(GENERAL_PWRMGT);
2009                         tmp |= DYN_SPREAD_SPECTRUM_EN;
2010                         WREG32_SMC(GENERAL_PWRMGT, tmp);
2011                 }
2012         } else {
2013                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2014                 tmp &= ~SSEN;
2015                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2016
2017                 tmp = RREG32_SMC(GENERAL_PWRMGT);
2018                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2019                 WREG32_SMC(GENERAL_PWRMGT, tmp);
2020         }
2021 }
2022
2023 static void ci_program_sstp(struct radeon_device *rdev)
2024 {
2025         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2026 }
2027
2028 static void ci_enable_display_gap(struct radeon_device *rdev)
2029 {
2030         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2031
2032         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2033         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2034                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2035
2036         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2037 }
2038
2039 static void ci_program_vc(struct radeon_device *rdev)
2040 {
2041         u32 tmp;
2042
2043         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2044         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2045         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2046
2047         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2048         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2049         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2050         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2051         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2052         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2053         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2054         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2055 }
2056
2057 static void ci_clear_vc(struct radeon_device *rdev)
2058 {
2059         u32 tmp;
2060
2061         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2062         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2063         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2064
2065         WREG32_SMC(CG_FTV_0, 0);
2066         WREG32_SMC(CG_FTV_1, 0);
2067         WREG32_SMC(CG_FTV_2, 0);
2068         WREG32_SMC(CG_FTV_3, 0);
2069         WREG32_SMC(CG_FTV_4, 0);
2070         WREG32_SMC(CG_FTV_5, 0);
2071         WREG32_SMC(CG_FTV_6, 0);
2072         WREG32_SMC(CG_FTV_7, 0);
2073 }
2074
2075 static int ci_upload_firmware(struct radeon_device *rdev)
2076 {
2077         struct ci_power_info *pi = ci_get_pi(rdev);
2078         int i, ret;
2079
2080         for (i = 0; i < rdev->usec_timeout; i++) {
2081                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2082                         break;
2083         }
2084         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2085
2086         ci_stop_smc_clock(rdev);
2087         ci_reset_smc(rdev);
2088
2089         ret = ci_load_smc_ucode(rdev, pi->sram_end);
2090
2091         return ret;
2092
2093 }
2094
2095 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2096                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2097                                      struct atom_voltage_table *voltage_table)
2098 {
2099         u32 i;
2100
2101         if (voltage_dependency_table == NULL)
2102                 return -EINVAL;
2103
2104         voltage_table->mask_low = 0;
2105         voltage_table->phase_delay = 0;
2106
2107         voltage_table->count = voltage_dependency_table->count;
2108         for (i = 0; i < voltage_table->count; i++) {
2109                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2110                 voltage_table->entries[i].smio_low = 0;
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2117 {
2118         struct ci_power_info *pi = ci_get_pi(rdev);
2119         int ret;
2120
2121         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2122                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2123                                                     VOLTAGE_OBJ_GPIO_LUT,
2124                                                     &pi->vddc_voltage_table);
2125                 if (ret)
2126                         return ret;
2127         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2128                 ret = ci_get_svi2_voltage_table(rdev,
2129                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2130                                                 &pi->vddc_voltage_table);
2131                 if (ret)
2132                         return ret;
2133         }
2134
2135         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2136                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2137                                                          &pi->vddc_voltage_table);
2138
2139         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2140                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2141                                                     VOLTAGE_OBJ_GPIO_LUT,
2142                                                     &pi->vddci_voltage_table);
2143                 if (ret)
2144                         return ret;
2145         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2146                 ret = ci_get_svi2_voltage_table(rdev,
2147                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2148                                                 &pi->vddci_voltage_table);
2149                 if (ret)
2150                         return ret;
2151         }
2152
2153         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2154                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2155                                                          &pi->vddci_voltage_table);
2156
2157         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2158                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2159                                                     VOLTAGE_OBJ_GPIO_LUT,
2160                                                     &pi->mvdd_voltage_table);
2161                 if (ret)
2162                         return ret;
2163         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2164                 ret = ci_get_svi2_voltage_table(rdev,
2165                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2166                                                 &pi->mvdd_voltage_table);
2167                 if (ret)
2168                         return ret;
2169         }
2170
2171         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2172                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2173                                                          &pi->mvdd_voltage_table);
2174
2175         return 0;
2176 }
2177
2178 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2179                                           struct atom_voltage_table_entry *voltage_table,
2180                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
2181 {
2182         int ret;
2183
2184         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2185                                             &smc_voltage_table->StdVoltageHiSidd,
2186                                             &smc_voltage_table->StdVoltageLoSidd);
2187
2188         if (ret) {
2189                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2190                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2191         }
2192
2193         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2194         smc_voltage_table->StdVoltageHiSidd =
2195                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2196         smc_voltage_table->StdVoltageLoSidd =
2197                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2198 }
2199
2200 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2201                                       SMU7_Discrete_DpmTable *table)
2202 {
2203         struct ci_power_info *pi = ci_get_pi(rdev);
2204         unsigned int count;
2205
2206         table->VddcLevelCount = pi->vddc_voltage_table.count;
2207         for (count = 0; count < table->VddcLevelCount; count++) {
2208                 ci_populate_smc_voltage_table(rdev,
2209                                               &pi->vddc_voltage_table.entries[count],
2210                                               &table->VddcLevel[count]);
2211
2212                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2213                         table->VddcLevel[count].Smio |=
2214                                 pi->vddc_voltage_table.entries[count].smio_low;
2215                 else
2216                         table->VddcLevel[count].Smio = 0;
2217         }
2218         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2219
2220         return 0;
2221 }
2222
2223 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2224                                        SMU7_Discrete_DpmTable *table)
2225 {
2226         unsigned int count;
2227         struct ci_power_info *pi = ci_get_pi(rdev);
2228
2229         table->VddciLevelCount = pi->vddci_voltage_table.count;
2230         for (count = 0; count < table->VddciLevelCount; count++) {
2231                 ci_populate_smc_voltage_table(rdev,
2232                                               &pi->vddci_voltage_table.entries[count],
2233                                               &table->VddciLevel[count]);
2234
2235                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2236                         table->VddciLevel[count].Smio |=
2237                                 pi->vddci_voltage_table.entries[count].smio_low;
2238                 else
2239                         table->VddciLevel[count].Smio = 0;
2240         }
2241         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2242
2243         return 0;
2244 }
2245
2246 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2247                                       SMU7_Discrete_DpmTable *table)
2248 {
2249         struct ci_power_info *pi = ci_get_pi(rdev);
2250         unsigned int count;
2251
2252         table->MvddLevelCount = pi->mvdd_voltage_table.count;
2253         for (count = 0; count < table->MvddLevelCount; count++) {
2254                 ci_populate_smc_voltage_table(rdev,
2255                                               &pi->mvdd_voltage_table.entries[count],
2256                                               &table->MvddLevel[count]);
2257
2258                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2259                         table->MvddLevel[count].Smio |=
2260                                 pi->mvdd_voltage_table.entries[count].smio_low;
2261                 else
2262                         table->MvddLevel[count].Smio = 0;
2263         }
2264         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2265
2266         return 0;
2267 }
2268
2269 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2270                                           SMU7_Discrete_DpmTable *table)
2271 {
2272         int ret;
2273
2274         ret = ci_populate_smc_vddc_table(rdev, table);
2275         if (ret)
2276                 return ret;
2277
2278         ret = ci_populate_smc_vddci_table(rdev, table);
2279         if (ret)
2280                 return ret;
2281
2282         ret = ci_populate_smc_mvdd_table(rdev, table);
2283         if (ret)
2284                 return ret;
2285
2286         return 0;
2287 }
2288
2289 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2290                                   SMU7_Discrete_VoltageLevel *voltage)
2291 {
2292         struct ci_power_info *pi = ci_get_pi(rdev);
2293         u32 i = 0;
2294
2295         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2296                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2297                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2298                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2299                                 break;
2300                         }
2301                 }
2302
2303                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2304                         return -EINVAL;
2305         }
2306
2307         return -EINVAL;
2308 }
2309
2310 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2311                                          struct atom_voltage_table_entry *voltage_table,
2312                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2313 {
2314         u16 v_index, idx;
2315         bool voltage_found = false;
2316         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2317         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2318
2319         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2320                 return -EINVAL;
2321
2322         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2323                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2324                         if (voltage_table->value ==
2325                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2326                                 voltage_found = true;
2327                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2328                                         idx = v_index;
2329                                 else
2330                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2331                                 *std_voltage_lo_sidd =
2332                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2333                                 *std_voltage_hi_sidd =
2334                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2335                                 break;
2336                         }
2337                 }
2338
2339                 if (!voltage_found) {
2340                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2341                                 if (voltage_table->value <=
2342                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2343                                         voltage_found = true;
2344                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2345                                                 idx = v_index;
2346                                         else
2347                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2348                                         *std_voltage_lo_sidd =
2349                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2350                                         *std_voltage_hi_sidd =
2351                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2352                                         break;
2353                                 }
2354                         }
2355                 }
2356         }
2357
2358         return 0;
2359 }
2360
2361 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2362                                                   const struct radeon_phase_shedding_limits_table *limits,
2363                                                   u32 sclk,
2364                                                   u32 *phase_shedding)
2365 {
2366         unsigned int i;
2367
2368         *phase_shedding = 1;
2369
2370         for (i = 0; i < limits->count; i++) {
2371                 if (sclk < limits->entries[i].sclk) {
2372                         *phase_shedding = i;
2373                         break;
2374                 }
2375         }
2376 }
2377
2378 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2379                                                   const struct radeon_phase_shedding_limits_table *limits,
2380                                                   u32 mclk,
2381                                                   u32 *phase_shedding)
2382 {
2383         unsigned int i;
2384
2385         *phase_shedding = 1;
2386
2387         for (i = 0; i < limits->count; i++) {
2388                 if (mclk < limits->entries[i].mclk) {
2389                         *phase_shedding = i;
2390                         break;
2391                 }
2392         }
2393 }
2394
2395 static int ci_init_arb_table_index(struct radeon_device *rdev)
2396 {
2397         struct ci_power_info *pi = ci_get_pi(rdev);
2398         u32 tmp;
2399         int ret;
2400
2401         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2402                                      &tmp, pi->sram_end);
2403         if (ret)
2404                 return ret;
2405
2406         tmp &= 0x00FFFFFF;
2407         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2408
2409         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2410                                        tmp, pi->sram_end);
2411 }
2412
2413 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2414                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2415                                          u32 clock, u32 *voltage)
2416 {
2417         u32 i = 0;
2418
2419         if (allowed_clock_voltage_table->count == 0)
2420                 return -EINVAL;
2421
2422         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2423                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2424                         *voltage = allowed_clock_voltage_table->entries[i].v;
2425                         return 0;
2426                 }
2427         }
2428
2429         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2430
2431         return 0;
2432 }
2433
2434 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2435                                              u32 sclk, u32 min_sclk_in_sr)
2436 {
2437         u32 i;
2438         u32 tmp;
2439         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2440                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2441
2442         if (sclk < min)
2443                 return 0;
2444
2445         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2446                 tmp = sclk / (1 << i);
2447                 if (tmp >= min || i == 0)
2448                         break;
2449         }
2450
2451         return (u8)i;
2452 }
2453
2454 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2455 {
2456         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2457 }
2458
2459 static int ci_reset_to_default(struct radeon_device *rdev)
2460 {
2461         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2462                 0 : -EINVAL;
2463 }
2464
2465 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2466 {
2467         u32 tmp;
2468
2469         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2470
2471         if (tmp == MC_CG_ARB_FREQ_F0)
2472                 return 0;
2473
2474         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2475 }
2476
2477 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2478                                         const u32 engine_clock,
2479                                         const u32 memory_clock,
2480                                         u32 *dram_timimg2)
2481 {
2482         bool patch;
2483         u32 tmp, tmp2;
2484
2485         tmp = RREG32(MC_SEQ_MISC0);
2486         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2487
2488         if (patch &&
2489             ((rdev->pdev->device == 0x67B0) ||
2490              (rdev->pdev->device == 0x67B1))) {
2491                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2492                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2493                         *dram_timimg2 &= ~0x00ff0000;
2494                         *dram_timimg2 |= tmp2 << 16;
2495                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2496                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2497                         *dram_timimg2 &= ~0x00ff0000;
2498                         *dram_timimg2 |= tmp2 << 16;
2499                 }
2500         }
2501 }
2502
2503
2504 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2505                                                 u32 sclk,
2506                                                 u32 mclk,
2507                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2508 {
2509         u32 dram_timing;
2510         u32 dram_timing2;
2511         u32 burst_time;
2512
2513         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2514
2515         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2516         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2517         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2518
2519         ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2520
2521         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2522         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2523         arb_regs->McArbBurstTime = (u8)burst_time;
2524
2525         return 0;
2526 }
2527
2528 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2529 {
2530         struct ci_power_info *pi = ci_get_pi(rdev);
2531         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2532         u32 i, j;
2533         int ret =  0;
2534
2535         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2536
2537         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2538                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2539                         ret = ci_populate_memory_timing_parameters(rdev,
2540                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2541                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2542                                                                    &arb_regs.entries[i][j]);
2543                         if (ret)
2544                                 break;
2545                 }
2546         }
2547
2548         if (ret == 0)
2549                 ret = ci_copy_bytes_to_smc(rdev,
2550                                            pi->arb_table_start,
2551                                            (u8 *)&arb_regs,
2552                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2553                                            pi->sram_end);
2554
2555         return ret;
2556 }
2557
2558 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2559 {
2560         struct ci_power_info *pi = ci_get_pi(rdev);
2561
2562         if (pi->need_update_smu7_dpm_table == 0)
2563                 return 0;
2564
2565         return ci_do_program_memory_timing_parameters(rdev);
2566 }
2567
2568 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2569                                           struct radeon_ps *radeon_boot_state)
2570 {
2571         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2572         struct ci_power_info *pi = ci_get_pi(rdev);
2573         u32 level = 0;
2574
2575         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2576                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2577                     boot_state->performance_levels[0].sclk) {
2578                         pi->smc_state_table.GraphicsBootLevel = level;
2579                         break;
2580                 }
2581         }
2582
2583         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2584                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2585                     boot_state->performance_levels[0].mclk) {
2586                         pi->smc_state_table.MemoryBootLevel = level;
2587                         break;
2588                 }
2589         }
2590 }
2591
2592 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2593 {
2594         u32 i;
2595         u32 mask_value = 0;
2596
2597         for (i = dpm_table->count; i > 0; i--) {
2598                 mask_value = mask_value << 1;
2599                 if (dpm_table->dpm_levels[i-1].enabled)
2600                         mask_value |= 0x1;
2601                 else
2602                         mask_value &= 0xFFFFFFFE;
2603         }
2604
2605         return mask_value;
2606 }
2607
2608 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2609                                        SMU7_Discrete_DpmTable *table)
2610 {
2611         struct ci_power_info *pi = ci_get_pi(rdev);
2612         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2613         u32 i;
2614
2615         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2616                 table->LinkLevel[i].PcieGenSpeed =
2617                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2618                 table->LinkLevel[i].PcieLaneCount =
2619                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2620                 table->LinkLevel[i].EnabledForActivity = 1;
2621                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2622                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2623         }
2624
2625         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2626         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2627                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2628 }
2629
2630 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2631                                      SMU7_Discrete_DpmTable *table)
2632 {
2633         u32 count;
2634         struct atom_clock_dividers dividers;
2635         int ret = -EINVAL;
2636
2637         table->UvdLevelCount =
2638                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2639
2640         for (count = 0; count < table->UvdLevelCount; count++) {
2641                 table->UvdLevel[count].VclkFrequency =
2642                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2643                 table->UvdLevel[count].DclkFrequency =
2644                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2645                 table->UvdLevel[count].MinVddc =
2646                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2647                 table->UvdLevel[count].MinVddcPhases = 1;
2648
2649                 ret = radeon_atom_get_clock_dividers(rdev,
2650                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2651                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2652                 if (ret)
2653                         return ret;
2654
2655                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2656
2657                 ret = radeon_atom_get_clock_dividers(rdev,
2658                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2659                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2660                 if (ret)
2661                         return ret;
2662
2663                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2664
2665                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2666                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2667                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2668         }
2669
2670         return ret;
2671 }
2672
2673 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2674                                      SMU7_Discrete_DpmTable *table)
2675 {
2676         u32 count;
2677         struct atom_clock_dividers dividers;
2678         int ret = -EINVAL;
2679
2680         table->VceLevelCount =
2681                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2682
2683         for (count = 0; count < table->VceLevelCount; count++) {
2684                 table->VceLevel[count].Frequency =
2685                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2686                 table->VceLevel[count].MinVoltage =
2687                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2688                 table->VceLevel[count].MinPhases = 1;
2689
2690                 ret = radeon_atom_get_clock_dividers(rdev,
2691                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2692                                                      table->VceLevel[count].Frequency, false, &dividers);
2693                 if (ret)
2694                         return ret;
2695
2696                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2697
2698                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2699                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2700         }
2701
2702         return ret;
2703
2704 }
2705
2706 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2707                                      SMU7_Discrete_DpmTable *table)
2708 {
2709         u32 count;
2710         struct atom_clock_dividers dividers;
2711         int ret = -EINVAL;
2712
2713         table->AcpLevelCount = (u8)
2714                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2715
2716         for (count = 0; count < table->AcpLevelCount; count++) {
2717                 table->AcpLevel[count].Frequency =
2718                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2719                 table->AcpLevel[count].MinVoltage =
2720                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2721                 table->AcpLevel[count].MinPhases = 1;
2722
2723                 ret = radeon_atom_get_clock_dividers(rdev,
2724                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2725                                                      table->AcpLevel[count].Frequency, false, &dividers);
2726                 if (ret)
2727                         return ret;
2728
2729                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2730
2731                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2732                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2733         }
2734
2735         return ret;
2736 }
2737
2738 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2739                                       SMU7_Discrete_DpmTable *table)
2740 {
2741         u32 count;
2742         struct atom_clock_dividers dividers;
2743         int ret = -EINVAL;
2744
2745         table->SamuLevelCount =
2746                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2747
2748         for (count = 0; count < table->SamuLevelCount; count++) {
2749                 table->SamuLevel[count].Frequency =
2750                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2751                 table->SamuLevel[count].MinVoltage =
2752                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2753                 table->SamuLevel[count].MinPhases = 1;
2754
2755                 ret = radeon_atom_get_clock_dividers(rdev,
2756                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2757                                                      table->SamuLevel[count].Frequency, false, &dividers);
2758                 if (ret)
2759                         return ret;
2760
2761                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2762
2763                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2764                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2765         }
2766
2767         return ret;
2768 }
2769
2770 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2771                                     u32 memory_clock,
2772                                     SMU7_Discrete_MemoryLevel *mclk,
2773                                     bool strobe_mode,
2774                                     bool dll_state_on)
2775 {
2776         struct ci_power_info *pi = ci_get_pi(rdev);
2777         u32  dll_cntl = pi->clock_registers.dll_cntl;
2778         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2779         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2780         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2781         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2782         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2783         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2784         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2785         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2786         struct atom_mpll_param mpll_param;
2787         int ret;
2788
2789         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2790         if (ret)
2791                 return ret;
2792
2793         mpll_func_cntl &= ~BWCTRL_MASK;
2794         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2795
2796         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2797         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2798                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2799
2800         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2801         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2802
2803         if (pi->mem_gddr5) {
2804                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2805                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2806                         YCLK_POST_DIV(mpll_param.post_div);
2807         }
2808
2809         if (pi->caps_mclk_ss_support) {
2810                 struct radeon_atom_ss ss;
2811                 u32 freq_nom;
2812                 u32 tmp;
2813                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2814
2815                 if (mpll_param.qdr == 1)
2816                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2817                 else
2818                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2819
2820                 tmp = (freq_nom / reference_clock);
2821                 tmp = tmp * tmp;
2822                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2823                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2824                         u32 clks = reference_clock * 5 / ss.rate;
2825                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2826
2827                         mpll_ss1 &= ~CLKV_MASK;
2828                         mpll_ss1 |= CLKV(clkv);
2829
2830                         mpll_ss2 &= ~CLKS_MASK;
2831                         mpll_ss2 |= CLKS(clks);
2832                 }
2833         }
2834
2835         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2836         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2837
2838         if (dll_state_on)
2839                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2840         else
2841                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2842
2843         mclk->MclkFrequency = memory_clock;
2844         mclk->MpllFuncCntl = mpll_func_cntl;
2845         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2846         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2847         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2848         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2849         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2850         mclk->DllCntl = dll_cntl;
2851         mclk->MpllSs1 = mpll_ss1;
2852         mclk->MpllSs2 = mpll_ss2;
2853
2854         return 0;
2855 }
2856
2857 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2858                                            u32 memory_clock,
2859                                            SMU7_Discrete_MemoryLevel *memory_level)
2860 {
2861         struct ci_power_info *pi = ci_get_pi(rdev);
2862         int ret;
2863         bool dll_state_on;
2864
2865         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2866                 ret = ci_get_dependency_volt_by_clk(rdev,
2867                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2868                                                     memory_clock, &memory_level->MinVddc);
2869                 if (ret)
2870                         return ret;
2871         }
2872
2873         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2874                 ret = ci_get_dependency_volt_by_clk(rdev,
2875                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2876                                                     memory_clock, &memory_level->MinVddci);
2877                 if (ret)
2878                         return ret;
2879         }
2880
2881         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2882                 ret = ci_get_dependency_volt_by_clk(rdev,
2883                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2884                                                     memory_clock, &memory_level->MinMvdd);
2885                 if (ret)
2886                         return ret;
2887         }
2888
2889         memory_level->MinVddcPhases = 1;
2890
2891         if (pi->vddc_phase_shed_control)
2892                 ci_populate_phase_value_based_on_mclk(rdev,
2893                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2894                                                       memory_clock,
2895                                                       &memory_level->MinVddcPhases);
2896
2897         memory_level->EnabledForThrottle = 1;
2898         memory_level->UpH = 0;
2899         memory_level->DownH = 100;
2900         memory_level->VoltageDownH = 0;
2901         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2902
2903         memory_level->StutterEnable = false;
2904         memory_level->StrobeEnable = false;
2905         memory_level->EdcReadEnable = false;
2906         memory_level->EdcWriteEnable = false;
2907         memory_level->RttEnable = false;
2908
2909         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2910
2911         if (pi->mclk_stutter_mode_threshold &&
2912             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2913             (pi->uvd_enabled == false) &&
2914             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2915             (rdev->pm.dpm.new_active_crtc_count <= 2))
2916                 memory_level->StutterEnable = true;
2917
2918         if (pi->mclk_strobe_mode_threshold &&
2919             (memory_clock <= pi->mclk_strobe_mode_threshold))
2920                 memory_level->StrobeEnable = 1;
2921
2922         if (pi->mem_gddr5) {
2923                 memory_level->StrobeRatio =
2924                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2925                 if (pi->mclk_edc_enable_threshold &&
2926                     (memory_clock > pi->mclk_edc_enable_threshold))
2927                         memory_level->EdcReadEnable = true;
2928
2929                 if (pi->mclk_edc_wr_enable_threshold &&
2930                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2931                         memory_level->EdcWriteEnable = true;
2932
2933                 if (memory_level->StrobeEnable) {
2934                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2935                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2936                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2937                         else
2938                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2939                 } else {
2940                         dll_state_on = pi->dll_default_on;
2941                 }
2942         } else {
2943                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2944                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2945         }
2946
2947         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2948         if (ret)
2949                 return ret;
2950
2951         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2952         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2953         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2954         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2955
2956         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2957         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2958         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2959         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2960         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2961         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2962         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2963         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2964         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2965         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2966         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2967
2968         return 0;
2969 }
2970
2971 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2972                                       SMU7_Discrete_DpmTable *table)
2973 {
2974         struct ci_power_info *pi = ci_get_pi(rdev);
2975         struct atom_clock_dividers dividers;
2976         SMU7_Discrete_VoltageLevel voltage_level;
2977         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2978         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2979         u32 dll_cntl = pi->clock_registers.dll_cntl;
2980         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2981         int ret;
2982
2983         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2984
2985         if (pi->acpi_vddc)
2986                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2987         else
2988                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2989
2990         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2991
2992         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2993
2994         ret = radeon_atom_get_clock_dividers(rdev,
2995                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2996                                              table->ACPILevel.SclkFrequency, false, &dividers);
2997         if (ret)
2998                 return ret;
2999
3000         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3001         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3002         table->ACPILevel.DeepSleepDivId = 0;
3003
3004         spll_func_cntl &= ~SPLL_PWRON;
3005         spll_func_cntl |= SPLL_RESET;
3006
3007         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3008         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3009
3010         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3011         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3012         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3013         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3014         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3015         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3016         table->ACPILevel.CcPwrDynRm = 0;
3017         table->ACPILevel.CcPwrDynRm1 = 0;
3018
3019         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3020         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3021         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3022         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3023         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3024         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3025         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3026         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3027         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3028         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3029         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3030
3031         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3032         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3033
3034         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3035                 if (pi->acpi_vddci)
3036                         table->MemoryACPILevel.MinVddci =
3037                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3038                 else
3039                         table->MemoryACPILevel.MinVddci =
3040                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3041         }
3042
3043         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3044                 table->MemoryACPILevel.MinMvdd = 0;
3045         else
3046                 table->MemoryACPILevel.MinMvdd =
3047                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3048
3049         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3050         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3051
3052         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3053
3054         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3055         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3056         table->MemoryACPILevel.MpllAdFuncCntl =
3057                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3058         table->MemoryACPILevel.MpllDqFuncCntl =
3059                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3060         table->MemoryACPILevel.MpllFuncCntl =
3061                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3062         table->MemoryACPILevel.MpllFuncCntl_1 =
3063                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3064         table->MemoryACPILevel.MpllFuncCntl_2 =
3065                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3066         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3067         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3068
3069         table->MemoryACPILevel.EnabledForThrottle = 0;
3070         table->MemoryACPILevel.EnabledForActivity = 0;
3071         table->MemoryACPILevel.UpH = 0;
3072         table->MemoryACPILevel.DownH = 100;
3073         table->MemoryACPILevel.VoltageDownH = 0;
3074         table->MemoryACPILevel.ActivityLevel =
3075                 cpu_to_be16((u16)pi->mclk_activity_target);
3076
3077         table->MemoryACPILevel.StutterEnable = false;
3078         table->MemoryACPILevel.StrobeEnable = false;
3079         table->MemoryACPILevel.EdcReadEnable = false;
3080         table->MemoryACPILevel.EdcWriteEnable = false;
3081         table->MemoryACPILevel.RttEnable = false;
3082
3083         return 0;
3084 }
3085
3086
3087 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3088 {
3089         struct ci_power_info *pi = ci_get_pi(rdev);
3090         struct ci_ulv_parm *ulv = &pi->ulv;
3091
3092         if (ulv->supported) {
3093                 if (enable)
3094                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3095                                 0 : -EINVAL;
3096                 else
3097                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3098                                 0 : -EINVAL;
3099         }
3100
3101         return 0;
3102 }
3103
3104 static int ci_populate_ulv_level(struct radeon_device *rdev,
3105                                  SMU7_Discrete_Ulv *state)
3106 {
3107         struct ci_power_info *pi = ci_get_pi(rdev);
3108         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3109
3110         state->CcPwrDynRm = 0;
3111         state->CcPwrDynRm1 = 0;
3112
3113         if (ulv_voltage == 0) {
3114                 pi->ulv.supported = false;
3115                 return 0;
3116         }
3117
3118         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3119                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3120                         state->VddcOffset = 0;
3121                 else
3122                         state->VddcOffset =
3123                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3124         } else {
3125                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3126                         state->VddcOffsetVid = 0;
3127                 else
3128                         state->VddcOffsetVid = (u8)
3129                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3130                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3131         }
3132         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3133
3134         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3135         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3136         state->VddcOffset = cpu_to_be16(state->VddcOffset);
3137
3138         return 0;
3139 }
3140
3141 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3142                                     u32 engine_clock,
3143                                     SMU7_Discrete_GraphicsLevel *sclk)
3144 {
3145         struct ci_power_info *pi = ci_get_pi(rdev);
3146         struct atom_clock_dividers dividers;
3147         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3148         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3149         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3150         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3151         u32 reference_clock = rdev->clock.spll.reference_freq;
3152         u32 reference_divider;
3153         u32 fbdiv;
3154         int ret;
3155
3156         ret = radeon_atom_get_clock_dividers(rdev,
3157                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3158                                              engine_clock, false, &dividers);
3159         if (ret)
3160                 return ret;
3161
3162         reference_divider = 1 + dividers.ref_div;
3163         fbdiv = dividers.fb_div & 0x3FFFFFF;
3164
3165         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3166         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3167         spll_func_cntl_3 |= SPLL_DITHEN;
3168
3169         if (pi->caps_sclk_ss_support) {
3170                 struct radeon_atom_ss ss;
3171                 u32 vco_freq = engine_clock * dividers.post_div;
3172
3173                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3174                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3175                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3176                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3177
3178                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
3179                         cg_spll_spread_spectrum |= CLK_S(clk_s);
3180                         cg_spll_spread_spectrum |= SSEN;
3181
3182                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3183                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3184                 }
3185         }
3186
3187         sclk->SclkFrequency = engine_clock;
3188         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3189         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3190         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3191         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
3192         sclk->SclkDid = (u8)dividers.post_divider;
3193
3194         return 0;
3195 }
3196
3197 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3198                                             u32 engine_clock,
3199                                             u16 sclk_activity_level_t,
3200                                             SMU7_Discrete_GraphicsLevel *graphic_level)
3201 {
3202         struct ci_power_info *pi = ci_get_pi(rdev);
3203         int ret;
3204
3205         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3206         if (ret)
3207                 return ret;
3208
3209         ret = ci_get_dependency_volt_by_clk(rdev,
3210                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3211                                             engine_clock, &graphic_level->MinVddc);
3212         if (ret)
3213                 return ret;
3214
3215         graphic_level->SclkFrequency = engine_clock;
3216
3217         graphic_level->Flags =  0;
3218         graphic_level->MinVddcPhases = 1;
3219
3220         if (pi->vddc_phase_shed_control)
3221                 ci_populate_phase_value_based_on_sclk(rdev,
3222                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3223                                                       engine_clock,
3224                                                       &graphic_level->MinVddcPhases);
3225
3226         graphic_level->ActivityLevel = sclk_activity_level_t;
3227
3228         graphic_level->CcPwrDynRm = 0;
3229         graphic_level->CcPwrDynRm1 = 0;
3230         graphic_level->EnabledForThrottle = 1;
3231         graphic_level->UpH = 0;
3232         graphic_level->DownH = 0;
3233         graphic_level->VoltageDownH = 0;
3234         graphic_level->PowerThrottle = 0;
3235
3236         if (pi->caps_sclk_ds)
3237                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3238                                                                                    engine_clock,
3239                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
3240
3241         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3242
3243         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3244         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3245         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3246         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3247         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3248         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3249         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3250         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3251         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3252         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3253         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3254
3255         return 0;
3256 }
3257
3258 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3259 {
3260         struct ci_power_info *pi = ci_get_pi(rdev);
3261         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3262         u32 level_array_address = pi->dpm_table_start +
3263                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3264         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3265                 SMU7_MAX_LEVELS_GRAPHICS;
3266         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3267         u32 i, ret;
3268
3269         memset(levels, 0, level_array_size);
3270
3271         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3272                 ret = ci_populate_single_graphic_level(rdev,
3273                                                        dpm_table->sclk_table.dpm_levels[i].value,
3274                                                        (u16)pi->activity_target[i],
3275                                                        &pi->smc_state_table.GraphicsLevel[i]);
3276                 if (ret)
3277                         return ret;
3278                 if (i > 1)
3279                         pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3280                 if (i == (dpm_table->sclk_table.count - 1))
3281                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3282                                 PPSMC_DISPLAY_WATERMARK_HIGH;
3283         }
3284         pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3285
3286         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3287         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3288                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3289
3290         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3291                                    (u8 *)levels, level_array_size,
3292                                    pi->sram_end);
3293         if (ret)
3294                 return ret;
3295
3296         return 0;
3297 }
3298
3299 static int ci_populate_ulv_state(struct radeon_device *rdev,
3300                                  SMU7_Discrete_Ulv *ulv_level)
3301 {
3302         return ci_populate_ulv_level(rdev, ulv_level);
3303 }
3304
3305 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3306 {
3307         struct ci_power_info *pi = ci_get_pi(rdev);
3308         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3309         u32 level_array_address = pi->dpm_table_start +
3310                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3311         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3312                 SMU7_MAX_LEVELS_MEMORY;
3313         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3314         u32 i, ret;
3315
3316         memset(levels, 0, level_array_size);
3317
3318         for (i = 0; i < dpm_table->mclk_table.count; i++) {
3319                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3320                         return -EINVAL;
3321                 ret = ci_populate_single_memory_level(rdev,
3322                                                       dpm_table->mclk_table.dpm_levels[i].value,
3323                                                       &pi->smc_state_table.MemoryLevel[i]);
3324                 if (ret)
3325                         return ret;
3326         }
3327
3328         pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3329
3330         if ((dpm_table->mclk_table.count >= 2) &&
3331             ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3332                 pi->smc_state_table.MemoryLevel[1].MinVddc =
3333                         pi->smc_state_table.MemoryLevel[0].MinVddc;
3334                 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3335                         pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3336         }
3337
3338         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3339
3340         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3341         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3342                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3343
3344         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3345                 PPSMC_DISPLAY_WATERMARK_HIGH;
3346
3347         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3348                                    (u8 *)levels, level_array_size,
3349                                    pi->sram_end);
3350         if (ret)
3351                 return ret;
3352
3353         return 0;
3354 }
3355
3356 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3357                                       struct ci_single_dpm_table* dpm_table,
3358                                       u32 count)
3359 {
3360         u32 i;
3361
3362         dpm_table->count = count;
3363         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3364                 dpm_table->dpm_levels[i].enabled = false;
3365 }
3366
3367 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3368                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
3369 {
3370         dpm_table->dpm_levels[index].value = pcie_gen;
3371         dpm_table->dpm_levels[index].param1 = pcie_lanes;
3372         dpm_table->dpm_levels[index].enabled = true;
3373 }
3374
3375 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3376 {
3377         struct ci_power_info *pi = ci_get_pi(rdev);
3378
3379         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3380                 return -EINVAL;
3381
3382         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3383                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3384                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3385         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3386                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3387                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3388         }
3389
3390         ci_reset_single_dpm_table(rdev,
3391                                   &pi->dpm_table.pcie_speed_table,
3392                                   SMU7_MAX_LEVELS_LINK);
3393
3394         if (rdev->family == CHIP_BONAIRE)
3395                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3396                                           pi->pcie_gen_powersaving.min,
3397                                           pi->pcie_lane_powersaving.max);
3398         else
3399                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3400                                           pi->pcie_gen_powersaving.min,
3401                                           pi->pcie_lane_powersaving.min);
3402         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3403                                   pi->pcie_gen_performance.min,
3404                                   pi->pcie_lane_performance.min);
3405         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3406                                   pi->pcie_gen_powersaving.min,
3407                                   pi->pcie_lane_powersaving.max);
3408         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3409                                   pi->pcie_gen_performance.min,
3410                                   pi->pcie_lane_performance.max);
3411         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3412                                   pi->pcie_gen_powersaving.max,
3413                                   pi->pcie_lane_powersaving.max);
3414         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3415                                   pi->pcie_gen_performance.max,
3416                                   pi->pcie_lane_performance.max);
3417
3418         pi->dpm_table.pcie_speed_table.count = 6;
3419
3420         return 0;
3421 }
3422
3423 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3424 {
3425         struct ci_power_info *pi = ci_get_pi(rdev);
3426         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3427                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3428         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3429                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3430         struct radeon_cac_leakage_table *std_voltage_table =
3431                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3432         u32 i;
3433
3434         if (allowed_sclk_vddc_table == NULL)
3435                 return -EINVAL;
3436         if (allowed_sclk_vddc_table->count < 1)
3437                 return -EINVAL;
3438         if (allowed_mclk_table == NULL)
3439                 return -EINVAL;
3440         if (allowed_mclk_table->count < 1)
3441                 return -EINVAL;
3442
3443         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3444
3445         ci_reset_single_dpm_table(rdev,
3446                                   &pi->dpm_table.sclk_table,
3447                                   SMU7_MAX_LEVELS_GRAPHICS);
3448         ci_reset_single_dpm_table(rdev,
3449                                   &pi->dpm_table.mclk_table,
3450                                   SMU7_MAX_LEVELS_MEMORY);
3451         ci_reset_single_dpm_table(rdev,
3452                                   &pi->dpm_table.vddc_table,
3453                                   SMU7_MAX_LEVELS_VDDC);
3454         ci_reset_single_dpm_table(rdev,
3455                                   &pi->dpm_table.vddci_table,
3456                                   SMU7_MAX_LEVELS_VDDCI);
3457         ci_reset_single_dpm_table(rdev,
3458                                   &pi->dpm_table.mvdd_table,
3459                                   SMU7_MAX_LEVELS_MVDD);
3460
3461         pi->dpm_table.sclk_table.count = 0;
3462         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3463                 if ((i == 0) ||
3464                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3465                      allowed_sclk_vddc_table->entries[i].clk)) {
3466                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3467                                 allowed_sclk_vddc_table->entries[i].clk;
3468                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3469                                 (i == 0) ? true : false;
3470                         pi->dpm_table.sclk_table.count++;
3471                 }
3472         }
3473
3474         pi->dpm_table.mclk_table.count = 0;
3475         for (i = 0; i < allowed_mclk_table->count; i++) {
3476                 if ((i == 0) ||
3477                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3478                      allowed_mclk_table->entries[i].clk)) {
3479                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3480                                 allowed_mclk_table->entries[i].clk;
3481                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3482                                 (i == 0) ? true : false;
3483                         pi->dpm_table.mclk_table.count++;
3484                 }
3485         }
3486
3487         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3488                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3489                         allowed_sclk_vddc_table->entries[i].v;
3490                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3491                         std_voltage_table->entries[i].leakage;
3492                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3493         }
3494         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3495
3496         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3497         if (allowed_mclk_table) {
3498                 for (i = 0; i < allowed_mclk_table->count; i++) {
3499                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3500                                 allowed_mclk_table->entries[i].v;
3501                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3502                 }
3503                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3504         }
3505
3506         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3507         if (allowed_mclk_table) {
3508                 for (i = 0; i < allowed_mclk_table->count; i++) {
3509                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3510                                 allowed_mclk_table->entries[i].v;
3511                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3512                 }
3513                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3514         }
3515
3516         ci_setup_default_pcie_tables(rdev);
3517
3518         return 0;
3519 }
3520
3521 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3522                               u32 value, u32 *boot_level)
3523 {
3524         u32 i;
3525         int ret = -EINVAL;
3526
3527         for(i = 0; i < table->count; i++) {
3528                 if (value == table->dpm_levels[i].value) {
3529                         *boot_level = i;
3530                         ret = 0;
3531                 }
3532         }
3533
3534         return ret;
3535 }
3536
3537 static int ci_init_smc_table(struct radeon_device *rdev)
3538 {
3539         struct ci_power_info *pi = ci_get_pi(rdev);
3540         struct ci_ulv_parm *ulv = &pi->ulv;
3541         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3542         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3543         int ret;
3544
3545         ret = ci_setup_default_dpm_tables(rdev);
3546         if (ret)
3547                 return ret;
3548
3549         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3550                 ci_populate_smc_voltage_tables(rdev, table);
3551
3552         ci_init_fps_limits(rdev);
3553
3554         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3555                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3556
3557         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3558                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3559
3560         if (pi->mem_gddr5)
3561                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3562
3563         if (ulv->supported) {
3564                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3565                 if (ret)
3566                         return ret;
3567                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3568         }
3569
3570         ret = ci_populate_all_graphic_levels(rdev);
3571         if (ret)
3572                 return ret;
3573
3574         ret = ci_populate_all_memory_levels(rdev);
3575         if (ret)
3576                 return ret;
3577
3578         ci_populate_smc_link_level(rdev, table);
3579
3580         ret = ci_populate_smc_acpi_level(rdev, table);
3581         if (ret)
3582                 return ret;
3583
3584         ret = ci_populate_smc_vce_level(rdev, table);
3585         if (ret)
3586                 return ret;
3587
3588         ret = ci_populate_smc_acp_level(rdev, table);
3589         if (ret)
3590                 return ret;
3591
3592         ret = ci_populate_smc_samu_level(rdev, table);
3593         if (ret)
3594                 return ret;
3595
3596         ret = ci_do_program_memory_timing_parameters(rdev);
3597         if (ret)
3598                 return ret;
3599
3600         ret = ci_populate_smc_uvd_level(rdev, table);
3601         if (ret)
3602                 return ret;
3603
3604         table->UvdBootLevel  = 0;
3605         table->VceBootLevel  = 0;
3606         table->AcpBootLevel  = 0;
3607         table->SamuBootLevel  = 0;
3608         table->GraphicsBootLevel  = 0;
3609         table->MemoryBootLevel  = 0;
3610
3611         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3612                                  pi->vbios_boot_state.sclk_bootup_value,
3613                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3614
3615         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3616                                  pi->vbios_boot_state.mclk_bootup_value,
3617                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3618
3619         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3620         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3621         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3622
3623         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3624
3625         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3626         if (ret)
3627                 return ret;
3628
3629         table->UVDInterval = 1;
3630         table->VCEInterval = 1;
3631         table->ACPInterval = 1;
3632         table->SAMUInterval = 1;
3633         table->GraphicsVoltageChangeEnable = 1;
3634         table->GraphicsThermThrottleEnable = 1;
3635         table->GraphicsInterval = 1;
3636         table->VoltageInterval = 1;
3637         table->ThermalInterval = 1;
3638         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3639                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3640         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3641                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3642         table->MemoryVoltageChangeEnable = 1;
3643         table->MemoryInterval = 1;
3644         table->VoltageResponseTime = 0;
3645         table->VddcVddciDelta = 4000;
3646         table->PhaseResponseTime = 0;
3647         table->MemoryThermThrottleEnable = 1;
3648         table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3649         table->PCIeGenInterval = 1;
3650         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3651                 table->SVI2Enable  = 1;
3652         else
3653                 table->SVI2Enable  = 0;
3654
3655         table->ThermGpio = 17;
3656         table->SclkStepSize = 0x4000;
3657
3658         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3659         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3660         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3661         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3662         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3663         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3664         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3665         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3666         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3667         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3668         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3669         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3670         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3671         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3672
3673         ret = ci_copy_bytes_to_smc(rdev,
3674                                    pi->dpm_table_start +
3675                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3676                                    (u8 *)&table->SystemFlags,
3677                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3678                                    pi->sram_end);
3679         if (ret)
3680                 return ret;
3681
3682         return 0;
3683 }
3684
3685 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3686                                       struct ci_single_dpm_table *dpm_table,
3687                                       u32 low_limit, u32 high_limit)
3688 {
3689         u32 i;
3690
3691         for (i = 0; i < dpm_table->count; i++) {
3692                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3693                     (dpm_table->dpm_levels[i].value > high_limit))
3694                         dpm_table->dpm_levels[i].enabled = false;
3695                 else
3696                         dpm_table->dpm_levels[i].enabled = true;
3697         }
3698 }
3699
3700 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3701                                     u32 speed_low, u32 lanes_low,
3702                                     u32 speed_high, u32 lanes_high)
3703 {
3704         struct ci_power_info *pi = ci_get_pi(rdev);
3705         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3706         u32 i, j;
3707
3708         for (i = 0; i < pcie_table->count; i++) {
3709                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3710                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3711                     (pcie_table->dpm_levels[i].value > speed_high) ||
3712                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3713                         pcie_table->dpm_levels[i].enabled = false;
3714                 else
3715                         pcie_table->dpm_levels[i].enabled = true;
3716         }
3717
3718         for (i = 0; i < pcie_table->count; i++) {
3719                 if (pcie_table->dpm_levels[i].enabled) {
3720                         for (j = i + 1; j < pcie_table->count; j++) {
3721                                 if (pcie_table->dpm_levels[j].enabled) {
3722                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3723                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3724                                                 pcie_table->dpm_levels[j].enabled = false;
3725                                 }
3726                         }
3727                 }
3728         }
3729 }
3730
3731 static int ci_trim_dpm_states(struct radeon_device *rdev,
3732                               struct radeon_ps *radeon_state)
3733 {
3734         struct ci_ps *state = ci_get_ps(radeon_state);
3735         struct ci_power_info *pi = ci_get_pi(rdev);
3736         u32 high_limit_count;
3737
3738         if (state->performance_level_count < 1)
3739                 return -EINVAL;
3740
3741         if (state->performance_level_count == 1)
3742                 high_limit_count = 0;
3743         else
3744                 high_limit_count = 1;
3745
3746         ci_trim_single_dpm_states(rdev,
3747                                   &pi->dpm_table.sclk_table,
3748                                   state->performance_levels[0].sclk,
3749                                   state->performance_levels[high_limit_count].sclk);
3750
3751         ci_trim_single_dpm_states(rdev,
3752                                   &pi->dpm_table.mclk_table,
3753                                   state->performance_levels[0].mclk,
3754                                   state->performance_levels[high_limit_count].mclk);
3755
3756         ci_trim_pcie_dpm_states(rdev,
3757                                 state->performance_levels[0].pcie_gen,
3758                                 state->performance_levels[0].pcie_lane,
3759                                 state->performance_levels[high_limit_count].pcie_gen,
3760                                 state->performance_levels[high_limit_count].pcie_lane);
3761
3762         return 0;
3763 }
3764
3765 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3766 {
3767         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3768                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3769         struct radeon_clock_voltage_dependency_table *vddc_table =
3770                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3771         u32 requested_voltage = 0;
3772         u32 i;
3773
3774         if (disp_voltage_table == NULL)
3775                 return -EINVAL;
3776         if (!disp_voltage_table->count)
3777                 return -EINVAL;
3778
3779         for (i = 0; i < disp_voltage_table->count; i++) {
3780                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3781                         requested_voltage = disp_voltage_table->entries[i].v;
3782         }
3783
3784         for (i = 0; i < vddc_table->count; i++) {
3785                 if (requested_voltage <= vddc_table->entries[i].v) {
3786                         requested_voltage = vddc_table->entries[i].v;
3787                         return (ci_send_msg_to_smc_with_parameter(rdev,
3788                                                                   PPSMC_MSG_VddC_Request,
3789                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3790                                 0 : -EINVAL;
3791                 }
3792         }
3793
3794         return -EINVAL;
3795 }
3796
3797 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3798 {
3799         struct ci_power_info *pi = ci_get_pi(rdev);
3800         PPSMC_Result result;
3801
3802         ci_apply_disp_minimum_voltage_request(rdev);
3803
3804         if (!pi->sclk_dpm_key_disabled) {
3805                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3806                         result = ci_send_msg_to_smc_with_parameter(rdev,
3807                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3808                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3809                         if (result != PPSMC_Result_OK)
3810                                 return -EINVAL;
3811                 }
3812         }
3813
3814         if (!pi->mclk_dpm_key_disabled) {
3815                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3816                         result = ci_send_msg_to_smc_with_parameter(rdev,
3817                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3818                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3819                         if (result != PPSMC_Result_OK)
3820                                 return -EINVAL;
3821                 }
3822         }
3823 #if 0
3824         if (!pi->pcie_dpm_key_disabled) {
3825                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3826                         result = ci_send_msg_to_smc_with_parameter(rdev,
3827                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3828                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3829                         if (result != PPSMC_Result_OK)
3830                                 return -EINVAL;
3831                 }
3832         }
3833 #endif
3834         return 0;
3835 }
3836
3837 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3838                                                    struct radeon_ps *radeon_state)
3839 {
3840         struct ci_power_info *pi = ci_get_pi(rdev);
3841         struct ci_ps *state = ci_get_ps(radeon_state);
3842         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3843         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3844         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3845         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3846         u32 i;
3847
3848         pi->need_update_smu7_dpm_table = 0;
3849
3850         for (i = 0; i < sclk_table->count; i++) {
3851                 if (sclk == sclk_table->dpm_levels[i].value)
3852                         break;
3853         }
3854
3855         if (i >= sclk_table->count) {
3856                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3857         } else {
3858                 /* XXX The current code always reprogrammed the sclk levels,
3859                  * but we don't currently handle disp sclk requirements
3860                  * so just skip it.
3861                  */
3862                 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3863                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3864         }
3865
3866         for (i = 0; i < mclk_table->count; i++) {
3867                 if (mclk == mclk_table->dpm_levels[i].value)
3868                         break;
3869         }
3870
3871         if (i >= mclk_table->count)
3872                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3873
3874         if (rdev->pm.dpm.current_active_crtc_count !=
3875             rdev->pm.dpm.new_active_crtc_count)
3876                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3877 }
3878
3879 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3880                                                        struct radeon_ps *radeon_state)
3881 {
3882         struct ci_power_info *pi = ci_get_pi(rdev);
3883         struct ci_ps *state = ci_get_ps(radeon_state);
3884         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3885         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3886         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3887         int ret;
3888
3889         if (!pi->need_update_smu7_dpm_table)
3890                 return 0;
3891
3892         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3893                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3894
3895         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3896                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3897
3898         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3899                 ret = ci_populate_all_graphic_levels(rdev);
3900                 if (ret)
3901                         return ret;
3902         }
3903
3904         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3905                 ret = ci_populate_all_memory_levels(rdev);
3906                 if (ret)
3907                         return ret;
3908         }
3909
3910         return 0;
3911 }
3912
3913 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3914 {
3915         struct ci_power_info *pi = ci_get_pi(rdev);
3916         const struct radeon_clock_and_voltage_limits *max_limits;
3917         int i;
3918
3919         if (rdev->pm.dpm.ac_power)
3920                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3921         else
3922                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3923
3924         if (enable) {
3925                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3926
3927                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3928                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3929                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3930
3931                                 if (!pi->caps_uvd_dpm)
3932                                         break;
3933                         }
3934                 }
3935
3936                 ci_send_msg_to_smc_with_parameter(rdev,
3937                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3938                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3939
3940                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3941                         pi->uvd_enabled = true;
3942                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3943                         ci_send_msg_to_smc_with_parameter(rdev,
3944                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3945                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3946                 }
3947         } else {
3948                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3949                         pi->uvd_enabled = false;
3950                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3951                         ci_send_msg_to_smc_with_parameter(rdev,
3952                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3953                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3954                 }
3955         }
3956
3957         return (ci_send_msg_to_smc(rdev, enable ?
3958                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3959                 0 : -EINVAL;
3960 }
3961
3962 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3963 {
3964         struct ci_power_info *pi = ci_get_pi(rdev);
3965         const struct radeon_clock_and_voltage_limits *max_limits;
3966         int i;
3967
3968         if (rdev->pm.dpm.ac_power)
3969                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3970         else
3971                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3972
3973         if (enable) {
3974                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3975                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3976                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3977                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3978
3979                                 if (!pi->caps_vce_dpm)
3980                                         break;
3981                         }
3982                 }
3983
3984                 ci_send_msg_to_smc_with_parameter(rdev,
3985                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3986                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3987         }
3988
3989         return (ci_send_msg_to_smc(rdev, enable ?
3990                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3991                 0 : -EINVAL;
3992 }
3993
3994 #if 0
3995 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3996 {
3997         struct ci_power_info *pi = ci_get_pi(rdev);
3998         const struct radeon_clock_and_voltage_limits *max_limits;
3999         int i;
4000
4001         if (rdev->pm.dpm.ac_power)
4002                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4003         else
4004                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4005
4006         if (enable) {
4007                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4008                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4009                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4010                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4011
4012                                 if (!pi->caps_samu_dpm)
4013                                         break;
4014                         }
4015                 }
4016
4017                 ci_send_msg_to_smc_with_parameter(rdev,
4018                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
4019                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4020         }
4021         return (ci_send_msg_to_smc(rdev, enable ?
4022                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4023                 0 : -EINVAL;
4024 }
4025
4026 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4027 {
4028         struct ci_power_info *pi = ci_get_pi(rdev);
4029         const struct radeon_clock_and_voltage_limits *max_limits;
4030         int i;
4031
4032         if (rdev->pm.dpm.ac_power)
4033                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4034         else
4035                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4036
4037         if (enable) {
4038                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4039                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4040                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4041                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4042
4043                                 if (!pi->caps_acp_dpm)
4044                                         break;
4045                         }
4046                 }
4047
4048                 ci_send_msg_to_smc_with_parameter(rdev,
4049                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
4050                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4051         }
4052
4053         return (ci_send_msg_to_smc(rdev, enable ?
4054                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4055                 0 : -EINVAL;
4056 }
4057 #endif
4058
4059 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4060 {
4061         struct ci_power_info *pi = ci_get_pi(rdev);
4062         u32 tmp;
4063
4064         if (!gate) {
4065                 if (pi->caps_uvd_dpm ||
4066                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4067                         pi->smc_state_table.UvdBootLevel = 0;
4068                 else
4069                         pi->smc_state_table.UvdBootLevel =
4070                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4071
4072                 tmp = RREG32_SMC(DPM_TABLE_475);
4073                 tmp &= ~UvdBootLevel_MASK;
4074                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4075                 WREG32_SMC(DPM_TABLE_475, tmp);
4076         }
4077
4078         return ci_enable_uvd_dpm(rdev, !gate);
4079 }
4080
4081 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4082 {
4083         u8 i;
4084         u32 min_evclk = 30000; /* ??? */
4085         struct radeon_vce_clock_voltage_dependency_table *table =
4086                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4087
4088         for (i = 0; i < table->count; i++) {
4089                 if (table->entries[i].evclk >= min_evclk)
4090                         return i;
4091         }
4092
4093         return table->count - 1;
4094 }
4095
4096 static int ci_update_vce_dpm(struct radeon_device *rdev,
4097                              struct radeon_ps *radeon_new_state,
4098                              struct radeon_ps *radeon_current_state)
4099 {
4100         struct ci_power_info *pi = ci_get_pi(rdev);
4101         int ret = 0;
4102         u32 tmp;
4103
4104         if (radeon_current_state->evclk != radeon_new_state->evclk) {
4105                 if (radeon_new_state->evclk) {
4106                         /* turn the clocks on when encoding */
4107                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4108
4109                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4110                         tmp = RREG32_SMC(DPM_TABLE_475);
4111                         tmp &= ~VceBootLevel_MASK;
4112                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4113                         WREG32_SMC(DPM_TABLE_475, tmp);
4114
4115                         ret = ci_enable_vce_dpm(rdev, true);
4116                 } else {
4117                         /* turn the clocks off when not encoding */
4118                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4119
4120                         ret = ci_enable_vce_dpm(rdev, false);
4121                 }
4122         }
4123         return ret;
4124 }
4125
4126 #if 0
4127 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4128 {
4129         return ci_enable_samu_dpm(rdev, gate);
4130 }
4131
4132 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4133 {
4134         struct ci_power_info *pi = ci_get_pi(rdev);
4135         u32 tmp;
4136
4137         if (!gate) {
4138                 pi->smc_state_table.AcpBootLevel = 0;
4139
4140                 tmp = RREG32_SMC(DPM_TABLE_475);
4141                 tmp &= ~AcpBootLevel_MASK;
4142                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4143                 WREG32_SMC(DPM_TABLE_475, tmp);
4144         }
4145
4146         return ci_enable_acp_dpm(rdev, !gate);
4147 }
4148 #endif
4149
4150 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4151                                              struct radeon_ps *radeon_state)
4152 {
4153         struct ci_power_info *pi = ci_get_pi(rdev);
4154         int ret;
4155
4156         ret = ci_trim_dpm_states(rdev, radeon_state);
4157         if (ret)
4158                 return ret;
4159
4160         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4161                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4162         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4163                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4164         pi->last_mclk_dpm_enable_mask =
4165                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4166         if (pi->uvd_enabled) {
4167                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4168                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4169         }
4170         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4171                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4172
4173         return 0;
4174 }
4175
4176 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4177                                        u32 level_mask)
4178 {
4179         u32 level = 0;
4180
4181         while ((level_mask & (1 << level)) == 0)
4182                 level++;
4183
4184         return level;
4185 }
4186
4187
4188 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4189                                    enum radeon_dpm_forced_level level)
4190 {
4191         struct ci_power_info *pi = ci_get_pi(rdev);
4192         u32 tmp, levels, i;
4193         int ret;
4194
4195         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4196                 if ((!pi->pcie_dpm_key_disabled) &&
4197                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4198                         levels = 0;
4199                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4200                         while (tmp >>= 1)
4201                                 levels++;
4202                         if (levels) {
4203                                 ret = ci_dpm_force_state_pcie(rdev, level);
4204                                 if (ret)
4205                                         return ret;
4206                                 for (i = 0; i < rdev->usec_timeout; i++) {
4207                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4208                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4209                                         if (tmp == levels)
4210                                                 break;
4211                                         udelay(1);
4212                                 }
4213                         }
4214                 }
4215                 if ((!pi->sclk_dpm_key_disabled) &&
4216                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4217                         levels = 0;
4218                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4219                         while (tmp >>= 1)
4220                                 levels++;
4221                         if (levels) {
4222                                 ret = ci_dpm_force_state_sclk(rdev, levels);
4223                                 if (ret)
4224                                         return ret;
4225                                 for (i = 0; i < rdev->usec_timeout; i++) {
4226                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4227                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4228                                         if (tmp == levels)
4229                                                 break;
4230                                         udelay(1);
4231                                 }
4232                         }
4233                 }
4234                 if ((!pi->mclk_dpm_key_disabled) &&
4235                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4236                         levels = 0;
4237                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4238                         while (tmp >>= 1)
4239                                 levels++;
4240                         if (levels) {
4241                                 ret = ci_dpm_force_state_mclk(rdev, levels);
4242                                 if (ret)
4243                                         return ret;
4244                                 for (i = 0; i < rdev->usec_timeout; i++) {
4245                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4246                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4247                                         if (tmp == levels)
4248                                                 break;
4249                                         udelay(1);
4250                                 }
4251                         }
4252                 }
4253         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4254                 if ((!pi->sclk_dpm_key_disabled) &&
4255                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4256                         levels = ci_get_lowest_enabled_level(rdev,
4257                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4258                         ret = ci_dpm_force_state_sclk(rdev, levels);
4259                         if (ret)
4260                                 return ret;
4261                         for (i = 0; i < rdev->usec_timeout; i++) {
4262                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4263                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4264                                 if (tmp == levels)
4265                                         break;
4266                                 udelay(1);
4267                         }
4268                 }
4269                 if ((!pi->mclk_dpm_key_disabled) &&
4270                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4271                         levels = ci_get_lowest_enabled_level(rdev,
4272                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4273                         ret = ci_dpm_force_state_mclk(rdev, levels);
4274                         if (ret)
4275                                 return ret;
4276                         for (i = 0; i < rdev->usec_timeout; i++) {
4277                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4278                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4279                                 if (tmp == levels)
4280                                         break;
4281                                 udelay(1);
4282                         }
4283                 }
4284                 if ((!pi->pcie_dpm_key_disabled) &&
4285                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4286                         levels = ci_get_lowest_enabled_level(rdev,
4287                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4288                         ret = ci_dpm_force_state_pcie(rdev, levels);
4289                         if (ret)
4290                                 return ret;
4291                         for (i = 0; i < rdev->usec_timeout; i++) {
4292                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4293                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4294                                 if (tmp == levels)
4295                                         break;
4296                                 udelay(1);
4297                         }
4298                 }
4299         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4300                 if (!pi->pcie_dpm_key_disabled) {
4301                         PPSMC_Result smc_result;
4302
4303                         smc_result = ci_send_msg_to_smc(rdev,
4304                                                         PPSMC_MSG_PCIeDPM_UnForceLevel);
4305                         if (smc_result != PPSMC_Result_OK)
4306                                 return -EINVAL;
4307                 }
4308                 ret = ci_upload_dpm_level_enable_mask(rdev);
4309                 if (ret)
4310                         return ret;
4311         }
4312
4313         rdev->pm.dpm.forced_level = level;
4314
4315         return 0;
4316 }
4317
4318 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4319                                        struct ci_mc_reg_table *table)
4320 {
4321         struct ci_power_info *pi = ci_get_pi(rdev);
4322         u8 i, j, k;
4323         u32 temp_reg;
4324
4325         for (i = 0, j = table->last; i < table->last; i++) {
4326                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4327                         return -EINVAL;
4328                 switch(table->mc_reg_address[i].s1 << 2) {
4329                 case MC_SEQ_MISC1:
4330                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
4331                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4332                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4333                         for (k = 0; k < table->num_entries; k++) {
4334                                 table->mc_reg_table_entry[k].mc_data[j] =
4335                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4336                         }
4337                         j++;
4338                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4339                                 return -EINVAL;
4340
4341                         temp_reg = RREG32(MC_PMG_CMD_MRS);
4342                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4343                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4344                         for (k = 0; k < table->num_entries; k++) {
4345                                 table->mc_reg_table_entry[k].mc_data[j] =
4346                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4347                                 if (!pi->mem_gddr5)
4348                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4349                         }
4350                         j++;
4351                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4352                                 return -EINVAL;
4353
4354                         if (!pi->mem_gddr5) {
4355                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4356                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4357                                 for (k = 0; k < table->num_entries; k++) {
4358                                         table->mc_reg_table_entry[k].mc_data[j] =
4359                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4360                                 }
4361                                 j++;
4362                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4363                                         return -EINVAL;
4364                         }
4365                         break;
4366                 case MC_SEQ_RESERVE_M:
4367                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
4368                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4369                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4370                         for (k = 0; k < table->num_entries; k++) {
4371                                 table->mc_reg_table_entry[k].mc_data[j] =
4372                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4373                         }
4374                         j++;
4375                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4376                                 return -EINVAL;
4377                         break;
4378                 default:
4379                         break;
4380                 }
4381
4382         }
4383
4384         table->last = j;
4385
4386         return 0;
4387 }
4388
4389 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4390 {
4391         bool result = true;
4392
4393         switch(in_reg) {
4394         case MC_SEQ_RAS_TIMING >> 2:
4395                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4396                 break;
4397         case MC_SEQ_DLL_STBY >> 2:
4398                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4399                 break;
4400         case MC_SEQ_G5PDX_CMD0 >> 2:
4401                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4402                 break;
4403         case MC_SEQ_G5PDX_CMD1 >> 2:
4404                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4405                 break;
4406         case MC_SEQ_G5PDX_CTRL >> 2:
4407                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4408                 break;
4409         case MC_SEQ_CAS_TIMING >> 2:
4410                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4411                 break;
4412         case MC_SEQ_MISC_TIMING >> 2:
4413                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4414                 break;
4415         case MC_SEQ_MISC_TIMING2 >> 2:
4416                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4417                 break;
4418         case MC_SEQ_PMG_DVS_CMD >> 2:
4419                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4420                 break;
4421         case MC_SEQ_PMG_DVS_CTL >> 2:
4422                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4423                 break;
4424         case MC_SEQ_RD_CTL_D0 >> 2:
4425                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4426                 break;
4427         case MC_SEQ_RD_CTL_D1 >> 2:
4428                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4429                 break;
4430         case MC_SEQ_WR_CTL_D0 >> 2:
4431                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4432                 break;
4433         case MC_SEQ_WR_CTL_D1 >> 2:
4434                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4435                 break;
4436         case MC_PMG_CMD_EMRS >> 2:
4437                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4438                 break;
4439         case MC_PMG_CMD_MRS >> 2:
4440                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4441                 break;
4442         case MC_PMG_CMD_MRS1 >> 2:
4443                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4444                 break;
4445         case MC_SEQ_PMG_TIMING >> 2:
4446                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4447                 break;
4448         case MC_PMG_CMD_MRS2 >> 2:
4449                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4450                 break;
4451         case MC_SEQ_WR_CTL_2 >> 2:
4452                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4453                 break;
4454         default:
4455                 result = false;
4456                 break;
4457         }
4458
4459         return result;
4460 }
4461
4462 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4463 {
4464         u8 i, j;
4465
4466         for (i = 0; i < table->last; i++) {
4467                 for (j = 1; j < table->num_entries; j++) {
4468                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4469                             table->mc_reg_table_entry[j].mc_data[i]) {
4470                                 table->valid_flag |= 1 << i;
4471                                 break;
4472                         }
4473                 }
4474         }
4475 }
4476
4477 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4478 {
4479         u32 i;
4480         u16 address;
4481
4482         for (i = 0; i < table->last; i++) {
4483                 table->mc_reg_address[i].s0 =
4484                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4485                         address : table->mc_reg_address[i].s1;
4486         }
4487 }
4488
4489 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4490                                       struct ci_mc_reg_table *ci_table)
4491 {
4492         u8 i, j;
4493
4494         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4495                 return -EINVAL;
4496         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4497                 return -EINVAL;
4498
4499         for (i = 0; i < table->last; i++)
4500                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4501
4502         ci_table->last = table->last;
4503
4504         for (i = 0; i < table->num_entries; i++) {
4505                 ci_table->mc_reg_table_entry[i].mclk_max =
4506                         table->mc_reg_table_entry[i].mclk_max;
4507                 for (j = 0; j < table->last; j++)
4508                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4509                                 table->mc_reg_table_entry[i].mc_data[j];
4510         }
4511         ci_table->num_entries = table->num_entries;
4512
4513         return 0;
4514 }
4515
4516 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4517                                        struct ci_mc_reg_table *table)
4518 {
4519         u8 i, k;
4520         u32 tmp;
4521         bool patch;
4522
4523         tmp = RREG32(MC_SEQ_MISC0);
4524         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4525
4526         if (patch &&
4527             ((rdev->pdev->device == 0x67B0) ||
4528              (rdev->pdev->device == 0x67B1))) {
4529                 for (i = 0; i < table->last; i++) {
4530                         if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4531                                 return -EINVAL;
4532                         switch(table->mc_reg_address[i].s1 >> 2) {
4533                         case MC_SEQ_MISC1:
4534                                 for (k = 0; k < table->num_entries; k++) {
4535                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4536                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4537                                                 table->mc_reg_table_entry[k].mc_data[i] =
4538                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4539                                                         0x00000007;
4540                                 }
4541                                 break;
4542                         case MC_SEQ_WR_CTL_D0:
4543                                 for (k = 0; k < table->num_entries; k++) {
4544                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4545                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4546                                                 table->mc_reg_table_entry[k].mc_data[i] =
4547                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4548                                                         0x0000D0DD;
4549                                 }
4550                                 break;
4551                         case MC_SEQ_WR_CTL_D1:
4552                                 for (k = 0; k < table->num_entries; k++) {
4553                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4554                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4555                                                 table->mc_reg_table_entry[k].mc_data[i] =
4556                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4557                                                         0x0000D0DD;
4558                                 }
4559                                 break;
4560                         case MC_SEQ_WR_CTL_2:
4561                                 for (k = 0; k < table->num_entries; k++) {
4562                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4563                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4564                                                 table->mc_reg_table_entry[k].mc_data[i] = 0;
4565                                 }
4566                                 break;
4567                         case MC_SEQ_CAS_TIMING:
4568                                 for (k = 0; k < table->num_entries; k++) {
4569                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4570                                                 table->mc_reg_table_entry[k].mc_data[i] =
4571                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4572                                                         0x000C0140;
4573                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4574                                                 table->mc_reg_table_entry[k].mc_data[i] =
4575                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4576                                                         0x000C0150;
4577                                 }
4578                                 break;
4579                         case MC_SEQ_MISC_TIMING:
4580                                 for (k = 0; k < table->num_entries; k++) {
4581                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4582                                                 table->mc_reg_table_entry[k].mc_data[i] =
4583                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4584                                                         0x00000030;
4585                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4586                                                 table->mc_reg_table_entry[k].mc_data[i] =
4587                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4588                                                         0x00000035;
4589                                 }
4590                                 break;
4591                         default:
4592                                 break;
4593                         }
4594                 }
4595
4596                 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4597                 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4598                 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4599                 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4600                 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4601         }
4602
4603         return 0;
4604 }
4605
4606 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4607 {
4608         struct ci_power_info *pi = ci_get_pi(rdev);
4609         struct atom_mc_reg_table *table;
4610         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4611         u8 module_index = rv770_get_memory_module_index(rdev);
4612         int ret;
4613
4614         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4615         if (!table)
4616                 return -ENOMEM;
4617
4618         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4619         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4620         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4621         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4622         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4623         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4624         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4625         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4626         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4627         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4628         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4629         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4630         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4631         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4632         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4633         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4634         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4635         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4636         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4637         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4638
4639         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4640         if (ret)
4641                 goto init_mc_done;
4642
4643         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4644         if (ret)
4645                 goto init_mc_done;
4646
4647         ci_set_s0_mc_reg_index(ci_table);
4648
4649         ret = ci_register_patching_mc_seq(rdev, ci_table);
4650         if (ret)
4651                 goto init_mc_done;
4652
4653         ret = ci_set_mc_special_registers(rdev, ci_table);
4654         if (ret)
4655                 goto init_mc_done;
4656
4657         ci_set_valid_flag(ci_table);
4658
4659 init_mc_done:
4660         kfree(table);
4661
4662         return ret;
4663 }
4664
4665 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4666                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4667 {
4668         struct ci_power_info *pi = ci_get_pi(rdev);
4669         u32 i, j;
4670
4671         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4672                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4673                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4674                                 return -EINVAL;
4675                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4676                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4677                         i++;
4678                 }
4679         }
4680
4681         mc_reg_table->last = (u8)i;
4682
4683         return 0;
4684 }
4685
4686 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4687                                     SMU7_Discrete_MCRegisterSet *data,
4688                                     u32 num_entries, u32 valid_flag)
4689 {
4690         u32 i, j;
4691
4692         for (i = 0, j = 0; j < num_entries; j++) {
4693                 if (valid_flag & (1 << j)) {
4694                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4695                         i++;
4696                 }
4697         }
4698 }
4699
4700 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4701                                                  const u32 memory_clock,
4702                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4703 {
4704         struct ci_power_info *pi = ci_get_pi(rdev);
4705         u32 i = 0;
4706
4707         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4708                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4709                         break;
4710         }
4711
4712         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4713                 --i;
4714
4715         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4716                                 mc_reg_table_data, pi->mc_reg_table.last,
4717                                 pi->mc_reg_table.valid_flag);
4718 }
4719
4720 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4721                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4722 {
4723         struct ci_power_info *pi = ci_get_pi(rdev);
4724         u32 i;
4725
4726         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4727                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4728                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4729                                                      &mc_reg_table->data[i]);
4730 }
4731
4732 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4733 {
4734         struct ci_power_info *pi = ci_get_pi(rdev);
4735         int ret;
4736
4737         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4738
4739         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4740         if (ret)
4741                 return ret;
4742         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4743
4744         return ci_copy_bytes_to_smc(rdev,
4745                                     pi->mc_reg_table_start,
4746                                     (u8 *)&pi->smc_mc_reg_table,
4747                                     sizeof(SMU7_Discrete_MCRegisters),
4748                                     pi->sram_end);
4749 }
4750
4751 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4752 {
4753         struct ci_power_info *pi = ci_get_pi(rdev);
4754
4755         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4756                 return 0;
4757
4758         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4759
4760         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4761
4762         return ci_copy_bytes_to_smc(rdev,
4763                                     pi->mc_reg_table_start +
4764                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4765                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4766                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4767                                     pi->dpm_table.mclk_table.count,
4768                                     pi->sram_end);
4769 }
4770
4771 static void ci_enable_voltage_control(struct radeon_device *rdev)
4772 {
4773         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4774
4775         tmp |= VOLT_PWRMGT_EN;
4776         WREG32_SMC(GENERAL_PWRMGT, tmp);
4777 }
4778
4779 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4780                                                       struct radeon_ps *radeon_state)
4781 {
4782         struct ci_ps *state = ci_get_ps(radeon_state);
4783         int i;
4784         u16 pcie_speed, max_speed = 0;
4785
4786         for (i = 0; i < state->performance_level_count; i++) {
4787                 pcie_speed = state->performance_levels[i].pcie_gen;
4788                 if (max_speed < pcie_speed)
4789                         max_speed = pcie_speed;
4790         }
4791
4792         return max_speed;
4793 }
4794
4795 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4796 {
4797         u32 speed_cntl = 0;
4798
4799         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4800         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4801
4802         return (u16)speed_cntl;
4803 }
4804
4805 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4806 {
4807         u32 link_width = 0;
4808
4809         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4810         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4811
4812         switch (link_width) {
4813         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4814                 return 1;
4815         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4816                 return 2;
4817         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4818                 return 4;
4819         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4820                 return 8;
4821         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4822                 /* not actually supported */
4823                 return 12;
4824         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4825         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4826         default:
4827                 return 16;
4828         }
4829 }
4830
4831 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4832                                                              struct radeon_ps *radeon_new_state,
4833                                                              struct radeon_ps *radeon_current_state)
4834 {
4835         struct ci_power_info *pi = ci_get_pi(rdev);
4836         enum radeon_pcie_gen target_link_speed =
4837                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4838         enum radeon_pcie_gen current_link_speed;
4839
4840         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4841                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4842         else
4843                 current_link_speed = pi->force_pcie_gen;
4844
4845         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4846         pi->pspp_notify_required = false;
4847         if (target_link_speed > current_link_speed) {
4848                 switch (target_link_speed) {
4849 #ifdef CONFIG_ACPI
4850                 case RADEON_PCIE_GEN3:
4851                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4852                                 break;
4853                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4854                         if (current_link_speed == RADEON_PCIE_GEN2)
4855                                 break;
4856                 case RADEON_PCIE_GEN2:
4857                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4858                                 break;
4859 #endif
4860                 default:
4861                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4862                         break;
4863                 }
4864         } else {
4865                 if (target_link_speed < current_link_speed)
4866                         pi->pspp_notify_required = true;
4867         }
4868 }
4869
4870 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4871                                                            struct radeon_ps *radeon_new_state,
4872                                                            struct radeon_ps *radeon_current_state)
4873 {
4874         struct ci_power_info *pi = ci_get_pi(rdev);
4875         enum radeon_pcie_gen target_link_speed =
4876                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4877         u8 request;
4878
4879         if (pi->pspp_notify_required) {
4880                 if (target_link_speed == RADEON_PCIE_GEN3)
4881                         request = PCIE_PERF_REQ_PECI_GEN3;
4882                 else if (target_link_speed == RADEON_PCIE_GEN2)
4883                         request = PCIE_PERF_REQ_PECI_GEN2;
4884                 else
4885                         request = PCIE_PERF_REQ_PECI_GEN1;
4886
4887                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4888                     (ci_get_current_pcie_speed(rdev) > 0))
4889                         return;
4890
4891 #ifdef CONFIG_ACPI
4892                 radeon_acpi_pcie_performance_request(rdev, request, false);
4893 #endif
4894         }
4895 }
4896
4897 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4898 {
4899         struct ci_power_info *pi = ci_get_pi(rdev);
4900         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4901                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4902         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4903                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4904         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4905                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4906
4907         if (allowed_sclk_vddc_table == NULL)
4908                 return -EINVAL;
4909         if (allowed_sclk_vddc_table->count < 1)
4910                 return -EINVAL;
4911         if (allowed_mclk_vddc_table == NULL)
4912                 return -EINVAL;
4913         if (allowed_mclk_vddc_table->count < 1)
4914                 return -EINVAL;
4915         if (allowed_mclk_vddci_table == NULL)
4916                 return -EINVAL;
4917         if (allowed_mclk_vddci_table->count < 1)
4918                 return -EINVAL;
4919
4920         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4921         pi->max_vddc_in_pp_table =
4922                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4923
4924         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4925         pi->max_vddci_in_pp_table =
4926                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4927
4928         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4929                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4930         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4931                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4932         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4933                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4934         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4935                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4936
4937         return 0;
4938 }
4939
4940 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4941 {
4942         struct ci_power_info *pi = ci_get_pi(rdev);
4943         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4944         u32 leakage_index;
4945
4946         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4947                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4948                         *vddc = leakage_table->actual_voltage[leakage_index];
4949                         break;
4950                 }
4951         }
4952 }
4953
4954 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4955 {
4956         struct ci_power_info *pi = ci_get_pi(rdev);
4957         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4958         u32 leakage_index;
4959
4960         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4961                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4962                         *vddci = leakage_table->actual_voltage[leakage_index];
4963                         break;
4964                 }
4965         }
4966 }
4967
4968 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4969                                                                       struct radeon_clock_voltage_dependency_table *table)
4970 {
4971         u32 i;
4972
4973         if (table) {
4974                 for (i = 0; i < table->count; i++)
4975                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4976         }
4977 }
4978
4979 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4980                                                                        struct radeon_clock_voltage_dependency_table *table)
4981 {
4982         u32 i;
4983
4984         if (table) {
4985                 for (i = 0; i < table->count; i++)
4986                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4987         }
4988 }
4989
4990 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4991                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4992 {
4993         u32 i;
4994
4995         if (table) {
4996                 for (i = 0; i < table->count; i++)
4997                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4998         }
4999 }
5000
5001 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
5002                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
5003 {
5004         u32 i;
5005
5006         if (table) {
5007                 for (i = 0; i < table->count; i++)
5008                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5009         }
5010 }
5011
5012 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5013                                                                    struct radeon_phase_shedding_limits_table *table)
5014 {
5015         u32 i;
5016
5017         if (table) {
5018                 for (i = 0; i < table->count; i++)
5019                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5020         }
5021 }
5022
5023 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5024                                                             struct radeon_clock_and_voltage_limits *table)
5025 {
5026         if (table) {
5027                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5028                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5029         }
5030 }
5031
5032 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5033                                                          struct radeon_cac_leakage_table *table)
5034 {
5035         u32 i;
5036
5037         if (table) {
5038                 for (i = 0; i < table->count; i++)
5039                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5040         }
5041 }
5042
5043 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5044 {
5045
5046         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5047                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5048         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5049                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5050         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5051                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5052         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5053                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5054         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5055                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5056         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5057                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5058         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5059                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5060         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5061                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5062         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5063                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5064         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5065                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5066         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5067                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5068         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5069                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
5070
5071 }
5072
5073 static void ci_get_memory_type(struct radeon_device *rdev)
5074 {
5075         struct ci_power_info *pi = ci_get_pi(rdev);
5076         u32 tmp;
5077
5078         tmp = RREG32(MC_SEQ_MISC0);
5079
5080         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5081             MC_SEQ_MISC0_GDDR5_VALUE)
5082                 pi->mem_gddr5 = true;
5083         else
5084                 pi->mem_gddr5 = false;
5085
5086 }
5087
5088 static void ci_update_current_ps(struct radeon_device *rdev,
5089                                  struct radeon_ps *rps)
5090 {
5091         struct ci_ps *new_ps = ci_get_ps(rps);
5092         struct ci_power_info *pi = ci_get_pi(rdev);
5093
5094         pi->current_rps = *rps;
5095         pi->current_ps = *new_ps;
5096         pi->current_rps.ps_priv = &pi->current_ps;
5097 }
5098
5099 static void ci_update_requested_ps(struct radeon_device *rdev,
5100                                    struct radeon_ps *rps)
5101 {
5102         struct ci_ps *new_ps = ci_get_ps(rps);
5103         struct ci_power_info *pi = ci_get_pi(rdev);
5104
5105         pi->requested_rps = *rps;
5106         pi->requested_ps = *new_ps;
5107         pi->requested_rps.ps_priv = &pi->requested_ps;
5108 }
5109
5110 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5111 {
5112         struct ci_power_info *pi = ci_get_pi(rdev);
5113         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5114         struct radeon_ps *new_ps = &requested_ps;
5115
5116         ci_update_requested_ps(rdev, new_ps);
5117
5118         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5119
5120         return 0;
5121 }
5122
5123 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5124 {
5125         struct ci_power_info *pi = ci_get_pi(rdev);
5126         struct radeon_ps *new_ps = &pi->requested_rps;
5127
5128         ci_update_current_ps(rdev, new_ps);
5129 }
5130
5131
5132 void ci_dpm_setup_asic(struct radeon_device *rdev)
5133 {
5134         int r;
5135
5136         r = ci_mc_load_microcode(rdev);
5137         if (r)
5138                 DRM_ERROR("Failed to load MC firmware!\n");
5139         ci_read_clock_registers(rdev);
5140         ci_get_memory_type(rdev);
5141         ci_enable_acpi_power_management(rdev);
5142         ci_init_sclk_t(rdev);
5143 }
5144
5145 int ci_dpm_enable(struct radeon_device *rdev)
5146 {
5147         struct ci_power_info *pi = ci_get_pi(rdev);
5148         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5149         int ret;
5150
5151         if (ci_is_smc_running(rdev))
5152                 return -EINVAL;
5153         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5154                 ci_enable_voltage_control(rdev);
5155                 ret = ci_construct_voltage_tables(rdev);
5156                 if (ret) {
5157                         DRM_ERROR("ci_construct_voltage_tables failed\n");
5158                         return ret;
5159                 }
5160         }
5161         if (pi->caps_dynamic_ac_timing) {
5162                 ret = ci_initialize_mc_reg_table(rdev);
5163                 if (ret)
5164                         pi->caps_dynamic_ac_timing = false;
5165         }
5166         if (pi->dynamic_ss)
5167                 ci_enable_spread_spectrum(rdev, true);
5168         if (pi->thermal_protection)
5169                 ci_enable_thermal_protection(rdev, true);
5170         ci_program_sstp(rdev);
5171         ci_enable_display_gap(rdev);
5172         ci_program_vc(rdev);
5173         ret = ci_upload_firmware(rdev);
5174         if (ret) {
5175                 DRM_ERROR("ci_upload_firmware failed\n");
5176                 return ret;
5177         }
5178         ret = ci_process_firmware_header(rdev);
5179         if (ret) {
5180                 DRM_ERROR("ci_process_firmware_header failed\n");
5181                 return ret;
5182         }
5183         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5184         if (ret) {
5185                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5186                 return ret;
5187         }
5188         ret = ci_init_smc_table(rdev);
5189         if (ret) {
5190                 DRM_ERROR("ci_init_smc_table failed\n");
5191                 return ret;
5192         }
5193         ret = ci_init_arb_table_index(rdev);
5194         if (ret) {
5195                 DRM_ERROR("ci_init_arb_table_index failed\n");
5196                 return ret;
5197         }
5198         if (pi->caps_dynamic_ac_timing) {
5199                 ret = ci_populate_initial_mc_reg_table(rdev);
5200                 if (ret) {
5201                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5202                         return ret;
5203                 }
5204         }
5205         ret = ci_populate_pm_base(rdev);
5206         if (ret) {
5207                 DRM_ERROR("ci_populate_pm_base failed\n");
5208                 return ret;
5209         }
5210         ci_dpm_start_smc(rdev);
5211         ci_enable_vr_hot_gpio_interrupt(rdev);
5212         ret = ci_notify_smc_display_change(rdev, false);
5213         if (ret) {
5214                 DRM_ERROR("ci_notify_smc_display_change failed\n");
5215                 return ret;
5216         }
5217         ci_enable_sclk_control(rdev, true);
5218         ret = ci_enable_ulv(rdev, true);
5219         if (ret) {
5220                 DRM_ERROR("ci_enable_ulv failed\n");
5221                 return ret;
5222         }
5223         ret = ci_enable_ds_master_switch(rdev, true);
5224         if (ret) {
5225                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5226                 return ret;
5227         }
5228         ret = ci_start_dpm(rdev);
5229         if (ret) {
5230                 DRM_ERROR("ci_start_dpm failed\n");
5231                 return ret;
5232         }
5233         ret = ci_enable_didt(rdev, true);
5234         if (ret) {
5235                 DRM_ERROR("ci_enable_didt failed\n");
5236                 return ret;
5237         }
5238         ret = ci_enable_smc_cac(rdev, true);
5239         if (ret) {
5240                 DRM_ERROR("ci_enable_smc_cac failed\n");
5241                 return ret;
5242         }
5243         ret = ci_enable_power_containment(rdev, true);
5244         if (ret) {
5245                 DRM_ERROR("ci_enable_power_containment failed\n");
5246                 return ret;
5247         }
5248
5249         ret = ci_power_control_set_level(rdev);
5250         if (ret) {
5251                 DRM_ERROR("ci_power_control_set_level failed\n");
5252                 return ret;
5253         }
5254
5255         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5256
5257         ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5258         if (ret) {
5259                 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5260                 return ret;
5261         }
5262
5263         ci_thermal_start_thermal_controller(rdev);
5264
5265         ci_update_current_ps(rdev, boot_ps);
5266
5267         return 0;
5268 }
5269
5270 static int ci_set_temperature_range(struct radeon_device *rdev)
5271 {
5272         int ret;
5273
5274         ret = ci_thermal_enable_alert(rdev, false);
5275         if (ret)
5276                 return ret;
5277         ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5278         if (ret)
5279                 return ret;
5280         ret = ci_thermal_enable_alert(rdev, true);
5281         if (ret)
5282                 return ret;
5283
5284         return ret;
5285 }
5286
5287 int ci_dpm_late_enable(struct radeon_device *rdev)
5288 {
5289         int ret;
5290
5291         ret = ci_set_temperature_range(rdev);
5292         if (ret)
5293                 return ret;
5294
5295         ci_dpm_powergate_uvd(rdev, true);
5296
5297         return 0;
5298 }
5299
5300 void ci_dpm_disable(struct radeon_device *rdev)
5301 {
5302         struct ci_power_info *pi = ci_get_pi(rdev);
5303         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5304
5305         ci_dpm_powergate_uvd(rdev, false);
5306
5307         if (!ci_is_smc_running(rdev))
5308                 return;
5309
5310         ci_thermal_stop_thermal_controller(rdev);
5311
5312         if (pi->thermal_protection)
5313                 ci_enable_thermal_protection(rdev, false);
5314         ci_enable_power_containment(rdev, false);
5315         ci_enable_smc_cac(rdev, false);
5316         ci_enable_didt(rdev, false);
5317         ci_enable_spread_spectrum(rdev, false);
5318         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5319         ci_stop_dpm(rdev);
5320         ci_enable_ds_master_switch(rdev, false);
5321         ci_enable_ulv(rdev, false);
5322         ci_clear_vc(rdev);
5323         ci_reset_to_default(rdev);
5324         ci_dpm_stop_smc(rdev);
5325         ci_force_switch_to_arb_f0(rdev);
5326         ci_enable_thermal_based_sclk_dpm(rdev, false);
5327
5328         ci_update_current_ps(rdev, boot_ps);
5329 }
5330
5331 int ci_dpm_set_power_state(struct radeon_device *rdev)
5332 {
5333         struct ci_power_info *pi = ci_get_pi(rdev);
5334         struct radeon_ps *new_ps = &pi->requested_rps;
5335         struct radeon_ps *old_ps = &pi->current_rps;
5336         int ret;
5337
5338         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5339         if (pi->pcie_performance_request)
5340                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5341         ret = ci_freeze_sclk_mclk_dpm(rdev);
5342         if (ret) {
5343                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5344                 return ret;
5345         }
5346         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5347         if (ret) {
5348                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5349                 return ret;
5350         }
5351         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5352         if (ret) {
5353                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5354                 return ret;
5355         }
5356
5357         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5358         if (ret) {
5359                 DRM_ERROR("ci_update_vce_dpm failed\n");
5360                 return ret;
5361         }
5362
5363         ret = ci_update_sclk_t(rdev);
5364         if (ret) {
5365                 DRM_ERROR("ci_update_sclk_t failed\n");
5366                 return ret;
5367         }
5368         if (pi->caps_dynamic_ac_timing) {
5369                 ret = ci_update_and_upload_mc_reg_table(rdev);
5370                 if (ret) {
5371                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5372                         return ret;
5373                 }
5374         }
5375         ret = ci_program_memory_timing_parameters(rdev);
5376         if (ret) {
5377                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5378                 return ret;
5379         }
5380         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5381         if (ret) {
5382                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5383                 return ret;
5384         }
5385         ret = ci_upload_dpm_level_enable_mask(rdev);
5386         if (ret) {
5387                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5388                 return ret;
5389         }
5390         if (pi->pcie_performance_request)
5391                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5392
5393         return 0;
5394 }
5395
5396 #if 0
5397 void ci_dpm_reset_asic(struct radeon_device *rdev)
5398 {
5399         ci_set_boot_state(rdev);
5400 }
5401 #endif
5402
5403 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5404 {
5405         ci_program_display_gap(rdev);
5406 }
5407
5408 union power_info {
5409         struct _ATOM_POWERPLAY_INFO info;
5410         struct _ATOM_POWERPLAY_INFO_V2 info_2;
5411         struct _ATOM_POWERPLAY_INFO_V3 info_3;
5412         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5413         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5414         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5415 };
5416
5417 union pplib_clock_info {
5418         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5419         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5420         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5421         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5422         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5423         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5424 };
5425
5426 union pplib_power_state {
5427         struct _ATOM_PPLIB_STATE v1;
5428         struct _ATOM_PPLIB_STATE_V2 v2;
5429 };
5430
5431 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5432                                           struct radeon_ps *rps,
5433                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5434                                           u8 table_rev)
5435 {
5436         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5437         rps->class = le16_to_cpu(non_clock_info->usClassification);
5438         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5439
5440         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5441                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5442                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5443         } else {
5444                 rps->vclk = 0;
5445                 rps->dclk = 0;
5446         }
5447
5448         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5449                 rdev->pm.dpm.boot_ps = rps;
5450         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5451                 rdev->pm.dpm.uvd_ps = rps;
5452 }
5453
5454 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5455                                       struct radeon_ps *rps, int index,
5456                                       union pplib_clock_info *clock_info)
5457 {
5458         struct ci_power_info *pi = ci_get_pi(rdev);
5459         struct ci_ps *ps = ci_get_ps(rps);
5460         struct ci_pl *pl = &ps->performance_levels[index];
5461
5462         ps->performance_level_count = index + 1;
5463
5464         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5465         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5466         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5467         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5468
5469         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5470                                                  pi->sys_pcie_mask,
5471                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
5472                                                  clock_info->ci.ucPCIEGen);
5473         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5474                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
5475                                                    le16_to_cpu(clock_info->ci.usPCIELane));
5476
5477         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5478                 pi->acpi_pcie_gen = pl->pcie_gen;
5479         }
5480
5481         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5482                 pi->ulv.supported = true;
5483                 pi->ulv.pl = *pl;
5484                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5485         }
5486
5487         /* patch up boot state */
5488         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5489                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5490                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5491                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5492                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5493         }
5494
5495         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5496         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5497                 pi->use_pcie_powersaving_levels = true;
5498                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5499                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
5500                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5501                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
5502                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5503                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
5504                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5505                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
5506                 break;
5507         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5508                 pi->use_pcie_performance_levels = true;
5509                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5510                         pi->pcie_gen_performance.max = pl->pcie_gen;
5511                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5512                         pi->pcie_gen_performance.min = pl->pcie_gen;
5513                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5514                         pi->pcie_lane_performance.max = pl->pcie_lane;
5515                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5516                         pi->pcie_lane_performance.min = pl->pcie_lane;
5517                 break;
5518         default:
5519                 break;
5520         }
5521 }
5522
5523 static int ci_parse_power_table(struct radeon_device *rdev)
5524 {
5525         struct radeon_mode_info *mode_info = &rdev->mode_info;
5526         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5527         union pplib_power_state *power_state;
5528         int i, j, k, non_clock_array_index, clock_array_index;
5529         union pplib_clock_info *clock_info;
5530         struct _StateArray *state_array;
5531         struct _ClockInfoArray *clock_info_array;
5532         struct _NonClockInfoArray *non_clock_info_array;
5533         union power_info *power_info;
5534         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5535         u16 data_offset;
5536         u8 frev, crev;
5537         u8 *power_state_offset;
5538         struct ci_ps *ps;
5539
5540         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5541                                    &frev, &crev, &data_offset))
5542                 return -EINVAL;
5543         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5544
5545         state_array = (struct _StateArray *)
5546                 (mode_info->atom_context->bios + data_offset +
5547                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
5548         clock_info_array = (struct _ClockInfoArray *)
5549                 (mode_info->atom_context->bios + data_offset +
5550                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5551         non_clock_info_array = (struct _NonClockInfoArray *)
5552                 (mode_info->atom_context->bios + data_offset +
5553                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5554
5555         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5556                                   state_array->ucNumEntries, GFP_KERNEL);
5557         if (!rdev->pm.dpm.ps)
5558                 return -ENOMEM;
5559         power_state_offset = (u8 *)state_array->states;
5560         rdev->pm.dpm.num_ps = 0;
5561         for (i = 0; i < state_array->ucNumEntries; i++) {
5562                 u8 *idx;
5563                 power_state = (union pplib_power_state *)power_state_offset;
5564                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5565                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5566                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5567                 if (!rdev->pm.power_state[i].clock_info)
5568                         return -EINVAL;
5569                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5570                 if (ps == NULL)
5571                         return -ENOMEM;
5572                 rdev->pm.dpm.ps[i].ps_priv = ps;
5573                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5574                                               non_clock_info,
5575                                               non_clock_info_array->ucEntrySize);
5576                 k = 0;
5577                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5578                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5579                         clock_array_index = idx[j];
5580                         if (clock_array_index >= clock_info_array->ucNumEntries)
5581                                 continue;
5582                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5583                                 break;
5584                         clock_info = (union pplib_clock_info *)
5585                                 ((u8 *)&clock_info_array->clockInfo[0] +
5586                                  (clock_array_index * clock_info_array->ucEntrySize));
5587                         ci_parse_pplib_clock_info(rdev,
5588                                                   &rdev->pm.dpm.ps[i], k,
5589                                                   clock_info);
5590                         k++;
5591                 }
5592                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5593                 rdev->pm.dpm.num_ps = i + 1;
5594         }
5595
5596         /* fill in the vce power states */
5597         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5598                 u32 sclk, mclk;
5599                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5600                 clock_info = (union pplib_clock_info *)
5601                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5602                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5603                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5604                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5605                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5606                 rdev->pm.dpm.vce_states[i].sclk = sclk;
5607                 rdev->pm.dpm.vce_states[i].mclk = mclk;
5608         }
5609
5610         return 0;
5611 }
5612
5613 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5614                                     struct ci_vbios_boot_state *boot_state)
5615 {
5616         struct radeon_mode_info *mode_info = &rdev->mode_info;
5617         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5618         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5619         u8 frev, crev;
5620         u16 data_offset;
5621
5622         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5623                                    &frev, &crev, &data_offset)) {
5624                 firmware_info =
5625                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5626                                                     data_offset);
5627                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5628                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5629                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5630                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5631                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5632                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5633                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5634
5635                 return 0;
5636         }
5637         return -EINVAL;
5638 }
5639
5640 void ci_dpm_fini(struct radeon_device *rdev)
5641 {
5642         int i;
5643
5644         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5645                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5646         }
5647         kfree(rdev->pm.dpm.ps);
5648         kfree(rdev->pm.dpm.priv);
5649         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5650         r600_free_extended_power_table(rdev);
5651 }
5652
5653 int ci_dpm_init(struct radeon_device *rdev)
5654 {
5655         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5656         SMU7_Discrete_DpmTable  *dpm_table;
5657         struct radeon_gpio_rec gpio;
5658         u16 data_offset, size;
5659         u8 frev, crev;
5660         struct ci_power_info *pi;
5661         int ret;
5662         u32 mask;
5663
5664         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5665         if (pi == NULL)
5666                 return -ENOMEM;
5667         rdev->pm.dpm.priv = pi;
5668
5669         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5670         if (ret)
5671                 pi->sys_pcie_mask = 0;
5672         else
5673                 pi->sys_pcie_mask = mask;
5674         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5675
5676         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5677         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5678         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5679         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5680
5681         pi->pcie_lane_performance.max = 0;
5682         pi->pcie_lane_performance.min = 16;
5683         pi->pcie_lane_powersaving.max = 0;
5684         pi->pcie_lane_powersaving.min = 16;
5685
5686         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5687         if (ret) {
5688                 ci_dpm_fini(rdev);
5689                 return ret;
5690         }
5691
5692         ret = r600_get_platform_caps(rdev);
5693         if (ret) {
5694                 ci_dpm_fini(rdev);
5695                 return ret;
5696         }
5697
5698         ret = r600_parse_extended_power_table(rdev);
5699         if (ret) {
5700                 ci_dpm_fini(rdev);
5701                 return ret;
5702         }
5703
5704         ret = ci_parse_power_table(rdev);
5705         if (ret) {
5706                 ci_dpm_fini(rdev);
5707                 return ret;
5708         }
5709
5710         pi->dll_default_on = false;
5711         pi->sram_end = SMC_RAM_END;
5712
5713         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5714         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5715         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5716         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5717         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5718         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5719         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5720         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5721
5722         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5723
5724         pi->sclk_dpm_key_disabled = 0;
5725         pi->mclk_dpm_key_disabled = 0;
5726         pi->pcie_dpm_key_disabled = 0;
5727         pi->thermal_sclk_dpm_enabled = 0;
5728
5729         /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5730         if ((rdev->pdev->device == 0x6658) &&
5731             (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5732                 pi->mclk_dpm_key_disabled = 1;
5733         }
5734
5735         pi->caps_sclk_ds = true;
5736
5737         pi->mclk_strobe_mode_threshold = 40000;
5738         pi->mclk_stutter_mode_threshold = 40000;
5739         pi->mclk_edc_enable_threshold = 40000;
5740         pi->mclk_edc_wr_enable_threshold = 40000;
5741
5742         ci_initialize_powertune_defaults(rdev);
5743
5744         pi->caps_fps = false;
5745
5746         pi->caps_sclk_throttle_low_notification = false;
5747
5748         pi->caps_uvd_dpm = true;
5749         pi->caps_vce_dpm = true;
5750
5751         ci_get_leakage_voltages(rdev);
5752         ci_patch_dependency_tables_with_leakage(rdev);
5753         ci_set_private_data_variables_based_on_pptable(rdev);
5754
5755         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5756                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5757         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5758                 ci_dpm_fini(rdev);
5759                 return -ENOMEM;
5760         }
5761         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5762         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5763         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5764         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5765         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5766         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5767         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5768         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5769         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5770
5771         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5772         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5773         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5774
5775         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5776         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5777         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5778         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5779
5780         if (rdev->family == CHIP_HAWAII) {
5781                 pi->thermal_temp_setting.temperature_low = 94500;
5782                 pi->thermal_temp_setting.temperature_high = 95000;
5783                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5784         } else {
5785                 pi->thermal_temp_setting.temperature_low = 99500;
5786                 pi->thermal_temp_setting.temperature_high = 100000;
5787                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5788         }
5789
5790         pi->uvd_enabled = false;
5791
5792         dpm_table = &pi->smc_state_table;
5793
5794         gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5795         if (gpio.valid) {
5796                 dpm_table->VRHotGpio = gpio.shift;
5797                 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5798         } else {
5799                 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5800                 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5801         }
5802
5803         gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5804         if (gpio.valid) {
5805                 dpm_table->AcDcGpio = gpio.shift;
5806                 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5807         } else {
5808                 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5809                 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5810         }
5811
5812         gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5813         if (gpio.valid) {
5814                 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5815
5816                 switch (gpio.shift) {
5817                 case 0:
5818                         tmp &= ~GNB_SLOW_MODE_MASK;
5819                         tmp |= GNB_SLOW_MODE(1);
5820                         break;
5821                 case 1:
5822                         tmp &= ~GNB_SLOW_MODE_MASK;
5823                         tmp |= GNB_SLOW_MODE(2);
5824                         break;
5825                 case 2:
5826                         tmp |= GNB_SLOW;
5827                         break;
5828                 case 3:
5829                         tmp |= FORCE_NB_PS1;
5830                         break;
5831                 case 4:
5832                         tmp |= DPM_ENABLED;
5833                         break;
5834                 default:
5835                         DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift);
5836                         break;
5837                 }
5838                 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5839         }
5840
5841         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5842         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5843         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5844         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5845                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5846         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5847                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5848
5849         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5850                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5851                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5852                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5853                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5854                 else
5855                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5856         }
5857
5858         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5859                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5860                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5861                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5862                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5863                 else
5864                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5865         }
5866
5867         pi->vddc_phase_shed_control = true;
5868
5869 #if defined(CONFIG_ACPI)
5870         pi->pcie_performance_request =
5871                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5872 #else
5873         pi->pcie_performance_request = false;
5874 #endif
5875
5876         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5877                                    &frev, &crev, &data_offset)) {
5878                 pi->caps_sclk_ss_support = true;
5879                 pi->caps_mclk_ss_support = true;
5880                 pi->dynamic_ss = true;
5881         } else {
5882                 pi->caps_sclk_ss_support = false;
5883                 pi->caps_mclk_ss_support = false;
5884                 pi->dynamic_ss = true;
5885         }
5886
5887         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5888                 pi->thermal_protection = true;
5889         else
5890                 pi->thermal_protection = false;
5891
5892         pi->caps_dynamic_ac_timing = true;
5893
5894         pi->uvd_power_gated = false;
5895
5896         /* make sure dc limits are valid */
5897         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5898             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5899                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5900                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5901
5902         pi->fan_ctrl_is_in_default_mode = true;
5903
5904         return 0;
5905 }
5906
5907 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5908                                                     struct seq_file *m)
5909 {
5910         struct ci_power_info *pi = ci_get_pi(rdev);
5911         struct radeon_ps *rps = &pi->current_rps;
5912         u32 sclk = ci_get_average_sclk_freq(rdev);
5913         u32 mclk = ci_get_average_mclk_freq(rdev);
5914
5915         seq_printf(m, "uvd    %sabled\n", pi->uvd_enabled ? "en" : "dis");
5916         seq_printf(m, "vce    %sabled\n", rps->vce_active ? "en" : "dis");
5917         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5918                    sclk, mclk);
5919 }
5920
5921 void ci_dpm_print_power_state(struct radeon_device *rdev,
5922                               struct radeon_ps *rps)
5923 {
5924         struct ci_ps *ps = ci_get_ps(rps);
5925         struct ci_pl *pl;
5926         int i;
5927
5928         r600_dpm_print_class_info(rps->class, rps->class2);
5929         r600_dpm_print_cap_info(rps->caps);
5930         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5931         for (i = 0; i < ps->performance_level_count; i++) {
5932                 pl = &ps->performance_levels[i];
5933                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5934                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5935         }
5936         r600_dpm_print_ps_status(rdev, rps);
5937 }
5938
5939 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5940 {
5941         u32 sclk = ci_get_average_sclk_freq(rdev);
5942
5943         return sclk;
5944 }
5945
5946 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5947 {
5948         u32 mclk = ci_get_average_mclk_freq(rdev);
5949
5950         return mclk;
5951 }
5952
5953 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5954 {
5955         struct ci_power_info *pi = ci_get_pi(rdev);
5956         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5957
5958         if (low)
5959                 return requested_state->performance_levels[0].sclk;
5960         else
5961                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5962 }
5963
5964 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5965 {
5966         struct ci_power_info *pi = ci_get_pi(rdev);
5967         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5968
5969         if (low)
5970                 return requested_state->performance_levels[0].mclk;
5971         else
5972                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5973 }