drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_audio.h"
  31 #include "atom.h"
  32 #include <linux/backlight.h>
  33 #include <linux/dmi.h>
  34
  35 extern int atom_debug;
  36
  37 static u8
  38 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  39 {
  40         u8 backlight_level;
  41         u32 bios_2_scratch;
  42
  43         if (rdev->family >= CHIP_R600)
  44                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  45         else
  46                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  47
  48         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  49                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  50
  51         return backlight_level;
  52 }
  53
  54 static void
  55 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  56                                        u8 backlight_level)
  57 {
  58         u32 bios_2_scratch;
  59
  60         if (rdev->family >= CHIP_R600)
  61                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  62         else
  63                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  64
  65         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  66         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  67                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  68
  69         if (rdev->family >= CHIP_R600)
  70                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  71         else
  72                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  73 }
  74
  75 u8
  76 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  77 {
  78         struct drm_device *dev = radeon_encoder->base.dev;
  79         struct radeon_device *rdev = dev->dev_private;
  80
  81         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  82                 return 0;
  83
  84         return radeon_atom_get_backlight_level_from_reg(rdev);
  85 }
  86
  87 void
  88 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  89 {
  90         struct drm_encoder *encoder = &radeon_encoder->base;
  91         struct drm_device *dev = radeon_encoder->base.dev;
  92         struct radeon_device *rdev = dev->dev_private;
  93         struct radeon_encoder_atom_dig *dig;
  94         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  95         int index;
  96
  97         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  98                 return;
  99
 100         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 101             radeon_encoder->enc_priv) {
 102                 dig = radeon_encoder->enc_priv;
 103                 dig->backlight_level = level;
 104                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 105
 106                 switch (radeon_encoder->encoder_id) {
 107                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 108                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 109                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 110                         if (dig->backlight_level == 0) {
 111                                 args.ucAction = ATOM_LCD_BLOFF;
 112                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 113                         } else {
 114                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 115                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                                 args.ucAction = ATOM_LCD_BLON;
 117                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118                         }
 119                         break;
 120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 121                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 123                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 124                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 125                         if (dig->backlight_level == 0)
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 127                         else {
 128                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 129                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 130                         }
 131                         break;
 132                 default:
 133                         break;
 134                 }
 135         }
 136 }
 137
 138 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 139
 140 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 141 {
 142         u8 level;
 143
 144         /* Convert brightness to hardware level */
 145         if (bd->props.brightness < 0)
 146                 level = 0;
 147         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 148                 level = RADEON_MAX_BL_LEVEL;
 149         else
 150                 level = bd->props.brightness;
 151
 152         return level;
 153 }
 154
 155 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 156 {
 157         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 158         struct radeon_encoder *radeon_encoder = pdata->encoder;
 159
 160         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 161
 162         return 0;
 163 }
 164
 165 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 166 {
 167         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 168         struct radeon_encoder *radeon_encoder = pdata->encoder;
 169         struct drm_device *dev = radeon_encoder->base.dev;
 170         struct radeon_device *rdev = dev->dev_private;
 171
 172         return radeon_atom_get_backlight_level_from_reg(rdev);
 173 }
 174
 175 static const struct backlight_ops radeon_atom_backlight_ops = {
 176         .get_brightness = radeon_atom_backlight_get_brightness,
 177         .update_status  = radeon_atom_backlight_update_status,
 178 };
 179
 180 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 181                                 struct drm_connector *drm_connector)
 182 {
 183         struct drm_device *dev = radeon_encoder->base.dev;
 184         struct radeon_device *rdev = dev->dev_private;
 185         struct backlight_device *bd;
 186         struct backlight_properties props;
 187         struct radeon_backlight_privdata *pdata;
 188         struct radeon_encoder_atom_dig *dig;
 189         char bl_name[16];
 190
 191         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 192          * so don't register a backlight device
 193          */
 194         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 195             (rdev->pdev->device == 0x6741) &&
 196             !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
 197                 return;
 198
 199         if (!radeon_encoder->enc_priv)
 200                 return;
 201
 202         if (!rdev->is_atom_bios)
 203                 return;
 204
 205         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 206                 return;
 207
 208         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 209         if (!pdata) {
 210                 DRM_ERROR("Memory allocation failed\n");
 211                 goto error;
 212         }
 213
 214         memset(&props, 0, sizeof(props));
 215         props.max_brightness = RADEON_MAX_BL_LEVEL;
 216         props.type = BACKLIGHT_RAW;
 217         snprintf(bl_name, sizeof(bl_name),
 218                  "radeon_bl%d", dev->primary->index);
 219         bd = backlight_device_register(bl_name, drm_connector->kdev,
 220                                        pdata, &radeon_atom_backlight_ops, &props);
 221         if (IS_ERR(bd)) {
 222                 DRM_ERROR("Backlight registration failed\n");
 223                 goto error;
 224         }
 225
 226         pdata->encoder = radeon_encoder;
 227
 228         dig = radeon_encoder->enc_priv;
 229         dig->bl_dev = bd;
 230
 231         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 232         /* Set a reasonable default here if the level is 0 otherwise
 233          * fbdev will attempt to turn the backlight on after console
 234          * unblanking and it will try and restore 0 which turns the backlight
 235          * off again.
 236          */
 237         if (bd->props.brightness == 0)
 238                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 239         bd->props.power = FB_BLANK_UNBLANK;
 240         backlight_update_status(bd);
 241
 242         DRM_INFO("radeon atom DIG backlight initialized\n");
 243         rdev->mode_info.bl_encoder = radeon_encoder;
 244
 245         return;
 246
 247 error:
 248         kfree(pdata);
 249         return;
 250 }
 251
 252 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 253 {
 254         struct drm_device *dev = radeon_encoder->base.dev;
 255         struct radeon_device *rdev = dev->dev_private;
 256         struct backlight_device *bd = NULL;
 257         struct radeon_encoder_atom_dig *dig;
 258
 259         if (!radeon_encoder->enc_priv)
 260                 return;
 261
 262         if (!rdev->is_atom_bios)
 263                 return;
 264
 265         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 266                 return;
 267
 268         dig = radeon_encoder->enc_priv;
 269         bd = dig->bl_dev;
 270         dig->bl_dev = NULL;
 271
 272         if (bd) {
 273                 struct radeon_legacy_backlight_privdata *pdata;
 274
 275                 pdata = bl_get_data(bd);
 276                 backlight_device_unregister(bd);
 277                 kfree(pdata);
 278
 279                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 280         }
 281 }
 282
 283 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 284
 285 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 286 {
 287 }
 288
 289 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 290 {
 291 }
 292
 293 #endif
 294
 295 /* evil but including atombios.h is much worse */
 296 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 297                                 struct drm_display_mode *mode);
 298
 299 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 300                                    const struct drm_display_mode *mode,
 301                                    struct drm_display_mode *adjusted_mode)
 302 {
 303         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 304         struct drm_device *dev = encoder->dev;
 305         struct radeon_device *rdev = dev->dev_private;
 306
 307         /* set the active encoder to connector routing */
 308         radeon_encoder_set_active_device(encoder);
 309         drm_mode_set_crtcinfo(adjusted_mode, 0);
 310
 311         /* hw bug */
 312         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 313             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 314                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 315
 316         /* vertical FP must be at least 1 */
 317         if (mode->crtc_vsync_start == mode->crtc_vdisplay)
 318                 adjusted_mode->crtc_vsync_start++;
 319
 320         /* get the native mode for scaling */
 321         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 322                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 323         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 324                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 325                 if (tv_dac) {
 326                         if (tv_dac->tv_std == TV_STD_NTSC ||
 327                             tv_dac->tv_std == TV_STD_NTSC_J ||
 328                             tv_dac->tv_std == TV_STD_PAL_M)
 329                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 330                         else
 331                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 332                 }
 333         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 334                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 335         }
 336
 337         if (ASIC_IS_DCE3(rdev) &&
 338             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 339              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 340                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 341                 radeon_dp_set_link_config(connector, adjusted_mode);
 342         }
 343
 344         return true;
 345 }
 346
 347 static void
 348 atombios_dac_setup(struct drm_encoder *encoder, int action)
 349 {
 350         struct drm_device *dev = encoder->dev;
 351         struct radeon_device *rdev = dev->dev_private;
 352         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 353         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 354         int index = 0;
 355         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 356
 357         memset(&args, 0, sizeof(args));
 358
 359         switch (radeon_encoder->encoder_id) {
 360         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 361         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 362                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 363                 break;
 364         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 365         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 366                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 367                 break;
 368         }
 369
 370         args.ucAction = action;
 371
 372         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 373                 args.ucDacStandard = ATOM_DAC1_PS2;
 374         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 375                 args.ucDacStandard = ATOM_DAC1_CV;
 376         else {
 377                 switch (dac_info->tv_std) {
 378                 case TV_STD_PAL:
 379                 case TV_STD_PAL_M:
 380                 case TV_STD_SCART_PAL:
 381                 case TV_STD_SECAM:
 382                 case TV_STD_PAL_CN:
 383                         args.ucDacStandard = ATOM_DAC1_PAL;
 384                         break;
 385                 case TV_STD_NTSC:
 386                 case TV_STD_NTSC_J:
 387                 case TV_STD_PAL_60:
 388                 default:
 389                         args.ucDacStandard = ATOM_DAC1_NTSC;
 390                         break;
 391                 }
 392         }
 393         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 394
 395         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 396
 397 }
 398
 399 static void
 400 atombios_tv_setup(struct drm_encoder *encoder, int action)
 401 {
 402         struct drm_device *dev = encoder->dev;
 403         struct radeon_device *rdev = dev->dev_private;
 404         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 405         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 406         int index = 0;
 407         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 408
 409         memset(&args, 0, sizeof(args));
 410
 411         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 412
 413         args.sTVEncoder.ucAction = action;
 414
 415         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 416                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 417         else {
 418                 switch (dac_info->tv_std) {
 419                 case TV_STD_NTSC:
 420                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 421                         break;
 422                 case TV_STD_PAL:
 423                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 424                         break;
 425                 case TV_STD_PAL_M:
 426                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 427                         break;
 428                 case TV_STD_PAL_60:
 429                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 430                         break;
 431                 case TV_STD_NTSC_J:
 432                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 433                         break;
 434                 case TV_STD_SCART_PAL:
 435                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 436                         break;
 437                 case TV_STD_SECAM:
 438                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 439                         break;
 440                 case TV_STD_PAL_CN:
 441                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 442                         break;
 443                 default:
 444                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 445                         break;
 446                 }
 447         }
 448
 449         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 450
 451         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 452
 453 }
 454
 455 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 456 {
 457         int bpc = 8;
 458
 459         if (encoder->crtc) {
 460                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 461                 bpc = radeon_crtc->bpc;
 462         }
 463
 464         switch (bpc) {
 465         case 0:
 466                 return PANEL_BPC_UNDEFINE;
 467         case 6:
 468                 return PANEL_6BIT_PER_COLOR;
 469         case 8:
 470         default:
 471                 return PANEL_8BIT_PER_COLOR;
 472         case 10:
 473                 return PANEL_10BIT_PER_COLOR;
 474         case 12:
 475                 return PANEL_12BIT_PER_COLOR;
 476         case 16:
 477                 return PANEL_16BIT_PER_COLOR;
 478         }
 479 }
 480
 481 union dvo_encoder_control {
 482         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 483         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 484         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 485         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 486 };
 487
 488 void
 489 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 490 {
 491         struct drm_device *dev = encoder->dev;
 492         struct radeon_device *rdev = dev->dev_private;
 493         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 494         union dvo_encoder_control args;
 495         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 496         uint8_t frev, crev;
 497
 498         memset(&args, 0, sizeof(args));
 499
 500         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 501                 return;
 502
 503         /* some R4xx chips have the wrong frev */
 504         if (rdev->family <= CHIP_RV410)
 505                 frev = 1;
 506
 507         switch (frev) {
 508         case 1:
 509                 switch (crev) {
 510                 case 1:
 511                         /* R4xx, R5xx */
 512                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 513
 514                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 515                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 516
 517                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 518                         break;
 519                 case 2:
 520                         /* RS600/690/740 */
 521                         args.dvo.sDVOEncoder.ucAction = action;
 522                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 523                         /* DFP1, CRT1, TV1 depending on the type of port */
 524                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 525
 526                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 527                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 528                         break;
 529                 case 3:
 530                         /* R6xx */
 531                         args.dvo_v3.ucAction = action;
 532                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 533                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 534                         break;
 535                 case 4:
 536                         /* DCE8 */
 537                         args.dvo_v4.ucAction = action;
 538                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 539                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 540                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 541                         break;
 542                 default:
 543                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 544                         break;
 545                 }
 546                 break;
 547         default:
 548                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 549                 break;
 550         }
 551
 552         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 553 }
 554
 555 union lvds_encoder_control {
 556         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 557         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 558 };
 559
 560 void
 561 atombios_digital_setup(struct drm_encoder *encoder, int action)
 562 {
 563         struct drm_device *dev = encoder->dev;
 564         struct radeon_device *rdev = dev->dev_private;
 565         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 566         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 567         union lvds_encoder_control args;
 568         int index = 0;
 569         int hdmi_detected = 0;
 570         uint8_t frev, crev;
 571
 572         if (!dig)
 573                 return;
 574
 575         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 576                 hdmi_detected = 1;
 577
 578         memset(&args, 0, sizeof(args));
 579
 580         switch (radeon_encoder->encoder_id) {
 581         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 582                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 583                 break;
 584         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 585         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 586                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 587                 break;
 588         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 589                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 590                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 591                 else
 592                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 593                 break;
 594         }
 595
 596         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 597                 return;
 598
 599         switch (frev) {
 600         case 1:
 601         case 2:
 602                 switch (crev) {
 603                 case 1:
 604                         args.v1.ucMisc = 0;
 605                         args.v1.ucAction = action;
 606                         if (hdmi_detected)
 607                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 608                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 609                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 610                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 611                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 612                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 613                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 614                         } else {
 615                                 if (dig->linkb)
 616                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 617                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 618                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 619                                 /*if (pScrn->rgbBits == 8) */
 620                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 621                         }
 622                         break;
 623                 case 2:
 624                 case 3:
 625                         args.v2.ucMisc = 0;
 626                         args.v2.ucAction = action;
 627                         if (crev == 3) {
 628                                 if (dig->coherent_mode)
 629                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 630                         }
 631                         if (hdmi_detected)
 632                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 633                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 634                         args.v2.ucTruncate = 0;
 635                         args.v2.ucSpatial = 0;
 636                         args.v2.ucTemporal = 0;
 637                         args.v2.ucFRC = 0;
 638                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 639                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 640                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 641                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 642                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 643                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 644                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 645                                 }
 646                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 647                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 648                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 649                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 650                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 651                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 652                                 }
 653                         } else {
 654                                 if (dig->linkb)
 655                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 656                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 657                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 658                         }
 659                         break;
 660                 default:
 661                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 662                         break;
 663                 }
 664                 break;
 665         default:
 666                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 667                 break;
 668         }
 669
 670         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 671 }
 672
 673 int
 674 atombios_get_encoder_mode(struct drm_encoder *encoder)
 675 {
 676         struct drm_device *dev = encoder->dev;
 677         struct radeon_device *rdev = dev->dev_private;
 678         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 679         struct drm_connector *connector;
 680         struct radeon_connector *radeon_connector;
 681         struct radeon_connector_atom_dig *dig_connector;
 682         struct radeon_encoder_atom_dig *dig_enc;
 683
 684         if (radeon_encoder_is_digital(encoder)) {
 685                 dig_enc = radeon_encoder->enc_priv;
 686                 if (dig_enc->active_mst_links)
 687                         return ATOM_ENCODER_MODE_DP_MST;
 688         }
 689         if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 690                 return ATOM_ENCODER_MODE_DP_MST;
 691         /* dp bridges are always DP */
 692         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 693                 return ATOM_ENCODER_MODE_DP;
 694
 695         /* DVO is always DVO */
 696         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 697             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 698                 return ATOM_ENCODER_MODE_DVO;
 699
 700         connector = radeon_get_connector_for_encoder(encoder);
 701         /* if we don't have an active device yet, just use one of
 702          * the connectors tied to the encoder.
 703          */
 704         if (!connector)
 705                 connector = radeon_get_connector_for_encoder_init(encoder);
 706         radeon_connector = to_radeon_connector(connector);
 707
 708         switch (connector->connector_type) {
 709         case DRM_MODE_CONNECTOR_DVII:
 710         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 711                 if (radeon_audio != 0) {
 712                         if (radeon_connector->use_digital &&
 713                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 714                                 return ATOM_ENCODER_MODE_HDMI;
 715                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 716                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 717                                 return ATOM_ENCODER_MODE_HDMI;
 718                         else if (radeon_connector->use_digital)
 719                                 return ATOM_ENCODER_MODE_DVI;
 720                         else
 721                                 return ATOM_ENCODER_MODE_CRT;
 722                 } else if (radeon_connector->use_digital) {
 723                         return ATOM_ENCODER_MODE_DVI;
 724                 } else {
 725                         return ATOM_ENCODER_MODE_CRT;
 726                 }
 727                 break;
 728         case DRM_MODE_CONNECTOR_DVID:
 729         case DRM_MODE_CONNECTOR_HDMIA:
 730         default:
 731                 if (radeon_audio != 0) {
 732                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 733                                 return ATOM_ENCODER_MODE_HDMI;
 734                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 735                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 736                                 return ATOM_ENCODER_MODE_HDMI;
 737                         else
 738                                 return ATOM_ENCODER_MODE_DVI;
 739                 } else {
 740                         return ATOM_ENCODER_MODE_DVI;
 741                 }
 742                 break;
 743         case DRM_MODE_CONNECTOR_LVDS:
 744                 return ATOM_ENCODER_MODE_LVDS;
 745                 break;
 746         case DRM_MODE_CONNECTOR_DisplayPort:
 747                 dig_connector = radeon_connector->con_priv;
 748                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 749                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 750                         if (radeon_audio != 0 &&
 751                             drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 752                             ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 753                                 return ATOM_ENCODER_MODE_DP_AUDIO;
 754                         return ATOM_ENCODER_MODE_DP;
 755                 } else if (radeon_audio != 0) {
 756                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 757                                 return ATOM_ENCODER_MODE_HDMI;
 758                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 759                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 760                                 return ATOM_ENCODER_MODE_HDMI;
 761                         else
 762                                 return ATOM_ENCODER_MODE_DVI;
 763                 } else {
 764                         return ATOM_ENCODER_MODE_DVI;
 765                 }
 766                 break;
 767         case DRM_MODE_CONNECTOR_eDP:
 768                 if (radeon_audio != 0 &&
 769                     drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 770                     ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 771                         return ATOM_ENCODER_MODE_DP_AUDIO;
 772                 return ATOM_ENCODER_MODE_DP;
 773         case DRM_MODE_CONNECTOR_DVIA:
 774         case DRM_MODE_CONNECTOR_VGA:
 775                 return ATOM_ENCODER_MODE_CRT;
 776                 break;
 777         case DRM_MODE_CONNECTOR_Composite:
 778         case DRM_MODE_CONNECTOR_SVIDEO:
 779         case DRM_MODE_CONNECTOR_9PinDIN:
 780                 /* fix me */
 781                 return ATOM_ENCODER_MODE_TV;
 782                 /*return ATOM_ENCODER_MODE_CV;*/
 783                 break;
 784         }
 785 }
 786
 787 /*
 788  * DIG Encoder/Transmitter Setup
 789  *
 790  * DCE 3.0/3.1
 791  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 792  * Supports up to 3 digital outputs
 793  * - 2 DIG encoder blocks.
 794  * DIG1 can drive UNIPHY link A or link B
 795  * DIG2 can drive UNIPHY link B or LVTMA
 796  *
 797  * DCE 3.2
 798  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 799  * Supports up to 5 digital outputs
 800  * - 2 DIG encoder blocks.
 801  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 802  *
 803  * DCE 4.0/5.0/6.0
 804  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 805  * Supports up to 6 digital outputs
 806  * - 6 DIG encoder blocks.
 807  * - DIG to PHY mapping is hardcoded
 808  * DIG1 drives UNIPHY0 link A, A+B
 809  * DIG2 drives UNIPHY0 link B
 810  * DIG3 drives UNIPHY1 link A, A+B
 811  * DIG4 drives UNIPHY1 link B
 812  * DIG5 drives UNIPHY2 link A, A+B
 813  * DIG6 drives UNIPHY2 link B
 814  *
 815  * DCE 4.1
 816  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 817  * Supports up to 6 digital outputs
 818  * - 2 DIG encoder blocks.
 819  * llano
 820  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 821  * ontario
 822  * DIG1 drives UNIPHY0/1/2 link A
 823  * DIG2 drives UNIPHY0/1/2 link B
 824  *
 825  * Routing
 826  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 827  * Examples:
 828  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 829  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 830  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 831  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 832  */
 833
 834 union dig_encoder_control {
 835         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 836         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 837         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 838         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 839 };
 840
 841 void
 842 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 843 {
 844         struct drm_device *dev = encoder->dev;
 845         struct radeon_device *rdev = dev->dev_private;
 846         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 847         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 848         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 849         union dig_encoder_control args;
 850         int index = 0;
 851         uint8_t frev, crev;
 852         int dp_clock = 0;
 853         int dp_lane_count = 0;
 854         int hpd_id = RADEON_HPD_NONE;
 855
 856         if (connector) {
 857                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 858                 struct radeon_connector_atom_dig *dig_connector =
 859                         radeon_connector->con_priv;
 860
 861                 dp_clock = dig_connector->dp_clock;
 862                 dp_lane_count = dig_connector->dp_lane_count;
 863                 hpd_id = radeon_connector->hpd.hpd;
 864         }
 865
 866         /* no dig encoder assigned */
 867         if (dig->dig_encoder == -1)
 868                 return;
 869
 870         memset(&args, 0, sizeof(args));
 871
 872         if (ASIC_IS_DCE4(rdev))
 873                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 874         else {
 875                 if (dig->dig_encoder)
 876                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 877                 else
 878                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 879         }
 880
 881         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 882                 return;
 883
 884         switch (frev) {
 885         case 1:
 886                 switch (crev) {
 887                 case 1:
 888                         args.v1.ucAction = action;
 889                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 890                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 891                                 args.v3.ucPanelMode = panel_mode;
 892                         else
 893                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 894
 895                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 896                                 args.v1.ucLaneNum = dp_lane_count;
 897                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 898                                 args.v1.ucLaneNum = 8;
 899                         else
 900                                 args.v1.ucLaneNum = 4;
 901
 902                         switch (radeon_encoder->encoder_id) {
 903                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 904                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 905                                 break;
 906                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 907                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 908                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 909                                 break;
 910                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 911                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 912                                 break;
 913                         }
 914                         if (dig->linkb)
 915                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 916                         else
 917                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 918
 919                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 920                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 921
 922                         break;
 923                 case 2:
 924                 case 3:
 925                         args.v3.ucAction = action;
 926                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 927                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 928                                 args.v3.ucPanelMode = panel_mode;
 929                         else
 930                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 931
 932                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 933                                 args.v3.ucLaneNum = dp_lane_count;
 934                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 935                                 args.v3.ucLaneNum = 8;
 936                         else
 937                                 args.v3.ucLaneNum = 4;
 938
 939                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 940                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 941                         if (enc_override != -1)
 942                                 args.v3.acConfig.ucDigSel = enc_override;
 943                         else
 944                                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 945                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 946                         break;
 947                 case 4:
 948                         args.v4.ucAction = action;
 949                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 950                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 951                                 args.v4.ucPanelMode = panel_mode;
 952                         else
 953                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 954
 955                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 956                                 args.v4.ucLaneNum = dp_lane_count;
 957                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 958                                 args.v4.ucLaneNum = 8;
 959                         else
 960                                 args.v4.ucLaneNum = 4;
 961
 962                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 963                                 if (dp_clock == 540000)
 964                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 965                                 else if (dp_clock == 324000)
 966                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 967                                 else if (dp_clock == 270000)
 968                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 969                                 else
 970                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 971                         }
 972
 973                         if (enc_override != -1)
 974                                 args.v4.acConfig.ucDigSel = enc_override;
 975                         else
 976                                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 977                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 978                         if (hpd_id == RADEON_HPD_NONE)
 979                                 args.v4.ucHPD_ID = 0;
 980                         else
 981                                 args.v4.ucHPD_ID = hpd_id + 1;
 982                         break;
 983                 default:
 984                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 985                         break;
 986                 }
 987                 break;
 988         default:
 989                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 990                 break;
 991         }
 992
 993         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 994
 995 }
 996
 997 void
 998 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 999 {
1000         atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1001 }
1002
1003 union dig_transmitter_control {
1004         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1005         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1006         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1007         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1008         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1009 };
1010
1011 void
1012 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1013 {
1014         struct drm_device *dev = encoder->dev;
1015         struct radeon_device *rdev = dev->dev_private;
1016         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1017         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1018         struct drm_connector *connector;
1019         union dig_transmitter_control args;
1020         int index = 0;
1021         uint8_t frev, crev;
1022         bool is_dp = false;
1023         int pll_id = 0;
1024         int dp_clock = 0;
1025         int dp_lane_count = 0;
1026         int connector_object_id = 0;
1027         int igp_lane_info = 0;
1028         int dig_encoder = dig->dig_encoder;
1029         int hpd_id = RADEON_HPD_NONE;
1030
1031         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1032                 connector = radeon_get_connector_for_encoder_init(encoder);
1033                 /* just needed to avoid bailing in the encoder check.  the encoder
1034                  * isn't used for init
1035                  */
1036                 dig_encoder = 0;
1037         } else
1038                 connector = radeon_get_connector_for_encoder(encoder);
1039
1040         if (connector) {
1041                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1042                 struct radeon_connector_atom_dig *dig_connector =
1043                         radeon_connector->con_priv;
1044
1045                 hpd_id = radeon_connector->hpd.hpd;
1046                 dp_clock = dig_connector->dp_clock;
1047                 dp_lane_count = dig_connector->dp_lane_count;
1048                 connector_object_id =
1049                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1050                 igp_lane_info = dig_connector->igp_lane_info;
1051         }
1052
1053         if (encoder->crtc) {
1054                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1055                 pll_id = radeon_crtc->pll_id;
1056         }
1057
1058         /* no dig encoder assigned */
1059         if (dig_encoder == -1)
1060                 return;
1061
1062         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1063                 is_dp = true;
1064
1065         memset(&args, 0, sizeof(args));
1066
1067         switch (radeon_encoder->encoder_id) {
1068         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1069                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1070                 break;
1071         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1072         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1073         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1074         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1075                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1076                 break;
1077         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1078                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1079                 break;
1080         }
1081
1082         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1083                 return;
1084
1085         switch (frev) {
1086         case 1:
1087                 switch (crev) {
1088                 case 1:
1089                         args.v1.ucAction = action;
1090                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1091                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1092                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1093                                 args.v1.asMode.ucLaneSel = lane_num;
1094                                 args.v1.asMode.ucLaneSet = lane_set;
1095                         } else {
1096                                 if (is_dp)
1097                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1098                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1099                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1100                                 else
1101                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1102                         }
1103
1104                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1105
1106                         if (dig_encoder)
1107                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1108                         else
1109                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1110
1111                         if ((rdev->flags & RADEON_IS_IGP) &&
1112                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1113                                 if (is_dp ||
1114                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1115                                         if (igp_lane_info & 0x1)
1116                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1117                                         else if (igp_lane_info & 0x2)
1118                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1119                                         else if (igp_lane_info & 0x4)
1120                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1121                                         else if (igp_lane_info & 0x8)
1122                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1123                                 } else {
1124                                         if (igp_lane_info & 0x3)
1125                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1126                                         else if (igp_lane_info & 0xc)
1127                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1128                                 }
1129                         }
1130
1131                         if (dig->linkb)
1132                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1133                         else
1134                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1135
1136                         if (is_dp)
1137                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1138                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1139                                 if (dig->coherent_mode)
1140                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1141                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1142                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1143                         }
1144                         break;
1145                 case 2:
1146                         args.v2.ucAction = action;
1147                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1148                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1149                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1150                                 args.v2.asMode.ucLaneSel = lane_num;
1151                                 args.v2.asMode.ucLaneSet = lane_set;
1152                         } else {
1153                                 if (is_dp)
1154                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1155                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1156                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1157                                 else
1158                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1159                         }
1160
1161                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1162                         if (dig->linkb)
1163                                 args.v2.acConfig.ucLinkSel = 1;
1164
1165                         switch (radeon_encoder->encoder_id) {
1166                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1167                                 args.v2.acConfig.ucTransmitterSel = 0;
1168                                 break;
1169                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1170                                 args.v2.acConfig.ucTransmitterSel = 1;
1171                                 break;
1172                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1173                                 args.v2.acConfig.ucTransmitterSel = 2;
1174                                 break;
1175                         }
1176
1177                         if (is_dp) {
1178                                 args.v2.acConfig.fCoherentMode = 1;
1179                                 args.v2.acConfig.fDPConnector = 1;
1180                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1181                                 if (dig->coherent_mode)
1182                                         args.v2.acConfig.fCoherentMode = 1;
1183                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1184                                         args.v2.acConfig.fDualLinkConnector = 1;
1185                         }
1186                         break;
1187                 case 3:
1188                         args.v3.ucAction = action;
1189                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1190                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1191                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1192                                 args.v3.asMode.ucLaneSel = lane_num;
1193                                 args.v3.asMode.ucLaneSet = lane_set;
1194                         } else {
1195                                 if (is_dp)
1196                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1197                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1198                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1199                                 else
1200                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1201                         }
1202
1203                         if (is_dp)
1204                                 args.v3.ucLaneNum = dp_lane_count;
1205                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1206                                 args.v3.ucLaneNum = 8;
1207                         else
1208                                 args.v3.ucLaneNum = 4;
1209
1210                         if (dig->linkb)
1211                                 args.v3.acConfig.ucLinkSel = 1;
1212                         if (dig_encoder & 1)
1213                                 args.v3.acConfig.ucEncoderSel = 1;
1214
1215                         /* Select the PLL for the PHY
1216                          * DP PHY should be clocked from external src if there is
1217                          * one.
1218                          */
1219                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1220                         if (is_dp && rdev->clock.dp_extclk)
1221                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1222                         else
1223                                 args.v3.acConfig.ucRefClkSource = pll_id;
1224
1225                         switch (radeon_encoder->encoder_id) {
1226                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1227                                 args.v3.acConfig.ucTransmitterSel = 0;
1228                                 break;
1229                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1230                                 args.v3.acConfig.ucTransmitterSel = 1;
1231                                 break;
1232                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1233                                 args.v3.acConfig.ucTransmitterSel = 2;
1234                                 break;
1235                         }
1236
1237                         if (is_dp)
1238                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1239                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1240                                 if (dig->coherent_mode)
1241                                         args.v3.acConfig.fCoherentMode = 1;
1242                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1243                                         args.v3.acConfig.fDualLinkConnector = 1;
1244                         }
1245                         break;
1246                 case 4:
1247                         args.v4.ucAction = action;
1248                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1249                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1250                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1251                                 args.v4.asMode.ucLaneSel = lane_num;
1252                                 args.v4.asMode.ucLaneSet = lane_set;
1253                         } else {
1254                                 if (is_dp)
1255                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1256                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1257                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1258                                 else
1259                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1260                         }
1261
1262                         if (is_dp)
1263                                 args.v4.ucLaneNum = dp_lane_count;
1264                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1265                                 args.v4.ucLaneNum = 8;
1266                         else
1267                                 args.v4.ucLaneNum = 4;
1268
1269                         if (dig->linkb)
1270                                 args.v4.acConfig.ucLinkSel = 1;
1271                         if (dig_encoder & 1)
1272                                 args.v4.acConfig.ucEncoderSel = 1;
1273
1274                         /* Select the PLL for the PHY
1275                          * DP PHY should be clocked from external src if there is
1276                          * one.
1277                          */
1278                         /* On DCE5 DCPLL usually generates the DP ref clock */
1279                         if (is_dp) {
1280                                 if (rdev->clock.dp_extclk)
1281                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1282                                 else
1283                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1284                         } else
1285                                 args.v4.acConfig.ucRefClkSource = pll_id;
1286
1287                         switch (radeon_encoder->encoder_id) {
1288                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1289                                 args.v4.acConfig.ucTransmitterSel = 0;
1290                                 break;
1291                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1292                                 args.v4.acConfig.ucTransmitterSel = 1;
1293                                 break;
1294                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1295                                 args.v4.acConfig.ucTransmitterSel = 2;
1296                                 break;
1297                         }
1298
1299                         if (is_dp)
1300                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1301                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1302                                 if (dig->coherent_mode)
1303                                         args.v4.acConfig.fCoherentMode = 1;
1304                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1305                                         args.v4.acConfig.fDualLinkConnector = 1;
1306                         }
1307                         break;
1308                 case 5:
1309                         args.v5.ucAction = action;
1310                         if (is_dp)
1311                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1312                         else
1313                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1314
1315                         switch (radeon_encoder->encoder_id) {
1316                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1317                                 if (dig->linkb)
1318                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1319                                 else
1320                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1321                                 break;
1322                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1323                                 if (dig->linkb)
1324                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1325                                 else
1326                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1327                                 break;
1328                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1329                                 if (dig->linkb)
1330                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1331                                 else
1332                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1333                                 break;
1334                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1335                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1336                                 break;
1337                         }
1338                         if (is_dp)
1339                                 args.v5.ucLaneNum = dp_lane_count;
1340                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1341                                 args.v5.ucLaneNum = 8;
1342                         else
1343                                 args.v5.ucLaneNum = 4;
1344                         args.v5.ucConnObjId = connector_object_id;
1345                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1346
1347                         if (is_dp && rdev->clock.dp_extclk)
1348                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1349                         else
1350                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1351
1352                         if (is_dp)
1353                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1354                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1355                                 if (dig->coherent_mode)
1356                                         args.v5.asConfig.ucCoherentMode = 1;
1357                         }
1358                         if (hpd_id == RADEON_HPD_NONE)
1359                                 args.v5.asConfig.ucHPDSel = 0;
1360                         else
1361                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1362                         args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1363                         args.v5.ucDPLaneSet = lane_set;
1364                         break;
1365                 default:
1366                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1367                         break;
1368                 }
1369                 break;
1370         default:
1371                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1372                 break;
1373         }
1374
1375         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1376 }
1377
1378 void
1379 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1380 {
1381         atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1382 }
1383
1384 bool
1385 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1386 {
1387         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1388         struct drm_device *dev = radeon_connector->base.dev;
1389         struct radeon_device *rdev = dev->dev_private;
1390         union dig_transmitter_control args;
1391         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1392         uint8_t frev, crev;
1393
1394         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1395                 goto done;
1396
1397         if (!ASIC_IS_DCE4(rdev))
1398                 goto done;
1399
1400         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1401             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1402                 goto done;
1403
1404         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1405                 goto done;
1406
1407         memset(&args, 0, sizeof(args));
1408
1409         args.v1.ucAction = action;
1410
1411         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1412
1413         /* wait for the panel to power up */
1414         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1415                 int i;
1416
1417                 for (i = 0; i < 300; i++) {
1418                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1419                                 return true;
1420                         mdelay(1);
1421                 }
1422                 return false;
1423         }
1424 done:
1425         return true;
1426 }
1427
1428 union external_encoder_control {
1429         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1430         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1431 };
1432
1433 static void
1434 atombios_external_encoder_setup(struct drm_encoder *encoder,
1435                                 struct drm_encoder *ext_encoder,
1436                                 int action)
1437 {
1438         struct drm_device *dev = encoder->dev;
1439         struct radeon_device *rdev = dev->dev_private;
1440         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1441         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1442         union external_encoder_control args;
1443         struct drm_connector *connector;
1444         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1445         u8 frev, crev;
1446         int dp_clock = 0;
1447         int dp_lane_count = 0;
1448         int connector_object_id = 0;
1449         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1450
1451         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1452                 connector = radeon_get_connector_for_encoder_init(encoder);
1453         else
1454                 connector = radeon_get_connector_for_encoder(encoder);
1455
1456         if (connector) {
1457                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1458                 struct radeon_connector_atom_dig *dig_connector =
1459                         radeon_connector->con_priv;
1460
1461                 dp_clock = dig_connector->dp_clock;
1462                 dp_lane_count = dig_connector->dp_lane_count;
1463                 connector_object_id =
1464                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1465         }
1466
1467         memset(&args, 0, sizeof(args));
1468
1469         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1470                 return;
1471
1472         switch (frev) {
1473         case 1:
1474                 /* no params on frev 1 */
1475                 break;
1476         case 2:
1477                 switch (crev) {
1478                 case 1:
1479                 case 2:
1480                         args.v1.sDigEncoder.ucAction = action;
1481                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1482                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1483
1484                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1485                                 if (dp_clock == 270000)
1486                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1487                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1488                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1489                                 args.v1.sDigEncoder.ucLaneNum = 8;
1490                         else
1491                                 args.v1.sDigEncoder.ucLaneNum = 4;
1492                         break;
1493                 case 3:
1494                         args.v3.sExtEncoder.ucAction = action;
1495                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1496                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1497                         else
1498                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1499                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1500
1501                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1502                                 if (dp_clock == 270000)
1503                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1504                                 else if (dp_clock == 540000)
1505                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1506                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1507                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1508                                 args.v3.sExtEncoder.ucLaneNum = 8;
1509                         else
1510                                 args.v3.sExtEncoder.ucLaneNum = 4;
1511                         switch (ext_enum) {
1512                         case GRAPH_OBJECT_ENUM_ID1:
1513                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1514                                 break;
1515                         case GRAPH_OBJECT_ENUM_ID2:
1516                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1517                                 break;
1518                         case GRAPH_OBJECT_ENUM_ID3:
1519                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1520                                 break;
1521                         }
1522                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1523                         break;
1524                 default:
1525                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1526                         return;
1527                 }
1528                 break;
1529         default:
1530                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1531                 return;
1532         }
1533         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1534 }
1535
1536 static void
1537 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1538 {
1539         struct drm_device *dev = encoder->dev;
1540         struct radeon_device *rdev = dev->dev_private;
1541         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1542         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1543         ENABLE_YUV_PS_ALLOCATION args;
1544         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1545         uint32_t temp, reg;
1546
1547         memset(&args, 0, sizeof(args));
1548
1549         if (rdev->family >= CHIP_R600)
1550                 reg = R600_BIOS_3_SCRATCH;
1551         else
1552                 reg = RADEON_BIOS_3_SCRATCH;
1553
1554         /* XXX: fix up scratch reg handling */
1555         temp = RREG32(reg);
1556         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1557                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1558                              (radeon_crtc->crtc_id << 18)));
1559         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1560                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1561         else
1562                 WREG32(reg, 0);
1563
1564         if (enable)
1565                 args.ucEnable = ATOM_ENABLE;
1566         args.ucCRTC = radeon_crtc->crtc_id;
1567
1568         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1569
1570         WREG32(reg, temp);
1571 }
1572
1573 static void
1574 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1575 {
1576         struct drm_device *dev = encoder->dev;
1577         struct radeon_device *rdev = dev->dev_private;
1578         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1579         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1580         int index = 0;
1581
1582         memset(&args, 0, sizeof(args));
1583
1584         switch (radeon_encoder->encoder_id) {
1585         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1586         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1587                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1588                 break;
1589         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1590         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1591         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1592                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1593                 break;
1594         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1595                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1596                 break;
1597         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1598                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1599                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1600                 else
1601                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1602                 break;
1603         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1604         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1605                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1606                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1607                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1608                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1609                 else
1610                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1611                 break;
1612         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1613         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1614                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1615                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1616                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1617                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1618                 else
1619                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1620                 break;
1621         default:
1622                 return;
1623         }
1624
1625         switch (mode) {
1626         case DRM_MODE_DPMS_ON:
1627                 args.ucAction = ATOM_ENABLE;
1628                 /* workaround for DVOOutputControl on some RS690 systems */
1629                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1630                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1631                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1632                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1633                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1634                 } else
1635                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1636                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1637                         if (rdev->mode_info.bl_encoder) {
1638                                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1639
1640                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1641                         } else {
1642                                 args.ucAction = ATOM_LCD_BLON;
1643                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1644                         }
1645                 }
1646                 break;
1647         case DRM_MODE_DPMS_STANDBY:
1648         case DRM_MODE_DPMS_SUSPEND:
1649         case DRM_MODE_DPMS_OFF:
1650                 args.ucAction = ATOM_DISABLE;
1651                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1652                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1653                         args.ucAction = ATOM_LCD_BLOFF;
1654                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1655                 }
1656                 break;
1657         }
1658 }
1659
1660 static void
1661 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1662 {
1663         struct drm_device *dev = encoder->dev;
1664         struct radeon_device *rdev = dev->dev_private;
1665         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1666         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1667         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1668         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1669         struct radeon_connector *radeon_connector = NULL;
1670         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1671         bool travis_quirk = false;
1672
1673         if (connector) {
1674                 radeon_connector = to_radeon_connector(connector);
1675                 radeon_dig_connector = radeon_connector->con_priv;
1676                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1677                      ENCODER_OBJECT_ID_TRAVIS) &&
1678                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1679                     !ASIC_IS_DCE5(rdev))
1680                         travis_quirk = true;
1681         }
1682
1683         switch (mode) {
1684         case DRM_MODE_DPMS_ON:
1685                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1686                         if (!connector)
1687                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1688                         else
1689                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1690
1691                         /* setup and enable the encoder */
1692                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1693                         atombios_dig_encoder_setup(encoder,
1694                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1695                                                    dig->panel_mode);
1696                         if (ext_encoder) {
1697                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1698                                         atombios_external_encoder_setup(encoder, ext_encoder,
1699                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1700                         }
1701                 } else if (ASIC_IS_DCE4(rdev)) {
1702                         /* setup and enable the encoder */
1703                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1704                 } else {
1705                         /* setup and enable the encoder and transmitter */
1706                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1707                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1708                 }
1709                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1710                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1711                                 atombios_set_edp_panel_power(connector,
1712                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1713                                 radeon_dig_connector->edp_on = true;
1714                         }
1715                 }
1716                 /* enable the transmitter */
1717                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1718                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1719                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1720                         radeon_dp_link_train(encoder, connector);
1721                         if (ASIC_IS_DCE4(rdev))
1722                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1723                 }
1724                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1725                         if (rdev->mode_info.bl_encoder)
1726                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1727                         else
1728                                 atombios_dig_transmitter_setup(encoder,
1729                                                                ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1730                 }
1731                 if (ext_encoder)
1732                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1733                 break;
1734         case DRM_MODE_DPMS_STANDBY:
1735         case DRM_MODE_DPMS_SUSPEND:
1736         case DRM_MODE_DPMS_OFF:
1737
1738                 /* don't power off encoders with active MST links */
1739                 if (dig->active_mst_links)
1740                         return;
1741
1742                 if (ASIC_IS_DCE4(rdev)) {
1743                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1744                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1745                 }
1746                 if (ext_encoder)
1747                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1748                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1749                         atombios_dig_transmitter_setup(encoder,
1750                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1751
1752                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1753                     connector && !travis_quirk)
1754                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1755                 if (ASIC_IS_DCE4(rdev)) {
1756                         /* disable the transmitter */
1757                         atombios_dig_transmitter_setup(encoder,
1758                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1759                 } else {
1760                         /* disable the encoder and transmitter */
1761                         atombios_dig_transmitter_setup(encoder,
1762                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1763                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1764                 }
1765                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1766                         if (travis_quirk)
1767                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1768                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1769                                 atombios_set_edp_panel_power(connector,
1770                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1771                                 radeon_dig_connector->edp_on = false;
1772                         }
1773                 }
1774                 break;
1775         }
1776 }
1777
1778 static void
1779 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1780 {
1781         struct drm_device *dev = encoder->dev;
1782         struct radeon_device *rdev = dev->dev_private;
1783         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1784         int encoder_mode = atombios_get_encoder_mode(encoder);
1785
1786         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1787                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1788                   radeon_encoder->active_device);
1789
1790         if ((radeon_audio != 0) &&
1791             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1792              ENCODER_MODE_IS_DP(encoder_mode)))
1793                 radeon_audio_dpms(encoder, mode);
1794
1795         switch (radeon_encoder->encoder_id) {
1796         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1797         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1798         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1799         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1800         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1801         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1802         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1803         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1804                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1805                 break;
1806         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1807         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1808         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1809         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1810         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1811                 radeon_atom_encoder_dpms_dig(encoder, mode);
1812                 break;
1813         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1814                 if (ASIC_IS_DCE5(rdev)) {
1815                         switch (mode) {
1816                         case DRM_MODE_DPMS_ON:
1817                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1818                                 break;
1819                         case DRM_MODE_DPMS_STANDBY:
1820                         case DRM_MODE_DPMS_SUSPEND:
1821                         case DRM_MODE_DPMS_OFF:
1822                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1823                                 break;
1824                         }
1825                 } else if (ASIC_IS_DCE3(rdev))
1826                         radeon_atom_encoder_dpms_dig(encoder, mode);
1827                 else
1828                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1829                 break;
1830         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1831         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1832                 if (ASIC_IS_DCE5(rdev)) {
1833                         switch (mode) {
1834                         case DRM_MODE_DPMS_ON:
1835                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1836                                 break;
1837                         case DRM_MODE_DPMS_STANDBY:
1838                         case DRM_MODE_DPMS_SUSPEND:
1839                         case DRM_MODE_DPMS_OFF:
1840                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1841                                 break;
1842                         }
1843                 } else
1844                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1845                 break;
1846         default:
1847                 return;
1848         }
1849
1850         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1851
1852 }
1853
1854 union crtc_source_param {
1855         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1856         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1857 };
1858
1859 static void
1860 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1861 {
1862         struct drm_device *dev = encoder->dev;
1863         struct radeon_device *rdev = dev->dev_private;
1864         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1865         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1866         union crtc_source_param args;
1867         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1868         uint8_t frev, crev;
1869         struct radeon_encoder_atom_dig *dig;
1870
1871         memset(&args, 0, sizeof(args));
1872
1873         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1874                 return;
1875
1876         switch (frev) {
1877         case 1:
1878                 switch (crev) {
1879                 case 1:
1880                 default:
1881                         if (ASIC_IS_AVIVO(rdev))
1882                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1883                         else {
1884                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1885                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1886                                 } else {
1887                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1888                                 }
1889                         }
1890                         switch (radeon_encoder->encoder_id) {
1891                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1892                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1893                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1894                                 break;
1895                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1896                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1897                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1898                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1899                                 else
1900                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1901                                 break;
1902                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1903                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1904                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1905                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1906                                 break;
1907                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1908                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1909                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1910                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1911                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1912                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1913                                 else
1914                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1915                                 break;
1916                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1917                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1918                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1919                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1920                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1921                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1922                                 else
1923                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1924                                 break;
1925                         }
1926                         break;
1927                 case 2:
1928                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1929                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1930                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1931
1932                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1933                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1934                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1935                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1936                                 else
1937                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1938                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1939                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1940                         } else {
1941                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1942                         }
1943                         switch (radeon_encoder->encoder_id) {
1944                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1945                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1946                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1947                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1948                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1949                                 dig = radeon_encoder->enc_priv;
1950                                 switch (dig->dig_encoder) {
1951                                 case 0:
1952                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1953                                         break;
1954                                 case 1:
1955                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1956                                         break;
1957                                 case 2:
1958                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1959                                         break;
1960                                 case 3:
1961                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1962                                         break;
1963                                 case 4:
1964                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1965                                         break;
1966                                 case 5:
1967                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1968                                         break;
1969                                 case 6:
1970                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1971                                         break;
1972                                 }
1973                                 break;
1974                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1975                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1976                                 break;
1977                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1978                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1979                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1980                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1981                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1982                                 else
1983                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1984                                 break;
1985                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1986                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1987                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1988                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1989                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1990                                 else
1991                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1992                                 break;
1993                         }
1994                         break;
1995                 }
1996                 break;
1997         default:
1998                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1999                 return;
2000         }
2001
2002         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2003
2004         /* update scratch regs with new routing */
2005         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2006 }
2007
2008 void
2009 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2010 {
2011         struct drm_device *dev = encoder->dev;
2012         struct radeon_device *rdev = dev->dev_private;
2013         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2014         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2015         uint8_t frev, crev;
2016         union crtc_source_param args;
2017
2018         memset(&args, 0, sizeof(args));
2019
2020         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2021                 return;
2022
2023         if (frev != 1 && crev != 2)
2024                 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2025
2026         args.v2.ucCRTC = radeon_crtc->crtc_id;
2027         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2028
2029         switch (fe) {
2030         case 0:
2031                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2032                 break;
2033         case 1:
2034                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2035                 break;
2036         case 2:
2037                 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2038                 break;
2039         case 3:
2040                 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2041                 break;
2042         case 4:
2043                 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2044                 break;
2045         case 5:
2046                 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2047                 break;
2048         case 6:
2049                 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2050                 break;
2051         }
2052         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2053 }
2054
2055 static void
2056 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2057                               struct drm_display_mode *mode)
2058 {
2059         struct drm_device *dev = encoder->dev;
2060         struct radeon_device *rdev = dev->dev_private;
2061         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2062         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2063
2064         /* Funky macbooks */
2065         if ((dev->pdev->device == 0x71C5) &&
2066             (dev->pdev->subsystem_vendor == 0x106b) &&
2067             (dev->pdev->subsystem_device == 0x0080)) {
2068                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2069                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2070
2071                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2072                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2073
2074                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2075                 }
2076         }
2077
2078         /* set scaler clears this on some chips */
2079         if (ASIC_IS_AVIVO(rdev) &&
2080             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2081                 if (ASIC_IS_DCE8(rdev)) {
2082                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2083                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2084                                        CIK_INTERLEAVE_EN);
2085                         else
2086                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2087                 } else if (ASIC_IS_DCE4(rdev)) {
2088                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2089                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2090                                        EVERGREEN_INTERLEAVE_EN);
2091                         else
2092                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2093                 } else {
2094                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2095                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2096                                        AVIVO_D1MODE_INTERLEAVE_EN);
2097                         else
2098                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2099                 }
2100         }
2101 }
2102
2103 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2104 {
2105         if (enc_idx < 0)
2106                 return;
2107         rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2108 }
2109
2110 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2111 {
2112         struct drm_device *dev = encoder->dev;
2113         struct radeon_device *rdev = dev->dev_private;
2114         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2115         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2116         struct drm_encoder *test_encoder;
2117         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2118         uint32_t dig_enc_in_use = 0;
2119         int enc_idx = -1;
2120
2121         if (fe_idx >= 0) {
2122                 enc_idx = fe_idx;
2123                 goto assigned;
2124         }
2125         if (ASIC_IS_DCE6(rdev)) {
2126                 /* DCE6 */
2127                 switch (radeon_encoder->encoder_id) {
2128                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2129                         if (dig->linkb)
2130                                 enc_idx = 1;
2131                         else
2132                                 enc_idx = 0;
2133                         break;
2134                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2135                         if (dig->linkb)
2136                                 enc_idx = 3;
2137                         else
2138                                 enc_idx = 2;
2139                         break;
2140                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2141                         if (dig->linkb)
2142                                 enc_idx = 5;
2143                         else
2144                                 enc_idx = 4;
2145                         break;
2146                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2147                         enc_idx = 6;
2148                         break;
2149                 }
2150                 goto assigned;
2151         } else if (ASIC_IS_DCE4(rdev)) {
2152                 /* DCE4/5 */
2153                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2154                         /* ontario follows DCE4 */
2155                         if (rdev->family == CHIP_PALM) {
2156                                 if (dig->linkb)
2157                                         enc_idx = 1;
2158                                 else
2159                                         enc_idx = 0;
2160                         } else
2161                                 /* llano follows DCE3.2 */
2162                                 enc_idx = radeon_crtc->crtc_id;
2163                 } else {
2164                         switch (radeon_encoder->encoder_id) {
2165                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2166                                 if (dig->linkb)
2167                                         enc_idx = 1;
2168                                 else
2169                                         enc_idx = 0;
2170                                 break;
2171                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2172                                 if (dig->linkb)
2173                                         enc_idx = 3;
2174                                 else
2175                                         enc_idx = 2;
2176                                 break;
2177                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2178                                 if (dig->linkb)
2179                                         enc_idx = 5;
2180                                 else
2181                                         enc_idx = 4;
2182                                 break;
2183                         }
2184                 }
2185                 goto assigned;
2186         }
2187
2188         /*
2189          * On DCE32 any encoder can drive any block so usually just use crtc id,
2190          * but Apple thinks different at least on iMac10,1, so there use linkb,
2191          * otherwise the internal eDP panel will stay dark.
2192          */
2193         if (ASIC_IS_DCE32(rdev)) {
2194                 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2195                         enc_idx = (dig->linkb) ? 1 : 0;
2196                 else
2197                         enc_idx = radeon_crtc->crtc_id;
2198
2199                 goto assigned;
2200         }
2201
2202         /* on DCE3 - LVTMA can only be driven by DIGB */
2203         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2204                 struct radeon_encoder *radeon_test_encoder;
2205
2206                 if (encoder == test_encoder)
2207                         continue;
2208
2209                 if (!radeon_encoder_is_digital(test_encoder))
2210                         continue;
2211
2212                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2213                 dig = radeon_test_encoder->enc_priv;
2214
2215                 if (dig->dig_encoder >= 0)
2216                         dig_enc_in_use |= (1 << dig->dig_encoder);
2217         }
2218
2219         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2220                 if (dig_enc_in_use & 0x2)
2221                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2222                 return 1;
2223         }
2224         if (!(dig_enc_in_use & 1))
2225                 return 0;
2226         return 1;
2227
2228 assigned:
2229         if (enc_idx == -1) {
2230                 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2231                 return 0;
2232         }
2233         if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2234                 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2235         }
2236         rdev->mode_info.active_encoders |= (1 << enc_idx);
2237         return enc_idx;
2238 }
2239
2240 /* This only needs to be called once at startup */
2241 void
2242 radeon_atom_encoder_init(struct radeon_device *rdev)
2243 {
2244         struct drm_device *dev = rdev->ddev;
2245         struct drm_encoder *encoder;
2246
2247         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2248                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2249                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2250
2251                 switch (radeon_encoder->encoder_id) {
2252                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2253                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2254                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2255                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2256                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2257                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2258                         break;
2259                 default:
2260                         break;
2261                 }
2262
2263                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2264                         atombios_external_encoder_setup(encoder, ext_encoder,
2265                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2266         }
2267 }
2268
2269 static void
2270 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2271                              struct drm_display_mode *mode,
2272                              struct drm_display_mode *adjusted_mode)
2273 {
2274         struct drm_device *dev = encoder->dev;
2275         struct radeon_device *rdev = dev->dev_private;
2276         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2277         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2278         int encoder_mode;
2279
2280         radeon_encoder->pixel_clock = adjusted_mode->clock;
2281
2282         /* need to call this here rather than in prepare() since we need some crtc info */
2283         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2284
2285         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2286                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2287                         atombios_yuv_setup(encoder, true);
2288                 else
2289                         atombios_yuv_setup(encoder, false);
2290         }
2291
2292         switch (radeon_encoder->encoder_id) {
2293         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2294         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2295         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2296         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2297                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2298                 break;
2299         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2300         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2301         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2302         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2303         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2304                 /* handled in dpms */
2305                 break;
2306         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2307         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2308         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2309                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2310                 break;
2311         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2312         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2313         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2314         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2315                 atombios_dac_setup(encoder, ATOM_ENABLE);
2316                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2317                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2318                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2319                         else
2320                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2321                 }
2322                 break;
2323         }
2324
2325         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2326
2327         encoder_mode = atombios_get_encoder_mode(encoder);
2328         if (connector && (radeon_audio != 0) &&
2329             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2330              ENCODER_MODE_IS_DP(encoder_mode)))
2331                 radeon_audio_mode_set(encoder, adjusted_mode);
2332 }
2333
2334 static bool
2335 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2336 {
2337         struct drm_device *dev = encoder->dev;
2338         struct radeon_device *rdev = dev->dev_private;
2339         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2340         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2341
2342         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2343                                        ATOM_DEVICE_CV_SUPPORT |
2344                                        ATOM_DEVICE_CRT_SUPPORT)) {
2345                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2346                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2347                 uint8_t frev, crev;
2348
2349                 memset(&args, 0, sizeof(args));
2350
2351                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2352                         return false;
2353
2354                 args.sDacload.ucMisc = 0;
2355
2356                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2357                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2358                         args.sDacload.ucDacType = ATOM_DAC_A;
2359                 else
2360                         args.sDacload.ucDacType = ATOM_DAC_B;
2361
2362                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2363                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2364                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2365                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2366                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2367                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2368                         if (crev >= 3)
2369                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2370                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2371                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2372                         if (crev >= 3)
2373                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2374                 }
2375
2376                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2377
2378                 return true;
2379         } else
2380                 return false;
2381 }
2382
2383 static enum drm_connector_status
2384 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2385 {
2386         struct drm_device *dev = encoder->dev;
2387         struct radeon_device *rdev = dev->dev_private;
2388         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2389         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2390         uint32_t bios_0_scratch;
2391
2392         if (!atombios_dac_load_detect(encoder, connector)) {
2393                 DRM_DEBUG_KMS("detect returned false \n");
2394                 return connector_status_unknown;
2395         }
2396
2397         if (rdev->family >= CHIP_R600)
2398                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2399         else
2400                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2401
2402         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2403         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2404                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2405                         return connector_status_connected;
2406         }
2407         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2408                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2409                         return connector_status_connected;
2410         }
2411         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2412                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2413                         return connector_status_connected;
2414         }
2415         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2416                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2417                         return connector_status_connected; /* CTV */
2418                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2419                         return connector_status_connected; /* STV */
2420         }
2421         return connector_status_disconnected;
2422 }
2423
2424 static enum drm_connector_status
2425 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2426 {
2427         struct drm_device *dev = encoder->dev;
2428         struct radeon_device *rdev = dev->dev_private;
2429         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2430         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2431         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2432         u32 bios_0_scratch;
2433
2434         if (!ASIC_IS_DCE4(rdev))
2435                 return connector_status_unknown;
2436
2437         if (!ext_encoder)
2438                 return connector_status_unknown;
2439
2440         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2441                 return connector_status_unknown;
2442
2443         /* load detect on the dp bridge */
2444         atombios_external_encoder_setup(encoder, ext_encoder,
2445                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2446
2447         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2448
2449         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2450         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2451                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2452                         return connector_status_connected;
2453         }
2454         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2455                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2456                         return connector_status_connected;
2457         }
2458         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2459                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2460                         return connector_status_connected;
2461         }
2462         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2463                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2464                         return connector_status_connected; /* CTV */
2465                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2466                         return connector_status_connected; /* STV */
2467         }
2468         return connector_status_disconnected;
2469 }
2470
2471 void
2472 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2473 {
2474         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2475
2476         if (ext_encoder)
2477                 /* ddc_setup on the dp bridge */
2478                 atombios_external_encoder_setup(encoder, ext_encoder,
2479                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2480
2481 }
2482
2483 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2484 {
2485         struct radeon_device *rdev = encoder->dev->dev_private;
2486         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2487         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2488
2489         if ((radeon_encoder->active_device &
2490              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2491             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2492              ENCODER_OBJECT_ID_NONE)) {
2493                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2494                 if (dig) {
2495                         if (dig->dig_encoder >= 0)
2496                                 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2497                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2498                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2499                                 if (rdev->family >= CHIP_R600)
2500                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2501                                 else
2502                                         /* RS600/690/740 have only 1 afmt block */
2503                                         dig->afmt = rdev->mode_info.afmt[0];
2504                         }
2505                 }
2506         }
2507
2508         radeon_atom_output_lock(encoder, true);
2509
2510         if (connector) {
2511                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2512
2513                 /* select the clock/data port if it uses a router */
2514                 if (radeon_connector->router.cd_valid)
2515                         radeon_router_select_cd_port(radeon_connector);
2516
2517                 /* turn eDP panel on for mode set */
2518                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2519                         atombios_set_edp_panel_power(connector,
2520                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2521         }
2522
2523         /* this is needed for the pll/ss setup to work correctly in some cases */
2524         atombios_set_encoder_crtc_source(encoder);
2525         /* set up the FMT blocks */
2526         if (ASIC_IS_DCE8(rdev))
2527                 dce8_program_fmt(encoder);
2528         else if (ASIC_IS_DCE4(rdev))
2529                 dce4_program_fmt(encoder);
2530         else if (ASIC_IS_DCE3(rdev))
2531                 dce3_program_fmt(encoder);
2532         else if (ASIC_IS_AVIVO(rdev))
2533                 avivo_program_fmt(encoder);
2534 }
2535
2536 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2537 {
2538         /* need to call this here as we need the crtc set up */
2539         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2540         radeon_atom_output_lock(encoder, false);
2541 }
2542
2543 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2544 {
2545         struct drm_device *dev = encoder->dev;
2546         struct radeon_device *rdev = dev->dev_private;
2547         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2548         struct radeon_encoder_atom_dig *dig;
2549
2550         /* check for pre-DCE3 cards with shared encoders;
2551          * can't really use the links individually, so don't disable
2552          * the encoder if it's in use by another connector
2553          */
2554         if (!ASIC_IS_DCE3(rdev)) {
2555                 struct drm_encoder *other_encoder;
2556                 struct radeon_encoder *other_radeon_encoder;
2557
2558                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2559                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2560                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2561                             drm_helper_encoder_in_use(other_encoder))
2562                                 goto disable_done;
2563                 }
2564         }
2565
2566         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2567
2568         switch (radeon_encoder->encoder_id) {
2569         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2570         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2571         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2572         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2573                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2574                 break;
2575         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2576         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2577         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2578         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2579         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2580                 /* handled in dpms */
2581                 break;
2582         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2583         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2584         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2585                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2586                 break;
2587         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2588         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2589         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2590         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2591                 atombios_dac_setup(encoder, ATOM_DISABLE);
2592                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2593                         atombios_tv_setup(encoder, ATOM_DISABLE);
2594                 break;
2595         }
2596
2597 disable_done:
2598         if (radeon_encoder_is_digital(encoder)) {
2599                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2600                         if (rdev->asic->display.hdmi_enable)
2601                                 radeon_hdmi_enable(rdev, encoder, false);
2602                 }
2603                 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2604                         dig = radeon_encoder->enc_priv;
2605                         radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2606                         dig->dig_encoder = -1;
2607                         radeon_encoder->active_device = 0;
2608                 }
2609         } else
2610                 radeon_encoder->active_device = 0;
2611 }
2612
2613 /* these are handled by the primary encoders */
2614 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2615 {
2616
2617 }
2618
2619 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2620 {
2621
2622 }
2623
2624 static void
2625 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2626                          struct drm_display_mode *mode,
2627                          struct drm_display_mode *adjusted_mode)
2628 {
2629
2630 }
2631
2632 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2633 {
2634
2635 }
2636
2637 static void
2638 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2639 {
2640
2641 }
2642
2643 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2644         .dpms = radeon_atom_ext_dpms,
2645         .prepare = radeon_atom_ext_prepare,
2646         .mode_set = radeon_atom_ext_mode_set,
2647         .commit = radeon_atom_ext_commit,
2648         .disable = radeon_atom_ext_disable,
2649         /* no detect for TMDS/LVDS yet */
2650 };
2651
2652 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2653         .dpms = radeon_atom_encoder_dpms,
2654         .mode_fixup = radeon_atom_mode_fixup,
2655         .prepare = radeon_atom_encoder_prepare,
2656         .mode_set = radeon_atom_encoder_mode_set,
2657         .commit = radeon_atom_encoder_commit,
2658         .disable = radeon_atom_encoder_disable,
2659         .detect = radeon_atom_dig_detect,
2660 };
2661
2662 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2663         .dpms = radeon_atom_encoder_dpms,
2664         .mode_fixup = radeon_atom_mode_fixup,
2665         .prepare = radeon_atom_encoder_prepare,
2666         .mode_set = radeon_atom_encoder_mode_set,
2667         .commit = radeon_atom_encoder_commit,
2668         .detect = radeon_atom_dac_detect,
2669 };
2670
2671 void radeon_enc_destroy(struct drm_encoder *encoder)
2672 {
2673         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2674         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2675                 radeon_atom_backlight_exit(radeon_encoder);
2676         kfree(radeon_encoder->enc_priv);
2677         drm_encoder_cleanup(encoder);
2678         kfree(radeon_encoder);
2679 }
2680
2681 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2682         .destroy = radeon_enc_destroy,
2683 };
2684
2685 static struct radeon_encoder_atom_dac *
2686 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2687 {
2688         struct drm_device *dev = radeon_encoder->base.dev;
2689         struct radeon_device *rdev = dev->dev_private;
2690         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2691
2692         if (!dac)
2693                 return NULL;
2694
2695         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2696         return dac;
2697 }
2698
2699 static struct radeon_encoder_atom_dig *
2700 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2701 {
2702         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2703         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2704
2705         if (!dig)
2706                 return NULL;
2707
2708         /* coherent mode by default */
2709         dig->coherent_mode = true;
2710         dig->dig_encoder = -1;
2711
2712         if (encoder_enum == 2)
2713                 dig->linkb = true;
2714         else
2715                 dig->linkb = false;
2716
2717         return dig;
2718 }
2719
2720 void
2721 radeon_add_atom_encoder(struct drm_device *dev,
2722                         uint32_t encoder_enum,
2723                         uint32_t supported_device,
2724                         u16 caps)
2725 {
2726         struct radeon_device *rdev = dev->dev_private;
2727         struct drm_encoder *encoder;
2728         struct radeon_encoder *radeon_encoder;
2729
2730         /* see if we already added it */
2731         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2732                 radeon_encoder = to_radeon_encoder(encoder);
2733                 if (radeon_encoder->encoder_enum == encoder_enum) {
2734                         radeon_encoder->devices |= supported_device;
2735                         return;
2736                 }
2737
2738         }
2739
2740         /* add a new one */
2741         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2742         if (!radeon_encoder)
2743                 return;
2744
2745         encoder = &radeon_encoder->base;
2746         switch (rdev->num_crtc) {
2747         case 1:
2748                 encoder->possible_crtcs = 0x1;
2749                 break;
2750         case 2:
2751         default:
2752                 encoder->possible_crtcs = 0x3;
2753                 break;
2754         case 4:
2755                 encoder->possible_crtcs = 0xf;
2756                 break;
2757         case 6:
2758                 encoder->possible_crtcs = 0x3f;
2759                 break;
2760         }
2761
2762         radeon_encoder->enc_priv = NULL;
2763
2764         radeon_encoder->encoder_enum = encoder_enum;
2765         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2766         radeon_encoder->devices = supported_device;
2767         radeon_encoder->rmx_type = RMX_OFF;
2768         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2769         radeon_encoder->is_ext_encoder = false;
2770         radeon_encoder->caps = caps;
2771
2772         switch (radeon_encoder->encoder_id) {
2773         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2774         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2775         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2776         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2777                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2778                         radeon_encoder->rmx_type = RMX_FULL;
2779                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2780                                          DRM_MODE_ENCODER_LVDS, NULL);
2781                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2782                 } else {
2783                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2784                                          DRM_MODE_ENCODER_TMDS, NULL);
2785                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2786                 }
2787                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2788                 break;
2789         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2790                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2791                                  DRM_MODE_ENCODER_DAC, NULL);
2792                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2793                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2794                 break;
2795         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2796         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2797         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2798                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2799                                  DRM_MODE_ENCODER_TVDAC, NULL);
2800                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2801                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2802                 break;
2803         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2804         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2805         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2806         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2807         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2808         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2809         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2810         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2811                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2812                         radeon_encoder->rmx_type = RMX_FULL;
2813                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2814                                          DRM_MODE_ENCODER_LVDS, NULL);
2815                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2816                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2817                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2818                                          DRM_MODE_ENCODER_DAC, NULL);
2819                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2820                 } else {
2821                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2822                                          DRM_MODE_ENCODER_TMDS, NULL);
2823                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2824                 }
2825                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2826                 break;
2827         case ENCODER_OBJECT_ID_SI170B:
2828         case ENCODER_OBJECT_ID_CH7303:
2829         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2830         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2831         case ENCODER_OBJECT_ID_TITFP513:
2832         case ENCODER_OBJECT_ID_VT1623:
2833         case ENCODER_OBJECT_ID_HDMI_SI1930:
2834         case ENCODER_OBJECT_ID_TRAVIS:
2835         case ENCODER_OBJECT_ID_NUTMEG:
2836                 /* these are handled by the primary encoders */
2837                 radeon_encoder->is_ext_encoder = true;
2838                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2839                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2840                                          DRM_MODE_ENCODER_LVDS, NULL);
2841                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2842                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2843                                          DRM_MODE_ENCODER_DAC, NULL);
2844                 else
2845                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2846                                          DRM_MODE_ENCODER_TMDS, NULL);
2847                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2848                 break;
2849         }
2850 }