drivers/gpu/drm/r128/r128_drv.h

   1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
   3  */
   4 /*
   5  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   6  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   7  * All rights reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Rickard E. (Rik) Faith <faith@valinux.com>
  30  *    Kevin E. Martin <martin@valinux.com>
  31  *    Gareth Hughes <gareth@valinux.com>
  32  *    Michel D�zer <daenzerm@student.ethz.ch>
  33  */
  34
  35 #ifndef __R128_DRV_H__
  36 #define __R128_DRV_H__
  37
  38 #include <linux/delay.h>
  39 #include <linux/io.h>
  40 #include <linux/irqreturn.h>
  41
  42 #include <drm/drm_ioctl.h>
  43 #include <drm/drm_legacy.h>
  44 #include <drm/r128_drm.h>
  45
  46 #include "ati_pcigart.h"
  47
  48 /* General customization:
  49  */
  50 #define DRIVER_AUTHOR           "Gareth Hughes, VA Linux Systems Inc."
  51
  52 #define DRIVER_NAME             "r128"
  53 #define DRIVER_DESC             "ATI Rage 128"
  54 #define DRIVER_DATE             "20030725"
  55
  56 /* Interface history:
  57  *
  58  * ??  - ??
  59  * 2.4 - Add support for ycbcr textures (no new ioctls)
  60  * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
  61  */
  62 #define DRIVER_MAJOR            2
  63 #define DRIVER_MINOR            5
  64 #define DRIVER_PATCHLEVEL       0
  65
  66 #define GET_RING_HEAD(dev_priv)         R128_READ(R128_PM4_BUFFER_DL_RPTR)
  67
  68 typedef struct drm_r128_freelist {
  69         unsigned int age;
  70         struct drm_buf *buf;
  71         struct drm_r128_freelist *next;
  72         struct drm_r128_freelist *prev;
  73 } drm_r128_freelist_t;
  74
  75 typedef struct drm_r128_ring_buffer {
  76         u32 *start;
  77         u32 *end;
  78         int size;
  79         int size_l2qw;
  80
  81         u32 tail;
  82         u32 tail_mask;
  83         int space;
  84
  85         int high_mark;
  86 } drm_r128_ring_buffer_t;
  87
  88 typedef struct drm_r128_private {
  89         drm_r128_ring_buffer_t ring;
  90         drm_r128_sarea_t *sarea_priv;
  91
  92         int cce_mode;
  93         int cce_fifo_size;
  94         int cce_running;
  95
  96         drm_r128_freelist_t *head;
  97         drm_r128_freelist_t *tail;
  98
  99         int usec_timeout;
 100         int is_pci;
 101         unsigned long cce_buffers_offset;
 102
 103         atomic_t idle_count;
 104
 105         int page_flipping;
 106         int current_page;
 107         u32 crtc_offset;
 108         u32 crtc_offset_cntl;
 109
 110         atomic_t vbl_received;
 111
 112         u32 color_fmt;
 113         unsigned int front_offset;
 114         unsigned int front_pitch;
 115         unsigned int back_offset;
 116         unsigned int back_pitch;
 117
 118         u32 depth_fmt;
 119         unsigned int depth_offset;
 120         unsigned int depth_pitch;
 121         unsigned int span_offset;
 122
 123         u32 front_pitch_offset_c;
 124         u32 back_pitch_offset_c;
 125         u32 depth_pitch_offset_c;
 126         u32 span_pitch_offset_c;
 127
 128         drm_local_map_t *sarea;
 129         drm_local_map_t *mmio;
 130         drm_local_map_t *cce_ring;
 131         drm_local_map_t *ring_rptr;
 132         drm_local_map_t *agp_textures;
 133         struct drm_ati_pcigart_info gart_info;
 134 } drm_r128_private_t;
 135
 136 typedef struct drm_r128_buf_priv {
 137         u32 age;
 138         int prim;
 139         int discard;
 140         int dispatched;
 141         drm_r128_freelist_t *list_entry;
 142 } drm_r128_buf_priv_t;
 143
 144 extern const struct drm_ioctl_desc r128_ioctls[];
 145 extern int r128_max_ioctl;
 146
 147                                 /* r128_cce.c */
 148 extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
 149 extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
 150 extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
 151 extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
 152 extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
 153 extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
 154 extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
 155 extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
 156
 157 extern int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv);
 158 extern int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv);
 159 extern int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv);
 160
 161 extern void r128_freelist_reset(struct drm_device *dev);
 162
 163 extern int r128_wait_ring(drm_r128_private_t *dev_priv, int n);
 164
 165 extern int r128_do_cce_idle(drm_r128_private_t *dev_priv);
 166 extern int r128_do_cleanup_cce(struct drm_device *dev);
 167
 168 extern int r128_enable_vblank(struct drm_device *dev, unsigned int pipe);
 169 extern void r128_disable_vblank(struct drm_device *dev, unsigned int pipe);
 170 extern u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
 171 extern irqreturn_t r128_driver_irq_handler(int irq, void *arg);
 172 extern void r128_driver_irq_preinstall(struct drm_device *dev);
 173 extern int r128_driver_irq_postinstall(struct drm_device *dev);
 174 extern void r128_driver_irq_uninstall(struct drm_device *dev);
 175 extern void r128_driver_lastclose(struct drm_device *dev);
 176 extern int r128_driver_load(struct drm_device *dev, unsigned long flags);
 177 extern void r128_driver_preclose(struct drm_device *dev,
 178                                  struct drm_file *file_priv);
 179
 180 extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
 181                               unsigned long arg);
 182
 183 /* Register definitions, register access macros and drmAddMap constants
 184  * for Rage 128 kernel driver.
 185  */
 186
 187 #define R128_AUX_SC_CNTL                0x1660
 188 #       define R128_AUX1_SC_EN                  (1 << 0)
 189 #       define R128_AUX1_SC_MODE_OR             (0 << 1)
 190 #       define R128_AUX1_SC_MODE_NAND           (1 << 1)
 191 #       define R128_AUX2_SC_EN                  (1 << 2)
 192 #       define R128_AUX2_SC_MODE_OR             (0 << 3)
 193 #       define R128_AUX2_SC_MODE_NAND           (1 << 3)
 194 #       define R128_AUX3_SC_EN                  (1 << 4)
 195 #       define R128_AUX3_SC_MODE_OR             (0 << 5)
 196 #       define R128_AUX3_SC_MODE_NAND           (1 << 5)
 197 #define R128_AUX1_SC_LEFT               0x1664
 198 #define R128_AUX1_SC_RIGHT              0x1668
 199 #define R128_AUX1_SC_TOP                0x166c
 200 #define R128_AUX1_SC_BOTTOM             0x1670
 201 #define R128_AUX2_SC_LEFT               0x1674
 202 #define R128_AUX2_SC_RIGHT              0x1678
 203 #define R128_AUX2_SC_TOP                0x167c
 204 #define R128_AUX2_SC_BOTTOM             0x1680
 205 #define R128_AUX3_SC_LEFT               0x1684
 206 #define R128_AUX3_SC_RIGHT              0x1688
 207 #define R128_AUX3_SC_TOP                0x168c
 208 #define R128_AUX3_SC_BOTTOM             0x1690
 209
 210 #define R128_BRUSH_DATA0                0x1480
 211 #define R128_BUS_CNTL                   0x0030
 212 #       define R128_BUS_MASTER_DIS              (1 << 6)
 213
 214 #define R128_CLOCK_CNTL_INDEX           0x0008
 215 #define R128_CLOCK_CNTL_DATA            0x000c
 216 #       define R128_PLL_WR_EN                   (1 << 7)
 217 #define R128_CONSTANT_COLOR_C           0x1d34
 218 #define R128_CRTC_OFFSET                0x0224
 219 #define R128_CRTC_OFFSET_CNTL           0x0228
 220 #       define R128_CRTC_OFFSET_FLIP_CNTL       (1 << 16)
 221
 222 #define R128_DP_GUI_MASTER_CNTL         0x146c
 223 #       define R128_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)
 224 #       define R128_GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)
 225 #       define R128_GMC_BRUSH_SOLID_COLOR       (13   <<  4)
 226 #       define R128_GMC_BRUSH_NONE              (15   <<  4)
 227 #       define R128_GMC_DST_16BPP               (4    <<  8)
 228 #       define R128_GMC_DST_24BPP               (5    <<  8)
 229 #       define R128_GMC_DST_32BPP               (6    <<  8)
 230 #       define R128_GMC_DST_DATATYPE_SHIFT      8
 231 #       define R128_GMC_SRC_DATATYPE_COLOR      (3    << 12)
 232 #       define R128_DP_SRC_SOURCE_MEMORY        (2    << 24)
 233 #       define R128_DP_SRC_SOURCE_HOST_DATA     (3    << 24)
 234 #       define R128_GMC_CLR_CMP_CNTL_DIS        (1    << 28)
 235 #       define R128_GMC_AUX_CLIP_DIS            (1    << 29)
 236 #       define R128_GMC_WR_MSK_DIS              (1    << 30)
 237 #       define R128_ROP3_S                      0x00cc0000
 238 #       define R128_ROP3_P                      0x00f00000
 239 #define R128_DP_WRITE_MASK              0x16cc
 240 #define R128_DST_PITCH_OFFSET_C         0x1c80
 241 #       define R128_DST_TILE                    (1 << 31)
 242
 243 #define R128_GEN_INT_CNTL               0x0040
 244 #       define R128_CRTC_VBLANK_INT_EN          (1 <<  0)
 245 #define R128_GEN_INT_STATUS             0x0044
 246 #       define R128_CRTC_VBLANK_INT             (1 <<  0)
 247 #       define R128_CRTC_VBLANK_INT_AK          (1 <<  0)
 248 #define R128_GEN_RESET_CNTL             0x00f0
 249 #       define R128_SOFT_RESET_GUI              (1 <<  0)
 250
 251 #define R128_GUI_SCRATCH_REG0           0x15e0
 252 #define R128_GUI_SCRATCH_REG1           0x15e4
 253 #define R128_GUI_SCRATCH_REG2           0x15e8
 254 #define R128_GUI_SCRATCH_REG3           0x15ec
 255 #define R128_GUI_SCRATCH_REG4           0x15f0
 256 #define R128_GUI_SCRATCH_REG5           0x15f4
 257
 258 #define R128_GUI_STAT                   0x1740
 259 #       define R128_GUI_FIFOCNT_MASK            0x0fff
 260 #       define R128_GUI_ACTIVE                  (1 << 31)
 261
 262 #define R128_MCLK_CNTL                  0x000f
 263 #       define R128_FORCE_GCP                   (1 << 16)
 264 #       define R128_FORCE_PIPE3D_CP             (1 << 17)
 265 #       define R128_FORCE_RCP                   (1 << 18)
 266
 267 #define R128_PC_GUI_CTLSTAT             0x1748
 268 #define R128_PC_NGUI_CTLSTAT            0x0184
 269 #       define R128_PC_FLUSH_GUI                (3 << 0)
 270 #       define R128_PC_RI_GUI                   (1 << 2)
 271 #       define R128_PC_FLUSH_ALL                0x00ff
 272 #       define R128_PC_BUSY                     (1 << 31)
 273
 274 #define R128_PCI_GART_PAGE              0x017c
 275 #define R128_PRIM_TEX_CNTL_C            0x1cb0
 276
 277 #define R128_SCALE_3D_CNTL              0x1a00
 278 #define R128_SEC_TEX_CNTL_C             0x1d00
 279 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
 280 #define R128_SETUP_CNTL                 0x1bc4
 281 #define R128_STEN_REF_MASK_C            0x1d40
 282
 283 #define R128_TEX_CNTL_C                 0x1c9c
 284 #       define R128_TEX_CACHE_FLUSH             (1 << 23)
 285
 286 #define R128_WAIT_UNTIL                 0x1720
 287 #       define R128_EVENT_CRTC_OFFSET           (1 << 0)
 288 #define R128_WINDOW_XY_OFFSET           0x1bcc
 289
 290 /* CCE registers
 291  */
 292 #define R128_PM4_BUFFER_OFFSET          0x0700
 293 #define R128_PM4_BUFFER_CNTL            0x0704
 294 #       define R128_PM4_MASK                    (15 << 28)
 295 #       define R128_PM4_NONPM4                  (0  << 28)
 296 #       define R128_PM4_192PIO                  (1  << 28)
 297 #       define R128_PM4_192BM                   (2  << 28)
 298 #       define R128_PM4_128PIO_64INDBM          (3  << 28)
 299 #       define R128_PM4_128BM_64INDBM           (4  << 28)
 300 #       define R128_PM4_64PIO_128INDBM          (5  << 28)
 301 #       define R128_PM4_64BM_128INDBM           (6  << 28)
 302 #       define R128_PM4_64PIO_64VCBM_64INDBM    (7  << 28)
 303 #       define R128_PM4_64BM_64VCBM_64INDBM     (8  << 28)
 304 #       define R128_PM4_64PIO_64VCPIO_64INDPIO  (15 << 28)
 305 #       define R128_PM4_BUFFER_CNTL_NOUPDATE    (1  << 27)
 306
 307 #define R128_PM4_BUFFER_WM_CNTL         0x0708
 308 #       define R128_WMA_SHIFT                   0
 309 #       define R128_WMB_SHIFT                   8
 310 #       define R128_WMC_SHIFT                   16
 311 #       define R128_WB_WM_SHIFT                 24
 312
 313 #define R128_PM4_BUFFER_DL_RPTR_ADDR    0x070c
 314 #define R128_PM4_BUFFER_DL_RPTR         0x0710
 315 #define R128_PM4_BUFFER_DL_WPTR         0x0714
 316 #       define R128_PM4_BUFFER_DL_DONE          (1 << 31)
 317
 318 #define R128_PM4_VC_FPU_SETUP           0x071c
 319
 320 #define R128_PM4_IW_INDOFF              0x0738
 321 #define R128_PM4_IW_INDSIZE             0x073c
 322
 323 #define R128_PM4_STAT                   0x07b8
 324 #       define R128_PM4_FIFOCNT_MASK            0x0fff
 325 #       define R128_PM4_BUSY                    (1 << 16)
 326 #       define R128_PM4_GUI_ACTIVE              (1 << 31)
 327
 328 #define R128_PM4_MICROCODE_ADDR         0x07d4
 329 #define R128_PM4_MICROCODE_RADDR        0x07d8
 330 #define R128_PM4_MICROCODE_DATAH        0x07dc
 331 #define R128_PM4_MICROCODE_DATAL        0x07e0
 332
 333 #define R128_PM4_BUFFER_ADDR            0x07f0
 334 #define R128_PM4_MICRO_CNTL             0x07fc
 335 #       define R128_PM4_MICRO_FREERUN           (1 << 30)
 336
 337 #define R128_PM4_FIFO_DATA_EVEN         0x1000
 338 #define R128_PM4_FIFO_DATA_ODD          0x1004
 339
 340 /* CCE command packets
 341  */
 342 #define R128_CCE_PACKET0                0x00000000
 343 #define R128_CCE_PACKET1                0x40000000
 344 #define R128_CCE_PACKET2                0x80000000
 345 #define R128_CCE_PACKET3                0xC0000000
 346 #       define R128_CNTL_HOSTDATA_BLT           0x00009400
 347 #       define R128_CNTL_PAINT_MULTI            0x00009A00
 348 #       define R128_CNTL_BITBLT_MULTI           0x00009B00
 349 #       define R128_3D_RNDR_GEN_INDX_PRIM       0x00002300
 350
 351 #define R128_CCE_PACKET_MASK            0xC0000000
 352 #define R128_CCE_PACKET_COUNT_MASK      0x3fff0000
 353 #define R128_CCE_PACKET0_REG_MASK       0x000007ff
 354 #define R128_CCE_PACKET1_REG0_MASK      0x000007ff
 355 #define R128_CCE_PACKET1_REG1_MASK      0x003ff800
 356
 357 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE         0x00000000
 358 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT        0x00000001
 359 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE         0x00000002
 360 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE    0x00000003
 361 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST     0x00000004
 362 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN      0x00000005
 363 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP    0x00000006
 364 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2    0x00000007
 365 #define R128_CCE_VC_CNTL_PRIM_WALK_IND          0x00000010
 366 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST         0x00000020
 367 #define R128_CCE_VC_CNTL_PRIM_WALK_RING         0x00000030
 368 #define R128_CCE_VC_CNTL_NUM_SHIFT              16
 369
 370 #define R128_DATATYPE_VQ                0
 371 #define R128_DATATYPE_CI4               1
 372 #define R128_DATATYPE_CI8               2
 373 #define R128_DATATYPE_ARGB1555          3
 374 #define R128_DATATYPE_RGB565            4
 375 #define R128_DATATYPE_RGB888            5
 376 #define R128_DATATYPE_ARGB8888          6
 377 #define R128_DATATYPE_RGB332            7
 378 #define R128_DATATYPE_Y8                8
 379 #define R128_DATATYPE_RGB8              9
 380 #define R128_DATATYPE_CI16              10
 381 #define R128_DATATYPE_YVYU422           11
 382 #define R128_DATATYPE_VYUY422           12
 383 #define R128_DATATYPE_AYUV444           14
 384 #define R128_DATATYPE_ARGB4444          15
 385
 386 /* Constants */
 387 #define R128_AGP_OFFSET                 0x02000000
 388
 389 #define R128_WATERMARK_L                16
 390 #define R128_WATERMARK_M                8
 391 #define R128_WATERMARK_N                8
 392 #define R128_WATERMARK_K                128
 393
 394 #define R128_MAX_USEC_TIMEOUT           100000  /* 100 ms */
 395
 396 #define R128_LAST_FRAME_REG             R128_GUI_SCRATCH_REG0
 397 #define R128_LAST_DISPATCH_REG          R128_GUI_SCRATCH_REG1
 398 #define R128_MAX_VB_AGE                 0x7fffffff
 399 #define R128_MAX_VB_VERTS               (0xffff)
 400
 401 #define R128_RING_HIGH_MARK             128
 402
 403 #define R128_PERFORMANCE_BOXES          0
 404
 405 #define R128_PCIGART_TABLE_SIZE         32768
 406
 407 #define R128_READ(reg)          readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
 408 #define R128_WRITE(reg, val)    writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
 409 #define R128_READ8(reg)         readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
 410 #define R128_WRITE8(reg, val)   writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
 411
 412 #define R128_WRITE_PLL(addr, val)                                       \
 413 do {                                                                    \
 414         R128_WRITE8(R128_CLOCK_CNTL_INDEX,                              \
 415                     ((addr) & 0x1f) | R128_PLL_WR_EN);                  \
 416         R128_WRITE(R128_CLOCK_CNTL_DATA, (val));                        \
 417 } while (0)
 418
 419 #define CCE_PACKET0(reg, n)             (R128_CCE_PACKET0 |             \
 420                                          ((n) << 16) | ((reg) >> 2))
 421 #define CCE_PACKET1(reg0, reg1)         (R128_CCE_PACKET1 |             \
 422                                          (((reg1) >> 2) << 11) | ((reg0) >> 2))
 423 #define CCE_PACKET2()                   (R128_CCE_PACKET2)
 424 #define CCE_PACKET3(pkt, n)             (R128_CCE_PACKET3 |             \
 425                                          (pkt) | ((n) << 16))
 426
 427 static __inline__ void r128_update_ring_snapshot(drm_r128_private_t *dev_priv)
 428 {
 429         drm_r128_ring_buffer_t *ring = &dev_priv->ring;
 430         ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
 431         if (ring->space <= 0)
 432                 ring->space += ring->size;
 433 }
 434
 435 /* ================================================================
 436  * Misc helper macros
 437  */
 438
 439 #define DEV_INIT_TEST_WITH_RETURN(_dev_priv)                            \
 440 do {                                                                    \
 441         if (!_dev_priv) {                                               \
 442                 DRM_ERROR("called with no initialization\n");           \
 443                 return -EINVAL;                                         \
 444         }                                                               \
 445 } while (0)
 446
 447 #define RING_SPACE_TEST_WITH_RETURN(dev_priv)                           \
 448 do {                                                                    \
 449         drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;          \
 450         if (ring->space < ring->high_mark) {                            \
 451                 for (i = 0 ; i < dev_priv->usec_timeout ; i++) {        \
 452                         r128_update_ring_snapshot(dev_priv);            \
 453                         if (ring->space >= ring->high_mark)             \
 454                                 goto __ring_space_done;                 \
 455                         udelay(1);                                      \
 456                 }                                                       \
 457                 DRM_ERROR("ring space check failed!\n");                \
 458                 return -EBUSY;                                          \
 459         }                                                               \
 460  __ring_space_done:                                                     \
 461         ;                                                               \
 462 } while (0)
 463
 464 #define VB_AGE_TEST_WITH_RETURN(dev_priv)                               \
 465 do {                                                                    \
 466         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;            \
 467         if (sarea_priv->last_dispatch >= R128_MAX_VB_AGE) {             \
 468                 int __ret = r128_do_cce_idle(dev_priv);                 \
 469                 if (__ret)                                              \
 470                         return __ret;                                   \
 471                 sarea_priv->last_dispatch = 0;                          \
 472                 r128_freelist_reset(dev);                               \
 473         }                                                               \
 474 } while (0)
 475
 476 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do {                             \
 477         OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0));                      \
 478         OUT_RING(R128_EVENT_CRTC_OFFSET);                               \
 479 } while (0)
 480
 481 /* ================================================================
 482  * Ring control
 483  */
 484
 485 #define R128_VERBOSE    0
 486
 487 #define RING_LOCALS                                                     \
 488         int write, _nr; unsigned int tail_mask; volatile u32 *ring;
 489
 490 #define BEGIN_RING(n) do {                                              \
 491         if (R128_VERBOSE)                                               \
 492                 DRM_INFO("BEGIN_RING(%d)\n", (n));                      \
 493         if (dev_priv->ring.space <= (n) * sizeof(u32)) {                \
 494                 COMMIT_RING();                                          \
 495                 r128_wait_ring(dev_priv, (n) * sizeof(u32));            \
 496         }                                                               \
 497         _nr = n; dev_priv->ring.space -= (n) * sizeof(u32);             \
 498         ring = dev_priv->ring.start;                                    \
 499         write = dev_priv->ring.tail;                                    \
 500         tail_mask = dev_priv->ring.tail_mask;                           \
 501 } while (0)
 502
 503 /* You can set this to zero if you want.  If the card locks up, you'll
 504  * need to keep this set.  It works around a bug in early revs of the
 505  * Rage 128 chipset, where the CCE would read 32 dwords past the end of
 506  * the ring buffer before wrapping around.
 507  */
 508 #define R128_BROKEN_CCE 1
 509
 510 #define ADVANCE_RING() do {                                             \
 511         if (R128_VERBOSE)                                               \
 512                 DRM_INFO("ADVANCE_RING() wr=0x%06x tail=0x%06x\n",      \
 513                          write, dev_priv->ring.tail);                   \
 514         if (R128_BROKEN_CCE && write < 32)                              \
 515                 memcpy(dev_priv->ring.end,                              \
 516                        dev_priv->ring.start,                            \
 517                        write * sizeof(u32));                            \
 518         if (((dev_priv->ring.tail + _nr) & tail_mask) != write)         \
 519                 DRM_ERROR(                                              \
 520                         "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",        \
 521                         ((dev_priv->ring.tail + _nr) & tail_mask),      \
 522                         write, __LINE__);                               \
 523         else                                                            \
 524                 dev_priv->ring.tail = write;                            \
 525 } while (0)
 526
 527 #define COMMIT_RING() do {                                              \
 528         if (R128_VERBOSE)                                               \
 529                 DRM_INFO("COMMIT_RING() tail=0x%06x\n",                 \
 530                          dev_priv->ring.tail);                          \
 531         mb();                                           \
 532         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail);       \
 533         R128_READ(R128_PM4_BUFFER_DL_WPTR);                             \
 534 } while (0)
 535
 536 #define OUT_RING(x) do {                                                \
 537         if (R128_VERBOSE)                                               \
 538                 DRM_INFO("   OUT_RING( 0x%08x ) at 0x%x\n",             \
 539                          (unsigned int)(x), write);                     \
 540         ring[write++] = cpu_to_le32(x);                                 \
 541         write &= tail_mask;                                             \
 542 } while (0)
 543
 544 #endif                          /* __R128_DRV_H__ */