drivers/gpu/drm/r128/r128_cce.c

   1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
   2  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
   3  */
   4 /*
   5  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   6  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include <linux/firmware.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36
  37 #include <drm/drmP.h>
  38 #include <drm/r128_drm.h>
  39 #include "r128_drv.h"
  40
  41 #define R128_FIFO_DEBUG         0
  42
  43 #define FIRMWARE_NAME           "/*(DEBLOBBED)*/"
  44
  45 /*(DEBLOBBED)*/
  46
  47 static int R128_READ_PLL(struct drm_device *dev, int addr)
  48 {
  49         drm_r128_private_t *dev_priv = dev->dev_private;
  50
  51         R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
  52         return R128_READ(R128_CLOCK_CNTL_DATA);
  53 }
  54
  55 #if R128_FIFO_DEBUG
  56 static void r128_status(drm_r128_private_t *dev_priv)
  57 {
  58         printk("GUI_STAT           = 0x%08x\n",
  59                (unsigned int)R128_READ(R128_GUI_STAT));
  60         printk("PM4_STAT           = 0x%08x\n",
  61                (unsigned int)R128_READ(R128_PM4_STAT));
  62         printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
  63                (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
  64         printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
  65                (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
  66         printk("PM4_MICRO_CNTL     = 0x%08x\n",
  67                (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
  68         printk("PM4_BUFFER_CNTL    = 0x%08x\n",
  69                (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
  70 }
  71 #endif
  72
  73 /* ================================================================
  74  * Engine, FIFO control
  75  */
  76
  77 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv)
  78 {
  79         u32 tmp;
  80         int i;
  81
  82         tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
  83         R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
  84
  85         for (i = 0; i < dev_priv->usec_timeout; i++) {
  86                 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
  87                         return 0;
  88                 DRM_UDELAY(1);
  89         }
  90
  91 #if R128_FIFO_DEBUG
  92         DRM_ERROR("failed!\n");
  93 #endif
  94         return -EBUSY;
  95 }
  96
  97 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries)
  98 {
  99         int i;
 100
 101         for (i = 0; i < dev_priv->usec_timeout; i++) {
 102                 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
 103                 if (slots >= entries)
 104                         return 0;
 105                 DRM_UDELAY(1);
 106         }
 107
 108 #if R128_FIFO_DEBUG
 109         DRM_ERROR("failed!\n");
 110 #endif
 111         return -EBUSY;
 112 }
 113
 114 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv)
 115 {
 116         int i, ret;
 117
 118         ret = r128_do_wait_for_fifo(dev_priv, 64);
 119         if (ret)
 120                 return ret;
 121
 122         for (i = 0; i < dev_priv->usec_timeout; i++) {
 123                 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
 124                         r128_do_pixcache_flush(dev_priv);
 125                         return 0;
 126                 }
 127                 DRM_UDELAY(1);
 128         }
 129
 130 #if R128_FIFO_DEBUG
 131         DRM_ERROR("failed!\n");
 132 #endif
 133         return -EBUSY;
 134 }
 135
 136 /* ================================================================
 137  * CCE control, initialization
 138  */
 139
 140 /* Load the microcode for the CCE */
 141 static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
 142 {
 143         struct platform_device *pdev;
 144         const struct firmware *fw;
 145         const __be32 *fw_data;
 146         int rc, i;
 147
 148         DRM_DEBUG("\n");
 149
 150         pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
 151         if (IS_ERR(pdev)) {
 152                 pr_err("r128_cce: Failed to register firmware\n");
 153                 return PTR_ERR(pdev);
 154         }
 155         rc = reject_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
 156         platform_device_unregister(pdev);
 157         if (rc) {
 158                 pr_err("r128_cce: Failed to load firmware \"%s\"\n",
 159                        FIRMWARE_NAME);
 160                 return rc;
 161         }
 162
 163         if (fw->size != 256 * 8) {
 164                 pr_err("r128_cce: Bogus length %zu in firmware \"%s\"\n",
 165                        fw->size, FIRMWARE_NAME);
 166                 rc = -EINVAL;
 167                 goto out_release;
 168         }
 169
 170         r128_do_wait_for_idle(dev_priv);
 171
 172         fw_data = (const __be32 *)fw->data;
 173         R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
 174         for (i = 0; i < 256; i++) {
 175                 R128_WRITE(R128_PM4_MICROCODE_DATAH,
 176                            be32_to_cpup(&fw_data[i * 2]));
 177                 R128_WRITE(R128_PM4_MICROCODE_DATAL,
 178                            be32_to_cpup(&fw_data[i * 2 + 1]));
 179         }
 180
 181 out_release:
 182         release_firmware(fw);
 183         return rc;
 184 }
 185
 186 /* Flush any pending commands to the CCE.  This should only be used just
 187  * prior to a wait for idle, as it informs the engine that the command
 188  * stream is ending.
 189  */
 190 static void r128_do_cce_flush(drm_r128_private_t *dev_priv)
 191 {
 192         u32 tmp;
 193
 194         tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
 195         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
 196 }
 197
 198 /* Wait for the CCE to go idle.
 199  */
 200 int r128_do_cce_idle(drm_r128_private_t *dev_priv)
 201 {
 202         int i;
 203
 204         for (i = 0; i < dev_priv->usec_timeout; i++) {
 205                 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
 206                         int pm4stat = R128_READ(R128_PM4_STAT);
 207                         if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
 208                              dev_priv->cce_fifo_size) &&
 209                             !(pm4stat & (R128_PM4_BUSY |
 210                                          R128_PM4_GUI_ACTIVE))) {
 211                                 return r128_do_pixcache_flush(dev_priv);
 212                         }
 213                 }
 214                 DRM_UDELAY(1);
 215         }
 216
 217 #if R128_FIFO_DEBUG
 218         DRM_ERROR("failed!\n");
 219         r128_status(dev_priv);
 220 #endif
 221         return -EBUSY;
 222 }
 223
 224 /* Start the Concurrent Command Engine.
 225  */
 226 static void r128_do_cce_start(drm_r128_private_t *dev_priv)
 227 {
 228         r128_do_wait_for_idle(dev_priv);
 229
 230         R128_WRITE(R128_PM4_BUFFER_CNTL,
 231                    dev_priv->cce_mode | dev_priv->ring.size_l2qw
 232                    | R128_PM4_BUFFER_CNTL_NOUPDATE);
 233         R128_READ(R128_PM4_BUFFER_ADDR);        /* as per the sample code */
 234         R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
 235
 236         dev_priv->cce_running = 1;
 237 }
 238
 239 /* Reset the Concurrent Command Engine.  This will not flush any pending
 240  * commands, so you must wait for the CCE command stream to complete
 241  * before calling this routine.
 242  */
 243 static void r128_do_cce_reset(drm_r128_private_t *dev_priv)
 244 {
 245         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
 246         R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
 247         dev_priv->ring.tail = 0;
 248 }
 249
 250 /* Stop the Concurrent Command Engine.  This will not flush any pending
 251  * commands, so you must flush the command stream and wait for the CCE
 252  * to go idle before calling this routine.
 253  */
 254 static void r128_do_cce_stop(drm_r128_private_t *dev_priv)
 255 {
 256         R128_WRITE(R128_PM4_MICRO_CNTL, 0);
 257         R128_WRITE(R128_PM4_BUFFER_CNTL,
 258                    R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
 259
 260         dev_priv->cce_running = 0;
 261 }
 262
 263 /* Reset the engine.  This will stop the CCE if it is running.
 264  */
 265 static int r128_do_engine_reset(struct drm_device *dev)
 266 {
 267         drm_r128_private_t *dev_priv = dev->dev_private;
 268         u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
 269
 270         r128_do_pixcache_flush(dev_priv);
 271
 272         clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
 273         mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
 274
 275         R128_WRITE_PLL(R128_MCLK_CNTL,
 276                        mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
 277
 278         gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
 279
 280         /* Taken from the sample code - do not change */
 281         R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
 282         R128_READ(R128_GEN_RESET_CNTL);
 283         R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
 284         R128_READ(R128_GEN_RESET_CNTL);
 285
 286         R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
 287         R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
 288         R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
 289
 290         /* Reset the CCE ring */
 291         r128_do_cce_reset(dev_priv);
 292
 293         /* The CCE is no longer running after an engine reset */
 294         dev_priv->cce_running = 0;
 295
 296         /* Reset any pending vertex, indirect buffers */
 297         r128_freelist_reset(dev);
 298
 299         return 0;
 300 }
 301
 302 static void r128_cce_init_ring_buffer(struct drm_device *dev,
 303                                       drm_r128_private_t *dev_priv)
 304 {
 305         u32 ring_start;
 306         u32 tmp;
 307
 308         DRM_DEBUG("\n");
 309
 310         /* The manual (p. 2) says this address is in "VM space".  This
 311          * means it's an offset from the start of AGP space.
 312          */
 313 #if IS_ENABLED(CONFIG_AGP)
 314         if (!dev_priv->is_pci)
 315                 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
 316         else
 317 #endif
 318                 ring_start = dev_priv->cce_ring->offset -
 319                     (unsigned long)dev->sg->virtual;
 320
 321         R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
 322
 323         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
 324         R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
 325
 326         /* Set watermark control */
 327         R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
 328                    ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
 329                    | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
 330                    | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
 331                    | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
 332
 333         /* Force read.  Why?  Because it's in the examples... */
 334         R128_READ(R128_PM4_BUFFER_ADDR);
 335
 336         /* Turn on bus mastering */
 337         tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
 338         R128_WRITE(R128_BUS_CNTL, tmp);
 339 }
 340
 341 static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init)
 342 {
 343         drm_r128_private_t *dev_priv;
 344         int rc;
 345
 346         DRM_DEBUG("\n");
 347
 348         if (dev->dev_private) {
 349                 DRM_DEBUG("called when already initialized\n");
 350                 return -EINVAL;
 351         }
 352
 353         dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
 354         if (dev_priv == NULL)
 355                 return -ENOMEM;
 356
 357         dev_priv->is_pci = init->is_pci;
 358
 359         if (dev_priv->is_pci && !dev->sg) {
 360                 DRM_ERROR("PCI GART memory not allocated!\n");
 361                 dev->dev_private = (void *)dev_priv;
 362                 r128_do_cleanup_cce(dev);
 363                 return -EINVAL;
 364         }
 365
 366         dev_priv->usec_timeout = init->usec_timeout;
 367         if (dev_priv->usec_timeout < 1 ||
 368             dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
 369                 DRM_DEBUG("TIMEOUT problem!\n");
 370                 dev->dev_private = (void *)dev_priv;
 371                 r128_do_cleanup_cce(dev);
 372                 return -EINVAL;
 373         }
 374
 375         dev_priv->cce_mode = init->cce_mode;
 376
 377         /* GH: Simple idle check.
 378          */
 379         atomic_set(&dev_priv->idle_count, 0);
 380
 381         /* We don't support anything other than bus-mastering ring mode,
 382          * but the ring can be in either AGP or PCI space for the ring
 383          * read pointer.
 384          */
 385         if ((init->cce_mode != R128_PM4_192BM) &&
 386             (init->cce_mode != R128_PM4_128BM_64INDBM) &&
 387             (init->cce_mode != R128_PM4_64BM_128INDBM) &&
 388             (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
 389                 DRM_DEBUG("Bad cce_mode!\n");
 390                 dev->dev_private = (void *)dev_priv;
 391                 r128_do_cleanup_cce(dev);
 392                 return -EINVAL;
 393         }
 394
 395         switch (init->cce_mode) {
 396         case R128_PM4_NONPM4:
 397                 dev_priv->cce_fifo_size = 0;
 398                 break;
 399         case R128_PM4_192PIO:
 400         case R128_PM4_192BM:
 401                 dev_priv->cce_fifo_size = 192;
 402                 break;
 403         case R128_PM4_128PIO_64INDBM:
 404         case R128_PM4_128BM_64INDBM:
 405                 dev_priv->cce_fifo_size = 128;
 406                 break;
 407         case R128_PM4_64PIO_128INDBM:
 408         case R128_PM4_64BM_128INDBM:
 409         case R128_PM4_64PIO_64VCBM_64INDBM:
 410         case R128_PM4_64BM_64VCBM_64INDBM:
 411         case R128_PM4_64PIO_64VCPIO_64INDPIO:
 412                 dev_priv->cce_fifo_size = 64;
 413                 break;
 414         }
 415
 416         switch (init->fb_bpp) {
 417         case 16:
 418                 dev_priv->color_fmt = R128_DATATYPE_RGB565;
 419                 break;
 420         case 32:
 421         default:
 422                 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
 423                 break;
 424         }
 425         dev_priv->front_offset = init->front_offset;
 426         dev_priv->front_pitch = init->front_pitch;
 427         dev_priv->back_offset = init->back_offset;
 428         dev_priv->back_pitch = init->back_pitch;
 429
 430         switch (init->depth_bpp) {
 431         case 16:
 432                 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
 433                 break;
 434         case 24:
 435         case 32:
 436         default:
 437                 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
 438                 break;
 439         }
 440         dev_priv->depth_offset = init->depth_offset;
 441         dev_priv->depth_pitch = init->depth_pitch;
 442         dev_priv->span_offset = init->span_offset;
 443
 444         dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
 445                                           (dev_priv->front_offset >> 5));
 446         dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
 447                                          (dev_priv->back_offset >> 5));
 448         dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
 449                                           (dev_priv->depth_offset >> 5) |
 450                                           R128_DST_TILE);
 451         dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
 452                                          (dev_priv->span_offset >> 5));
 453
 454         dev_priv->sarea = drm_legacy_getsarea(dev);
 455         if (!dev_priv->sarea) {
 456                 DRM_ERROR("could not find sarea!\n");
 457                 dev->dev_private = (void *)dev_priv;
 458                 r128_do_cleanup_cce(dev);
 459                 return -EINVAL;
 460         }
 461
 462         dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
 463         if (!dev_priv->mmio) {
 464                 DRM_ERROR("could not find mmio region!\n");
 465                 dev->dev_private = (void *)dev_priv;
 466                 r128_do_cleanup_cce(dev);
 467                 return -EINVAL;
 468         }
 469         dev_priv->cce_ring = drm_legacy_findmap(dev, init->ring_offset);
 470         if (!dev_priv->cce_ring) {
 471                 DRM_ERROR("could not find cce ring region!\n");
 472                 dev->dev_private = (void *)dev_priv;
 473                 r128_do_cleanup_cce(dev);
 474                 return -EINVAL;
 475         }
 476         dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
 477         if (!dev_priv->ring_rptr) {
 478                 DRM_ERROR("could not find ring read pointer!\n");
 479                 dev->dev_private = (void *)dev_priv;
 480                 r128_do_cleanup_cce(dev);
 481                 return -EINVAL;
 482         }
 483         dev->agp_buffer_token = init->buffers_offset;
 484         dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
 485         if (!dev->agp_buffer_map) {
 486                 DRM_ERROR("could not find dma buffer region!\n");
 487                 dev->dev_private = (void *)dev_priv;
 488                 r128_do_cleanup_cce(dev);
 489                 return -EINVAL;
 490         }
 491
 492         if (!dev_priv->is_pci) {
 493                 dev_priv->agp_textures =
 494                     drm_legacy_findmap(dev, init->agp_textures_offset);
 495                 if (!dev_priv->agp_textures) {
 496                         DRM_ERROR("could not find agp texture region!\n");
 497                         dev->dev_private = (void *)dev_priv;
 498                         r128_do_cleanup_cce(dev);
 499                         return -EINVAL;
 500                 }
 501         }
 502
 503         dev_priv->sarea_priv =
 504             (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 505                                   init->sarea_priv_offset);
 506
 507 #if IS_ENABLED(CONFIG_AGP)
 508         if (!dev_priv->is_pci) {
 509                 drm_legacy_ioremap_wc(dev_priv->cce_ring, dev);
 510                 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
 511                 drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
 512                 if (!dev_priv->cce_ring->handle ||
 513                     !dev_priv->ring_rptr->handle ||
 514                     !dev->agp_buffer_map->handle) {
 515                         DRM_ERROR("Could not ioremap agp regions!\n");
 516                         dev->dev_private = (void *)dev_priv;
 517                         r128_do_cleanup_cce(dev);
 518                         return -ENOMEM;
 519                 }
 520         } else
 521 #endif
 522         {
 523                 dev_priv->cce_ring->handle =
 524                         (void *)(unsigned long)dev_priv->cce_ring->offset;
 525                 dev_priv->ring_rptr->handle =
 526                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
 527                 dev->agp_buffer_map->handle =
 528                         (void *)(unsigned long)dev->agp_buffer_map->offset;
 529         }
 530
 531 #if IS_ENABLED(CONFIG_AGP)
 532         if (!dev_priv->is_pci)
 533                 dev_priv->cce_buffers_offset = dev->agp->base;
 534         else
 535 #endif
 536                 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
 537
 538         dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
 539         dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
 540                               + init->ring_size / sizeof(u32));
 541         dev_priv->ring.size = init->ring_size;
 542         dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
 543
 544         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
 545
 546         dev_priv->ring.high_mark = 128;
 547
 548         dev_priv->sarea_priv->last_frame = 0;
 549         R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 550
 551         dev_priv->sarea_priv->last_dispatch = 0;
 552         R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
 553
 554 #if IS_ENABLED(CONFIG_AGP)
 555         if (dev_priv->is_pci) {
 556 #endif
 557                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
 558                 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
 559                 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
 560                 dev_priv->gart_info.addr = NULL;
 561                 dev_priv->gart_info.bus_addr = 0;
 562                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
 563                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
 564                         DRM_ERROR("failed to init PCI GART!\n");
 565                         dev->dev_private = (void *)dev_priv;
 566                         r128_do_cleanup_cce(dev);
 567                         return -ENOMEM;
 568                 }
 569                 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
 570 #if IS_ENABLED(CONFIG_AGP)
 571         }
 572 #endif
 573
 574         r128_cce_init_ring_buffer(dev, dev_priv);
 575         rc = r128_cce_load_microcode(dev_priv);
 576
 577         dev->dev_private = (void *)dev_priv;
 578
 579         r128_do_engine_reset(dev);
 580
 581         if (rc) {
 582                 DRM_ERROR("Failed to load firmware!\n");
 583                 r128_do_cleanup_cce(dev);
 584         }
 585
 586         return rc;
 587 }
 588
 589 int r128_do_cleanup_cce(struct drm_device *dev)
 590 {
 591
 592         /* Make sure interrupts are disabled here because the uninstall ioctl
 593          * may not have been called from userspace and after dev_private
 594          * is freed, it's too late.
 595          */
 596         if (dev->irq_enabled)
 597                 drm_irq_uninstall(dev);
 598
 599         if (dev->dev_private) {
 600                 drm_r128_private_t *dev_priv = dev->dev_private;
 601
 602 #if IS_ENABLED(CONFIG_AGP)
 603                 if (!dev_priv->is_pci) {
 604                         if (dev_priv->cce_ring != NULL)
 605                                 drm_legacy_ioremapfree(dev_priv->cce_ring, dev);
 606                         if (dev_priv->ring_rptr != NULL)
 607                                 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
 608                         if (dev->agp_buffer_map != NULL) {
 609                                 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
 610                                 dev->agp_buffer_map = NULL;
 611                         }
 612                 } else
 613 #endif
 614                 {
 615                         if (dev_priv->gart_info.bus_addr)
 616                                 if (!drm_ati_pcigart_cleanup(dev,
 617                                                         &dev_priv->gart_info))
 618                                         DRM_ERROR
 619                                             ("failed to cleanup PCI GART!\n");
 620                 }
 621
 622                 kfree(dev->dev_private);
 623                 dev->dev_private = NULL;
 624         }
 625
 626         return 0;
 627 }
 628
 629 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
 630 {
 631         drm_r128_init_t *init = data;
 632
 633         DRM_DEBUG("\n");
 634
 635         LOCK_TEST_WITH_RETURN(dev, file_priv);
 636
 637         switch (init->func) {
 638         case R128_INIT_CCE:
 639                 return r128_do_init_cce(dev, init);
 640         case R128_CLEANUP_CCE:
 641                 return r128_do_cleanup_cce(dev);
 642         }
 643
 644         return -EINVAL;
 645 }
 646
 647 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
 648 {
 649         drm_r128_private_t *dev_priv = dev->dev_private;
 650         DRM_DEBUG("\n");
 651
 652         LOCK_TEST_WITH_RETURN(dev, file_priv);
 653
 654         DEV_INIT_TEST_WITH_RETURN(dev_priv);
 655
 656         if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
 657                 DRM_DEBUG("while CCE running\n");
 658                 return 0;
 659         }
 660
 661         r128_do_cce_start(dev_priv);
 662
 663         return 0;
 664 }
 665
 666 /* Stop the CCE.  The engine must have been idled before calling this
 667  * routine.
 668  */
 669 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
 670 {
 671         drm_r128_private_t *dev_priv = dev->dev_private;
 672         drm_r128_cce_stop_t *stop = data;
 673         int ret;
 674         DRM_DEBUG("\n");
 675
 676         LOCK_TEST_WITH_RETURN(dev, file_priv);
 677
 678         DEV_INIT_TEST_WITH_RETURN(dev_priv);
 679
 680         /* Flush any pending CCE commands.  This ensures any outstanding
 681          * commands are exectuted by the engine before we turn it off.
 682          */
 683         if (stop->flush)
 684                 r128_do_cce_flush(dev_priv);
 685
 686         /* If we fail to make the engine go idle, we return an error
 687          * code so that the DRM ioctl wrapper can try again.
 688          */
 689         if (stop->idle) {
 690                 ret = r128_do_cce_idle(dev_priv);
 691                 if (ret)
 692                         return ret;
 693         }
 694
 695         /* Finally, we can turn off the CCE.  If the engine isn't idle,
 696          * we will get some dropped triangles as they won't be fully
 697          * rendered before the CCE is shut down.
 698          */
 699         r128_do_cce_stop(dev_priv);
 700
 701         /* Reset the engine */
 702         r128_do_engine_reset(dev);
 703
 704         return 0;
 705 }
 706
 707 /* Just reset the CCE ring.  Called as part of an X Server engine reset.
 708  */
 709 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
 710 {
 711         drm_r128_private_t *dev_priv = dev->dev_private;
 712         DRM_DEBUG("\n");
 713
 714         LOCK_TEST_WITH_RETURN(dev, file_priv);
 715
 716         DEV_INIT_TEST_WITH_RETURN(dev_priv);
 717
 718         r128_do_cce_reset(dev_priv);
 719
 720         /* The CCE is no longer running after an engine reset */
 721         dev_priv->cce_running = 0;
 722
 723         return 0;
 724 }
 725
 726 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
 727 {
 728         drm_r128_private_t *dev_priv = dev->dev_private;
 729         DRM_DEBUG("\n");
 730
 731         LOCK_TEST_WITH_RETURN(dev, file_priv);
 732
 733         DEV_INIT_TEST_WITH_RETURN(dev_priv);
 734
 735         if (dev_priv->cce_running)
 736                 r128_do_cce_flush(dev_priv);
 737
 738         return r128_do_cce_idle(dev_priv);
 739 }
 740
 741 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
 742 {
 743         DRM_DEBUG("\n");
 744
 745         LOCK_TEST_WITH_RETURN(dev, file_priv);
 746
 747         DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
 748
 749         return r128_do_engine_reset(dev);
 750 }
 751
 752 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
 753 {
 754         return -EINVAL;
 755 }
 756
 757 /* ================================================================
 758  * Freelist management
 759  */
 760 #define R128_BUFFER_USED        0xffffffff
 761 #define R128_BUFFER_FREE        0
 762
 763 #if 0
 764 static int r128_freelist_init(struct drm_device *dev)
 765 {
 766         struct drm_device_dma *dma = dev->dma;
 767         drm_r128_private_t *dev_priv = dev->dev_private;
 768         struct drm_buf *buf;
 769         drm_r128_buf_priv_t *buf_priv;
 770         drm_r128_freelist_t *entry;
 771         int i;
 772
 773         dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
 774         if (dev_priv->head == NULL)
 775                 return -ENOMEM;
 776
 777         dev_priv->head->age = R128_BUFFER_USED;
 778
 779         for (i = 0; i < dma->buf_count; i++) {
 780                 buf = dma->buflist[i];
 781                 buf_priv = buf->dev_private;
 782
 783                 entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
 784                 if (!entry)
 785                         return -ENOMEM;
 786
 787                 entry->age = R128_BUFFER_FREE;
 788                 entry->buf = buf;
 789                 entry->prev = dev_priv->head;
 790                 entry->next = dev_priv->head->next;
 791                 if (!entry->next)
 792                         dev_priv->tail = entry;
 793
 794                 buf_priv->discard = 0;
 795                 buf_priv->dispatched = 0;
 796                 buf_priv->list_entry = entry;
 797
 798                 dev_priv->head->next = entry;
 799
 800                 if (dev_priv->head->next)
 801                         dev_priv->head->next->prev = entry;
 802         }
 803
 804         return 0;
 805
 806 }
 807 #endif
 808
 809 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
 810 {
 811         struct drm_device_dma *dma = dev->dma;
 812         drm_r128_private_t *dev_priv = dev->dev_private;
 813         drm_r128_buf_priv_t *buf_priv;
 814         struct drm_buf *buf;
 815         int i, t;
 816
 817         /* FIXME: Optimize -- use freelist code */
 818
 819         for (i = 0; i < dma->buf_count; i++) {
 820                 buf = dma->buflist[i];
 821                 buf_priv = buf->dev_private;
 822                 if (!buf->file_priv)
 823                         return buf;
 824         }
 825
 826         for (t = 0; t < dev_priv->usec_timeout; t++) {
 827                 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
 828
 829                 for (i = 0; i < dma->buf_count; i++) {
 830                         buf = dma->buflist[i];
 831                         buf_priv = buf->dev_private;
 832                         if (buf->pending && buf_priv->age <= done_age) {
 833                                 /* The buffer has been processed, so it
 834                                  * can now be used.
 835                                  */
 836                                 buf->pending = 0;
 837                                 return buf;
 838                         }
 839                 }
 840                 DRM_UDELAY(1);
 841         }
 842
 843         DRM_DEBUG("returning NULL!\n");
 844         return NULL;
 845 }
 846
 847 void r128_freelist_reset(struct drm_device *dev)
 848 {
 849         struct drm_device_dma *dma = dev->dma;
 850         int i;
 851
 852         for (i = 0; i < dma->buf_count; i++) {
 853                 struct drm_buf *buf = dma->buflist[i];
 854                 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 855                 buf_priv->age = 0;
 856         }
 857 }
 858
 859 /* ================================================================
 860  * CCE command submission
 861  */
 862
 863 int r128_wait_ring(drm_r128_private_t *dev_priv, int n)
 864 {
 865         drm_r128_ring_buffer_t *ring = &dev_priv->ring;
 866         int i;
 867
 868         for (i = 0; i < dev_priv->usec_timeout; i++) {
 869                 r128_update_ring_snapshot(dev_priv);
 870                 if (ring->space >= n)
 871                         return 0;
 872                 DRM_UDELAY(1);
 873         }
 874
 875         /* FIXME: This is being ignored... */
 876         DRM_ERROR("failed!\n");
 877         return -EBUSY;
 878 }
 879
 880 static int r128_cce_get_buffers(struct drm_device *dev,
 881                                 struct drm_file *file_priv,
 882                                 struct drm_dma *d)
 883 {
 884         int i;
 885         struct drm_buf *buf;
 886
 887         for (i = d->granted_count; i < d->request_count; i++) {
 888                 buf = r128_freelist_get(dev);
 889                 if (!buf)
 890                         return -EAGAIN;
 891
 892                 buf->file_priv = file_priv;
 893
 894                 if (copy_to_user(&d->request_indices[i], &buf->idx,
 895                                      sizeof(buf->idx)))
 896                         return -EFAULT;
 897                 if (copy_to_user(&d->request_sizes[i], &buf->total,
 898                                      sizeof(buf->total)))
 899                         return -EFAULT;
 900
 901                 d->granted_count++;
 902         }
 903         return 0;
 904 }
 905
 906 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
 907 {
 908         struct drm_device_dma *dma = dev->dma;
 909         int ret = 0;
 910         struct drm_dma *d = data;
 911
 912         LOCK_TEST_WITH_RETURN(dev, file_priv);
 913
 914         /* Please don't send us buffers.
 915          */
 916         if (d->send_count != 0) {
 917                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
 918                           DRM_CURRENTPID, d->send_count);
 919                 return -EINVAL;
 920         }
 921
 922         /* We'll send you buffers.
 923          */
 924         if (d->request_count < 0 || d->request_count > dma->buf_count) {
 925                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
 926                           DRM_CURRENTPID, d->request_count, dma->buf_count);
 927                 return -EINVAL;
 928         }
 929
 930         d->granted_count = 0;
 931
 932         if (d->request_count)
 933                 ret = r128_cce_get_buffers(dev, file_priv, d);
 934
 935         return ret;
 936 }