1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4 #include <drm/panfrost_drm.h>
6 #include <linux/atomic.h>
7 #include <linux/bitfield.h>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/io-pgtable.h>
14 #include <linux/iommu.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/shmem_fs.h>
18 #include <linux/sizes.h>
20 #include "panfrost_device.h"
21 #include "panfrost_mmu.h"
22 #include "panfrost_gem.h"
23 #include "panfrost_features.h"
24 #include "panfrost_regs.h"
26 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg)
27 #define mmu_read(dev, reg) readl(dev->iomem + reg)
29 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr)
34 /* Wait for the MMU status to indicate there is no active command, in
35 * case one is pending. */
36 ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr),
37 val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
40 /* The GPU hung, let's trigger a reset */
41 panfrost_device_schedule_reset(pfdev);
42 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n");
48 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd)
52 /* write AS_COMMAND when MMU is ready to accept another command */
53 status = wait_ready(pfdev, as_nr);
55 mmu_write(pfdev, AS_COMMAND(as_nr), cmd);
60 static void lock_region(struct panfrost_device *pfdev, u32 as_nr,
61 u64 region_start, u64 size)
65 u64 region_end = region_start + size;
71 * The locked region is a naturally aligned power of 2 block encoded as
73 * Calculate the desired start/end and look for the highest bit which
74 * differs. The smallest naturally aligned block must include this bit
75 * change, the desired region starts with this bit (and subsequent bits)
76 * zeroed and ends with the bit (and subsequent bits) set to one.
78 region_width = max(fls64(region_start ^ (region_end - 1)),
79 const_ilog2(AS_LOCK_REGION_MIN_SIZE)) - 1;
82 * Mask off the low bits of region_start (which would be ignored by
83 * the hardware anyway)
85 region_start &= GENMASK_ULL(63, region_width);
87 region = region_width | region_start;
89 /* Lock the region that needs to be updated */
90 mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region));
91 mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region));
92 write_cmd(pfdev, as_nr, AS_COMMAND_LOCK);
96 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr,
97 u64 iova, u64 size, u32 op)
102 if (op != AS_COMMAND_UNLOCK)
103 lock_region(pfdev, as_nr, iova, size);
105 /* Run the MMU operation */
106 write_cmd(pfdev, as_nr, op);
108 /* Wait for the flush to complete */
109 return wait_ready(pfdev, as_nr);
112 static int mmu_hw_do_operation(struct panfrost_device *pfdev,
113 struct panfrost_mmu *mmu,
114 u64 iova, u64 size, u32 op)
118 spin_lock(&pfdev->as_lock);
119 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op);
120 spin_unlock(&pfdev->as_lock);
124 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
127 struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
128 u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
129 u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
131 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
133 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab));
134 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab));
136 /* Need to revisit mem attrs.
137 * NC is the default, Mali driver is inner WT.
139 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr));
140 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr));
142 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
145 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
147 mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
149 mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
150 mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
152 mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0);
153 mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0);
155 write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
158 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
162 spin_lock(&pfdev->as_lock);
166 int en = atomic_inc_return(&mmu->as_count);
167 u32 mask = BIT(as) | BIT(16 + as);
170 * AS can be retained by active jobs or a perfcnt context,
171 * hence the '+ 1' here.
173 WARN_ON(en >= (NUM_JOB_SLOTS + 1));
175 list_move(&mmu->list, &pfdev->as_lru_list);
177 if (pfdev->as_faulty_mask & mask) {
178 /* Unhandled pagefault on this AS, the MMU was
179 * disabled. We need to re-enable the MMU after
180 * clearing+unmasking the AS interrupts.
182 mmu_write(pfdev, MMU_INT_CLEAR, mask);
183 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
184 pfdev->as_faulty_mask &= ~mask;
185 panfrost_mmu_enable(pfdev, mmu);
191 /* Check for a free AS */
192 as = ffz(pfdev->as_alloc_mask);
193 if (!(BIT(as) & pfdev->features.as_present)) {
194 struct panfrost_mmu *lru_mmu;
196 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) {
197 if (!atomic_read(&lru_mmu->as_count))
200 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list);
202 list_del_init(&lru_mmu->list);
209 /* Assign the free or reclaimed AS to the FD */
211 set_bit(as, &pfdev->as_alloc_mask);
212 atomic_set(&mmu->as_count, 1);
213 list_add(&mmu->list, &pfdev->as_lru_list);
215 dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
217 panfrost_mmu_enable(pfdev, mmu);
220 spin_unlock(&pfdev->as_lock);
224 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
226 atomic_dec(&mmu->as_count);
227 WARN_ON(atomic_read(&mmu->as_count) < 0);
230 void panfrost_mmu_reset(struct panfrost_device *pfdev)
232 struct panfrost_mmu *mmu, *mmu_tmp;
234 spin_lock(&pfdev->as_lock);
236 pfdev->as_alloc_mask = 0;
237 pfdev->as_faulty_mask = 0;
239 list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) {
241 atomic_set(&mmu->as_count, 0);
242 list_del_init(&mmu->list);
245 spin_unlock(&pfdev->as_lock);
247 mmu_write(pfdev, MMU_INT_CLEAR, ~0);
248 mmu_write(pfdev, MMU_INT_MASK, ~0);
251 static size_t get_pgsize(u64 addr, size_t size)
253 if (addr & (SZ_2M - 1) || size < SZ_2M)
259 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev,
260 struct panfrost_mmu *mmu,
266 pm_runtime_get_noresume(pfdev->dev);
268 /* Flush the PTs only if we're already awake */
269 if (pm_runtime_active(pfdev->dev))
270 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT);
272 pm_runtime_put_sync_autosuspend(pfdev->dev);
275 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu,
276 u64 iova, int prot, struct sg_table *sgt)
279 struct scatterlist *sgl;
280 struct io_pgtable_ops *ops = mmu->pgtbl_ops;
281 u64 start_iova = iova;
283 for_each_sgtable_dma_sg(sgt, sgl, count) {
284 unsigned long paddr = sg_dma_address(sgl);
285 size_t len = sg_dma_len(sgl);
287 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len);
290 size_t pgsize = get_pgsize(iova | paddr, len);
292 ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL);
299 panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova);
304 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping)
306 struct panfrost_gem_object *bo = mapping->obj;
307 struct drm_gem_shmem_object *shmem = &bo->base;
308 struct drm_gem_object *obj = &shmem->base;
309 struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
310 struct sg_table *sgt;
311 int prot = IOMMU_READ | IOMMU_WRITE;
313 if (WARN_ON(mapping->active))
317 prot |= IOMMU_NOEXEC;
319 sgt = drm_gem_shmem_get_pages_sgt(shmem);
320 if (WARN_ON(IS_ERR(sgt)))
323 mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT,
325 mapping->active = true;
330 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping)
332 struct panfrost_gem_object *bo = mapping->obj;
333 struct drm_gem_object *obj = &bo->base.base;
334 struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
335 struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops;
336 u64 iova = mapping->mmnode.start << PAGE_SHIFT;
337 size_t len = mapping->mmnode.size << PAGE_SHIFT;
338 size_t unmapped_len = 0;
340 if (WARN_ON(!mapping->active))
343 dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx",
344 mapping->mmu->as, iova, len);
346 while (unmapped_len < len) {
347 size_t unmapped_page;
348 size_t pgsize = get_pgsize(iova, len - unmapped_len);
350 if (ops->iova_to_phys(ops, iova)) {
351 unmapped_page = ops->unmap(ops, iova, pgsize, NULL);
352 WARN_ON(unmapped_page != pgsize);
355 unmapped_len += pgsize;
358 panfrost_mmu_flush_range(pfdev, mapping->mmu,
359 mapping->mmnode.start << PAGE_SHIFT, len);
360 mapping->active = false;
363 static void mmu_tlb_inv_context_s1(void *cookie)
366 static void mmu_tlb_sync_context(void *cookie)
368 //struct panfrost_mmu *mmu = cookie;
369 // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X
372 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule,
375 mmu_tlb_sync_context(cookie);
378 static const struct iommu_flush_ops mmu_tlb_ops = {
379 .tlb_flush_all = mmu_tlb_inv_context_s1,
380 .tlb_flush_walk = mmu_tlb_flush_walk,
383 static struct panfrost_gem_mapping *
384 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr)
386 struct panfrost_gem_mapping *mapping = NULL;
387 struct drm_mm_node *node;
388 u64 offset = addr >> PAGE_SHIFT;
389 struct panfrost_mmu *mmu;
391 spin_lock(&pfdev->as_lock);
392 list_for_each_entry(mmu, &pfdev->as_lru_list, list) {
400 spin_lock(&mmu->mm_lock);
402 drm_mm_for_each_node(node, &mmu->mm) {
403 if (offset >= node->start &&
404 offset < (node->start + node->size)) {
405 mapping = drm_mm_node_to_panfrost_mapping(node);
407 kref_get(&mapping->refcount);
412 spin_unlock(&mmu->mm_lock);
414 spin_unlock(&pfdev->as_lock);
418 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE)
420 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
424 struct panfrost_gem_mapping *bomapping;
425 struct panfrost_gem_object *bo;
426 struct address_space *mapping;
428 struct sg_table *sgt;
431 bomapping = addr_to_mapping(pfdev, as, addr);
437 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)",
438 bomapping->mmnode.start << PAGE_SHIFT);
442 WARN_ON(bomapping->mmu->as != as);
444 /* Assume 2MB alignment and size multiple */
445 addr &= ~((u64)SZ_2M - 1);
446 page_offset = addr >> PAGE_SHIFT;
447 page_offset -= bomapping->mmnode.start;
449 mutex_lock(&bo->base.pages_lock);
451 if (!bo->base.pages) {
452 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M,
453 sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO);
455 mutex_unlock(&bo->base.pages_lock);
460 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT,
461 sizeof(struct page *), GFP_KERNEL | __GFP_ZERO);
465 mutex_unlock(&bo->base.pages_lock);
469 bo->base.pages = pages;
470 bo->base.pages_use_count = 1;
472 pages = bo->base.pages;
473 if (pages[page_offset]) {
474 /* Pages are already mapped, bail out. */
475 mutex_unlock(&bo->base.pages_lock);
480 mapping = bo->base.base.filp->f_mapping;
481 mapping_set_unevictable(mapping);
483 for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) {
484 pages[i] = shmem_read_mapping_page(mapping, i);
485 if (IS_ERR(pages[i])) {
486 mutex_unlock(&bo->base.pages_lock);
487 ret = PTR_ERR(pages[i]);
492 mutex_unlock(&bo->base.pages_lock);
494 sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)];
495 ret = sg_alloc_table_from_pages(sgt, pages + page_offset,
496 NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL);
500 ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
504 mmu_map_sg(pfdev, bomapping->mmu, addr,
505 IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt);
507 bomapping->active = true;
509 dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr);
512 panfrost_gem_mapping_put(bomapping);
519 drm_gem_shmem_put_pages(&bo->base);
521 drm_gem_object_put(&bo->base.base);
525 static void panfrost_mmu_release_ctx(struct kref *kref)
527 struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu,
529 struct panfrost_device *pfdev = mmu->pfdev;
531 spin_lock(&pfdev->as_lock);
533 pm_runtime_get_noresume(pfdev->dev);
534 if (pm_runtime_active(pfdev->dev))
535 panfrost_mmu_disable(pfdev, mmu->as);
536 pm_runtime_put_autosuspend(pfdev->dev);
538 clear_bit(mmu->as, &pfdev->as_alloc_mask);
539 clear_bit(mmu->as, &pfdev->as_in_use_mask);
540 list_del(&mmu->list);
542 spin_unlock(&pfdev->as_lock);
544 free_io_pgtable_ops(mmu->pgtbl_ops);
545 drm_mm_takedown(&mmu->mm);
549 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu)
551 kref_put(&mmu->refcount, panfrost_mmu_release_ctx);
554 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu)
556 kref_get(&mmu->refcount);
561 #define PFN_4G (SZ_4G >> PAGE_SHIFT)
562 #define PFN_4G_MASK (PFN_4G - 1)
563 #define PFN_16M (SZ_16M >> PAGE_SHIFT)
565 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node,
567 u64 *start, u64 *end)
569 /* Executable buffers can't start or end on a 4GB boundary */
570 if (!(color & PANFROST_BO_NOEXEC)) {
573 if ((*start & PFN_4G_MASK) == 0)
576 if ((*end & PFN_4G_MASK) == 0)
579 next_seg = ALIGN(*start, PFN_4G);
580 if (next_seg - *start <= PFN_16M)
581 *start = next_seg + 1;
583 *end = min(*end, ALIGN(*start, PFN_4G) - 1);
587 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev)
589 struct panfrost_mmu *mmu;
591 mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
593 return ERR_PTR(-ENOMEM);
596 spin_lock_init(&mmu->mm_lock);
598 /* 4G enough for now. can be 48-bit */
599 drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT);
600 mmu->mm.color_adjust = panfrost_drm_mm_color_adjust;
602 INIT_LIST_HEAD(&mmu->list);
605 mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
606 .pgsize_bitmap = SZ_4K | SZ_2M,
607 .ias = FIELD_GET(0xff, pfdev->features.mmu_features),
608 .oas = FIELD_GET(0xff00, pfdev->features.mmu_features),
609 .coherent_walk = pfdev->coherent,
611 .iommu_dev = pfdev->dev,
614 mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg,
616 if (!mmu->pgtbl_ops) {
618 return ERR_PTR(-EINVAL);
621 kref_init(&mmu->refcount);
626 static const char *access_type_name(struct panfrost_device *pfdev,
629 switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) {
630 case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC:
631 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU))
635 case AS_FAULTSTATUS_ACCESS_TYPE_READ:
637 case AS_FAULTSTATUS_ACCESS_TYPE_WRITE:
639 case AS_FAULTSTATUS_ACCESS_TYPE_EX:
647 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data)
649 struct panfrost_device *pfdev = data;
651 if (!mmu_read(pfdev, MMU_INT_STAT))
654 mmu_write(pfdev, MMU_INT_MASK, 0);
655 return IRQ_WAKE_THREAD;
658 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
660 struct panfrost_device *pfdev = data;
661 u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT);
665 u32 as = ffs(status | (status >> 16)) - 1;
666 u32 mask = BIT(as) | BIT(as + 16);
673 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as));
674 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as));
675 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32;
677 /* decode the fault status */
678 exception_type = fault_status & 0xFF;
679 access_type = (fault_status >> 8) & 0x3;
680 source_id = (fault_status >> 16);
682 mmu_write(pfdev, MMU_INT_CLEAR, mask);
684 /* Page fault only */
686 if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0)
687 ret = panfrost_mmu_map_fault_addr(pfdev, as, addr);
690 /* terminal fault, print info about the fault */
692 "Unhandled Page fault in AS%d at VA 0x%016llX\n"
694 "raw fault status: 0x%X\n"
695 "decoded fault status: %s\n"
696 "exception type 0x%X: %s\n"
697 "access type 0x%X: %s\n"
702 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
703 exception_type, panfrost_exception_name(exception_type),
704 access_type, access_type_name(pfdev, fault_status),
707 spin_lock(&pfdev->as_lock);
708 /* Ignore MMU interrupts on this AS until it's been
711 pfdev->as_faulty_mask |= mask;
713 /* Disable the MMU to kill jobs on this AS. */
714 panfrost_mmu_disable(pfdev, as);
715 spin_unlock(&pfdev->as_lock);
720 /* If we received new MMU interrupts, process them before returning. */
722 status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask;
725 spin_lock(&pfdev->as_lock);
726 mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
727 spin_unlock(&pfdev->as_lock);
732 int panfrost_mmu_init(struct panfrost_device *pfdev)
736 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu");
740 err = devm_request_threaded_irq(pfdev->dev, irq,
741 panfrost_mmu_irq_handler,
742 panfrost_mmu_irq_handler_thread,
743 IRQF_SHARED, KBUILD_MODNAME "-mmu",
747 dev_err(pfdev->dev, "failed to request mmu irq");
754 void panfrost_mmu_fini(struct panfrost_device *pfdev)
756 mmu_write(pfdev, MMU_INT_MASK, 0);