drivers/gpu/drm/panfrost/panfrost_mmu.c

   1 // SPDX-License-Identifier:     GPL-2.0
   2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
   3
   4 #include <drm/panfrost_drm.h>
   5
   6 #include <linux/atomic.h>
   7 #include <linux/bitfield.h>
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/io-pgtable.h>
  14 #include <linux/iommu.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/shmem_fs.h>
  18 #include <linux/sizes.h>
  19
  20 #include "panfrost_device.h"
  21 #include "panfrost_mmu.h"
  22 #include "panfrost_gem.h"
  23 #include "panfrost_features.h"
  24 #include "panfrost_regs.h"
  25
  26 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg)
  27 #define mmu_read(dev, reg) readl(dev->iomem + reg)
  28
  29 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr)
  30 {
  31         int ret;
  32         u32 val;
  33
  34         /* Wait for the MMU status to indicate there is no active command, in
  35          * case one is pending. */
  36         ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr),
  37                 val, !(val & AS_STATUS_AS_ACTIVE), 10, 1000);
  38
  39         if (ret)
  40                 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n");
  41
  42         return ret;
  43 }
  44
  45 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd)
  46 {
  47         int status;
  48
  49         /* write AS_COMMAND when MMU is ready to accept another command */
  50         status = wait_ready(pfdev, as_nr);
  51         if (!status)
  52                 mmu_write(pfdev, AS_COMMAND(as_nr), cmd);
  53
  54         return status;
  55 }
  56
  57 static void lock_region(struct panfrost_device *pfdev, u32 as_nr,
  58                         u64 iova, u64 size)
  59 {
  60         u8 region_width;
  61         u64 region = iova & PAGE_MASK;
  62
  63         /* The size is encoded as ceil(log2) minus(1), which may be calculated
  64          * with fls. The size must be clamped to hardware bounds.
  65          */
  66         size = max_t(u64, size, AS_LOCK_REGION_MIN_SIZE);
  67         region_width = fls64(size - 1) - 1;
  68         region |= region_width;
  69
  70         /* Lock the region that needs to be updated */
  71         mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), region & 0xFFFFFFFFUL);
  72         mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), (region >> 32) & 0xFFFFFFFFUL);
  73         write_cmd(pfdev, as_nr, AS_COMMAND_LOCK);
  74 }
  75
  76
  77 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr,
  78                                       u64 iova, u64 size, u32 op)
  79 {
  80         if (as_nr < 0)
  81                 return 0;
  82
  83         if (op != AS_COMMAND_UNLOCK)
  84                 lock_region(pfdev, as_nr, iova, size);
  85
  86         /* Run the MMU operation */
  87         write_cmd(pfdev, as_nr, op);
  88
  89         /* Wait for the flush to complete */
  90         return wait_ready(pfdev, as_nr);
  91 }
  92
  93 static int mmu_hw_do_operation(struct panfrost_device *pfdev,
  94                                struct panfrost_mmu *mmu,
  95                                u64 iova, u64 size, u32 op)
  96 {
  97         int ret;
  98
  99         spin_lock(&pfdev->as_lock);
 100         ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op);
 101         spin_unlock(&pfdev->as_lock);
 102         return ret;
 103 }
 104
 105 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
 106 {
 107         int as_nr = mmu->as;
 108         struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
 109         u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
 110         u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
 111
 112         mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
 113
 114         mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
 115         mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);
 116
 117         /* Need to revisit mem attrs.
 118          * NC is the default, Mali driver is inner WT.
 119          */
 120         mmu_write(pfdev, AS_MEMATTR_LO(as_nr), memattr & 0xffffffffUL);
 121         mmu_write(pfdev, AS_MEMATTR_HI(as_nr), memattr >> 32);
 122
 123         write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
 124 }
 125
 126 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
 127 {
 128         mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
 129
 130         mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
 131         mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
 132
 133         mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0);
 134         mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0);
 135
 136         write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
 137 }
 138
 139 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
 140 {
 141         int as;
 142
 143         spin_lock(&pfdev->as_lock);
 144
 145         as = mmu->as;
 146         if (as >= 0) {
 147                 int en = atomic_inc_return(&mmu->as_count);
 148
 149                 /*
 150                  * AS can be retained by active jobs or a perfcnt context,
 151                  * hence the '+ 1' here.
 152                  */
 153                 WARN_ON(en >= (NUM_JOB_SLOTS + 1));
 154
 155                 list_move(&mmu->list, &pfdev->as_lru_list);
 156                 goto out;
 157         }
 158
 159         /* Check for a free AS */
 160         as = ffz(pfdev->as_alloc_mask);
 161         if (!(BIT(as) & pfdev->features.as_present)) {
 162                 struct panfrost_mmu *lru_mmu;
 163
 164                 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) {
 165                         if (!atomic_read(&lru_mmu->as_count))
 166                                 break;
 167                 }
 168                 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list);
 169
 170                 list_del_init(&lru_mmu->list);
 171                 as = lru_mmu->as;
 172
 173                 WARN_ON(as < 0);
 174                 lru_mmu->as = -1;
 175         }
 176
 177         /* Assign the free or reclaimed AS to the FD */
 178         mmu->as = as;
 179         set_bit(as, &pfdev->as_alloc_mask);
 180         atomic_set(&mmu->as_count, 1);
 181         list_add(&mmu->list, &pfdev->as_lru_list);
 182
 183         dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
 184
 185         panfrost_mmu_enable(pfdev, mmu);
 186
 187 out:
 188         spin_unlock(&pfdev->as_lock);
 189         return as;
 190 }
 191
 192 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
 193 {
 194         atomic_dec(&mmu->as_count);
 195         WARN_ON(atomic_read(&mmu->as_count) < 0);
 196 }
 197
 198 void panfrost_mmu_reset(struct panfrost_device *pfdev)
 199 {
 200         struct panfrost_mmu *mmu, *mmu_tmp;
 201
 202         spin_lock(&pfdev->as_lock);
 203
 204         pfdev->as_alloc_mask = 0;
 205
 206         list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) {
 207                 mmu->as = -1;
 208                 atomic_set(&mmu->as_count, 0);
 209                 list_del_init(&mmu->list);
 210         }
 211
 212         spin_unlock(&pfdev->as_lock);
 213
 214         mmu_write(pfdev, MMU_INT_CLEAR, ~0);
 215         mmu_write(pfdev, MMU_INT_MASK, ~0);
 216 }
 217
 218 static size_t get_pgsize(u64 addr, size_t size)
 219 {
 220         if (addr & (SZ_2M - 1) || size < SZ_2M)
 221                 return SZ_4K;
 222
 223         return SZ_2M;
 224 }
 225
 226 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev,
 227                                      struct panfrost_mmu *mmu,
 228                                      u64 iova, u64 size)
 229 {
 230         if (mmu->as < 0)
 231                 return;
 232
 233         pm_runtime_get_noresume(pfdev->dev);
 234
 235         /* Flush the PTs only if we're already awake */
 236         if (pm_runtime_active(pfdev->dev))
 237                 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT);
 238
 239         pm_runtime_put_sync_autosuspend(pfdev->dev);
 240 }
 241
 242 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu,
 243                       u64 iova, int prot, struct sg_table *sgt)
 244 {
 245         unsigned int count;
 246         struct scatterlist *sgl;
 247         struct io_pgtable_ops *ops = mmu->pgtbl_ops;
 248         u64 start_iova = iova;
 249
 250         for_each_sgtable_dma_sg(sgt, sgl, count) {
 251                 unsigned long paddr = sg_dma_address(sgl);
 252                 size_t len = sg_dma_len(sgl);
 253
 254                 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len);
 255
 256                 while (len) {
 257                         size_t pgsize = get_pgsize(iova | paddr, len);
 258
 259                         ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL);
 260                         iova += pgsize;
 261                         paddr += pgsize;
 262                         len -= pgsize;
 263                 }
 264         }
 265
 266         panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova);
 267
 268         return 0;
 269 }
 270
 271 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping)
 272 {
 273         struct panfrost_gem_object *bo = mapping->obj;
 274         struct drm_gem_object *obj = &bo->base.base;
 275         struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
 276         struct sg_table *sgt;
 277         int prot = IOMMU_READ | IOMMU_WRITE;
 278
 279         if (WARN_ON(mapping->active))
 280                 return 0;
 281
 282         if (bo->noexec)
 283                 prot |= IOMMU_NOEXEC;
 284
 285         sgt = drm_gem_shmem_get_pages_sgt(obj);
 286         if (WARN_ON(IS_ERR(sgt)))
 287                 return PTR_ERR(sgt);
 288
 289         mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT,
 290                    prot, sgt);
 291         mapping->active = true;
 292
 293         return 0;
 294 }
 295
 296 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping)
 297 {
 298         struct panfrost_gem_object *bo = mapping->obj;
 299         struct drm_gem_object *obj = &bo->base.base;
 300         struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
 301         struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops;
 302         u64 iova = mapping->mmnode.start << PAGE_SHIFT;
 303         size_t len = mapping->mmnode.size << PAGE_SHIFT;
 304         size_t unmapped_len = 0;
 305
 306         if (WARN_ON(!mapping->active))
 307                 return;
 308
 309         dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx",
 310                 mapping->mmu->as, iova, len);
 311
 312         while (unmapped_len < len) {
 313                 size_t unmapped_page;
 314                 size_t pgsize = get_pgsize(iova, len - unmapped_len);
 315
 316                 if (ops->iova_to_phys(ops, iova)) {
 317                         unmapped_page = ops->unmap(ops, iova, pgsize, NULL);
 318                         WARN_ON(unmapped_page != pgsize);
 319                 }
 320                 iova += pgsize;
 321                 unmapped_len += pgsize;
 322         }
 323
 324         panfrost_mmu_flush_range(pfdev, mapping->mmu,
 325                                  mapping->mmnode.start << PAGE_SHIFT, len);
 326         mapping->active = false;
 327 }
 328
 329 static void mmu_tlb_inv_context_s1(void *cookie)
 330 {}
 331
 332 static void mmu_tlb_sync_context(void *cookie)
 333 {
 334         //struct panfrost_mmu *mmu = cookie;
 335         // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X
 336 }
 337
 338 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule,
 339                                void *cookie)
 340 {
 341         mmu_tlb_sync_context(cookie);
 342 }
 343
 344 static void mmu_tlb_flush_leaf(unsigned long iova, size_t size, size_t granule,
 345                                void *cookie)
 346 {
 347         mmu_tlb_sync_context(cookie);
 348 }
 349
 350 static const struct iommu_flush_ops mmu_tlb_ops = {
 351         .tlb_flush_all  = mmu_tlb_inv_context_s1,
 352         .tlb_flush_walk = mmu_tlb_flush_walk,
 353         .tlb_flush_leaf = mmu_tlb_flush_leaf,
 354 };
 355
 356 static struct panfrost_gem_mapping *
 357 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr)
 358 {
 359         struct panfrost_gem_mapping *mapping = NULL;
 360         struct drm_mm_node *node;
 361         u64 offset = addr >> PAGE_SHIFT;
 362         struct panfrost_mmu *mmu;
 363
 364         spin_lock(&pfdev->as_lock);
 365         list_for_each_entry(mmu, &pfdev->as_lru_list, list) {
 366                 if (as == mmu->as)
 367                         goto found_mmu;
 368         }
 369         goto out;
 370
 371 found_mmu:
 372
 373         spin_lock(&mmu->mm_lock);
 374
 375         drm_mm_for_each_node(node, &mmu->mm) {
 376                 if (offset >= node->start &&
 377                     offset < (node->start + node->size)) {
 378                         mapping = drm_mm_node_to_panfrost_mapping(node);
 379
 380                         kref_get(&mapping->refcount);
 381                         break;
 382                 }
 383         }
 384
 385         spin_unlock(&mmu->mm_lock);
 386 out:
 387         spin_unlock(&pfdev->as_lock);
 388         return mapping;
 389 }
 390
 391 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE)
 392
 393 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
 394                                        u64 addr)
 395 {
 396         int ret, i;
 397         struct panfrost_gem_mapping *bomapping;
 398         struct panfrost_gem_object *bo;
 399         struct address_space *mapping;
 400         pgoff_t page_offset;
 401         struct sg_table *sgt;
 402         struct page **pages;
 403
 404         bomapping = addr_to_mapping(pfdev, as, addr);
 405         if (!bomapping)
 406                 return -ENOENT;
 407
 408         bo = bomapping->obj;
 409         if (!bo->is_heap) {
 410                 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)",
 411                          bomapping->mmnode.start << PAGE_SHIFT);
 412                 ret = -EINVAL;
 413                 goto err_bo;
 414         }
 415         WARN_ON(bomapping->mmu->as != as);
 416
 417         /* Assume 2MB alignment and size multiple */
 418         addr &= ~((u64)SZ_2M - 1);
 419         page_offset = addr >> PAGE_SHIFT;
 420         page_offset -= bomapping->mmnode.start;
 421
 422         mutex_lock(&bo->base.pages_lock);
 423
 424         if (!bo->base.pages) {
 425                 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M,
 426                                      sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO);
 427                 if (!bo->sgts) {
 428                         mutex_unlock(&bo->base.pages_lock);
 429                         ret = -ENOMEM;
 430                         goto err_bo;
 431                 }
 432
 433                 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT,
 434                                        sizeof(struct page *), GFP_KERNEL | __GFP_ZERO);
 435                 if (!pages) {
 436                         kvfree(bo->sgts);
 437                         bo->sgts = NULL;
 438                         mutex_unlock(&bo->base.pages_lock);
 439                         ret = -ENOMEM;
 440                         goto err_bo;
 441                 }
 442                 bo->base.pages = pages;
 443                 bo->base.pages_use_count = 1;
 444         } else {
 445                 pages = bo->base.pages;
 446                 if (pages[page_offset]) {
 447                         /* Pages are already mapped, bail out. */
 448                         mutex_unlock(&bo->base.pages_lock);
 449                         goto out;
 450                 }
 451         }
 452
 453         mapping = bo->base.base.filp->f_mapping;
 454         mapping_set_unevictable(mapping);
 455
 456         for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) {
 457                 pages[i] = shmem_read_mapping_page(mapping, i);
 458                 if (IS_ERR(pages[i])) {
 459                         mutex_unlock(&bo->base.pages_lock);
 460                         ret = PTR_ERR(pages[i]);
 461                         goto err_pages;
 462                 }
 463         }
 464
 465         mutex_unlock(&bo->base.pages_lock);
 466
 467         sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)];
 468         ret = sg_alloc_table_from_pages(sgt, pages + page_offset,
 469                                         NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL);
 470         if (ret)
 471                 goto err_pages;
 472
 473         ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
 474         if (ret)
 475                 goto err_map;
 476
 477         mmu_map_sg(pfdev, bomapping->mmu, addr,
 478                    IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt);
 479
 480         bomapping->active = true;
 481
 482         dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr);
 483
 484 out:
 485         panfrost_gem_mapping_put(bomapping);
 486
 487         return 0;
 488
 489 err_map:
 490         sg_free_table(sgt);
 491 err_pages:
 492         drm_gem_shmem_put_pages(&bo->base);
 493 err_bo:
 494         panfrost_gem_mapping_put(bomapping);
 495         return ret;
 496 }
 497
 498 static void panfrost_mmu_release_ctx(struct kref *kref)
 499 {
 500         struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu,
 501                                                 refcount);
 502         struct panfrost_device *pfdev = mmu->pfdev;
 503
 504         spin_lock(&pfdev->as_lock);
 505         if (mmu->as >= 0) {
 506                 pm_runtime_get_noresume(pfdev->dev);
 507                 if (pm_runtime_active(pfdev->dev))
 508                         panfrost_mmu_disable(pfdev, mmu->as);
 509                 pm_runtime_put_autosuspend(pfdev->dev);
 510
 511                 clear_bit(mmu->as, &pfdev->as_alloc_mask);
 512                 clear_bit(mmu->as, &pfdev->as_in_use_mask);
 513                 list_del(&mmu->list);
 514         }
 515         spin_unlock(&pfdev->as_lock);
 516
 517         free_io_pgtable_ops(mmu->pgtbl_ops);
 518         drm_mm_takedown(&mmu->mm);
 519         kfree(mmu);
 520 }
 521
 522 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu)
 523 {
 524         kref_put(&mmu->refcount, panfrost_mmu_release_ctx);
 525 }
 526
 527 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu)
 528 {
 529         kref_get(&mmu->refcount);
 530
 531         return mmu;
 532 }
 533
 534 #define PFN_4G          (SZ_4G >> PAGE_SHIFT)
 535 #define PFN_4G_MASK     (PFN_4G - 1)
 536 #define PFN_16M         (SZ_16M >> PAGE_SHIFT)
 537
 538 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node,
 539                                          unsigned long color,
 540                                          u64 *start, u64 *end)
 541 {
 542         /* Executable buffers can't start or end on a 4GB boundary */
 543         if (!(color & PANFROST_BO_NOEXEC)) {
 544                 u64 next_seg;
 545
 546                 if ((*start & PFN_4G_MASK) == 0)
 547                         (*start)++;
 548
 549                 if ((*end & PFN_4G_MASK) == 0)
 550                         (*end)--;
 551
 552                 next_seg = ALIGN(*start, PFN_4G);
 553                 if (next_seg - *start <= PFN_16M)
 554                         *start = next_seg + 1;
 555
 556                 *end = min(*end, ALIGN(*start, PFN_4G) - 1);
 557         }
 558 }
 559
 560 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev)
 561 {
 562         struct panfrost_mmu *mmu;
 563
 564         mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
 565         if (!mmu)
 566                 return ERR_PTR(-ENOMEM);
 567
 568         mmu->pfdev = pfdev;
 569         spin_lock_init(&mmu->mm_lock);
 570
 571         /* 4G enough for now. can be 48-bit */
 572         drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT);
 573         mmu->mm.color_adjust = panfrost_drm_mm_color_adjust;
 574
 575         INIT_LIST_HEAD(&mmu->list);
 576         mmu->as = -1;
 577
 578         mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
 579                 .pgsize_bitmap  = SZ_4K | SZ_2M,
 580                 .ias            = FIELD_GET(0xff, pfdev->features.mmu_features),
 581                 .oas            = FIELD_GET(0xff00, pfdev->features.mmu_features),
 582                 .coherent_walk  = pfdev->coherent,
 583                 .tlb            = &mmu_tlb_ops,
 584                 .iommu_dev      = pfdev->dev,
 585         };
 586
 587         mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg,
 588                                               mmu);
 589         if (!mmu->pgtbl_ops) {
 590                 kfree(mmu);
 591                 return ERR_PTR(-EINVAL);
 592         }
 593
 594         kref_init(&mmu->refcount);
 595
 596         return mmu;
 597 }
 598
 599 static const char *access_type_name(struct panfrost_device *pfdev,
 600                 u32 fault_status)
 601 {
 602         switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) {
 603         case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC:
 604                 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU))
 605                         return "ATOMIC";
 606                 else
 607                         return "UNKNOWN";
 608         case AS_FAULTSTATUS_ACCESS_TYPE_READ:
 609                 return "READ";
 610         case AS_FAULTSTATUS_ACCESS_TYPE_WRITE:
 611                 return "WRITE";
 612         case AS_FAULTSTATUS_ACCESS_TYPE_EX:
 613                 return "EXECUTE";
 614         default:
 615                 WARN_ON(1);
 616                 return NULL;
 617         }
 618 }
 619
 620 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data)
 621 {
 622         struct panfrost_device *pfdev = data;
 623
 624         if (!mmu_read(pfdev, MMU_INT_STAT))
 625                 return IRQ_NONE;
 626
 627         mmu_write(pfdev, MMU_INT_MASK, 0);
 628         return IRQ_WAKE_THREAD;
 629 }
 630
 631 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
 632 {
 633         struct panfrost_device *pfdev = data;
 634         u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT);
 635         int i, ret;
 636
 637         for (i = 0; status; i++) {
 638                 u32 mask = BIT(i) | BIT(i + 16);
 639                 u64 addr;
 640                 u32 fault_status;
 641                 u32 exception_type;
 642                 u32 access_type;
 643                 u32 source_id;
 644
 645                 if (!(status & mask))
 646                         continue;
 647
 648                 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(i));
 649                 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(i));
 650                 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(i)) << 32;
 651
 652                 /* decode the fault status */
 653                 exception_type = fault_status & 0xFF;
 654                 access_type = (fault_status >> 8) & 0x3;
 655                 source_id = (fault_status >> 16);
 656
 657                 mmu_write(pfdev, MMU_INT_CLEAR, mask);
 658
 659                 /* Page fault only */
 660                 ret = -1;
 661                 if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0)
 662                         ret = panfrost_mmu_map_fault_addr(pfdev, i, addr);
 663
 664                 if (ret)
 665                         /* terminal fault, print info about the fault */
 666                         dev_err(pfdev->dev,
 667                                 "Unhandled Page fault in AS%d at VA 0x%016llX\n"
 668                                 "Reason: %s\n"
 669                                 "raw fault status: 0x%X\n"
 670                                 "decoded fault status: %s\n"
 671                                 "exception type 0x%X: %s\n"
 672                                 "access type 0x%X: %s\n"
 673                                 "source id 0x%X\n",
 674                                 i, addr,
 675                                 "TODO",
 676                                 fault_status,
 677                                 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
 678                                 exception_type, panfrost_exception_name(pfdev, exception_type),
 679                                 access_type, access_type_name(pfdev, fault_status),
 680                                 source_id);
 681
 682                 status &= ~mask;
 683         }
 684
 685         mmu_write(pfdev, MMU_INT_MASK, ~0);
 686         return IRQ_HANDLED;
 687 };
 688
 689 int panfrost_mmu_init(struct panfrost_device *pfdev)
 690 {
 691         int err, irq;
 692
 693         irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu");
 694         if (irq <= 0)
 695                 return -ENODEV;
 696
 697         err = devm_request_threaded_irq(pfdev->dev, irq,
 698                                         panfrost_mmu_irq_handler,
 699                                         panfrost_mmu_irq_handler_thread,
 700                                         IRQF_SHARED, KBUILD_MODNAME "-mmu",
 701                                         pfdev);
 702
 703         if (err) {
 704                 dev_err(pfdev->dev, "failed to request mmu irq");
 705                 return err;
 706         }
 707
 708         return 0;
 709 }
 710
 711 void panfrost_mmu_fini(struct panfrost_device *pfdev)
 712 {
 713         mmu_write(pfdev, MMU_INT_MASK, 0);
 714 }