drivers/gpu/drm/panfrost/panfrost_device.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
   3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
   4
   5 #ifndef __PANFROST_DEVICE_H__
   6 #define __PANFROST_DEVICE_H__
   7
   8 #include <linux/atomic.h>
   9 #include <linux/io-pgtable.h>
  10 #include <linux/regulator/consumer.h>
  11 #include <linux/spinlock.h>
  12 #include <drm/drm_device.h>
  13 #include <drm/drm_mm.h>
  14 #include <drm/gpu_scheduler.h>
  15
  16 #include "panfrost_devfreq.h"
  17
  18 struct panfrost_device;
  19 struct panfrost_mmu;
  20 struct panfrost_job_slot;
  21 struct panfrost_job;
  22 struct panfrost_perfcnt;
  23
  24 #define NUM_JOB_SLOTS 3
  25 #define MAX_PM_DOMAINS 3
  26
  27 struct panfrost_features {
  28         u16 id;
  29         u16 revision;
  30
  31         u64 shader_present;
  32         u64 tiler_present;
  33         u64 l2_present;
  34         u64 stack_present;
  35         u32 as_present;
  36         u32 js_present;
  37
  38         u32 l2_features;
  39         u32 core_features;
  40         u32 tiler_features;
  41         u32 mem_features;
  42         u32 mmu_features;
  43         u32 thread_features;
  44         u32 max_threads;
  45         u32 thread_max_workgroup_sz;
  46         u32 thread_max_barrier_sz;
  47         u32 coherency_features;
  48         u32 afbc_features;
  49         u32 texture_features[4];
  50         u32 js_features[16];
  51
  52         u32 nr_core_groups;
  53         u32 thread_tls_alloc;
  54
  55         unsigned long hw_features[64 / BITS_PER_LONG];
  56         unsigned long hw_issues[64 / BITS_PER_LONG];
  57 };
  58
  59 /*
  60  * Features that cannot be automatically detected and need matching using the
  61  * compatible string, typically SoC-specific.
  62  */
  63 struct panfrost_compatible {
  64         /* Supplies count and names. */
  65         int num_supplies;
  66         const char * const *supply_names;
  67         /*
  68          * Number of power domains required, note that values 0 and 1 are
  69          * handled identically, as only values > 1 need special handling.
  70          */
  71         int num_pm_domains;
  72         /* Only required if num_pm_domains > 1. */
  73         const char * const *pm_domain_names;
  74
  75         /* Vendor implementation quirks callback */
  76         void (*vendor_quirk)(struct panfrost_device *pfdev);
  77 };
  78
  79 struct panfrost_device {
  80         struct device *dev;
  81         struct drm_device *ddev;
  82         struct platform_device *pdev;
  83
  84         void __iomem *iomem;
  85         struct clk *clock;
  86         struct clk *bus_clock;
  87         struct regulator_bulk_data *regulators;
  88         struct reset_control *rstc;
  89         /* pm_domains for devices with more than one. */
  90         struct device *pm_domain_devs[MAX_PM_DOMAINS];
  91         struct device_link *pm_domain_links[MAX_PM_DOMAINS];
  92         bool coherent;
  93
  94         struct panfrost_features features;
  95         const struct panfrost_compatible *comp;
  96
  97         spinlock_t as_lock;
  98         unsigned long as_in_use_mask;
  99         unsigned long as_alloc_mask;
 100         unsigned long as_faulty_mask;
 101         struct list_head as_lru_list;
 102
 103         struct panfrost_job_slot *js;
 104
 105         struct panfrost_job *jobs[NUM_JOB_SLOTS][2];
 106         struct list_head scheduled_jobs;
 107
 108         struct panfrost_perfcnt *perfcnt;
 109
 110         struct mutex sched_lock;
 111
 112         struct {
 113                 struct workqueue_struct *wq;
 114                 struct work_struct work;
 115                 atomic_t pending;
 116         } reset;
 117
 118         struct mutex shrinker_lock;
 119         struct list_head shrinker_list;
 120         struct shrinker shrinker;
 121
 122         struct panfrost_devfreq pfdevfreq;
 123 };
 124
 125 struct panfrost_mmu {
 126         struct panfrost_device *pfdev;
 127         struct kref refcount;
 128         struct io_pgtable_cfg pgtbl_cfg;
 129         struct io_pgtable_ops *pgtbl_ops;
 130         struct drm_mm mm;
 131         spinlock_t mm_lock;
 132         int as;
 133         atomic_t as_count;
 134         struct list_head list;
 135 };
 136
 137 struct panfrost_file_priv {
 138         struct panfrost_device *pfdev;
 139
 140         struct drm_sched_entity sched_entity[NUM_JOB_SLOTS];
 141
 142         struct panfrost_mmu *mmu;
 143 };
 144
 145 static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev)
 146 {
 147         return ddev->dev_private;
 148 }
 149
 150 static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id)
 151 {
 152         s32 match_id = pfdev->features.id;
 153
 154         if (match_id & 0xf000)
 155                 match_id &= 0xf00f;
 156         return match_id - id;
 157 }
 158
 159 static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev)
 160 {
 161         return panfrost_model_cmp(pfdev, 0x1000) >= 0;
 162 }
 163
 164 static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id)
 165 {
 166         return !panfrost_model_cmp(pfdev, id);
 167 }
 168
 169 int panfrost_unstable_ioctl_check(void);
 170
 171 int panfrost_device_init(struct panfrost_device *pfdev);
 172 void panfrost_device_fini(struct panfrost_device *pfdev);
 173 void panfrost_device_reset(struct panfrost_device *pfdev);
 174
 175 int panfrost_device_resume(struct device *dev);
 176 int panfrost_device_suspend(struct device *dev);
 177
 178 enum drm_panfrost_exception_type {
 179         DRM_PANFROST_EXCEPTION_OK = 0x00,
 180         DRM_PANFROST_EXCEPTION_DONE = 0x01,
 181         DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02,
 182         DRM_PANFROST_EXCEPTION_STOPPED = 0x03,
 183         DRM_PANFROST_EXCEPTION_TERMINATED = 0x04,
 184         DRM_PANFROST_EXCEPTION_KABOOM = 0x05,
 185         DRM_PANFROST_EXCEPTION_EUREKA = 0x06,
 186         DRM_PANFROST_EXCEPTION_ACTIVE = 0x08,
 187         DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f,
 188         DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40,
 189         DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41,
 190         DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42,
 191         DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43,
 192         DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44,
 193         DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48,
 194         DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50,
 195         DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51,
 196         DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52,
 197         DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53,
 198         DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54,
 199         DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55,
 200         DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56,
 201         DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58,
 202         DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59,
 203         DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a,
 204         DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b,
 205         DRM_PANFROST_EXCEPTION_OOM = 0x60,
 206         DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61,
 207         DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f,
 208         DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80,
 209         DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88,
 210         DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89,
 211         DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a,
 212         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0,
 213         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1,
 214         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2,
 215         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3,
 216         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4,
 217         DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7,
 218         DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8,
 219         DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9,
 220         DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca,
 221         DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb,
 222         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0,
 223         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1,
 224         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2,
 225         DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3,
 226         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8,
 227         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9,
 228         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda,
 229         DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb,
 230         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0,
 231         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1,
 232         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2,
 233         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3,
 234         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4,
 235         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5,
 236         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6,
 237         DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7,
 238         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8,
 239         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9,
 240         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea,
 241         DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb,
 242         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec,
 243         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed,
 244         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee,
 245         DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef,
 246 };
 247
 248 static inline bool
 249 panfrost_exception_is_fault(u32 exception_code)
 250 {
 251         return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT;
 252 }
 253
 254 const char *panfrost_exception_name(u32 exception_code);
 255 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
 256                                     u32 exception_code);
 257
 258 static inline void
 259 panfrost_device_schedule_reset(struct panfrost_device *pfdev)
 260 {
 261         atomic_set(&pfdev->reset.pending, 1);
 262         queue_work(pfdev->reset.wq, &pfdev->reset.work);
 263 }
 264
 265 #endif