2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
89 unsigned int hpd_absent_delay;
92 unsigned int unprepare;
100 struct panel_simple {
101 struct drm_panel base;
106 const struct panel_desc *desc;
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
114 struct drm_display_mode override_mode;
116 enum drm_panel_orientation orientation;
119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
121 return container_of(panel, struct panel_simple, base);
124 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
125 struct drm_connector *connector)
127 struct drm_display_mode *mode;
128 unsigned int i, num = 0;
130 for (i = 0; i < panel->desc->num_timings; i++) {
131 const struct display_timing *dt = &panel->desc->timings[i];
134 videomode_from_timing(dt, &vm);
135 mode = drm_mode_create(connector->dev);
137 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
138 dt->hactive.typ, dt->vactive.typ);
142 drm_display_mode_from_videomode(&vm, mode);
144 mode->type |= DRM_MODE_TYPE_DRIVER;
146 if (panel->desc->num_timings == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
149 drm_mode_probed_add(connector, mode);
156 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
157 struct drm_connector *connector)
159 struct drm_display_mode *mode;
160 unsigned int i, num = 0;
162 for (i = 0; i < panel->desc->num_modes; i++) {
163 const struct drm_display_mode *m = &panel->desc->modes[i];
165 mode = drm_mode_duplicate(connector->dev, m);
167 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
168 m->hdisplay, m->vdisplay,
169 drm_mode_vrefresh(m));
173 mode->type |= DRM_MODE_TYPE_DRIVER;
175 if (panel->desc->num_modes == 1)
176 mode->type |= DRM_MODE_TYPE_PREFERRED;
178 drm_mode_set_name(mode);
180 drm_mode_probed_add(connector, mode);
187 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
188 struct drm_connector *connector)
190 struct drm_display_mode *mode;
191 bool has_override = panel->override_mode.type;
192 unsigned int num = 0;
198 mode = drm_mode_duplicate(connector->dev,
199 &panel->override_mode);
201 drm_mode_probed_add(connector, mode);
204 dev_err(panel->base.dev, "failed to add override mode\n");
208 /* Only add timings if override was not there or failed to validate */
209 if (num == 0 && panel->desc->num_timings)
210 num = panel_simple_get_timings_modes(panel, connector);
213 * Only add fixed modes if timings/override added no mode.
215 * We should only ever have either the display timings specified
216 * or a fixed mode. Anything else is rather bogus.
218 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
220 num = panel_simple_get_display_modes(panel, connector);
222 connector->display_info.bpc = panel->desc->bpc;
223 connector->display_info.width_mm = panel->desc->size.width;
224 connector->display_info.height_mm = panel->desc->size.height;
225 if (panel->desc->bus_format)
226 drm_display_info_set_bus_formats(&connector->display_info,
227 &panel->desc->bus_format, 1);
228 connector->display_info.bus_flags = panel->desc->bus_flags;
233 static int panel_simple_disable(struct drm_panel *panel)
235 struct panel_simple *p = to_panel_simple(panel);
240 if (p->desc->delay.disable)
241 msleep(p->desc->delay.disable);
248 static int panel_simple_unprepare(struct drm_panel *panel)
250 struct panel_simple *p = to_panel_simple(panel);
255 gpiod_set_value_cansleep(p->enable_gpio, 0);
257 regulator_disable(p->supply);
259 if (p->desc->delay.unprepare)
260 msleep(p->desc->delay.unprepare);
267 static int panel_simple_get_hpd_gpio(struct device *dev,
268 struct panel_simple *p, bool from_probe)
272 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
273 if (IS_ERR(p->hpd_gpio)) {
274 err = PTR_ERR(p->hpd_gpio);
277 * If we're called from probe we won't consider '-EPROBE_DEFER'
278 * to be an error--we'll leave the error code in "hpd_gpio".
279 * When we try to use it we'll try again. This allows for
280 * circular dependencies where the component providing the
281 * hpd gpio needs the panel to init before probing.
283 if (err != -EPROBE_DEFER || !from_probe) {
284 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
292 static int panel_simple_prepare(struct drm_panel *panel)
294 struct panel_simple *p = to_panel_simple(panel);
302 err = regulator_enable(p->supply);
304 dev_err(panel->dev, "failed to enable supply: %d\n", err);
308 gpiod_set_value_cansleep(p->enable_gpio, 1);
310 delay = p->desc->delay.prepare;
312 delay += p->desc->delay.hpd_absent_delay;
317 if (IS_ERR(p->hpd_gpio)) {
318 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
323 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
324 hpd_asserted, hpd_asserted,
326 if (hpd_asserted < 0)
331 "error waiting for hpd GPIO: %d\n", err);
341 static int panel_simple_enable(struct drm_panel *panel)
343 struct panel_simple *p = to_panel_simple(panel);
348 if (p->desc->delay.enable)
349 msleep(p->desc->delay.enable);
356 static int panel_simple_get_modes(struct drm_panel *panel,
357 struct drm_connector *connector)
359 struct panel_simple *p = to_panel_simple(panel);
362 /* probe EDID if a DDC bus is available */
364 struct edid *edid = drm_get_edid(connector, p->ddc);
366 drm_connector_update_edid_property(connector, edid);
368 num += drm_add_edid_modes(connector, edid);
373 /* add hard-coded panel modes */
374 num += panel_simple_get_non_edid_modes(p, connector);
376 /* set up connector's "panel orientation" property */
377 drm_connector_set_panel_orientation(connector, p->orientation);
382 static int panel_simple_get_timings(struct drm_panel *panel,
383 unsigned int num_timings,
384 struct display_timing *timings)
386 struct panel_simple *p = to_panel_simple(panel);
389 if (p->desc->num_timings < num_timings)
390 num_timings = p->desc->num_timings;
393 for (i = 0; i < num_timings; i++)
394 timings[i] = p->desc->timings[i];
396 return p->desc->num_timings;
399 static const struct drm_panel_funcs panel_simple_funcs = {
400 .disable = panel_simple_disable,
401 .unprepare = panel_simple_unprepare,
402 .prepare = panel_simple_prepare,
403 .enable = panel_simple_enable,
404 .get_modes = panel_simple_get_modes,
405 .get_timings = panel_simple_get_timings,
408 static struct panel_desc panel_dpi;
410 static int panel_dpi_probe(struct device *dev,
411 struct panel_simple *panel)
413 struct display_timing *timing;
414 const struct device_node *np;
415 struct panel_desc *desc;
416 unsigned int bus_flags;
421 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
425 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
429 ret = of_get_display_timing(np, "panel-timing", timing);
431 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
436 desc->timings = timing;
437 desc->num_timings = 1;
439 of_property_read_u32(np, "width-mm", &desc->size.width);
440 of_property_read_u32(np, "height-mm", &desc->size.height);
442 /* Extract bus_flags from display_timing */
444 vm.flags = timing->flags;
445 drm_bus_flags_from_videomode(&vm, &bus_flags);
446 desc->bus_flags = bus_flags;
448 /* We do not know the connector for the DT node, so guess it */
449 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
456 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
457 (to_check->field.typ >= bounds->field.min && \
458 to_check->field.typ <= bounds->field.max)
459 static void panel_simple_parse_panel_timing_node(struct device *dev,
460 struct panel_simple *panel,
461 const struct display_timing *ot)
463 const struct panel_desc *desc = panel->desc;
467 if (WARN_ON(desc->num_modes)) {
468 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
471 if (WARN_ON(!desc->num_timings)) {
472 dev_err(dev, "Reject override mode: no timings specified\n");
476 for (i = 0; i < panel->desc->num_timings; i++) {
477 const struct display_timing *dt = &panel->desc->timings[i];
479 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
489 if (ot->flags != dt->flags)
492 videomode_from_timing(ot, &vm);
493 drm_display_mode_from_videomode(&vm, &panel->override_mode);
494 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
495 DRM_MODE_TYPE_PREFERRED;
499 if (WARN_ON(!panel->override_mode.type))
500 dev_err(dev, "Reject override mode: No display_timing found\n");
503 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
505 struct panel_simple *panel;
506 struct display_timing dt;
507 struct device_node *ddc;
512 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
516 panel->enabled = false;
517 panel->prepared = false;
520 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
521 if (!panel->no_hpd) {
522 err = panel_simple_get_hpd_gpio(dev, panel, true);
527 panel->supply = devm_regulator_get(dev, "power");
528 if (IS_ERR(panel->supply))
529 return PTR_ERR(panel->supply);
531 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
533 if (IS_ERR(panel->enable_gpio)) {
534 err = PTR_ERR(panel->enable_gpio);
535 if (err != -EPROBE_DEFER)
536 dev_err(dev, "failed to request GPIO: %d\n", err);
540 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
542 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
546 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
548 panel->ddc = of_find_i2c_adapter_by_node(ddc);
552 return -EPROBE_DEFER;
555 if (desc == &panel_dpi) {
556 /* Handle the generic panel-dpi binding */
557 err = panel_dpi_probe(dev, panel);
562 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
563 panel_simple_parse_panel_timing_node(dev, panel, &dt);
566 connector_type = desc->connector_type;
567 /* Catch common mistakes for panels. */
568 switch (connector_type) {
570 dev_warn(dev, "Specify missing connector_type\n");
571 connector_type = DRM_MODE_CONNECTOR_DPI;
573 case DRM_MODE_CONNECTOR_LVDS:
574 WARN_ON(desc->bus_flags &
575 ~(DRM_BUS_FLAG_DE_LOW |
576 DRM_BUS_FLAG_DE_HIGH |
577 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
578 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
579 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
580 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
582 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
584 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
585 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
588 case DRM_MODE_CONNECTOR_eDP:
589 if (desc->bus_format == 0)
590 dev_warn(dev, "Specify missing bus_format\n");
591 if (desc->bpc != 6 && desc->bpc != 8)
592 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
594 case DRM_MODE_CONNECTOR_DSI:
595 if (desc->bpc != 6 && desc->bpc != 8)
596 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
598 case DRM_MODE_CONNECTOR_DPI:
599 bus_flags = DRM_BUS_FLAG_DE_LOW |
600 DRM_BUS_FLAG_DE_HIGH |
601 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
602 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
603 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
604 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
605 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
606 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
607 if (desc->bus_flags & ~bus_flags)
608 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
609 if (!(desc->bus_flags & bus_flags))
610 dev_warn(dev, "Specify missing bus_flags\n");
611 if (desc->bus_format == 0)
612 dev_warn(dev, "Specify missing bus_format\n");
613 if (desc->bpc != 6 && desc->bpc != 8)
614 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
617 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
618 connector_type = DRM_MODE_CONNECTOR_DPI;
622 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
624 err = drm_panel_of_backlight(&panel->base);
628 drm_panel_add(&panel->base);
630 dev_set_drvdata(dev, panel);
636 put_device(&panel->ddc->dev);
641 static int panel_simple_remove(struct device *dev)
643 struct panel_simple *panel = dev_get_drvdata(dev);
645 drm_panel_remove(&panel->base);
646 drm_panel_disable(&panel->base);
647 drm_panel_unprepare(&panel->base);
650 put_device(&panel->ddc->dev);
655 static void panel_simple_shutdown(struct device *dev)
657 struct panel_simple *panel = dev_get_drvdata(dev);
659 drm_panel_disable(&panel->base);
660 drm_panel_unprepare(&panel->base);
663 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
666 .hsync_start = 1280 + 40,
667 .hsync_end = 1280 + 40 + 80,
668 .htotal = 1280 + 40 + 80 + 40,
670 .vsync_start = 800 + 3,
671 .vsync_end = 800 + 3 + 10,
672 .vtotal = 800 + 3 + 10 + 10,
673 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
676 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
677 .modes = &ire_am_1280800n3tzqw_t00h_mode,
684 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
685 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
686 .connector_type = DRM_MODE_CONNECTOR_LVDS,
689 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
692 .hsync_start = 480 + 2,
693 .hsync_end = 480 + 2 + 41,
694 .htotal = 480 + 2 + 41 + 2,
696 .vsync_start = 272 + 2,
697 .vsync_end = 272 + 2 + 10,
698 .vtotal = 272 + 2 + 10 + 2,
699 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
702 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
703 .modes = &ire_am_480272h3tmqw_t01h_mode,
710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
713 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
716 .hsync_start = 800 + 0,
717 .hsync_end = 800 + 0 + 255,
718 .htotal = 800 + 0 + 255 + 0,
720 .vsync_start = 480 + 2,
721 .vsync_end = 480 + 2 + 45,
722 .vtotal = 480 + 2 + 45 + 0,
723 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
726 static const struct panel_desc ampire_am800480r3tmqwa1h = {
727 .modes = &ire_am800480r3tmqwa1h_mode,
734 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
737 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
738 .pixelclock = { 26400000, 33300000, 46800000 },
739 .hactive = { 800, 800, 800 },
740 .hfront_porch = { 16, 210, 354 },
741 .hback_porch = { 45, 36, 6 },
742 .hsync_len = { 1, 10, 40 },
743 .vactive = { 480, 480, 480 },
744 .vfront_porch = { 7, 22, 147 },
745 .vback_porch = { 22, 13, 3 },
746 .vsync_len = { 1, 10, 20 },
747 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
748 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
751 static const struct panel_desc armadeus_st0700_adapt = {
752 .timings = &santek_st0700i5y_rbslw_f_timing,
759 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
760 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
763 static const struct drm_display_mode auo_b101aw03_mode = {
766 .hsync_start = 1024 + 156,
767 .hsync_end = 1024 + 156 + 8,
768 .htotal = 1024 + 156 + 8 + 156,
770 .vsync_start = 600 + 16,
771 .vsync_end = 600 + 16 + 6,
772 .vtotal = 600 + 16 + 6 + 16,
775 static const struct panel_desc auo_b101aw03 = {
776 .modes = &auo_b101aw03_mode,
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
784 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
788 static const struct display_timing auo_b101ean01_timing = {
789 .pixelclock = { 65300000, 72500000, 75000000 },
790 .hactive = { 1280, 1280, 1280 },
791 .hfront_porch = { 18, 119, 119 },
792 .hback_porch = { 21, 21, 21 },
793 .hsync_len = { 32, 32, 32 },
794 .vactive = { 800, 800, 800 },
795 .vfront_porch = { 4, 4, 4 },
796 .vback_porch = { 8, 8, 8 },
797 .vsync_len = { 18, 20, 20 },
800 static const struct panel_desc auo_b101ean01 = {
801 .timings = &auo_b101ean01_timing,
810 static const struct drm_display_mode auo_b101xtn01_mode = {
813 .hsync_start = 1366 + 20,
814 .hsync_end = 1366 + 20 + 70,
815 .htotal = 1366 + 20 + 70,
817 .vsync_start = 768 + 14,
818 .vsync_end = 768 + 14 + 42,
819 .vtotal = 768 + 14 + 42,
820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
823 static const struct panel_desc auo_b101xtn01 = {
824 .modes = &auo_b101xtn01_mode,
833 static const struct drm_display_mode auo_b116xak01_mode = {
836 .hsync_start = 1366 + 48,
837 .hsync_end = 1366 + 48 + 32,
838 .htotal = 1366 + 48 + 32 + 10,
840 .vsync_start = 768 + 4,
841 .vsync_end = 768 + 4 + 6,
842 .vtotal = 768 + 4 + 6 + 15,
843 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
846 static const struct panel_desc auo_b116xak01 = {
847 .modes = &auo_b116xak01_mode,
855 .hpd_absent_delay = 200,
857 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
858 .connector_type = DRM_MODE_CONNECTOR_eDP,
861 static const struct drm_display_mode auo_b116xw03_mode = {
864 .hsync_start = 1366 + 40,
865 .hsync_end = 1366 + 40 + 40,
866 .htotal = 1366 + 40 + 40 + 32,
868 .vsync_start = 768 + 10,
869 .vsync_end = 768 + 10 + 12,
870 .vtotal = 768 + 10 + 12 + 6,
871 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
874 static const struct panel_desc auo_b116xw03 = {
875 .modes = &auo_b116xw03_mode,
885 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
887 .connector_type = DRM_MODE_CONNECTOR_eDP,
890 static const struct drm_display_mode auo_b133xtn01_mode = {
893 .hsync_start = 1366 + 48,
894 .hsync_end = 1366 + 48 + 32,
895 .htotal = 1366 + 48 + 32 + 20,
897 .vsync_start = 768 + 3,
898 .vsync_end = 768 + 3 + 6,
899 .vtotal = 768 + 3 + 6 + 13,
902 static const struct panel_desc auo_b133xtn01 = {
903 .modes = &auo_b133xtn01_mode,
912 static const struct drm_display_mode auo_b133htn01_mode = {
915 .hsync_start = 1920 + 172,
916 .hsync_end = 1920 + 172 + 80,
917 .htotal = 1920 + 172 + 80 + 60,
919 .vsync_start = 1080 + 25,
920 .vsync_end = 1080 + 25 + 10,
921 .vtotal = 1080 + 25 + 10 + 10,
924 static const struct panel_desc auo_b133htn01 = {
925 .modes = &auo_b133htn01_mode,
939 static const struct display_timing auo_g070vvn01_timings = {
940 .pixelclock = { 33300000, 34209000, 45000000 },
941 .hactive = { 800, 800, 800 },
942 .hfront_porch = { 20, 40, 200 },
943 .hback_porch = { 87, 40, 1 },
944 .hsync_len = { 1, 48, 87 },
945 .vactive = { 480, 480, 480 },
946 .vfront_porch = { 5, 13, 200 },
947 .vback_porch = { 31, 31, 29 },
948 .vsync_len = { 1, 1, 3 },
951 static const struct panel_desc auo_g070vvn01 = {
952 .timings = &auo_g070vvn01_timings,
967 static const struct drm_display_mode auo_g101evn010_mode = {
970 .hsync_start = 1280 + 82,
971 .hsync_end = 1280 + 82 + 2,
972 .htotal = 1280 + 82 + 2 + 84,
974 .vsync_start = 800 + 8,
975 .vsync_end = 800 + 8 + 2,
976 .vtotal = 800 + 8 + 2 + 6,
979 static const struct panel_desc auo_g101evn010 = {
980 .modes = &auo_g101evn010_mode,
987 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
988 .connector_type = DRM_MODE_CONNECTOR_LVDS,
991 static const struct drm_display_mode auo_g104sn02_mode = {
994 .hsync_start = 800 + 40,
995 .hsync_end = 800 + 40 + 216,
996 .htotal = 800 + 40 + 216 + 128,
998 .vsync_start = 600 + 10,
999 .vsync_end = 600 + 10 + 35,
1000 .vtotal = 600 + 10 + 35 + 2,
1003 static const struct panel_desc auo_g104sn02 = {
1004 .modes = &auo_g104sn02_mode,
1013 static const struct drm_display_mode auo_g121ean01_mode = {
1016 .hsync_start = 1280 + 58,
1017 .hsync_end = 1280 + 58 + 8,
1018 .htotal = 1280 + 58 + 8 + 70,
1020 .vsync_start = 800 + 6,
1021 .vsync_end = 800 + 6 + 4,
1022 .vtotal = 800 + 6 + 4 + 10,
1025 static const struct panel_desc auo_g121ean01 = {
1026 .modes = &auo_g121ean01_mode,
1033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1034 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1037 static const struct display_timing auo_g133han01_timings = {
1038 .pixelclock = { 134000000, 141200000, 149000000 },
1039 .hactive = { 1920, 1920, 1920 },
1040 .hfront_porch = { 39, 58, 77 },
1041 .hback_porch = { 59, 88, 117 },
1042 .hsync_len = { 28, 42, 56 },
1043 .vactive = { 1080, 1080, 1080 },
1044 .vfront_porch = { 3, 8, 11 },
1045 .vback_porch = { 5, 14, 19 },
1046 .vsync_len = { 4, 14, 19 },
1049 static const struct panel_desc auo_g133han01 = {
1050 .timings = &auo_g133han01_timings,
1063 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1064 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1067 static const struct drm_display_mode auo_g156xtn01_mode = {
1070 .hsync_start = 1366 + 33,
1071 .hsync_end = 1366 + 33 + 67,
1074 .vsync_start = 768 + 4,
1075 .vsync_end = 768 + 4 + 4,
1079 static const struct panel_desc auo_g156xtn01 = {
1080 .modes = &auo_g156xtn01_mode,
1087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1088 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1091 static const struct display_timing auo_g185han01_timings = {
1092 .pixelclock = { 120000000, 144000000, 175000000 },
1093 .hactive = { 1920, 1920, 1920 },
1094 .hfront_porch = { 36, 120, 148 },
1095 .hback_porch = { 24, 88, 108 },
1096 .hsync_len = { 20, 48, 64 },
1097 .vactive = { 1080, 1080, 1080 },
1098 .vfront_porch = { 6, 10, 40 },
1099 .vback_porch = { 2, 5, 20 },
1100 .vsync_len = { 2, 5, 20 },
1103 static const struct panel_desc auo_g185han01 = {
1104 .timings = &auo_g185han01_timings,
1117 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1118 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1121 static const struct display_timing auo_g190ean01_timings = {
1122 .pixelclock = { 90000000, 108000000, 135000000 },
1123 .hactive = { 1280, 1280, 1280 },
1124 .hfront_porch = { 126, 184, 1266 },
1125 .hback_porch = { 84, 122, 844 },
1126 .hsync_len = { 70, 102, 704 },
1127 .vactive = { 1024, 1024, 1024 },
1128 .vfront_porch = { 4, 26, 76 },
1129 .vback_porch = { 2, 8, 25 },
1130 .vsync_len = { 2, 8, 25 },
1133 static const struct panel_desc auo_g190ean01 = {
1134 .timings = &auo_g190ean01_timings,
1147 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1148 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1151 static const struct display_timing auo_p320hvn03_timings = {
1152 .pixelclock = { 106000000, 148500000, 164000000 },
1153 .hactive = { 1920, 1920, 1920 },
1154 .hfront_porch = { 25, 50, 130 },
1155 .hback_porch = { 25, 50, 130 },
1156 .hsync_len = { 20, 40, 105 },
1157 .vactive = { 1080, 1080, 1080 },
1158 .vfront_porch = { 8, 17, 150 },
1159 .vback_porch = { 8, 17, 150 },
1160 .vsync_len = { 4, 11, 100 },
1163 static const struct panel_desc auo_p320hvn03 = {
1164 .timings = &auo_p320hvn03_timings,
1176 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1177 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1180 static const struct drm_display_mode auo_t215hvn01_mode = {
1183 .hsync_start = 1920 + 88,
1184 .hsync_end = 1920 + 88 + 44,
1185 .htotal = 1920 + 88 + 44 + 148,
1187 .vsync_start = 1080 + 4,
1188 .vsync_end = 1080 + 4 + 5,
1189 .vtotal = 1080 + 4 + 5 + 36,
1192 static const struct panel_desc auo_t215hvn01 = {
1193 .modes = &auo_t215hvn01_mode,
1206 static const struct drm_display_mode avic_tm070ddh03_mode = {
1209 .hsync_start = 1024 + 160,
1210 .hsync_end = 1024 + 160 + 4,
1211 .htotal = 1024 + 160 + 4 + 156,
1213 .vsync_start = 600 + 17,
1214 .vsync_end = 600 + 17 + 1,
1215 .vtotal = 600 + 17 + 1 + 17,
1218 static const struct panel_desc avic_tm070ddh03 = {
1219 .modes = &avic_tm070ddh03_mode,
1233 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1236 .hsync_start = 800 + 40,
1237 .hsync_end = 800 + 40 + 48,
1238 .htotal = 800 + 40 + 48 + 40,
1240 .vsync_start = 480 + 13,
1241 .vsync_end = 480 + 13 + 3,
1242 .vtotal = 480 + 13 + 3 + 29,
1245 static const struct panel_desc bananapi_s070wv20_ct16 = {
1246 .modes = &bananapi_s070wv20_ct16_mode,
1255 static const struct drm_display_mode boe_hv070wsa_mode = {
1258 .hsync_start = 1024 + 30,
1259 .hsync_end = 1024 + 30 + 30,
1260 .htotal = 1024 + 30 + 30 + 30,
1262 .vsync_start = 600 + 10,
1263 .vsync_end = 600 + 10 + 10,
1264 .vtotal = 600 + 10 + 10 + 10,
1267 static const struct panel_desc boe_hv070wsa = {
1268 .modes = &boe_hv070wsa_mode,
1275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1276 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1277 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1280 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1284 .hsync_start = 1280 + 48,
1285 .hsync_end = 1280 + 48 + 32,
1286 .htotal = 1280 + 48 + 32 + 80,
1288 .vsync_start = 800 + 3,
1289 .vsync_end = 800 + 3 + 5,
1290 .vtotal = 800 + 3 + 5 + 24,
1295 .hsync_start = 1280 + 48,
1296 .hsync_end = 1280 + 48 + 32,
1297 .htotal = 1280 + 48 + 32 + 80,
1299 .vsync_start = 800 + 3,
1300 .vsync_end = 800 + 3 + 5,
1301 .vtotal = 800 + 3 + 5 + 24,
1305 static const struct panel_desc boe_nv101wxmn51 = {
1306 .modes = boe_nv101wxmn51_modes,
1307 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1320 /* Also used for boe_nv133fhm_n62 */
1321 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1324 .hsync_start = 1920 + 48,
1325 .hsync_end = 1920 + 48 + 32,
1326 .htotal = 1920 + 48 + 32 + 200,
1328 .vsync_start = 1080 + 3,
1329 .vsync_end = 1080 + 3 + 6,
1330 .vtotal = 1080 + 3 + 6 + 31,
1331 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1334 /* Also used for boe_nv133fhm_n62 */
1335 static const struct panel_desc boe_nv133fhm_n61 = {
1336 .modes = &boe_nv133fhm_n61_modes,
1345 * When power is first given to the panel there's a short
1346 * spike on the HPD line. It was explained that this spike
1347 * was until the TCON data download was complete. On
1348 * one system this was measured at 8 ms. We'll put 15 ms
1349 * in the prepare delay just to be safe and take it away
1350 * from the hpd_absent_delay (which would otherwise be 200 ms)
1351 * to handle this. That means:
1352 * - If HPD isn't hooked up you still have 200 ms delay.
1353 * - If HPD is hooked up we won't try to look at it for the
1357 .hpd_absent_delay = 185,
1361 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1362 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1363 .connector_type = DRM_MODE_CONNECTOR_eDP,
1366 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1370 .hsync_start = 1920 + 48,
1371 .hsync_end = 1920 + 48 + 32,
1374 .vsync_start = 1080 + 3,
1375 .vsync_end = 1080 + 3 + 5,
1380 static const struct panel_desc boe_nv140fhmn49 = {
1381 .modes = boe_nv140fhmn49_modes,
1382 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1393 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1394 .connector_type = DRM_MODE_CONNECTOR_eDP,
1397 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1400 .hsync_start = 480 + 5,
1401 .hsync_end = 480 + 5 + 5,
1402 .htotal = 480 + 5 + 5 + 40,
1404 .vsync_start = 272 + 8,
1405 .vsync_end = 272 + 8 + 8,
1406 .vtotal = 272 + 8 + 8 + 8,
1407 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1410 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1411 .modes = &cdtech_s043wq26h_ct7_mode,
1418 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1421 /* S070PWS19HP-FC21 2017/04/22 */
1422 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1425 .hsync_start = 1024 + 160,
1426 .hsync_end = 1024 + 160 + 20,
1427 .htotal = 1024 + 160 + 20 + 140,
1429 .vsync_start = 600 + 12,
1430 .vsync_end = 600 + 12 + 3,
1431 .vtotal = 600 + 12 + 3 + 20,
1432 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1435 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1436 .modes = &cdtech_s070pws19hp_fc21_mode,
1443 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1444 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1445 .connector_type = DRM_MODE_CONNECTOR_DPI,
1448 /* S070SWV29HG-DC44 2017/09/21 */
1449 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1452 .hsync_start = 800 + 210,
1453 .hsync_end = 800 + 210 + 2,
1454 .htotal = 800 + 210 + 2 + 44,
1456 .vsync_start = 480 + 22,
1457 .vsync_end = 480 + 22 + 2,
1458 .vtotal = 480 + 22 + 2 + 21,
1459 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1462 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1463 .modes = &cdtech_s070swv29hg_dc44_mode,
1470 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1472 .connector_type = DRM_MODE_CONNECTOR_DPI,
1475 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1478 .hsync_start = 800 + 40,
1479 .hsync_end = 800 + 40 + 40,
1480 .htotal = 800 + 40 + 40 + 48,
1482 .vsync_start = 480 + 29,
1483 .vsync_end = 480 + 29 + 13,
1484 .vtotal = 480 + 29 + 13 + 3,
1485 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1488 static const struct panel_desc cdtech_s070wv95_ct16 = {
1489 .modes = &cdtech_s070wv95_ct16_mode,
1498 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1499 .pixelclock = { 68900000, 71100000, 73400000 },
1500 .hactive = { 1280, 1280, 1280 },
1501 .hfront_porch = { 65, 80, 95 },
1502 .hback_porch = { 64, 79, 94 },
1503 .hsync_len = { 1, 1, 1 },
1504 .vactive = { 800, 800, 800 },
1505 .vfront_porch = { 7, 11, 14 },
1506 .vback_porch = { 7, 11, 14 },
1507 .vsync_len = { 1, 1, 1 },
1508 .flags = DISPLAY_FLAGS_DE_HIGH,
1511 static const struct panel_desc chefree_ch101olhlwh_002 = {
1512 .timings = &chefree_ch101olhlwh_002_timing,
1523 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1525 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1528 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1531 .hsync_start = 800 + 49,
1532 .hsync_end = 800 + 49 + 33,
1533 .htotal = 800 + 49 + 33 + 17,
1535 .vsync_start = 1280 + 1,
1536 .vsync_end = 1280 + 1 + 7,
1537 .vtotal = 1280 + 1 + 7 + 15,
1538 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1541 static const struct panel_desc chunghwa_claa070wp03xg = {
1542 .modes = &chunghwa_claa070wp03xg_mode,
1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1550 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1551 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1554 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1557 .hsync_start = 1366 + 58,
1558 .hsync_end = 1366 + 58 + 58,
1559 .htotal = 1366 + 58 + 58 + 58,
1561 .vsync_start = 768 + 4,
1562 .vsync_end = 768 + 4 + 4,
1563 .vtotal = 768 + 4 + 4 + 4,
1566 static const struct panel_desc chunghwa_claa101wa01a = {
1567 .modes = &chunghwa_claa101wa01a_mode,
1574 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1575 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1576 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1579 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1582 .hsync_start = 1366 + 48,
1583 .hsync_end = 1366 + 48 + 32,
1584 .htotal = 1366 + 48 + 32 + 20,
1586 .vsync_start = 768 + 16,
1587 .vsync_end = 768 + 16 + 8,
1588 .vtotal = 768 + 16 + 8 + 16,
1591 static const struct panel_desc chunghwa_claa101wb01 = {
1592 .modes = &chunghwa_claa101wb01_mode,
1599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1600 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1601 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1604 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1607 .hsync_start = 800 + 40,
1608 .hsync_end = 800 + 40 + 128,
1609 .htotal = 800 + 40 + 128 + 88,
1611 .vsync_start = 480 + 10,
1612 .vsync_end = 480 + 10 + 2,
1613 .vtotal = 480 + 10 + 2 + 33,
1614 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1617 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1618 .modes = &dataimage_scf0700c48ggu18_mode,
1625 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1626 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1629 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1630 .pixelclock = { 45000000, 51200000, 57000000 },
1631 .hactive = { 1024, 1024, 1024 },
1632 .hfront_porch = { 100, 106, 113 },
1633 .hback_porch = { 100, 106, 113 },
1634 .hsync_len = { 100, 108, 114 },
1635 .vactive = { 600, 600, 600 },
1636 .vfront_porch = { 8, 11, 15 },
1637 .vback_porch = { 8, 11, 15 },
1638 .vsync_len = { 9, 13, 15 },
1639 .flags = DISPLAY_FLAGS_DE_HIGH,
1642 static const struct panel_desc dlc_dlc0700yzg_1 = {
1643 .timings = &dlc_dlc0700yzg_1_timing,
1655 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1656 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1659 static const struct display_timing dlc_dlc1010gig_timing = {
1660 .pixelclock = { 68900000, 71100000, 73400000 },
1661 .hactive = { 1280, 1280, 1280 },
1662 .hfront_porch = { 43, 53, 63 },
1663 .hback_porch = { 43, 53, 63 },
1664 .hsync_len = { 44, 54, 64 },
1665 .vactive = { 800, 800, 800 },
1666 .vfront_porch = { 5, 8, 11 },
1667 .vback_porch = { 5, 8, 11 },
1668 .vsync_len = { 5, 7, 11 },
1669 .flags = DISPLAY_FLAGS_DE_HIGH,
1672 static const struct panel_desc dlc_dlc1010gig = {
1673 .timings = &dlc_dlc1010gig_timing,
1686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1687 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1690 static const struct drm_display_mode edt_et035012dm6_mode = {
1693 .hsync_start = 320 + 20,
1694 .hsync_end = 320 + 20 + 30,
1695 .htotal = 320 + 20 + 68,
1697 .vsync_start = 240 + 4,
1698 .vsync_end = 240 + 4 + 4,
1699 .vtotal = 240 + 4 + 4 + 14,
1700 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1703 static const struct panel_desc edt_et035012dm6 = {
1704 .modes = &edt_et035012dm6_mode,
1711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1712 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1715 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1718 .hsync_start = 480 + 8,
1719 .hsync_end = 480 + 8 + 4,
1720 .htotal = 480 + 8 + 4 + 41,
1723 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1728 .vsync_start = 288 + 2,
1729 .vsync_end = 288 + 2 + 4,
1730 .vtotal = 288 + 2 + 4 + 10,
1733 static const struct panel_desc edt_etm043080dh6gp = {
1734 .modes = &edt_etm043080dh6gp_mode,
1741 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1742 .connector_type = DRM_MODE_CONNECTOR_DPI,
1745 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1748 .hsync_start = 480 + 2,
1749 .hsync_end = 480 + 2 + 41,
1750 .htotal = 480 + 2 + 41 + 2,
1752 .vsync_start = 272 + 2,
1753 .vsync_end = 272 + 2 + 10,
1754 .vtotal = 272 + 2 + 10 + 2,
1755 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1758 static const struct panel_desc edt_etm0430g0dh6 = {
1759 .modes = &edt_etm0430g0dh6_mode,
1768 static const struct drm_display_mode edt_et057090dhu_mode = {
1771 .hsync_start = 640 + 16,
1772 .hsync_end = 640 + 16 + 30,
1773 .htotal = 640 + 16 + 30 + 114,
1775 .vsync_start = 480 + 10,
1776 .vsync_end = 480 + 10 + 3,
1777 .vtotal = 480 + 10 + 3 + 32,
1778 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1781 static const struct panel_desc edt_et057090dhu = {
1782 .modes = &edt_et057090dhu_mode,
1789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1791 .connector_type = DRM_MODE_CONNECTOR_DPI,
1794 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1797 .hsync_start = 800 + 40,
1798 .hsync_end = 800 + 40 + 128,
1799 .htotal = 800 + 40 + 128 + 88,
1801 .vsync_start = 480 + 10,
1802 .vsync_end = 480 + 10 + 2,
1803 .vtotal = 480 + 10 + 2 + 33,
1804 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1807 static const struct panel_desc edt_etm0700g0dh6 = {
1808 .modes = &edt_etm0700g0dh6_mode,
1815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1819 static const struct panel_desc edt_etm0700g0bdh6 = {
1820 .modes = &edt_etm0700g0dh6_mode,
1827 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1831 static const struct display_timing evervision_vgg804821_timing = {
1832 .pixelclock = { 27600000, 33300000, 50000000 },
1833 .hactive = { 800, 800, 800 },
1834 .hfront_porch = { 40, 66, 70 },
1835 .hback_porch = { 40, 67, 70 },
1836 .hsync_len = { 40, 67, 70 },
1837 .vactive = { 480, 480, 480 },
1838 .vfront_porch = { 6, 10, 10 },
1839 .vback_porch = { 7, 11, 11 },
1840 .vsync_len = { 7, 11, 11 },
1841 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1842 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1843 DISPLAY_FLAGS_SYNC_NEGEDGE,
1846 static const struct panel_desc evervision_vgg804821 = {
1847 .timings = &evervision_vgg804821_timing,
1854 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1855 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1858 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1861 .hsync_start = 800 + 168,
1862 .hsync_end = 800 + 168 + 64,
1863 .htotal = 800 + 168 + 64 + 88,
1865 .vsync_start = 480 + 37,
1866 .vsync_end = 480 + 37 + 2,
1867 .vtotal = 480 + 37 + 2 + 8,
1870 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1871 .modes = &foxlink_fl500wvr00_a0t_mode,
1878 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1881 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1885 .hsync_start = 320 + 44,
1886 .hsync_end = 320 + 44 + 16,
1887 .htotal = 320 + 44 + 16 + 20,
1889 .vsync_start = 240 + 2,
1890 .vsync_end = 240 + 2 + 6,
1891 .vtotal = 240 + 2 + 6 + 2,
1892 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1897 .hsync_start = 320 + 56,
1898 .hsync_end = 320 + 56 + 16,
1899 .htotal = 320 + 56 + 16 + 40,
1901 .vsync_start = 240 + 2,
1902 .vsync_end = 240 + 2 + 6,
1903 .vtotal = 240 + 2 + 6 + 2,
1904 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1908 static const struct panel_desc frida_frd350h54004 = {
1909 .modes = frida_frd350h54004_modes,
1910 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1918 .connector_type = DRM_MODE_CONNECTOR_DPI,
1921 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1924 .hsync_start = 800 + 20,
1925 .hsync_end = 800 + 20 + 24,
1926 .htotal = 800 + 20 + 24 + 20,
1928 .vsync_start = 1280 + 4,
1929 .vsync_end = 1280 + 4 + 8,
1930 .vtotal = 1280 + 4 + 8 + 4,
1931 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1934 static const struct panel_desc friendlyarm_hd702e = {
1935 .modes = &friendlyarm_hd702e_mode,
1943 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1946 .hsync_start = 480 + 5,
1947 .hsync_end = 480 + 5 + 1,
1948 .htotal = 480 + 5 + 1 + 40,
1950 .vsync_start = 272 + 8,
1951 .vsync_end = 272 + 8 + 1,
1952 .vtotal = 272 + 8 + 1 + 8,
1955 static const struct panel_desc giantplus_gpg482739qs5 = {
1956 .modes = &giantplus_gpg482739qs5_mode,
1963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1966 static const struct display_timing giantplus_gpm940b0_timing = {
1967 .pixelclock = { 13500000, 27000000, 27500000 },
1968 .hactive = { 320, 320, 320 },
1969 .hfront_porch = { 14, 686, 718 },
1970 .hback_porch = { 50, 70, 255 },
1971 .hsync_len = { 1, 1, 1 },
1972 .vactive = { 240, 240, 240 },
1973 .vfront_porch = { 1, 1, 179 },
1974 .vback_porch = { 1, 21, 31 },
1975 .vsync_len = { 1, 1, 6 },
1976 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1979 static const struct panel_desc giantplus_gpm940b0 = {
1980 .timings = &giantplus_gpm940b0_timing,
1987 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1988 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1991 static const struct display_timing hannstar_hsd070pww1_timing = {
1992 .pixelclock = { 64300000, 71100000, 82000000 },
1993 .hactive = { 1280, 1280, 1280 },
1994 .hfront_porch = { 1, 1, 10 },
1995 .hback_porch = { 1, 1, 10 },
1997 * According to the data sheet, the minimum horizontal blanking interval
1998 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1999 * minimum working horizontal blanking interval to be 60 clocks.
2001 .hsync_len = { 58, 158, 661 },
2002 .vactive = { 800, 800, 800 },
2003 .vfront_porch = { 1, 1, 10 },
2004 .vback_porch = { 1, 1, 10 },
2005 .vsync_len = { 1, 21, 203 },
2006 .flags = DISPLAY_FLAGS_DE_HIGH,
2009 static const struct panel_desc hannstar_hsd070pww1 = {
2010 .timings = &hannstar_hsd070pww1_timing,
2017 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2018 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2021 static const struct display_timing hannstar_hsd100pxn1_timing = {
2022 .pixelclock = { 55000000, 65000000, 75000000 },
2023 .hactive = { 1024, 1024, 1024 },
2024 .hfront_porch = { 40, 40, 40 },
2025 .hback_porch = { 220, 220, 220 },
2026 .hsync_len = { 20, 60, 100 },
2027 .vactive = { 768, 768, 768 },
2028 .vfront_porch = { 7, 7, 7 },
2029 .vback_porch = { 21, 21, 21 },
2030 .vsync_len = { 10, 10, 10 },
2031 .flags = DISPLAY_FLAGS_DE_HIGH,
2034 static const struct panel_desc hannstar_hsd100pxn1 = {
2035 .timings = &hannstar_hsd100pxn1_timing,
2042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2043 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2046 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2049 .hsync_start = 800 + 85,
2050 .hsync_end = 800 + 85 + 86,
2051 .htotal = 800 + 85 + 86 + 85,
2053 .vsync_start = 480 + 16,
2054 .vsync_end = 480 + 16 + 13,
2055 .vtotal = 480 + 16 + 13 + 16,
2058 static const struct panel_desc hitachi_tx23d38vm0caa = {
2059 .modes = &hitachi_tx23d38vm0caa_mode,
2072 static const struct drm_display_mode innolux_at043tn24_mode = {
2075 .hsync_start = 480 + 2,
2076 .hsync_end = 480 + 2 + 41,
2077 .htotal = 480 + 2 + 41 + 2,
2079 .vsync_start = 272 + 2,
2080 .vsync_end = 272 + 2 + 10,
2081 .vtotal = 272 + 2 + 10 + 2,
2082 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2085 static const struct panel_desc innolux_at043tn24 = {
2086 .modes = &innolux_at043tn24_mode,
2093 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2094 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2097 static const struct drm_display_mode innolux_at070tn92_mode = {
2100 .hsync_start = 800 + 210,
2101 .hsync_end = 800 + 210 + 20,
2102 .htotal = 800 + 210 + 20 + 46,
2104 .vsync_start = 480 + 22,
2105 .vsync_end = 480 + 22 + 10,
2106 .vtotal = 480 + 22 + 23 + 10,
2109 static const struct panel_desc innolux_at070tn92 = {
2110 .modes = &innolux_at070tn92_mode,
2116 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2119 static const struct display_timing innolux_g070y2_l01_timing = {
2120 .pixelclock = { 28000000, 29500000, 32000000 },
2121 .hactive = { 800, 800, 800 },
2122 .hfront_porch = { 61, 91, 141 },
2123 .hback_porch = { 60, 90, 140 },
2124 .hsync_len = { 12, 12, 12 },
2125 .vactive = { 480, 480, 480 },
2126 .vfront_porch = { 4, 9, 30 },
2127 .vback_porch = { 4, 8, 28 },
2128 .vsync_len = { 2, 2, 2 },
2129 .flags = DISPLAY_FLAGS_DE_HIGH,
2132 static const struct panel_desc innolux_g070y2_l01 = {
2133 .timings = &innolux_g070y2_l01_timing,
2146 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2147 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2148 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2151 static const struct display_timing innolux_g101ice_l01_timing = {
2152 .pixelclock = { 60400000, 71100000, 74700000 },
2153 .hactive = { 1280, 1280, 1280 },
2154 .hfront_porch = { 41, 80, 100 },
2155 .hback_porch = { 40, 79, 99 },
2156 .hsync_len = { 1, 1, 1 },
2157 .vactive = { 800, 800, 800 },
2158 .vfront_porch = { 5, 11, 14 },
2159 .vback_porch = { 4, 11, 14 },
2160 .vsync_len = { 1, 1, 1 },
2161 .flags = DISPLAY_FLAGS_DE_HIGH,
2164 static const struct panel_desc innolux_g101ice_l01 = {
2165 .timings = &innolux_g101ice_l01_timing,
2176 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2177 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2180 static const struct display_timing innolux_g121i1_l01_timing = {
2181 .pixelclock = { 67450000, 71000000, 74550000 },
2182 .hactive = { 1280, 1280, 1280 },
2183 .hfront_porch = { 40, 80, 160 },
2184 .hback_porch = { 39, 79, 159 },
2185 .hsync_len = { 1, 1, 1 },
2186 .vactive = { 800, 800, 800 },
2187 .vfront_porch = { 5, 11, 100 },
2188 .vback_porch = { 4, 11, 99 },
2189 .vsync_len = { 1, 1, 1 },
2192 static const struct panel_desc innolux_g121i1_l01 = {
2193 .timings = &innolux_g121i1_l01_timing,
2204 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2205 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2208 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2211 .hsync_start = 1024 + 0,
2212 .hsync_end = 1024 + 1,
2213 .htotal = 1024 + 0 + 1 + 320,
2215 .vsync_start = 768 + 38,
2216 .vsync_end = 768 + 38 + 1,
2217 .vtotal = 768 + 38 + 1 + 0,
2218 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2221 static const struct panel_desc innolux_g121x1_l03 = {
2222 .modes = &innolux_g121x1_l03_mode,
2237 * Datasheet specifies that at 60 Hz refresh rate:
2238 * - total horizontal time: { 1506, 1592, 1716 }
2239 * - total vertical time: { 788, 800, 868 }
2241 * ...but doesn't go into exactly how that should be split into a front
2242 * porch, back porch, or sync length. For now we'll leave a single setting
2243 * here which allows a bit of tweaking of the pixel clock at the expense of
2246 static const struct display_timing innolux_n116bge_timing = {
2247 .pixelclock = { 72600000, 76420000, 80240000 },
2248 .hactive = { 1366, 1366, 1366 },
2249 .hfront_porch = { 136, 136, 136 },
2250 .hback_porch = { 60, 60, 60 },
2251 .hsync_len = { 30, 30, 30 },
2252 .vactive = { 768, 768, 768 },
2253 .vfront_porch = { 8, 8, 8 },
2254 .vback_porch = { 12, 12, 12 },
2255 .vsync_len = { 12, 12, 12 },
2256 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2259 static const struct panel_desc innolux_n116bge = {
2260 .timings = &innolux_n116bge_timing,
2269 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2272 .hsync_start = 1366 + 16,
2273 .hsync_end = 1366 + 16 + 34,
2274 .htotal = 1366 + 16 + 34 + 50,
2276 .vsync_start = 768 + 2,
2277 .vsync_end = 768 + 2 + 6,
2278 .vtotal = 768 + 2 + 6 + 12,
2281 static const struct panel_desc innolux_n156bge_l21 = {
2282 .modes = &innolux_n156bge_l21_mode,
2289 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2290 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2291 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2294 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2297 .hsync_start = 2160 + 48,
2298 .hsync_end = 2160 + 48 + 32,
2299 .htotal = 2160 + 48 + 32 + 80,
2301 .vsync_start = 1440 + 3,
2302 .vsync_end = 1440 + 3 + 10,
2303 .vtotal = 1440 + 3 + 10 + 27,
2304 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2307 static const struct panel_desc innolux_p120zdg_bf1 = {
2308 .modes = &innolux_p120zdg_bf1_mode,
2316 .hpd_absent_delay = 200,
2321 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2324 .hsync_start = 1024 + 128,
2325 .hsync_end = 1024 + 128 + 64,
2326 .htotal = 1024 + 128 + 64 + 128,
2328 .vsync_start = 600 + 16,
2329 .vsync_end = 600 + 16 + 4,
2330 .vtotal = 600 + 16 + 4 + 16,
2333 static const struct panel_desc innolux_zj070na_01p = {
2334 .modes = &innolux_zj070na_01p_mode,
2343 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2346 .hsync_start = 1920 + 24,
2347 .hsync_end = 1920 + 24 + 48,
2348 .htotal = 1920 + 24 + 48 + 88,
2350 .vsync_start = 1080 + 3,
2351 .vsync_end = 1080 + 3 + 12,
2352 .vtotal = 1080 + 3 + 12 + 17,
2353 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2356 static const struct panel_desc ivo_m133nwf4_r0 = {
2357 .modes = &ivo_m133nwf4_r0_mode,
2365 .hpd_absent_delay = 200,
2368 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2369 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2370 .connector_type = DRM_MODE_CONNECTOR_eDP,
2373 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2376 .hsync_start = 1366 + 40,
2377 .hsync_end = 1366 + 40 + 32,
2378 .htotal = 1366 + 40 + 32 + 62,
2380 .vsync_start = 768 + 5,
2381 .vsync_end = 768 + 5 + 5,
2382 .vtotal = 768 + 5 + 5 + 122,
2383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2386 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2387 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2395 .hpd_absent_delay = 200,
2397 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2398 .connector_type = DRM_MODE_CONNECTOR_eDP,
2401 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2402 .pixelclock = { 5580000, 5850000, 6200000 },
2403 .hactive = { 320, 320, 320 },
2404 .hfront_porch = { 30, 30, 30 },
2405 .hback_porch = { 30, 30, 30 },
2406 .hsync_len = { 1, 5, 17 },
2407 .vactive = { 240, 240, 240 },
2408 .vfront_porch = { 6, 6, 6 },
2409 .vback_porch = { 5, 5, 5 },
2410 .vsync_len = { 1, 2, 11 },
2411 .flags = DISPLAY_FLAGS_DE_HIGH,
2414 static const struct panel_desc koe_tx14d24vm1bpa = {
2415 .timings = &koe_tx14d24vm1bpa_timing,
2424 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2425 .pixelclock = { 151820000, 156720000, 159780000 },
2426 .hactive = { 1920, 1920, 1920 },
2427 .hfront_porch = { 105, 130, 142 },
2428 .hback_porch = { 45, 70, 82 },
2429 .hsync_len = { 30, 30, 30 },
2430 .vactive = { 1200, 1200, 1200},
2431 .vfront_porch = { 3, 5, 10 },
2432 .vback_porch = { 2, 5, 10 },
2433 .vsync_len = { 5, 5, 5 },
2436 static const struct panel_desc koe_tx26d202vm0bwa = {
2437 .timings = &koe_tx26d202vm0bwa_timing,
2450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2451 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2452 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2455 static const struct display_timing koe_tx31d200vm0baa_timing = {
2456 .pixelclock = { 39600000, 43200000, 48000000 },
2457 .hactive = { 1280, 1280, 1280 },
2458 .hfront_porch = { 16, 36, 56 },
2459 .hback_porch = { 16, 36, 56 },
2460 .hsync_len = { 8, 8, 8 },
2461 .vactive = { 480, 480, 480 },
2462 .vfront_porch = { 6, 21, 33 },
2463 .vback_porch = { 6, 21, 33 },
2464 .vsync_len = { 8, 8, 8 },
2465 .flags = DISPLAY_FLAGS_DE_HIGH,
2468 static const struct panel_desc koe_tx31d200vm0baa = {
2469 .timings = &koe_tx31d200vm0baa_timing,
2476 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2477 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2480 static const struct display_timing kyo_tcg121xglp_timing = {
2481 .pixelclock = { 52000000, 65000000, 71000000 },
2482 .hactive = { 1024, 1024, 1024 },
2483 .hfront_porch = { 2, 2, 2 },
2484 .hback_porch = { 2, 2, 2 },
2485 .hsync_len = { 86, 124, 244 },
2486 .vactive = { 768, 768, 768 },
2487 .vfront_porch = { 2, 2, 2 },
2488 .vback_porch = { 2, 2, 2 },
2489 .vsync_len = { 6, 34, 73 },
2490 .flags = DISPLAY_FLAGS_DE_HIGH,
2493 static const struct panel_desc kyo_tcg121xglp = {
2494 .timings = &kyo_tcg121xglp_timing,
2501 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2502 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2505 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2508 .hsync_start = 320 + 20,
2509 .hsync_end = 320 + 20 + 30,
2510 .htotal = 320 + 20 + 30 + 38,
2512 .vsync_start = 240 + 4,
2513 .vsync_end = 240 + 4 + 3,
2514 .vtotal = 240 + 4 + 3 + 15,
2517 static const struct panel_desc lemaker_bl035_rgb_002 = {
2518 .modes = &lemaker_bl035_rgb_002_mode,
2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2525 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2528 static const struct drm_display_mode lg_lb070wv8_mode = {
2531 .hsync_start = 800 + 88,
2532 .hsync_end = 800 + 88 + 80,
2533 .htotal = 800 + 88 + 80 + 88,
2535 .vsync_start = 480 + 10,
2536 .vsync_end = 480 + 10 + 25,
2537 .vtotal = 480 + 10 + 25 + 10,
2540 static const struct panel_desc lg_lb070wv8 = {
2541 .modes = &lg_lb070wv8_mode,
2548 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2549 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2552 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2555 .hsync_start = 1536 + 12,
2556 .hsync_end = 1536 + 12 + 16,
2557 .htotal = 1536 + 12 + 16 + 48,
2559 .vsync_start = 2048 + 8,
2560 .vsync_end = 2048 + 8 + 4,
2561 .vtotal = 2048 + 8 + 4 + 8,
2562 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2565 static const struct panel_desc lg_lp079qx1_sp0v = {
2566 .modes = &lg_lp079qx1_sp0v_mode,
2574 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2577 .hsync_start = 2048 + 150,
2578 .hsync_end = 2048 + 150 + 5,
2579 .htotal = 2048 + 150 + 5 + 5,
2581 .vsync_start = 1536 + 3,
2582 .vsync_end = 1536 + 3 + 1,
2583 .vtotal = 1536 + 3 + 1 + 9,
2586 static const struct panel_desc lg_lp097qx1_spa1 = {
2587 .modes = &lg_lp097qx1_spa1_mode,
2595 static const struct drm_display_mode lg_lp120up1_mode = {
2598 .hsync_start = 1920 + 40,
2599 .hsync_end = 1920 + 40 + 40,
2600 .htotal = 1920 + 40 + 40+ 80,
2602 .vsync_start = 1280 + 4,
2603 .vsync_end = 1280 + 4 + 4,
2604 .vtotal = 1280 + 4 + 4 + 12,
2607 static const struct panel_desc lg_lp120up1 = {
2608 .modes = &lg_lp120up1_mode,
2615 .connector_type = DRM_MODE_CONNECTOR_eDP,
2618 static const struct drm_display_mode lg_lp129qe_mode = {
2621 .hsync_start = 2560 + 48,
2622 .hsync_end = 2560 + 48 + 32,
2623 .htotal = 2560 + 48 + 32 + 80,
2625 .vsync_start = 1700 + 3,
2626 .vsync_end = 1700 + 3 + 10,
2627 .vtotal = 1700 + 3 + 10 + 36,
2630 static const struct panel_desc lg_lp129qe = {
2631 .modes = &lg_lp129qe_mode,
2640 static const struct display_timing logictechno_lt161010_2nh_timing = {
2641 .pixelclock = { 26400000, 33300000, 46800000 },
2642 .hactive = { 800, 800, 800 },
2643 .hfront_porch = { 16, 210, 354 },
2644 .hback_porch = { 46, 46, 46 },
2645 .hsync_len = { 1, 20, 40 },
2646 .vactive = { 480, 480, 480 },
2647 .vfront_porch = { 7, 22, 147 },
2648 .vback_porch = { 23, 23, 23 },
2649 .vsync_len = { 1, 10, 20 },
2650 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2651 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2652 DISPLAY_FLAGS_SYNC_POSEDGE,
2655 static const struct panel_desc logictechno_lt161010_2nh = {
2656 .timings = &logictechno_lt161010_2nh_timing,
2662 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2663 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2664 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2665 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2666 .connector_type = DRM_MODE_CONNECTOR_DPI,
2669 static const struct display_timing logictechno_lt170410_2whc_timing = {
2670 .pixelclock = { 68900000, 71100000, 73400000 },
2671 .hactive = { 1280, 1280, 1280 },
2672 .hfront_porch = { 23, 60, 71 },
2673 .hback_porch = { 23, 60, 71 },
2674 .hsync_len = { 15, 40, 47 },
2675 .vactive = { 800, 800, 800 },
2676 .vfront_porch = { 5, 7, 10 },
2677 .vback_porch = { 5, 7, 10 },
2678 .vsync_len = { 6, 9, 12 },
2679 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2680 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2681 DISPLAY_FLAGS_SYNC_POSEDGE,
2684 static const struct panel_desc logictechno_lt170410_2whc = {
2685 .timings = &logictechno_lt170410_2whc_timing,
2691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2692 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2693 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2696 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2699 .hsync_start = 800 + 0,
2700 .hsync_end = 800 + 1,
2701 .htotal = 800 + 0 + 1 + 160,
2703 .vsync_start = 480 + 0,
2704 .vsync_end = 480 + 48 + 1,
2705 .vtotal = 480 + 48 + 1 + 0,
2706 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2709 static const struct drm_display_mode logicpd_type_28_mode = {
2712 .hsync_start = 480 + 3,
2713 .hsync_end = 480 + 3 + 42,
2714 .htotal = 480 + 3 + 42 + 2,
2717 .vsync_start = 272 + 2,
2718 .vsync_end = 272 + 2 + 11,
2719 .vtotal = 272 + 2 + 11 + 3,
2720 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2723 static const struct panel_desc logicpd_type_28 = {
2724 .modes = &logicpd_type_28_mode,
2737 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2738 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2739 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2740 .connector_type = DRM_MODE_CONNECTOR_DPI,
2743 static const struct panel_desc mitsubishi_aa070mc01 = {
2744 .modes = &mitsubishi_aa070mc01_mode,
2757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2758 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2759 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2762 static const struct display_timing nec_nl12880bc20_05_timing = {
2763 .pixelclock = { 67000000, 71000000, 75000000 },
2764 .hactive = { 1280, 1280, 1280 },
2765 .hfront_porch = { 2, 30, 30 },
2766 .hback_porch = { 6, 100, 100 },
2767 .hsync_len = { 2, 30, 30 },
2768 .vactive = { 800, 800, 800 },
2769 .vfront_porch = { 5, 5, 5 },
2770 .vback_porch = { 11, 11, 11 },
2771 .vsync_len = { 7, 7, 7 },
2774 static const struct panel_desc nec_nl12880bc20_05 = {
2775 .timings = &nec_nl12880bc20_05_timing,
2786 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2787 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2790 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2793 .hsync_start = 480 + 2,
2794 .hsync_end = 480 + 2 + 41,
2795 .htotal = 480 + 2 + 41 + 2,
2797 .vsync_start = 272 + 2,
2798 .vsync_end = 272 + 2 + 4,
2799 .vtotal = 272 + 2 + 4 + 2,
2800 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2803 static const struct panel_desc nec_nl4827hc19_05b = {
2804 .modes = &nec_nl4827hc19_05b_mode,
2811 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2812 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2815 static const struct drm_display_mode netron_dy_e231732_mode = {
2818 .hsync_start = 1024 + 160,
2819 .hsync_end = 1024 + 160 + 70,
2820 .htotal = 1024 + 160 + 70 + 90,
2822 .vsync_start = 600 + 127,
2823 .vsync_end = 600 + 127 + 20,
2824 .vtotal = 600 + 127 + 20 + 3,
2827 static const struct panel_desc netron_dy_e231732 = {
2828 .modes = &netron_dy_e231732_mode,
2834 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2837 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2841 .hsync_start = 1920 + 48,
2842 .hsync_end = 1920 + 48 + 32,
2843 .htotal = 1920 + 48 + 32 + 80,
2845 .vsync_start = 1080 + 3,
2846 .vsync_end = 1080 + 3 + 5,
2847 .vtotal = 1080 + 3 + 5 + 23,
2848 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2852 .hsync_start = 1920 + 48,
2853 .hsync_end = 1920 + 48 + 32,
2854 .htotal = 1920 + 48 + 32 + 80,
2856 .vsync_start = 1080 + 3,
2857 .vsync_end = 1080 + 3 + 5,
2858 .vtotal = 1080 + 3 + 5 + 23,
2859 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2863 static const struct panel_desc neweast_wjfh116008a = {
2864 .modes = neweast_wjfh116008a_modes,
2876 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2877 .connector_type = DRM_MODE_CONNECTOR_eDP,
2880 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2883 .hsync_start = 480 + 2,
2884 .hsync_end = 480 + 2 + 41,
2885 .htotal = 480 + 2 + 41 + 2,
2887 .vsync_start = 272 + 2,
2888 .vsync_end = 272 + 2 + 10,
2889 .vtotal = 272 + 2 + 10 + 2,
2890 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2893 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2894 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2901 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2902 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2903 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2904 .connector_type = DRM_MODE_CONNECTOR_DPI,
2907 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2908 .pixelclock = { 130000000, 148350000, 163000000 },
2909 .hactive = { 1920, 1920, 1920 },
2910 .hfront_porch = { 80, 100, 100 },
2911 .hback_porch = { 100, 120, 120 },
2912 .hsync_len = { 50, 60, 60 },
2913 .vactive = { 1080, 1080, 1080 },
2914 .vfront_porch = { 12, 30, 30 },
2915 .vback_porch = { 4, 10, 10 },
2916 .vsync_len = { 4, 5, 5 },
2919 static const struct panel_desc nlt_nl192108ac18_02d = {
2920 .timings = &nlt_nl192108ac18_02d_timing,
2930 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2931 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2934 static const struct drm_display_mode nvd_9128_mode = {
2937 .hsync_start = 800 + 130,
2938 .hsync_end = 800 + 130 + 98,
2939 .htotal = 800 + 0 + 130 + 98,
2941 .vsync_start = 480 + 10,
2942 .vsync_end = 480 + 10 + 50,
2943 .vtotal = 480 + 0 + 10 + 50,
2946 static const struct panel_desc nvd_9128 = {
2947 .modes = &nvd_9128_mode,
2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2955 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2958 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2959 .pixelclock = { 30000000, 30000000, 40000000 },
2960 .hactive = { 800, 800, 800 },
2961 .hfront_porch = { 40, 40, 40 },
2962 .hback_porch = { 40, 40, 40 },
2963 .hsync_len = { 1, 48, 48 },
2964 .vactive = { 480, 480, 480 },
2965 .vfront_porch = { 13, 13, 13 },
2966 .vback_porch = { 29, 29, 29 },
2967 .vsync_len = { 3, 3, 3 },
2968 .flags = DISPLAY_FLAGS_DE_HIGH,
2971 static const struct panel_desc okaya_rs800480t_7x0gp = {
2972 .timings = &okaya_rs800480t_7x0gp_timing,
2985 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2988 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2991 .hsync_start = 480 + 5,
2992 .hsync_end = 480 + 5 + 30,
2993 .htotal = 480 + 5 + 30 + 10,
2995 .vsync_start = 272 + 8,
2996 .vsync_end = 272 + 8 + 5,
2997 .vtotal = 272 + 8 + 5 + 3,
3000 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3001 .modes = &olimex_lcd_olinuxino_43ts_mode,
3007 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3011 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3012 * pixel clocks, but this is the timing that was being used in the Adafruit
3013 * installation instructions.
3015 static const struct drm_display_mode ontat_yx700wv03_mode = {
3025 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3030 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3032 static const struct panel_desc ontat_yx700wv03 = {
3033 .modes = &ontat_yx700wv03_mode,
3040 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3043 static const struct drm_display_mode ortustech_com37h3m_mode = {
3046 .hsync_start = 480 + 40,
3047 .hsync_end = 480 + 40 + 10,
3048 .htotal = 480 + 40 + 10 + 40,
3050 .vsync_start = 640 + 4,
3051 .vsync_end = 640 + 4 + 2,
3052 .vtotal = 640 + 4 + 2 + 4,
3053 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3056 static const struct panel_desc ortustech_com37h3m = {
3057 .modes = &ortustech_com37h3m_mode,
3061 .width = 56, /* 56.16mm */
3062 .height = 75, /* 74.88mm */
3064 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3065 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3066 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3069 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3072 .hsync_start = 480 + 10,
3073 .hsync_end = 480 + 10 + 10,
3074 .htotal = 480 + 10 + 10 + 15,
3076 .vsync_start = 800 + 3,
3077 .vsync_end = 800 + 3 + 3,
3078 .vtotal = 800 + 3 + 3 + 3,
3081 static const struct panel_desc ortustech_com43h4m85ulc = {
3082 .modes = &ortustech_com43h4m85ulc_mode,
3089 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3090 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3091 .connector_type = DRM_MODE_CONNECTOR_DPI,
3094 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3097 .hsync_start = 800 + 210,
3098 .hsync_end = 800 + 210 + 30,
3099 .htotal = 800 + 210 + 30 + 16,
3101 .vsync_start = 480 + 22,
3102 .vsync_end = 480 + 22 + 13,
3103 .vtotal = 480 + 22 + 13 + 10,
3104 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3107 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3108 .modes = &osddisplays_osd070t1718_19ts_mode,
3115 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3116 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3117 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3118 .connector_type = DRM_MODE_CONNECTOR_DPI,
3121 static const struct drm_display_mode pda_91_00156_a0_mode = {
3124 .hsync_start = 800 + 1,
3125 .hsync_end = 800 + 1 + 64,
3126 .htotal = 800 + 1 + 64 + 64,
3128 .vsync_start = 480 + 1,
3129 .vsync_end = 480 + 1 + 23,
3130 .vtotal = 480 + 1 + 23 + 22,
3133 static const struct panel_desc pda_91_00156_a0 = {
3134 .modes = &pda_91_00156_a0_mode,
3140 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3143 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3146 .hsync_start = 800 + 54,
3147 .hsync_end = 800 + 54 + 2,
3148 .htotal = 800 + 54 + 2 + 44,
3150 .vsync_start = 480 + 49,
3151 .vsync_end = 480 + 49 + 2,
3152 .vtotal = 480 + 49 + 2 + 22,
3155 static const struct panel_desc powertip_ph800480t013_idf02 = {
3156 .modes = &powertip_ph800480t013_idf02_mode,
3162 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3163 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3164 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3165 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3166 .connector_type = DRM_MODE_CONNECTOR_DPI,
3169 static const struct drm_display_mode qd43003c0_40_mode = {
3172 .hsync_start = 480 + 8,
3173 .hsync_end = 480 + 8 + 4,
3174 .htotal = 480 + 8 + 4 + 39,
3176 .vsync_start = 272 + 4,
3177 .vsync_end = 272 + 4 + 10,
3178 .vtotal = 272 + 4 + 10 + 2,
3181 static const struct panel_desc qd43003c0_40 = {
3182 .modes = &qd43003c0_40_mode,
3189 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3192 static const struct display_timing rocktech_rk070er9427_timing = {
3193 .pixelclock = { 26400000, 33300000, 46800000 },
3194 .hactive = { 800, 800, 800 },
3195 .hfront_porch = { 16, 210, 354 },
3196 .hback_porch = { 46, 46, 46 },
3197 .hsync_len = { 1, 1, 1 },
3198 .vactive = { 480, 480, 480 },
3199 .vfront_porch = { 7, 22, 147 },
3200 .vback_porch = { 23, 23, 23 },
3201 .vsync_len = { 1, 1, 1 },
3202 .flags = DISPLAY_FLAGS_DE_HIGH,
3205 static const struct panel_desc rocktech_rk070er9427 = {
3206 .timings = &rocktech_rk070er9427_timing,
3219 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3222 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3225 .hsync_start = 1280 + 48,
3226 .hsync_end = 1280 + 48 + 32,
3227 .htotal = 1280 + 48 + 32 + 80,
3229 .vsync_start = 800 + 2,
3230 .vsync_end = 800 + 2 + 5,
3231 .vtotal = 800 + 2 + 5 + 16,
3234 static const struct panel_desc rocktech_rk101ii01d_ct = {
3235 .modes = &rocktech_rk101ii01d_ct_mode,
3245 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3247 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3250 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3253 .hsync_start = 2560 + 48,
3254 .hsync_end = 2560 + 48 + 32,
3255 .htotal = 2560 + 48 + 32 + 80,
3257 .vsync_start = 1600 + 2,
3258 .vsync_end = 1600 + 2 + 5,
3259 .vtotal = 1600 + 2 + 5 + 57,
3262 static const struct panel_desc samsung_lsn122dl01_c01 = {
3263 .modes = &samsung_lsn122dl01_c01_mode,
3271 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3274 .hsync_start = 1024 + 24,
3275 .hsync_end = 1024 + 24 + 136,
3276 .htotal = 1024 + 24 + 136 + 160,
3278 .vsync_start = 600 + 3,
3279 .vsync_end = 600 + 3 + 6,
3280 .vtotal = 600 + 3 + 6 + 61,
3283 static const struct panel_desc samsung_ltn101nt05 = {
3284 .modes = &samsung_ltn101nt05_mode,
3291 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3292 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3293 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3296 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3299 .hsync_start = 1366 + 64,
3300 .hsync_end = 1366 + 64 + 48,
3301 .htotal = 1366 + 64 + 48 + 128,
3303 .vsync_start = 768 + 2,
3304 .vsync_end = 768 + 2 + 5,
3305 .vtotal = 768 + 2 + 5 + 17,
3308 static const struct panel_desc samsung_ltn140at29_301 = {
3309 .modes = &samsung_ltn140at29_301_mode,
3318 static const struct display_timing satoz_sat050at40h12r2_timing = {
3319 .pixelclock = {33300000, 33300000, 50000000},
3320 .hactive = {800, 800, 800},
3321 .hfront_porch = {16, 210, 354},
3322 .hback_porch = {46, 46, 46},
3323 .hsync_len = {1, 1, 40},
3324 .vactive = {480, 480, 480},
3325 .vfront_porch = {7, 22, 147},
3326 .vback_porch = {23, 23, 23},
3327 .vsync_len = {1, 1, 20},
3330 static const struct panel_desc satoz_sat050at40h12r2 = {
3331 .timings = &satoz_sat050at40h12r2_timing,
3338 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3339 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3342 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3345 .hsync_start = 1920 + 48,
3346 .hsync_end = 1920 + 48 + 32,
3347 .htotal = 1920 + 48 + 32 + 80,
3349 .vsync_start = 1280 + 3,
3350 .vsync_end = 1280 + 3 + 10,
3351 .vtotal = 1280 + 3 + 10 + 57,
3352 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3355 static const struct panel_desc sharp_ld_d5116z01b = {
3356 .modes = &sharp_ld_d5116z01b_mode,
3363 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3364 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3367 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3370 .hsync_start = 800 + 64,
3371 .hsync_end = 800 + 64 + 128,
3372 .htotal = 800 + 64 + 128 + 64,
3374 .vsync_start = 480 + 8,
3375 .vsync_end = 480 + 8 + 2,
3376 .vtotal = 480 + 8 + 2 + 35,
3377 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3380 static const struct panel_desc sharp_lq070y3dg3b = {
3381 .modes = &sharp_lq070y3dg3b_mode,
3385 .width = 152, /* 152.4mm */
3386 .height = 91, /* 91.4mm */
3388 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3389 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3390 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3393 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3396 .hsync_start = 240 + 16,
3397 .hsync_end = 240 + 16 + 7,
3398 .htotal = 240 + 16 + 7 + 5,
3400 .vsync_start = 320 + 9,
3401 .vsync_end = 320 + 9 + 1,
3402 .vtotal = 320 + 9 + 1 + 7,
3405 static const struct panel_desc sharp_lq035q7db03 = {
3406 .modes = &sharp_lq035q7db03_mode,
3413 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3416 static const struct display_timing sharp_lq101k1ly04_timing = {
3417 .pixelclock = { 60000000, 65000000, 80000000 },
3418 .hactive = { 1280, 1280, 1280 },
3419 .hfront_porch = { 20, 20, 20 },
3420 .hback_porch = { 20, 20, 20 },
3421 .hsync_len = { 10, 10, 10 },
3422 .vactive = { 800, 800, 800 },
3423 .vfront_porch = { 4, 4, 4 },
3424 .vback_porch = { 4, 4, 4 },
3425 .vsync_len = { 4, 4, 4 },
3426 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3429 static const struct panel_desc sharp_lq101k1ly04 = {
3430 .timings = &sharp_lq101k1ly04_timing,
3437 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3438 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3441 static const struct display_timing sharp_lq123p1jx31_timing = {
3442 .pixelclock = { 252750000, 252750000, 266604720 },
3443 .hactive = { 2400, 2400, 2400 },
3444 .hfront_porch = { 48, 48, 48 },
3445 .hback_porch = { 80, 80, 84 },
3446 .hsync_len = { 32, 32, 32 },
3447 .vactive = { 1600, 1600, 1600 },
3448 .vfront_porch = { 3, 3, 3 },
3449 .vback_porch = { 33, 33, 120 },
3450 .vsync_len = { 10, 10, 10 },
3451 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3454 static const struct panel_desc sharp_lq123p1jx31 = {
3455 .timings = &sharp_lq123p1jx31_timing,
3469 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3473 .hsync_start = 240 + 58,
3474 .hsync_end = 240 + 58 + 1,
3475 .htotal = 240 + 58 + 1 + 1,
3477 .vsync_start = 160 + 24,
3478 .vsync_end = 160 + 24 + 10,
3479 .vtotal = 160 + 24 + 10 + 6,
3480 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3485 .hsync_start = 240 + 8,
3486 .hsync_end = 240 + 8 + 1,
3487 .htotal = 240 + 8 + 1 + 1,
3489 .vsync_start = 160 + 24,
3490 .vsync_end = 160 + 24 + 10,
3491 .vtotal = 160 + 24 + 10 + 6,
3492 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3496 static const struct panel_desc sharp_ls020b1dd01d = {
3497 .modes = sharp_ls020b1dd01d_modes,
3498 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3504 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3505 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3506 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3507 | DRM_BUS_FLAG_SHARP_SIGNALS,
3510 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3513 .hsync_start = 800 + 1,
3514 .hsync_end = 800 + 1 + 64,
3515 .htotal = 800 + 1 + 64 + 64,
3517 .vsync_start = 480 + 1,
3518 .vsync_end = 480 + 1 + 23,
3519 .vtotal = 480 + 1 + 23 + 22,
3522 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3523 .modes = &shelly_sca07010_bfn_lnn_mode,
3529 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3532 static const struct drm_display_mode starry_kr070pe2t_mode = {
3535 .hsync_start = 800 + 209,
3536 .hsync_end = 800 + 209 + 1,
3537 .htotal = 800 + 209 + 1 + 45,
3539 .vsync_start = 480 + 22,
3540 .vsync_end = 480 + 22 + 1,
3541 .vtotal = 480 + 22 + 1 + 22,
3544 static const struct panel_desc starry_kr070pe2t = {
3545 .modes = &starry_kr070pe2t_mode,
3552 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3553 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3554 .connector_type = DRM_MODE_CONNECTOR_DPI,
3557 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3560 .hsync_start = 1920 + 16,
3561 .hsync_end = 1920 + 16 + 16,
3562 .htotal = 1920 + 16 + 16 + 32,
3564 .vsync_start = 1200 + 15,
3565 .vsync_end = 1200 + 15 + 2,
3566 .vtotal = 1200 + 15 + 2 + 18,
3567 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3570 static const struct panel_desc starry_kr122ea0sra = {
3571 .modes = &starry_kr122ea0sra_mode,
3578 .prepare = 10 + 200,
3580 .unprepare = 10 + 500,
3584 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3587 .hsync_start = 800 + 39,
3588 .hsync_end = 800 + 39 + 47,
3589 .htotal = 800 + 39 + 47 + 39,
3591 .vsync_start = 480 + 13,
3592 .vsync_end = 480 + 13 + 2,
3593 .vtotal = 480 + 13 + 2 + 29,
3596 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3597 .modes = &tfc_s9700rtwv43tr_01b_mode,
3604 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3605 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3608 static const struct display_timing tianma_tm070jdhg30_timing = {
3609 .pixelclock = { 62600000, 68200000, 78100000 },
3610 .hactive = { 1280, 1280, 1280 },
3611 .hfront_porch = { 15, 64, 159 },
3612 .hback_porch = { 5, 5, 5 },
3613 .hsync_len = { 1, 1, 256 },
3614 .vactive = { 800, 800, 800 },
3615 .vfront_porch = { 3, 40, 99 },
3616 .vback_porch = { 2, 2, 2 },
3617 .vsync_len = { 1, 1, 128 },
3618 .flags = DISPLAY_FLAGS_DE_HIGH,
3621 static const struct panel_desc tianma_tm070jdhg30 = {
3622 .timings = &tianma_tm070jdhg30_timing,
3629 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3630 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3633 static const struct panel_desc tianma_tm070jvhg33 = {
3634 .timings = &tianma_tm070jdhg30_timing,
3641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3642 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3645 static const struct display_timing tianma_tm070rvhg71_timing = {
3646 .pixelclock = { 27700000, 29200000, 39600000 },
3647 .hactive = { 800, 800, 800 },
3648 .hfront_porch = { 12, 40, 212 },
3649 .hback_porch = { 88, 88, 88 },
3650 .hsync_len = { 1, 1, 40 },
3651 .vactive = { 480, 480, 480 },
3652 .vfront_porch = { 1, 13, 88 },
3653 .vback_porch = { 32, 32, 32 },
3654 .vsync_len = { 1, 1, 3 },
3655 .flags = DISPLAY_FLAGS_DE_HIGH,
3658 static const struct panel_desc tianma_tm070rvhg71 = {
3659 .timings = &tianma_tm070rvhg71_timing,
3666 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3667 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3670 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3674 .hsync_start = 320 + 50,
3675 .hsync_end = 320 + 50 + 6,
3676 .htotal = 320 + 50 + 6 + 38,
3678 .vsync_start = 240 + 3,
3679 .vsync_end = 240 + 3 + 1,
3680 .vtotal = 240 + 3 + 1 + 17,
3681 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3685 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3686 .modes = ti_nspire_cx_lcd_mode,
3693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3694 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3697 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3701 .hsync_start = 320 + 6,
3702 .hsync_end = 320 + 6 + 6,
3703 .htotal = 320 + 6 + 6 + 6,
3705 .vsync_start = 240 + 0,
3706 .vsync_end = 240 + 0 + 1,
3707 .vtotal = 240 + 0 + 1 + 0,
3708 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3712 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3713 .modes = ti_nspire_classic_lcd_mode,
3715 /* The grayscale panel has 8 bit for the color .. Y (black) */
3721 /* This is the grayscale bus format */
3722 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3723 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3726 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3729 .hsync_start = 1280 + 192,
3730 .hsync_end = 1280 + 192 + 128,
3731 .htotal = 1280 + 192 + 128 + 64,
3733 .vsync_start = 768 + 20,
3734 .vsync_end = 768 + 20 + 7,
3735 .vtotal = 768 + 20 + 7 + 3,
3738 static const struct panel_desc toshiba_lt089ac29000 = {
3739 .modes = &toshiba_lt089ac29000_mode,
3745 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3746 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3747 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3750 static const struct drm_display_mode tpk_f07a_0102_mode = {
3753 .hsync_start = 800 + 40,
3754 .hsync_end = 800 + 40 + 128,
3755 .htotal = 800 + 40 + 128 + 88,
3757 .vsync_start = 480 + 10,
3758 .vsync_end = 480 + 10 + 2,
3759 .vtotal = 480 + 10 + 2 + 33,
3762 static const struct panel_desc tpk_f07a_0102 = {
3763 .modes = &tpk_f07a_0102_mode,
3769 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3772 static const struct drm_display_mode tpk_f10a_0102_mode = {
3775 .hsync_start = 1024 + 176,
3776 .hsync_end = 1024 + 176 + 5,
3777 .htotal = 1024 + 176 + 5 + 88,
3779 .vsync_start = 600 + 20,
3780 .vsync_end = 600 + 20 + 5,
3781 .vtotal = 600 + 20 + 5 + 25,
3784 static const struct panel_desc tpk_f10a_0102 = {
3785 .modes = &tpk_f10a_0102_mode,
3793 static const struct display_timing urt_umsh_8596md_timing = {
3794 .pixelclock = { 33260000, 33260000, 33260000 },
3795 .hactive = { 800, 800, 800 },
3796 .hfront_porch = { 41, 41, 41 },
3797 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3798 .hsync_len = { 71, 128, 128 },
3799 .vactive = { 480, 480, 480 },
3800 .vfront_porch = { 10, 10, 10 },
3801 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3802 .vsync_len = { 2, 2, 2 },
3803 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3804 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3807 static const struct panel_desc urt_umsh_8596md_lvds = {
3808 .timings = &urt_umsh_8596md_timing,
3815 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3816 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3819 static const struct panel_desc urt_umsh_8596md_parallel = {
3820 .timings = &urt_umsh_8596md_timing,
3827 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3830 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3833 .hsync_start = 800 + 210,
3834 .hsync_end = 800 + 210 + 20,
3835 .htotal = 800 + 210 + 20 + 46,
3837 .vsync_start = 480 + 22,
3838 .vsync_end = 480 + 22 + 10,
3839 .vtotal = 480 + 22 + 10 + 23,
3840 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3843 static const struct panel_desc vl050_8048nt_c01 = {
3844 .modes = &vl050_8048nt_c01_mode,
3851 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3852 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3855 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3858 .hsync_start = 320 + 20,
3859 .hsync_end = 320 + 20 + 30,
3860 .htotal = 320 + 20 + 30 + 38,
3862 .vsync_start = 240 + 4,
3863 .vsync_end = 240 + 4 + 3,
3864 .vtotal = 240 + 4 + 3 + 15,
3865 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3868 static const struct panel_desc winstar_wf35ltiacd = {
3869 .modes = &winstar_wf35ltiacd_mode,
3876 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3879 static const struct drm_display_mode arm_rtsm_mode[] = {
3883 .hsync_start = 1024 + 24,
3884 .hsync_end = 1024 + 24 + 136,
3885 .htotal = 1024 + 24 + 136 + 160,
3887 .vsync_start = 768 + 3,
3888 .vsync_end = 768 + 3 + 6,
3889 .vtotal = 768 + 3 + 6 + 29,
3890 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3894 static const struct panel_desc arm_rtsm = {
3895 .modes = arm_rtsm_mode,
3902 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3905 static const struct of_device_id platform_of_match[] = {
3907 .compatible = "ampire,am-1280800n3tzqw-t00h",
3908 .data = &ire_am_1280800n3tzqw_t00h,
3910 .compatible = "ampire,am-480272h3tmqw-t01h",
3911 .data = &ire_am_480272h3tmqw_t01h,
3913 .compatible = "ampire,am800480r3tmqwa1h",
3914 .data = &ire_am800480r3tmqwa1h,
3916 .compatible = "arm,rtsm-display",
3919 .compatible = "armadeus,st0700-adapt",
3920 .data = &armadeus_st0700_adapt,
3922 .compatible = "auo,b101aw03",
3923 .data = &auo_b101aw03,
3925 .compatible = "auo,b101ean01",
3926 .data = &auo_b101ean01,
3928 .compatible = "auo,b101xtn01",
3929 .data = &auo_b101xtn01,
3931 .compatible = "auo,b116xa01",
3932 .data = &auo_b116xak01,
3934 .compatible = "auo,b116xw03",
3935 .data = &auo_b116xw03,
3937 .compatible = "auo,b133htn01",
3938 .data = &auo_b133htn01,
3940 .compatible = "auo,b133xtn01",
3941 .data = &auo_b133xtn01,
3943 .compatible = "auo,g070vvn01",
3944 .data = &auo_g070vvn01,
3946 .compatible = "auo,g101evn010",
3947 .data = &auo_g101evn010,
3949 .compatible = "auo,g104sn02",
3950 .data = &auo_g104sn02,
3952 .compatible = "auo,g121ean01",
3953 .data = &auo_g121ean01,
3955 .compatible = "auo,g133han01",
3956 .data = &auo_g133han01,
3958 .compatible = "auo,g156xtn01",
3959 .data = &auo_g156xtn01,
3961 .compatible = "auo,g185han01",
3962 .data = &auo_g185han01,
3964 .compatible = "auo,g190ean01",
3965 .data = &auo_g190ean01,
3967 .compatible = "auo,p320hvn03",
3968 .data = &auo_p320hvn03,
3970 .compatible = "auo,t215hvn01",
3971 .data = &auo_t215hvn01,
3973 .compatible = "avic,tm070ddh03",
3974 .data = &avic_tm070ddh03,
3976 .compatible = "bananapi,s070wv20-ct16",
3977 .data = &bananapi_s070wv20_ct16,
3979 .compatible = "boe,hv070wsa-100",
3980 .data = &boe_hv070wsa
3982 .compatible = "boe,nv101wxmn51",
3983 .data = &boe_nv101wxmn51,
3985 .compatible = "boe,nv133fhm-n61",
3986 .data = &boe_nv133fhm_n61,
3988 .compatible = "boe,nv133fhm-n62",
3989 .data = &boe_nv133fhm_n61,
3991 .compatible = "boe,nv140fhmn49",
3992 .data = &boe_nv140fhmn49,
3994 .compatible = "cdtech,s043wq26h-ct7",
3995 .data = &cdtech_s043wq26h_ct7,
3997 .compatible = "cdtech,s070pws19hp-fc21",
3998 .data = &cdtech_s070pws19hp_fc21,
4000 .compatible = "cdtech,s070swv29hg-dc44",
4001 .data = &cdtech_s070swv29hg_dc44,
4003 .compatible = "cdtech,s070wv95-ct16",
4004 .data = &cdtech_s070wv95_ct16,
4006 .compatible = "chefree,ch101olhlwh-002",
4007 .data = &chefree_ch101olhlwh_002,
4009 .compatible = "chunghwa,claa070wp03xg",
4010 .data = &chunghwa_claa070wp03xg,
4012 .compatible = "chunghwa,claa101wa01a",
4013 .data = &chunghwa_claa101wa01a
4015 .compatible = "chunghwa,claa101wb01",
4016 .data = &chunghwa_claa101wb01
4018 .compatible = "dataimage,scf0700c48ggu18",
4019 .data = &dataimage_scf0700c48ggu18,
4021 .compatible = "dlc,dlc0700yzg-1",
4022 .data = &dlc_dlc0700yzg_1,
4024 .compatible = "dlc,dlc1010gig",
4025 .data = &dlc_dlc1010gig,
4027 .compatible = "edt,et035012dm6",
4028 .data = &edt_et035012dm6,
4030 .compatible = "edt,etm043080dh6gp",
4031 .data = &edt_etm043080dh6gp,
4033 .compatible = "edt,etm0430g0dh6",
4034 .data = &edt_etm0430g0dh6,
4036 .compatible = "edt,et057090dhu",
4037 .data = &edt_et057090dhu,
4039 .compatible = "edt,et070080dh6",
4040 .data = &edt_etm0700g0dh6,
4042 .compatible = "edt,etm0700g0dh6",
4043 .data = &edt_etm0700g0dh6,
4045 .compatible = "edt,etm0700g0bdh6",
4046 .data = &edt_etm0700g0bdh6,
4048 .compatible = "edt,etm0700g0edh6",
4049 .data = &edt_etm0700g0bdh6,
4051 .compatible = "evervision,vgg804821",
4052 .data = &evervision_vgg804821,
4054 .compatible = "foxlink,fl500wvr00-a0t",
4055 .data = &foxlink_fl500wvr00_a0t,
4057 .compatible = "frida,frd350h54004",
4058 .data = &frida_frd350h54004,
4060 .compatible = "friendlyarm,hd702e",
4061 .data = &friendlyarm_hd702e,
4063 .compatible = "giantplus,gpg482739qs5",
4064 .data = &giantplus_gpg482739qs5
4066 .compatible = "giantplus,gpm940b0",
4067 .data = &giantplus_gpm940b0,
4069 .compatible = "hannstar,hsd070pww1",
4070 .data = &hannstar_hsd070pww1,
4072 .compatible = "hannstar,hsd100pxn1",
4073 .data = &hannstar_hsd100pxn1,
4075 .compatible = "hit,tx23d38vm0caa",
4076 .data = &hitachi_tx23d38vm0caa
4078 .compatible = "innolux,at043tn24",
4079 .data = &innolux_at043tn24,
4081 .compatible = "innolux,at070tn92",
4082 .data = &innolux_at070tn92,
4084 .compatible = "innolux,g070y2-l01",
4085 .data = &innolux_g070y2_l01,
4087 .compatible = "innolux,g101ice-l01",
4088 .data = &innolux_g101ice_l01
4090 .compatible = "innolux,g121i1-l01",
4091 .data = &innolux_g121i1_l01
4093 .compatible = "innolux,g121x1-l03",
4094 .data = &innolux_g121x1_l03,
4096 .compatible = "innolux,n116bge",
4097 .data = &innolux_n116bge,
4099 .compatible = "innolux,n156bge-l21",
4100 .data = &innolux_n156bge_l21,
4102 .compatible = "innolux,p120zdg-bf1",
4103 .data = &innolux_p120zdg_bf1,
4105 .compatible = "innolux,zj070na-01p",
4106 .data = &innolux_zj070na_01p,
4108 .compatible = "ivo,m133nwf4-r0",
4109 .data = &ivo_m133nwf4_r0,
4111 .compatible = "kingdisplay,kd116n21-30nv-a010",
4112 .data = &kingdisplay_kd116n21_30nv_a010,
4114 .compatible = "koe,tx14d24vm1bpa",
4115 .data = &koe_tx14d24vm1bpa,
4117 .compatible = "koe,tx26d202vm0bwa",
4118 .data = &koe_tx26d202vm0bwa,
4120 .compatible = "koe,tx31d200vm0baa",
4121 .data = &koe_tx31d200vm0baa,
4123 .compatible = "kyo,tcg121xglp",
4124 .data = &kyo_tcg121xglp,
4126 .compatible = "lemaker,bl035-rgb-002",
4127 .data = &lemaker_bl035_rgb_002,
4129 .compatible = "lg,lb070wv8",
4130 .data = &lg_lb070wv8,
4132 .compatible = "lg,lp079qx1-sp0v",
4133 .data = &lg_lp079qx1_sp0v,
4135 .compatible = "lg,lp097qx1-spa1",
4136 .data = &lg_lp097qx1_spa1,
4138 .compatible = "lg,lp120up1",
4139 .data = &lg_lp120up1,
4141 .compatible = "lg,lp129qe",
4142 .data = &lg_lp129qe,
4144 .compatible = "logicpd,type28",
4145 .data = &logicpd_type_28,
4147 .compatible = "logictechno,lt161010-2nhc",
4148 .data = &logictechno_lt161010_2nh,
4150 .compatible = "logictechno,lt161010-2nhr",
4151 .data = &logictechno_lt161010_2nh,
4153 .compatible = "logictechno,lt170410-2whc",
4154 .data = &logictechno_lt170410_2whc,
4156 .compatible = "mitsubishi,aa070mc01-ca1",
4157 .data = &mitsubishi_aa070mc01,
4159 .compatible = "nec,nl12880bc20-05",
4160 .data = &nec_nl12880bc20_05,
4162 .compatible = "nec,nl4827hc19-05b",
4163 .data = &nec_nl4827hc19_05b,
4165 .compatible = "netron-dy,e231732",
4166 .data = &netron_dy_e231732,
4168 .compatible = "neweast,wjfh116008a",
4169 .data = &neweast_wjfh116008a,
4171 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4172 .data = &newhaven_nhd_43_480272ef_atxl,
4174 .compatible = "nlt,nl192108ac18-02d",
4175 .data = &nlt_nl192108ac18_02d,
4177 .compatible = "nvd,9128",
4180 .compatible = "okaya,rs800480t-7x0gp",
4181 .data = &okaya_rs800480t_7x0gp,
4183 .compatible = "olimex,lcd-olinuxino-43-ts",
4184 .data = &olimex_lcd_olinuxino_43ts,
4186 .compatible = "ontat,yx700wv03",
4187 .data = &ontat_yx700wv03,
4189 .compatible = "ortustech,com37h3m05dtc",
4190 .data = &ortustech_com37h3m,
4192 .compatible = "ortustech,com37h3m99dtc",
4193 .data = &ortustech_com37h3m,
4195 .compatible = "ortustech,com43h4m85ulc",
4196 .data = &ortustech_com43h4m85ulc,
4198 .compatible = "osddisplays,osd070t1718-19ts",
4199 .data = &osddisplays_osd070t1718_19ts,
4201 .compatible = "pda,91-00156-a0",
4202 .data = &pda_91_00156_a0,
4204 .compatible = "powertip,ph800480t013-idf02",
4205 .data = &powertip_ph800480t013_idf02,
4207 .compatible = "qiaodian,qd43003c0-40",
4208 .data = &qd43003c0_40,
4210 .compatible = "rocktech,rk070er9427",
4211 .data = &rocktech_rk070er9427,
4213 .compatible = "rocktech,rk101ii01d-ct",
4214 .data = &rocktech_rk101ii01d_ct,
4216 .compatible = "samsung,lsn122dl01-c01",
4217 .data = &samsung_lsn122dl01_c01,
4219 .compatible = "samsung,ltn101nt05",
4220 .data = &samsung_ltn101nt05,
4222 .compatible = "samsung,ltn140at29-301",
4223 .data = &samsung_ltn140at29_301,
4225 .compatible = "satoz,sat050at40h12r2",
4226 .data = &satoz_sat050at40h12r2,
4228 .compatible = "sharp,ld-d5116z01b",
4229 .data = &sharp_ld_d5116z01b,
4231 .compatible = "sharp,lq035q7db03",
4232 .data = &sharp_lq035q7db03,
4234 .compatible = "sharp,lq070y3dg3b",
4235 .data = &sharp_lq070y3dg3b,
4237 .compatible = "sharp,lq101k1ly04",
4238 .data = &sharp_lq101k1ly04,
4240 .compatible = "sharp,lq123p1jx31",
4241 .data = &sharp_lq123p1jx31,
4243 .compatible = "sharp,ls020b1dd01d",
4244 .data = &sharp_ls020b1dd01d,
4246 .compatible = "shelly,sca07010-bfn-lnn",
4247 .data = &shelly_sca07010_bfn_lnn,
4249 .compatible = "starry,kr070pe2t",
4250 .data = &starry_kr070pe2t,
4252 .compatible = "starry,kr122ea0sra",
4253 .data = &starry_kr122ea0sra,
4255 .compatible = "tfc,s9700rtwv43tr-01b",
4256 .data = &tfc_s9700rtwv43tr_01b,
4258 .compatible = "tianma,tm070jdhg30",
4259 .data = &tianma_tm070jdhg30,
4261 .compatible = "tianma,tm070jvhg33",
4262 .data = &tianma_tm070jvhg33,
4264 .compatible = "tianma,tm070rvhg71",
4265 .data = &tianma_tm070rvhg71,
4267 .compatible = "ti,nspire-cx-lcd-panel",
4268 .data = &ti_nspire_cx_lcd_panel,
4270 .compatible = "ti,nspire-classic-lcd-panel",
4271 .data = &ti_nspire_classic_lcd_panel,
4273 .compatible = "toshiba,lt089ac29000",
4274 .data = &toshiba_lt089ac29000,
4276 .compatible = "tpk,f07a-0102",
4277 .data = &tpk_f07a_0102,
4279 .compatible = "tpk,f10a-0102",
4280 .data = &tpk_f10a_0102,
4282 .compatible = "urt,umsh-8596md-t",
4283 .data = &urt_umsh_8596md_parallel,
4285 .compatible = "urt,umsh-8596md-1t",
4286 .data = &urt_umsh_8596md_parallel,
4288 .compatible = "urt,umsh-8596md-7t",
4289 .data = &urt_umsh_8596md_parallel,
4291 .compatible = "urt,umsh-8596md-11t",
4292 .data = &urt_umsh_8596md_lvds,
4294 .compatible = "urt,umsh-8596md-19t",
4295 .data = &urt_umsh_8596md_lvds,
4297 .compatible = "urt,umsh-8596md-20t",
4298 .data = &urt_umsh_8596md_parallel,
4300 .compatible = "vxt,vl050-8048nt-c01",
4301 .data = &vl050_8048nt_c01,
4303 .compatible = "winstar,wf35ltiacd",
4304 .data = &winstar_wf35ltiacd,
4306 /* Must be the last entry */
4307 .compatible = "panel-dpi",
4313 MODULE_DEVICE_TABLE(of, platform_of_match);
4315 static int panel_simple_platform_probe(struct platform_device *pdev)
4317 const struct of_device_id *id;
4319 id = of_match_node(platform_of_match, pdev->dev.of_node);
4323 return panel_simple_probe(&pdev->dev, id->data);
4326 static int panel_simple_platform_remove(struct platform_device *pdev)
4328 return panel_simple_remove(&pdev->dev);
4331 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4333 panel_simple_shutdown(&pdev->dev);
4336 static struct platform_driver panel_simple_platform_driver = {
4338 .name = "panel-simple",
4339 .of_match_table = platform_of_match,
4341 .probe = panel_simple_platform_probe,
4342 .remove = panel_simple_platform_remove,
4343 .shutdown = panel_simple_platform_shutdown,
4346 struct panel_desc_dsi {
4347 struct panel_desc desc;
4349 unsigned long flags;
4350 enum mipi_dsi_pixel_format format;
4354 static const struct drm_display_mode auo_b080uan01_mode = {
4357 .hsync_start = 1200 + 62,
4358 .hsync_end = 1200 + 62 + 4,
4359 .htotal = 1200 + 62 + 4 + 62,
4361 .vsync_start = 1920 + 9,
4362 .vsync_end = 1920 + 9 + 2,
4363 .vtotal = 1920 + 9 + 2 + 8,
4366 static const struct panel_desc_dsi auo_b080uan01 = {
4368 .modes = &auo_b080uan01_mode,
4375 .connector_type = DRM_MODE_CONNECTOR_DSI,
4377 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4378 .format = MIPI_DSI_FMT_RGB888,
4382 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4385 .hsync_start = 1200 + 120,
4386 .hsync_end = 1200 + 120 + 20,
4387 .htotal = 1200 + 120 + 20 + 21,
4389 .vsync_start = 1920 + 21,
4390 .vsync_end = 1920 + 21 + 3,
4391 .vtotal = 1920 + 21 + 3 + 18,
4392 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4395 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4397 .modes = &boe_tv080wum_nl0_mode,
4403 .connector_type = DRM_MODE_CONNECTOR_DSI,
4405 .flags = MIPI_DSI_MODE_VIDEO |
4406 MIPI_DSI_MODE_VIDEO_BURST |
4407 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4408 .format = MIPI_DSI_FMT_RGB888,
4412 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4415 .hsync_start = 800 + 32,
4416 .hsync_end = 800 + 32 + 1,
4417 .htotal = 800 + 32 + 1 + 57,
4419 .vsync_start = 1280 + 28,
4420 .vsync_end = 1280 + 28 + 1,
4421 .vtotal = 1280 + 28 + 1 + 14,
4424 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4426 .modes = &lg_ld070wx3_sl01_mode,
4433 .connector_type = DRM_MODE_CONNECTOR_DSI,
4435 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4436 .format = MIPI_DSI_FMT_RGB888,
4440 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4443 .hsync_start = 720 + 12,
4444 .hsync_end = 720 + 12 + 4,
4445 .htotal = 720 + 12 + 4 + 112,
4447 .vsync_start = 1280 + 8,
4448 .vsync_end = 1280 + 8 + 4,
4449 .vtotal = 1280 + 8 + 4 + 12,
4452 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4454 .modes = &lg_lh500wx1_sd03_mode,
4461 .connector_type = DRM_MODE_CONNECTOR_DSI,
4463 .flags = MIPI_DSI_MODE_VIDEO,
4464 .format = MIPI_DSI_FMT_RGB888,
4468 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4471 .hsync_start = 1920 + 154,
4472 .hsync_end = 1920 + 154 + 16,
4473 .htotal = 1920 + 154 + 16 + 32,
4475 .vsync_start = 1200 + 17,
4476 .vsync_end = 1200 + 17 + 2,
4477 .vtotal = 1200 + 17 + 2 + 16,
4480 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4482 .modes = &panasonic_vvx10f004b00_mode,
4489 .connector_type = DRM_MODE_CONNECTOR_DSI,
4491 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4492 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4493 .format = MIPI_DSI_FMT_RGB888,
4497 static const struct drm_display_mode lg_acx467akm_7_mode = {
4500 .hsync_start = 1080 + 2,
4501 .hsync_end = 1080 + 2 + 2,
4502 .htotal = 1080 + 2 + 2 + 2,
4504 .vsync_start = 1920 + 2,
4505 .vsync_end = 1920 + 2 + 2,
4506 .vtotal = 1920 + 2 + 2 + 2,
4509 static const struct panel_desc_dsi lg_acx467akm_7 = {
4511 .modes = &lg_acx467akm_7_mode,
4518 .connector_type = DRM_MODE_CONNECTOR_DSI,
4521 .format = MIPI_DSI_FMT_RGB888,
4525 static const struct drm_display_mode osd101t2045_53ts_mode = {
4528 .hsync_start = 1920 + 112,
4529 .hsync_end = 1920 + 112 + 16,
4530 .htotal = 1920 + 112 + 16 + 32,
4532 .vsync_start = 1200 + 16,
4533 .vsync_end = 1200 + 16 + 2,
4534 .vtotal = 1200 + 16 + 2 + 16,
4535 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4538 static const struct panel_desc_dsi osd101t2045_53ts = {
4540 .modes = &osd101t2045_53ts_mode,
4547 .connector_type = DRM_MODE_CONNECTOR_DSI,
4549 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4550 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4551 MIPI_DSI_MODE_EOT_PACKET,
4552 .format = MIPI_DSI_FMT_RGB888,
4556 static const struct of_device_id dsi_of_match[] = {
4558 .compatible = "auo,b080uan01",
4559 .data = &auo_b080uan01
4561 .compatible = "boe,tv080wum-nl0",
4562 .data = &boe_tv080wum_nl0
4564 .compatible = "lg,ld070wx3-sl01",
4565 .data = &lg_ld070wx3_sl01
4567 .compatible = "lg,lh500wx1-sd03",
4568 .data = &lg_lh500wx1_sd03
4570 .compatible = "panasonic,vvx10f004b00",
4571 .data = &panasonic_vvx10f004b00
4573 .compatible = "lg,acx467akm-7",
4574 .data = &lg_acx467akm_7
4576 .compatible = "osddisplays,osd101t2045-53ts",
4577 .data = &osd101t2045_53ts
4582 MODULE_DEVICE_TABLE(of, dsi_of_match);
4584 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4586 const struct panel_desc_dsi *desc;
4587 const struct of_device_id *id;
4590 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4596 err = panel_simple_probe(&dsi->dev, &desc->desc);
4600 dsi->mode_flags = desc->flags;
4601 dsi->format = desc->format;
4602 dsi->lanes = desc->lanes;
4604 err = mipi_dsi_attach(dsi);
4606 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4608 drm_panel_remove(&panel->base);
4614 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4618 err = mipi_dsi_detach(dsi);
4620 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4622 return panel_simple_remove(&dsi->dev);
4625 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4627 panel_simple_shutdown(&dsi->dev);
4630 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4632 .name = "panel-simple-dsi",
4633 .of_match_table = dsi_of_match,
4635 .probe = panel_simple_dsi_probe,
4636 .remove = panel_simple_dsi_remove,
4637 .shutdown = panel_simple_dsi_shutdown,
4640 static int __init panel_simple_init(void)
4644 err = platform_driver_register(&panel_simple_platform_driver);
4648 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4649 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4656 module_init(panel_simple_init);
4658 static void __exit panel_simple_exit(void)
4660 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4661 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4663 platform_driver_unregister(&panel_simple_platform_driver);
4665 module_exit(panel_simple_exit);
4667 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4668 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4669 MODULE_LICENSE("GPL and additional rights");