2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * struct panel_desc - Describes a simple panel.
46 * @modes: Pointer to array of fixed modes appropriate for this panel.
48 * If only one mode then this can just be the address of the mode.
49 * NOTE: cannot be used with "timings" and also if this is specified
50 * then you cannot override the mode in the device tree.
52 const struct drm_display_mode *modes;
54 /** @num_modes: Number of elements in modes array. */
55 unsigned int num_modes;
58 * @timings: Pointer to array of display timings
60 * NOTE: cannot be used with "modes" and also these will be used to
61 * validate a device tree override if one is present.
63 const struct display_timing *timings;
65 /** @num_timings: Number of elements in timings array. */
66 unsigned int num_timings;
68 /** @bpc: Bits per color. */
71 /** @size: Structure containing the physical size of this panel. */
74 * @size.width: Width (in mm) of the active display area.
79 * @size.height: Height (in mm) of the active display area.
84 /** @delay: Structure containing various delay values for this panel. */
87 * @delay.prepare: Time for the panel to become ready.
89 * The time (in milliseconds) that it takes for the panel to
90 * become ready and start receiving video data
95 * @delay.enable: Time for the panel to display a valid frame.
97 * The time (in milliseconds) that it takes for the panel to
98 * display the first valid frame after starting to receive
104 * @delay.disable: Time for the panel to turn the display off.
106 * The time (in milliseconds) that it takes for the panel to
107 * turn the display off (no content is visible).
109 unsigned int disable;
112 * @delay.unprepare: Time to power down completely.
114 * The time (in milliseconds) that it takes for the panel
115 * to power itself down completely.
117 * This time is used to prevent a future "prepare" from
118 * starting until at least this many milliseconds has passed.
119 * If at prepare time less time has passed since unprepare
120 * finished, the driver waits for the remaining time.
122 unsigned int unprepare;
125 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
128 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
131 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
135 struct panel_simple {
136 struct drm_panel base;
141 ktime_t prepared_time;
142 ktime_t unprepared_time;
144 const struct panel_desc *desc;
146 struct regulator *supply;
147 struct i2c_adapter *ddc;
149 struct gpio_desc *enable_gpio;
153 struct drm_display_mode override_mode;
155 enum drm_panel_orientation orientation;
158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
160 return container_of(panel, struct panel_simple, base);
163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
164 struct drm_connector *connector)
166 struct drm_display_mode *mode;
167 unsigned int i, num = 0;
169 for (i = 0; i < panel->desc->num_timings; i++) {
170 const struct display_timing *dt = &panel->desc->timings[i];
173 videomode_from_timing(dt, &vm);
174 mode = drm_mode_create(connector->dev);
176 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
177 dt->hactive.typ, dt->vactive.typ);
181 drm_display_mode_from_videomode(&vm, mode);
183 mode->type |= DRM_MODE_TYPE_DRIVER;
185 if (panel->desc->num_timings == 1)
186 mode->type |= DRM_MODE_TYPE_PREFERRED;
188 drm_mode_probed_add(connector, mode);
195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
196 struct drm_connector *connector)
198 struct drm_display_mode *mode;
199 unsigned int i, num = 0;
201 for (i = 0; i < panel->desc->num_modes; i++) {
202 const struct drm_display_mode *m = &panel->desc->modes[i];
204 mode = drm_mode_duplicate(connector->dev, m);
206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
207 m->hdisplay, m->vdisplay,
208 drm_mode_vrefresh(m));
212 mode->type |= DRM_MODE_TYPE_DRIVER;
214 if (panel->desc->num_modes == 1)
215 mode->type |= DRM_MODE_TYPE_PREFERRED;
217 drm_mode_set_name(mode);
219 drm_mode_probed_add(connector, mode);
226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
227 struct drm_connector *connector)
229 struct drm_display_mode *mode;
230 bool has_override = panel->override_mode.type;
231 unsigned int num = 0;
237 mode = drm_mode_duplicate(connector->dev,
238 &panel->override_mode);
240 drm_mode_probed_add(connector, mode);
243 dev_err(panel->base.dev, "failed to add override mode\n");
247 /* Only add timings if override was not there or failed to validate */
248 if (num == 0 && panel->desc->num_timings)
249 num = panel_simple_get_timings_modes(panel, connector);
252 * Only add fixed modes if timings/override added no mode.
254 * We should only ever have either the display timings specified
255 * or a fixed mode. Anything else is rather bogus.
257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
259 num = panel_simple_get_display_modes(panel, connector);
261 connector->display_info.bpc = panel->desc->bpc;
262 connector->display_info.width_mm = panel->desc->size.width;
263 connector->display_info.height_mm = panel->desc->size.height;
264 if (panel->desc->bus_format)
265 drm_display_info_set_bus_formats(&connector->display_info,
266 &panel->desc->bus_format, 1);
267 connector->display_info.bus_flags = panel->desc->bus_flags;
272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
274 ktime_t now_ktime, min_ktime;
279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
280 now_ktime = ktime_get();
282 if (ktime_before(now_ktime, min_ktime))
283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
286 static int panel_simple_disable(struct drm_panel *panel)
288 struct panel_simple *p = to_panel_simple(panel);
293 if (p->desc->delay.disable)
294 msleep(p->desc->delay.disable);
301 static int panel_simple_suspend(struct device *dev)
303 struct panel_simple *p = dev_get_drvdata(dev);
305 gpiod_set_value_cansleep(p->enable_gpio, 0);
306 regulator_disable(p->supply);
307 p->unprepared_time = ktime_get();
315 static int panel_simple_unprepare(struct drm_panel *panel)
317 struct panel_simple *p = to_panel_simple(panel);
320 /* Unpreparing when already unprepared is a no-op */
324 pm_runtime_mark_last_busy(panel->dev);
325 ret = pm_runtime_put_autosuspend(panel->dev);
333 static int panel_simple_resume(struct device *dev)
335 struct panel_simple *p = dev_get_drvdata(dev);
338 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
340 err = regulator_enable(p->supply);
342 dev_err(dev, "failed to enable supply: %d\n", err);
346 gpiod_set_value_cansleep(p->enable_gpio, 1);
348 if (p->desc->delay.prepare)
349 msleep(p->desc->delay.prepare);
351 p->prepared_time = ktime_get();
356 static int panel_simple_prepare(struct drm_panel *panel)
358 struct panel_simple *p = to_panel_simple(panel);
361 /* Preparing when already prepared is a no-op */
365 ret = pm_runtime_get_sync(panel->dev);
367 pm_runtime_put_autosuspend(panel->dev);
376 static int panel_simple_enable(struct drm_panel *panel)
378 struct panel_simple *p = to_panel_simple(panel);
383 if (p->desc->delay.enable)
384 msleep(p->desc->delay.enable);
391 static int panel_simple_get_modes(struct drm_panel *panel,
392 struct drm_connector *connector)
394 struct panel_simple *p = to_panel_simple(panel);
397 /* probe EDID if a DDC bus is available */
399 pm_runtime_get_sync(panel->dev);
402 p->edid = drm_get_edid(connector, p->ddc);
405 num += drm_add_edid_modes(connector, p->edid);
407 pm_runtime_mark_last_busy(panel->dev);
408 pm_runtime_put_autosuspend(panel->dev);
411 /* add hard-coded panel modes */
412 num += panel_simple_get_non_edid_modes(p, connector);
414 /* set up connector's "panel orientation" property */
415 drm_connector_set_panel_orientation(connector, p->orientation);
420 static int panel_simple_get_timings(struct drm_panel *panel,
421 unsigned int num_timings,
422 struct display_timing *timings)
424 struct panel_simple *p = to_panel_simple(panel);
427 if (p->desc->num_timings < num_timings)
428 num_timings = p->desc->num_timings;
431 for (i = 0; i < num_timings; i++)
432 timings[i] = p->desc->timings[i];
434 return p->desc->num_timings;
437 static const struct drm_panel_funcs panel_simple_funcs = {
438 .disable = panel_simple_disable,
439 .unprepare = panel_simple_unprepare,
440 .prepare = panel_simple_prepare,
441 .enable = panel_simple_enable,
442 .get_modes = panel_simple_get_modes,
443 .get_timings = panel_simple_get_timings,
446 static struct panel_desc panel_dpi;
448 static int panel_dpi_probe(struct device *dev,
449 struct panel_simple *panel)
451 struct display_timing *timing;
452 const struct device_node *np;
453 struct panel_desc *desc;
454 unsigned int bus_flags;
459 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
463 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
467 ret = of_get_display_timing(np, "panel-timing", timing);
469 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
474 desc->timings = timing;
475 desc->num_timings = 1;
477 of_property_read_u32(np, "width-mm", &desc->size.width);
478 of_property_read_u32(np, "height-mm", &desc->size.height);
480 /* Extract bus_flags from display_timing */
482 vm.flags = timing->flags;
483 drm_bus_flags_from_videomode(&vm, &bus_flags);
484 desc->bus_flags = bus_flags;
486 /* We do not know the connector for the DT node, so guess it */
487 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
494 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
495 (to_check->field.typ >= bounds->field.min && \
496 to_check->field.typ <= bounds->field.max)
497 static void panel_simple_parse_panel_timing_node(struct device *dev,
498 struct panel_simple *panel,
499 const struct display_timing *ot)
501 const struct panel_desc *desc = panel->desc;
505 if (WARN_ON(desc->num_modes)) {
506 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
509 if (WARN_ON(!desc->num_timings)) {
510 dev_err(dev, "Reject override mode: no timings specified\n");
514 for (i = 0; i < panel->desc->num_timings; i++) {
515 const struct display_timing *dt = &panel->desc->timings[i];
517 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
518 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
519 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
520 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
521 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
522 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
523 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
524 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
527 if (ot->flags != dt->flags)
530 videomode_from_timing(ot, &vm);
531 drm_display_mode_from_videomode(&vm, &panel->override_mode);
532 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
533 DRM_MODE_TYPE_PREFERRED;
537 if (WARN_ON(!panel->override_mode.type))
538 dev_err(dev, "Reject override mode: No display_timing found\n");
541 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
543 struct panel_simple *panel;
544 struct display_timing dt;
545 struct device_node *ddc;
550 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
554 panel->enabled = false;
555 panel->prepared_time = 0;
558 panel->supply = devm_regulator_get(dev, "power");
559 if (IS_ERR(panel->supply))
560 return PTR_ERR(panel->supply);
562 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
564 if (IS_ERR(panel->enable_gpio)) {
565 err = PTR_ERR(panel->enable_gpio);
566 if (err != -EPROBE_DEFER)
567 dev_err(dev, "failed to request GPIO: %d\n", err);
571 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
573 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
577 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
579 panel->ddc = of_find_i2c_adapter_by_node(ddc);
583 return -EPROBE_DEFER;
586 if (desc == &panel_dpi) {
587 /* Handle the generic panel-dpi binding */
588 err = panel_dpi_probe(dev, panel);
593 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
594 panel_simple_parse_panel_timing_node(dev, panel, &dt);
597 connector_type = desc->connector_type;
598 /* Catch common mistakes for panels. */
599 switch (connector_type) {
601 dev_warn(dev, "Specify missing connector_type\n");
602 connector_type = DRM_MODE_CONNECTOR_DPI;
604 case DRM_MODE_CONNECTOR_LVDS:
605 WARN_ON(desc->bus_flags &
606 ~(DRM_BUS_FLAG_DE_LOW |
607 DRM_BUS_FLAG_DE_HIGH |
608 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
609 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
610 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
611 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
612 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
613 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
615 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
616 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
619 case DRM_MODE_CONNECTOR_eDP:
620 dev_warn(dev, "eDP panels moved to panel-edp\n");
623 case DRM_MODE_CONNECTOR_DSI:
624 if (desc->bpc != 6 && desc->bpc != 8)
625 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
627 case DRM_MODE_CONNECTOR_DPI:
628 bus_flags = DRM_BUS_FLAG_DE_LOW |
629 DRM_BUS_FLAG_DE_HIGH |
630 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
631 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
632 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
633 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
634 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
635 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
636 if (desc->bus_flags & ~bus_flags)
637 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
638 if (!(desc->bus_flags & bus_flags))
639 dev_warn(dev, "Specify missing bus_flags\n");
640 if (desc->bus_format == 0)
641 dev_warn(dev, "Specify missing bus_format\n");
642 if (desc->bpc != 6 && desc->bpc != 8)
643 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
646 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
647 connector_type = DRM_MODE_CONNECTOR_DPI;
651 dev_set_drvdata(dev, panel);
654 * We use runtime PM for prepare / unprepare since those power the panel
655 * on and off and those can be very slow operations. This is important
656 * to optimize powering the panel on briefly to read the EDID before
657 * fully enabling the panel.
659 pm_runtime_enable(dev);
660 pm_runtime_set_autosuspend_delay(dev, 1000);
661 pm_runtime_use_autosuspend(dev);
663 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
665 err = drm_panel_of_backlight(&panel->base);
667 goto disable_pm_runtime;
669 drm_panel_add(&panel->base);
674 pm_runtime_dont_use_autosuspend(dev);
675 pm_runtime_disable(dev);
678 put_device(&panel->ddc->dev);
683 static int panel_simple_remove(struct device *dev)
685 struct panel_simple *panel = dev_get_drvdata(dev);
687 drm_panel_remove(&panel->base);
688 drm_panel_disable(&panel->base);
689 drm_panel_unprepare(&panel->base);
691 pm_runtime_dont_use_autosuspend(dev);
692 pm_runtime_disable(dev);
694 put_device(&panel->ddc->dev);
699 static void panel_simple_shutdown(struct device *dev)
701 struct panel_simple *panel = dev_get_drvdata(dev);
703 drm_panel_disable(&panel->base);
704 drm_panel_unprepare(&panel->base);
707 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
710 .hsync_start = 1280 + 40,
711 .hsync_end = 1280 + 40 + 80,
712 .htotal = 1280 + 40 + 80 + 40,
714 .vsync_start = 800 + 3,
715 .vsync_end = 800 + 3 + 10,
716 .vtotal = 800 + 3 + 10 + 10,
717 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
720 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
721 .modes = &ire_am_1280800n3tzqw_t00h_mode,
728 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
729 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
730 .connector_type = DRM_MODE_CONNECTOR_LVDS,
733 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
736 .hsync_start = 480 + 2,
737 .hsync_end = 480 + 2 + 41,
738 .htotal = 480 + 2 + 41 + 2,
740 .vsync_start = 272 + 2,
741 .vsync_end = 272 + 2 + 10,
742 .vtotal = 272 + 2 + 10 + 2,
743 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
746 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
747 .modes = &ire_am_480272h3tmqw_t01h_mode,
754 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
757 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
760 .hsync_start = 800 + 0,
761 .hsync_end = 800 + 0 + 255,
762 .htotal = 800 + 0 + 255 + 0,
764 .vsync_start = 480 + 2,
765 .vsync_end = 480 + 2 + 45,
766 .vtotal = 480 + 2 + 45 + 0,
767 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
770 static const struct panel_desc ampire_am800480r3tmqwa1h = {
771 .modes = &ire_am800480r3tmqwa1h_mode,
778 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
781 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
782 .pixelclock = { 26400000, 33300000, 46800000 },
783 .hactive = { 800, 800, 800 },
784 .hfront_porch = { 16, 210, 354 },
785 .hback_porch = { 45, 36, 6 },
786 .hsync_len = { 1, 10, 40 },
787 .vactive = { 480, 480, 480 },
788 .vfront_porch = { 7, 22, 147 },
789 .vback_porch = { 22, 13, 3 },
790 .vsync_len = { 1, 10, 20 },
791 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
792 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
795 static const struct panel_desc armadeus_st0700_adapt = {
796 .timings = &santek_st0700i5y_rbslw_f_timing,
803 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
807 static const struct drm_display_mode auo_b101aw03_mode = {
810 .hsync_start = 1024 + 156,
811 .hsync_end = 1024 + 156 + 8,
812 .htotal = 1024 + 156 + 8 + 156,
814 .vsync_start = 600 + 16,
815 .vsync_end = 600 + 16 + 6,
816 .vtotal = 600 + 16 + 6 + 16,
819 static const struct panel_desc auo_b101aw03 = {
820 .modes = &auo_b101aw03_mode,
827 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
828 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
829 .connector_type = DRM_MODE_CONNECTOR_LVDS,
832 static const struct drm_display_mode auo_b101xtn01_mode = {
835 .hsync_start = 1366 + 20,
836 .hsync_end = 1366 + 20 + 70,
837 .htotal = 1366 + 20 + 70,
839 .vsync_start = 768 + 14,
840 .vsync_end = 768 + 14 + 42,
841 .vtotal = 768 + 14 + 42,
842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
845 static const struct panel_desc auo_b101xtn01 = {
846 .modes = &auo_b101xtn01_mode,
855 static const struct display_timing auo_g070vvn01_timings = {
856 .pixelclock = { 33300000, 34209000, 45000000 },
857 .hactive = { 800, 800, 800 },
858 .hfront_porch = { 20, 40, 200 },
859 .hback_porch = { 87, 40, 1 },
860 .hsync_len = { 1, 48, 87 },
861 .vactive = { 480, 480, 480 },
862 .vfront_porch = { 5, 13, 200 },
863 .vback_porch = { 31, 31, 29 },
864 .vsync_len = { 1, 1, 3 },
867 static const struct panel_desc auo_g070vvn01 = {
868 .timings = &auo_g070vvn01_timings,
883 static const struct drm_display_mode auo_g101evn010_mode = {
886 .hsync_start = 1280 + 82,
887 .hsync_end = 1280 + 82 + 2,
888 .htotal = 1280 + 82 + 2 + 84,
890 .vsync_start = 800 + 8,
891 .vsync_end = 800 + 8 + 2,
892 .vtotal = 800 + 8 + 2 + 6,
895 static const struct panel_desc auo_g101evn010 = {
896 .modes = &auo_g101evn010_mode,
903 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
904 .connector_type = DRM_MODE_CONNECTOR_LVDS,
907 static const struct drm_display_mode auo_g104sn02_mode = {
910 .hsync_start = 800 + 40,
911 .hsync_end = 800 + 40 + 216,
912 .htotal = 800 + 40 + 216 + 128,
914 .vsync_start = 600 + 10,
915 .vsync_end = 600 + 10 + 35,
916 .vtotal = 600 + 10 + 35 + 2,
919 static const struct panel_desc auo_g104sn02 = {
920 .modes = &auo_g104sn02_mode,
927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
931 static const struct drm_display_mode auo_g121ean01_mode = {
934 .hsync_start = 1280 + 58,
935 .hsync_end = 1280 + 58 + 8,
936 .htotal = 1280 + 58 + 8 + 70,
938 .vsync_start = 800 + 6,
939 .vsync_end = 800 + 6 + 4,
940 .vtotal = 800 + 6 + 4 + 10,
943 static const struct panel_desc auo_g121ean01 = {
944 .modes = &auo_g121ean01_mode,
951 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
952 .connector_type = DRM_MODE_CONNECTOR_LVDS,
955 static const struct display_timing auo_g133han01_timings = {
956 .pixelclock = { 134000000, 141200000, 149000000 },
957 .hactive = { 1920, 1920, 1920 },
958 .hfront_porch = { 39, 58, 77 },
959 .hback_porch = { 59, 88, 117 },
960 .hsync_len = { 28, 42, 56 },
961 .vactive = { 1080, 1080, 1080 },
962 .vfront_porch = { 3, 8, 11 },
963 .vback_porch = { 5, 14, 19 },
964 .vsync_len = { 4, 14, 19 },
967 static const struct panel_desc auo_g133han01 = {
968 .timings = &auo_g133han01_timings,
981 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
982 .connector_type = DRM_MODE_CONNECTOR_LVDS,
985 static const struct drm_display_mode auo_g156xtn01_mode = {
988 .hsync_start = 1366 + 33,
989 .hsync_end = 1366 + 33 + 67,
992 .vsync_start = 768 + 4,
993 .vsync_end = 768 + 4 + 4,
997 static const struct panel_desc auo_g156xtn01 = {
998 .modes = &auo_g156xtn01_mode,
1005 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1006 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1009 static const struct display_timing auo_g185han01_timings = {
1010 .pixelclock = { 120000000, 144000000, 175000000 },
1011 .hactive = { 1920, 1920, 1920 },
1012 .hfront_porch = { 36, 120, 148 },
1013 .hback_porch = { 24, 88, 108 },
1014 .hsync_len = { 20, 48, 64 },
1015 .vactive = { 1080, 1080, 1080 },
1016 .vfront_porch = { 6, 10, 40 },
1017 .vback_porch = { 2, 5, 20 },
1018 .vsync_len = { 2, 5, 20 },
1021 static const struct panel_desc auo_g185han01 = {
1022 .timings = &auo_g185han01_timings,
1035 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1036 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1039 static const struct display_timing auo_g190ean01_timings = {
1040 .pixelclock = { 90000000, 108000000, 135000000 },
1041 .hactive = { 1280, 1280, 1280 },
1042 .hfront_porch = { 126, 184, 1266 },
1043 .hback_porch = { 84, 122, 844 },
1044 .hsync_len = { 70, 102, 704 },
1045 .vactive = { 1024, 1024, 1024 },
1046 .vfront_porch = { 4, 26, 76 },
1047 .vback_porch = { 2, 8, 25 },
1048 .vsync_len = { 2, 8, 25 },
1051 static const struct panel_desc auo_g190ean01 = {
1052 .timings = &auo_g190ean01_timings,
1065 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1066 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1069 static const struct display_timing auo_p320hvn03_timings = {
1070 .pixelclock = { 106000000, 148500000, 164000000 },
1071 .hactive = { 1920, 1920, 1920 },
1072 .hfront_porch = { 25, 50, 130 },
1073 .hback_porch = { 25, 50, 130 },
1074 .hsync_len = { 20, 40, 105 },
1075 .vactive = { 1080, 1080, 1080 },
1076 .vfront_porch = { 8, 17, 150 },
1077 .vback_porch = { 8, 17, 150 },
1078 .vsync_len = { 4, 11, 100 },
1081 static const struct panel_desc auo_p320hvn03 = {
1082 .timings = &auo_p320hvn03_timings,
1094 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1095 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1098 static const struct drm_display_mode auo_t215hvn01_mode = {
1101 .hsync_start = 1920 + 88,
1102 .hsync_end = 1920 + 88 + 44,
1103 .htotal = 1920 + 88 + 44 + 148,
1105 .vsync_start = 1080 + 4,
1106 .vsync_end = 1080 + 4 + 5,
1107 .vtotal = 1080 + 4 + 5 + 36,
1110 static const struct panel_desc auo_t215hvn01 = {
1111 .modes = &auo_t215hvn01_mode,
1124 static const struct drm_display_mode avic_tm070ddh03_mode = {
1127 .hsync_start = 1024 + 160,
1128 .hsync_end = 1024 + 160 + 4,
1129 .htotal = 1024 + 160 + 4 + 156,
1131 .vsync_start = 600 + 17,
1132 .vsync_end = 600 + 17 + 1,
1133 .vtotal = 600 + 17 + 1 + 17,
1136 static const struct panel_desc avic_tm070ddh03 = {
1137 .modes = &avic_tm070ddh03_mode,
1151 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1154 .hsync_start = 800 + 40,
1155 .hsync_end = 800 + 40 + 48,
1156 .htotal = 800 + 40 + 48 + 40,
1158 .vsync_start = 480 + 13,
1159 .vsync_end = 480 + 13 + 3,
1160 .vtotal = 480 + 13 + 3 + 29,
1163 static const struct panel_desc bananapi_s070wv20_ct16 = {
1164 .modes = &bananapi_s070wv20_ct16_mode,
1173 static const struct drm_display_mode boe_hv070wsa_mode = {
1176 .hsync_start = 1024 + 30,
1177 .hsync_end = 1024 + 30 + 30,
1178 .htotal = 1024 + 30 + 30 + 30,
1180 .vsync_start = 600 + 10,
1181 .vsync_end = 600 + 10 + 10,
1182 .vtotal = 600 + 10 + 10 + 10,
1185 static const struct panel_desc boe_hv070wsa = {
1186 .modes = &boe_hv070wsa_mode,
1193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1194 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1195 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1198 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1201 .hsync_start = 480 + 5,
1202 .hsync_end = 480 + 5 + 5,
1203 .htotal = 480 + 5 + 5 + 40,
1205 .vsync_start = 272 + 8,
1206 .vsync_end = 272 + 8 + 8,
1207 .vtotal = 272 + 8 + 8 + 8,
1208 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1211 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1212 .modes = &cdtech_s043wq26h_ct7_mode,
1219 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1222 /* S070PWS19HP-FC21 2017/04/22 */
1223 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1226 .hsync_start = 1024 + 160,
1227 .hsync_end = 1024 + 160 + 20,
1228 .htotal = 1024 + 160 + 20 + 140,
1230 .vsync_start = 600 + 12,
1231 .vsync_end = 600 + 12 + 3,
1232 .vtotal = 600 + 12 + 3 + 20,
1233 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1236 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1237 .modes = &cdtech_s070pws19hp_fc21_mode,
1244 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1245 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1246 .connector_type = DRM_MODE_CONNECTOR_DPI,
1249 /* S070SWV29HG-DC44 2017/09/21 */
1250 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1253 .hsync_start = 800 + 210,
1254 .hsync_end = 800 + 210 + 2,
1255 .htotal = 800 + 210 + 2 + 44,
1257 .vsync_start = 480 + 22,
1258 .vsync_end = 480 + 22 + 2,
1259 .vtotal = 480 + 22 + 2 + 21,
1260 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1263 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1264 .modes = &cdtech_s070swv29hg_dc44_mode,
1271 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1272 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1273 .connector_type = DRM_MODE_CONNECTOR_DPI,
1276 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1279 .hsync_start = 800 + 40,
1280 .hsync_end = 800 + 40 + 40,
1281 .htotal = 800 + 40 + 40 + 48,
1283 .vsync_start = 480 + 29,
1284 .vsync_end = 480 + 29 + 13,
1285 .vtotal = 480 + 29 + 13 + 3,
1286 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1289 static const struct panel_desc cdtech_s070wv95_ct16 = {
1290 .modes = &cdtech_s070wv95_ct16_mode,
1299 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1300 .pixelclock = { 68900000, 71100000, 73400000 },
1301 .hactive = { 1280, 1280, 1280 },
1302 .hfront_porch = { 65, 80, 95 },
1303 .hback_porch = { 64, 79, 94 },
1304 .hsync_len = { 1, 1, 1 },
1305 .vactive = { 800, 800, 800 },
1306 .vfront_porch = { 7, 11, 14 },
1307 .vback_porch = { 7, 11, 14 },
1308 .vsync_len = { 1, 1, 1 },
1309 .flags = DISPLAY_FLAGS_DE_HIGH,
1312 static const struct panel_desc chefree_ch101olhlwh_002 = {
1313 .timings = &chefree_ch101olhlwh_002_timing,
1324 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1326 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1329 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1332 .hsync_start = 800 + 49,
1333 .hsync_end = 800 + 49 + 33,
1334 .htotal = 800 + 49 + 33 + 17,
1336 .vsync_start = 1280 + 1,
1337 .vsync_end = 1280 + 1 + 7,
1338 .vtotal = 1280 + 1 + 7 + 15,
1339 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1342 static const struct panel_desc chunghwa_claa070wp03xg = {
1343 .modes = &chunghwa_claa070wp03xg_mode,
1350 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1351 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1352 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1355 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1358 .hsync_start = 1366 + 58,
1359 .hsync_end = 1366 + 58 + 58,
1360 .htotal = 1366 + 58 + 58 + 58,
1362 .vsync_start = 768 + 4,
1363 .vsync_end = 768 + 4 + 4,
1364 .vtotal = 768 + 4 + 4 + 4,
1367 static const struct panel_desc chunghwa_claa101wa01a = {
1368 .modes = &chunghwa_claa101wa01a_mode,
1375 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1376 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1377 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1380 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1383 .hsync_start = 1366 + 48,
1384 .hsync_end = 1366 + 48 + 32,
1385 .htotal = 1366 + 48 + 32 + 20,
1387 .vsync_start = 768 + 16,
1388 .vsync_end = 768 + 16 + 8,
1389 .vtotal = 768 + 16 + 8 + 16,
1392 static const struct panel_desc chunghwa_claa101wb01 = {
1393 .modes = &chunghwa_claa101wb01_mode,
1400 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1401 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1402 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1405 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1406 .pixelclock = { 5000000, 9000000, 12000000 },
1407 .hactive = { 480, 480, 480 },
1408 .hfront_porch = { 12, 12, 12 },
1409 .hback_porch = { 12, 12, 12 },
1410 .hsync_len = { 21, 21, 21 },
1411 .vactive = { 272, 272, 272 },
1412 .vfront_porch = { 4, 4, 4 },
1413 .vback_porch = { 4, 4, 4 },
1414 .vsync_len = { 8, 8, 8 },
1417 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1418 .timings = &dataimage_fg040346dsswbg04_timing,
1425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1426 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1427 .connector_type = DRM_MODE_CONNECTOR_DPI,
1430 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1433 .hsync_start = 800 + 40,
1434 .hsync_end = 800 + 40 + 128,
1435 .htotal = 800 + 40 + 128 + 88,
1437 .vsync_start = 480 + 10,
1438 .vsync_end = 480 + 10 + 2,
1439 .vtotal = 480 + 10 + 2 + 33,
1440 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1443 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1444 .modes = &dataimage_scf0700c48ggu18_mode,
1451 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1452 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1455 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1456 .pixelclock = { 45000000, 51200000, 57000000 },
1457 .hactive = { 1024, 1024, 1024 },
1458 .hfront_porch = { 100, 106, 113 },
1459 .hback_porch = { 100, 106, 113 },
1460 .hsync_len = { 100, 108, 114 },
1461 .vactive = { 600, 600, 600 },
1462 .vfront_porch = { 8, 11, 15 },
1463 .vback_porch = { 8, 11, 15 },
1464 .vsync_len = { 9, 13, 15 },
1465 .flags = DISPLAY_FLAGS_DE_HIGH,
1468 static const struct panel_desc dlc_dlc0700yzg_1 = {
1469 .timings = &dlc_dlc0700yzg_1_timing,
1481 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1482 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1485 static const struct display_timing dlc_dlc1010gig_timing = {
1486 .pixelclock = { 68900000, 71100000, 73400000 },
1487 .hactive = { 1280, 1280, 1280 },
1488 .hfront_porch = { 43, 53, 63 },
1489 .hback_porch = { 43, 53, 63 },
1490 .hsync_len = { 44, 54, 64 },
1491 .vactive = { 800, 800, 800 },
1492 .vfront_porch = { 5, 8, 11 },
1493 .vback_porch = { 5, 8, 11 },
1494 .vsync_len = { 5, 7, 11 },
1495 .flags = DISPLAY_FLAGS_DE_HIGH,
1498 static const struct panel_desc dlc_dlc1010gig = {
1499 .timings = &dlc_dlc1010gig_timing,
1512 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1513 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1516 static const struct drm_display_mode edt_et035012dm6_mode = {
1519 .hsync_start = 320 + 20,
1520 .hsync_end = 320 + 20 + 30,
1521 .htotal = 320 + 20 + 68,
1523 .vsync_start = 240 + 4,
1524 .vsync_end = 240 + 4 + 4,
1525 .vtotal = 240 + 4 + 4 + 14,
1526 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1529 static const struct panel_desc edt_et035012dm6 = {
1530 .modes = &edt_et035012dm6_mode,
1537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1538 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1541 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1544 .hsync_start = 320 + 20,
1545 .hsync_end = 320 + 20 + 68,
1546 .htotal = 320 + 20 + 68,
1548 .vsync_start = 240 + 4,
1549 .vsync_end = 240 + 4 + 18,
1550 .vtotal = 240 + 4 + 18,
1551 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1554 static const struct panel_desc edt_etm0350g0dh6 = {
1555 .modes = &edt_etm0350g0dh6_mode,
1562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1564 .connector_type = DRM_MODE_CONNECTOR_DPI,
1567 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1570 .hsync_start = 480 + 8,
1571 .hsync_end = 480 + 8 + 4,
1572 .htotal = 480 + 8 + 4 + 41,
1575 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1580 .vsync_start = 288 + 2,
1581 .vsync_end = 288 + 2 + 4,
1582 .vtotal = 288 + 2 + 4 + 10,
1585 static const struct panel_desc edt_etm043080dh6gp = {
1586 .modes = &edt_etm043080dh6gp_mode,
1593 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1594 .connector_type = DRM_MODE_CONNECTOR_DPI,
1597 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1600 .hsync_start = 480 + 2,
1601 .hsync_end = 480 + 2 + 41,
1602 .htotal = 480 + 2 + 41 + 2,
1604 .vsync_start = 272 + 2,
1605 .vsync_end = 272 + 2 + 10,
1606 .vtotal = 272 + 2 + 10 + 2,
1607 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1610 static const struct panel_desc edt_etm0430g0dh6 = {
1611 .modes = &edt_etm0430g0dh6_mode,
1618 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1620 .connector_type = DRM_MODE_CONNECTOR_DPI,
1623 static const struct drm_display_mode edt_et057090dhu_mode = {
1626 .hsync_start = 640 + 16,
1627 .hsync_end = 640 + 16 + 30,
1628 .htotal = 640 + 16 + 30 + 114,
1630 .vsync_start = 480 + 10,
1631 .vsync_end = 480 + 10 + 3,
1632 .vtotal = 480 + 10 + 3 + 32,
1633 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1636 static const struct panel_desc edt_et057090dhu = {
1637 .modes = &edt_et057090dhu_mode,
1644 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1645 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1646 .connector_type = DRM_MODE_CONNECTOR_DPI,
1649 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1652 .hsync_start = 800 + 40,
1653 .hsync_end = 800 + 40 + 128,
1654 .htotal = 800 + 40 + 128 + 88,
1656 .vsync_start = 480 + 10,
1657 .vsync_end = 480 + 10 + 2,
1658 .vtotal = 480 + 10 + 2 + 33,
1659 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1662 static const struct panel_desc edt_etm0700g0dh6 = {
1663 .modes = &edt_etm0700g0dh6_mode,
1670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1672 .connector_type = DRM_MODE_CONNECTOR_DPI,
1675 static const struct panel_desc edt_etm0700g0bdh6 = {
1676 .modes = &edt_etm0700g0dh6_mode,
1683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1685 .connector_type = DRM_MODE_CONNECTOR_DPI,
1688 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1692 .hsync_end = 640 + 16,
1693 .htotal = 640 + 16 + 30 + 114,
1695 .vsync_start = 480 + 10,
1696 .vsync_end = 480 + 10 + 3,
1697 .vtotal = 480 + 10 + 3 + 35,
1698 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1701 static const struct panel_desc edt_etmv570g2dhu = {
1702 .modes = &edt_etmv570g2dhu_mode,
1709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1710 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1711 .connector_type = DRM_MODE_CONNECTOR_DPI,
1714 static const struct display_timing eink_vb3300_kca_timing = {
1715 .pixelclock = { 40000000, 40000000, 40000000 },
1716 .hactive = { 334, 334, 334 },
1717 .hfront_porch = { 1, 1, 1 },
1718 .hback_porch = { 1, 1, 1 },
1719 .hsync_len = { 1, 1, 1 },
1720 .vactive = { 1405, 1405, 1405 },
1721 .vfront_porch = { 1, 1, 1 },
1722 .vback_porch = { 1, 1, 1 },
1723 .vsync_len = { 1, 1, 1 },
1724 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1725 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1728 static const struct panel_desc eink_vb3300_kca = {
1729 .timings = &eink_vb3300_kca_timing,
1736 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1737 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1738 .connector_type = DRM_MODE_CONNECTOR_DPI,
1741 static const struct display_timing evervision_vgg804821_timing = {
1742 .pixelclock = { 27600000, 33300000, 50000000 },
1743 .hactive = { 800, 800, 800 },
1744 .hfront_porch = { 40, 66, 70 },
1745 .hback_porch = { 40, 67, 70 },
1746 .hsync_len = { 40, 67, 70 },
1747 .vactive = { 480, 480, 480 },
1748 .vfront_porch = { 6, 10, 10 },
1749 .vback_porch = { 7, 11, 11 },
1750 .vsync_len = { 7, 11, 11 },
1751 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1752 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1753 DISPLAY_FLAGS_SYNC_NEGEDGE,
1756 static const struct panel_desc evervision_vgg804821 = {
1757 .timings = &evervision_vgg804821_timing,
1764 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1768 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1771 .hsync_start = 800 + 168,
1772 .hsync_end = 800 + 168 + 64,
1773 .htotal = 800 + 168 + 64 + 88,
1775 .vsync_start = 480 + 37,
1776 .vsync_end = 480 + 37 + 2,
1777 .vtotal = 480 + 37 + 2 + 8,
1780 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1781 .modes = &foxlink_fl500wvr00_a0t_mode,
1788 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1791 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1795 .hsync_start = 320 + 44,
1796 .hsync_end = 320 + 44 + 16,
1797 .htotal = 320 + 44 + 16 + 20,
1799 .vsync_start = 240 + 2,
1800 .vsync_end = 240 + 2 + 6,
1801 .vtotal = 240 + 2 + 6 + 2,
1802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1807 .hsync_start = 320 + 56,
1808 .hsync_end = 320 + 56 + 16,
1809 .htotal = 320 + 56 + 16 + 40,
1811 .vsync_start = 240 + 2,
1812 .vsync_end = 240 + 2 + 6,
1813 .vtotal = 240 + 2 + 6 + 2,
1814 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1818 static const struct panel_desc frida_frd350h54004 = {
1819 .modes = frida_frd350h54004_modes,
1820 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1826 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1828 .connector_type = DRM_MODE_CONNECTOR_DPI,
1831 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1834 .hsync_start = 800 + 20,
1835 .hsync_end = 800 + 20 + 24,
1836 .htotal = 800 + 20 + 24 + 20,
1838 .vsync_start = 1280 + 4,
1839 .vsync_end = 1280 + 4 + 8,
1840 .vtotal = 1280 + 4 + 8 + 4,
1841 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1844 static const struct panel_desc friendlyarm_hd702e = {
1845 .modes = &friendlyarm_hd702e_mode,
1853 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1856 .hsync_start = 480 + 5,
1857 .hsync_end = 480 + 5 + 1,
1858 .htotal = 480 + 5 + 1 + 40,
1860 .vsync_start = 272 + 8,
1861 .vsync_end = 272 + 8 + 1,
1862 .vtotal = 272 + 8 + 1 + 8,
1865 static const struct panel_desc giantplus_gpg482739qs5 = {
1866 .modes = &giantplus_gpg482739qs5_mode,
1873 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1876 static const struct display_timing giantplus_gpm940b0_timing = {
1877 .pixelclock = { 13500000, 27000000, 27500000 },
1878 .hactive = { 320, 320, 320 },
1879 .hfront_porch = { 14, 686, 718 },
1880 .hback_porch = { 50, 70, 255 },
1881 .hsync_len = { 1, 1, 1 },
1882 .vactive = { 240, 240, 240 },
1883 .vfront_porch = { 1, 1, 179 },
1884 .vback_porch = { 1, 21, 31 },
1885 .vsync_len = { 1, 1, 6 },
1886 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1889 static const struct panel_desc giantplus_gpm940b0 = {
1890 .timings = &giantplus_gpm940b0_timing,
1897 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1898 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1901 static const struct display_timing hannstar_hsd070pww1_timing = {
1902 .pixelclock = { 64300000, 71100000, 82000000 },
1903 .hactive = { 1280, 1280, 1280 },
1904 .hfront_porch = { 1, 1, 10 },
1905 .hback_porch = { 1, 1, 10 },
1907 * According to the data sheet, the minimum horizontal blanking interval
1908 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1909 * minimum working horizontal blanking interval to be 60 clocks.
1911 .hsync_len = { 58, 158, 661 },
1912 .vactive = { 800, 800, 800 },
1913 .vfront_porch = { 1, 1, 10 },
1914 .vback_porch = { 1, 1, 10 },
1915 .vsync_len = { 1, 21, 203 },
1916 .flags = DISPLAY_FLAGS_DE_HIGH,
1919 static const struct panel_desc hannstar_hsd070pww1 = {
1920 .timings = &hannstar_hsd070pww1_timing,
1927 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1931 static const struct display_timing hannstar_hsd100pxn1_timing = {
1932 .pixelclock = { 55000000, 65000000, 75000000 },
1933 .hactive = { 1024, 1024, 1024 },
1934 .hfront_porch = { 40, 40, 40 },
1935 .hback_porch = { 220, 220, 220 },
1936 .hsync_len = { 20, 60, 100 },
1937 .vactive = { 768, 768, 768 },
1938 .vfront_porch = { 7, 7, 7 },
1939 .vback_porch = { 21, 21, 21 },
1940 .vsync_len = { 10, 10, 10 },
1941 .flags = DISPLAY_FLAGS_DE_HIGH,
1944 static const struct panel_desc hannstar_hsd100pxn1 = {
1945 .timings = &hannstar_hsd100pxn1_timing,
1952 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1953 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1956 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1959 .hsync_start = 800 + 85,
1960 .hsync_end = 800 + 85 + 86,
1961 .htotal = 800 + 85 + 86 + 85,
1963 .vsync_start = 480 + 16,
1964 .vsync_end = 480 + 16 + 13,
1965 .vtotal = 480 + 16 + 13 + 16,
1968 static const struct panel_desc hitachi_tx23d38vm0caa = {
1969 .modes = &hitachi_tx23d38vm0caa_mode,
1982 static const struct drm_display_mode innolux_at043tn24_mode = {
1985 .hsync_start = 480 + 2,
1986 .hsync_end = 480 + 2 + 41,
1987 .htotal = 480 + 2 + 41 + 2,
1989 .vsync_start = 272 + 2,
1990 .vsync_end = 272 + 2 + 10,
1991 .vtotal = 272 + 2 + 10 + 2,
1992 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1995 static const struct panel_desc innolux_at043tn24 = {
1996 .modes = &innolux_at043tn24_mode,
2003 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2004 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2007 static const struct drm_display_mode innolux_at070tn92_mode = {
2010 .hsync_start = 800 + 210,
2011 .hsync_end = 800 + 210 + 20,
2012 .htotal = 800 + 210 + 20 + 46,
2014 .vsync_start = 480 + 22,
2015 .vsync_end = 480 + 22 + 10,
2016 .vtotal = 480 + 22 + 23 + 10,
2019 static const struct panel_desc innolux_at070tn92 = {
2020 .modes = &innolux_at070tn92_mode,
2026 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2029 static const struct display_timing innolux_g070y2_l01_timing = {
2030 .pixelclock = { 28000000, 29500000, 32000000 },
2031 .hactive = { 800, 800, 800 },
2032 .hfront_porch = { 61, 91, 141 },
2033 .hback_porch = { 60, 90, 140 },
2034 .hsync_len = { 12, 12, 12 },
2035 .vactive = { 480, 480, 480 },
2036 .vfront_porch = { 4, 9, 30 },
2037 .vback_porch = { 4, 8, 28 },
2038 .vsync_len = { 2, 2, 2 },
2039 .flags = DISPLAY_FLAGS_DE_HIGH,
2042 static const struct panel_desc innolux_g070y2_l01 = {
2043 .timings = &innolux_g070y2_l01_timing,
2056 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2057 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2058 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2061 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2064 .hsync_start = 800 + 210,
2065 .hsync_end = 800 + 210 + 20,
2066 .htotal = 800 + 210 + 20 + 46,
2068 .vsync_start = 480 + 22,
2069 .vsync_end = 480 + 22 + 10,
2070 .vtotal = 480 + 22 + 23 + 10,
2073 static const struct panel_desc innolux_g070y2_t02 = {
2074 .modes = &innolux_g070y2_t02_mode,
2081 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2082 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2083 .connector_type = DRM_MODE_CONNECTOR_DPI,
2086 static const struct display_timing innolux_g101ice_l01_timing = {
2087 .pixelclock = { 60400000, 71100000, 74700000 },
2088 .hactive = { 1280, 1280, 1280 },
2089 .hfront_porch = { 41, 80, 100 },
2090 .hback_porch = { 40, 79, 99 },
2091 .hsync_len = { 1, 1, 1 },
2092 .vactive = { 800, 800, 800 },
2093 .vfront_porch = { 5, 11, 14 },
2094 .vback_porch = { 4, 11, 14 },
2095 .vsync_len = { 1, 1, 1 },
2096 .flags = DISPLAY_FLAGS_DE_HIGH,
2099 static const struct panel_desc innolux_g101ice_l01 = {
2100 .timings = &innolux_g101ice_l01_timing,
2111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2112 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2115 static const struct display_timing innolux_g121i1_l01_timing = {
2116 .pixelclock = { 67450000, 71000000, 74550000 },
2117 .hactive = { 1280, 1280, 1280 },
2118 .hfront_porch = { 40, 80, 160 },
2119 .hback_porch = { 39, 79, 159 },
2120 .hsync_len = { 1, 1, 1 },
2121 .vactive = { 800, 800, 800 },
2122 .vfront_porch = { 5, 11, 100 },
2123 .vback_porch = { 4, 11, 99 },
2124 .vsync_len = { 1, 1, 1 },
2127 static const struct panel_desc innolux_g121i1_l01 = {
2128 .timings = &innolux_g121i1_l01_timing,
2139 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2140 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2143 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2146 .hsync_start = 1024 + 0,
2147 .hsync_end = 1024 + 1,
2148 .htotal = 1024 + 0 + 1 + 320,
2150 .vsync_start = 768 + 38,
2151 .vsync_end = 768 + 38 + 1,
2152 .vtotal = 768 + 38 + 1 + 0,
2153 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2156 static const struct panel_desc innolux_g121x1_l03 = {
2157 .modes = &innolux_g121x1_l03_mode,
2171 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2174 .hsync_start = 1366 + 16,
2175 .hsync_end = 1366 + 16 + 34,
2176 .htotal = 1366 + 16 + 34 + 50,
2178 .vsync_start = 768 + 2,
2179 .vsync_end = 768 + 2 + 6,
2180 .vtotal = 768 + 2 + 6 + 12,
2183 static const struct panel_desc innolux_n156bge_l21 = {
2184 .modes = &innolux_n156bge_l21_mode,
2191 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2192 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2193 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2196 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2199 .hsync_start = 1024 + 128,
2200 .hsync_end = 1024 + 128 + 64,
2201 .htotal = 1024 + 128 + 64 + 128,
2203 .vsync_start = 600 + 16,
2204 .vsync_end = 600 + 16 + 4,
2205 .vtotal = 600 + 16 + 4 + 16,
2208 static const struct panel_desc innolux_zj070na_01p = {
2209 .modes = &innolux_zj070na_01p_mode,
2218 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2219 .pixelclock = { 5580000, 5850000, 6200000 },
2220 .hactive = { 320, 320, 320 },
2221 .hfront_porch = { 30, 30, 30 },
2222 .hback_porch = { 30, 30, 30 },
2223 .hsync_len = { 1, 5, 17 },
2224 .vactive = { 240, 240, 240 },
2225 .vfront_porch = { 6, 6, 6 },
2226 .vback_porch = { 5, 5, 5 },
2227 .vsync_len = { 1, 2, 11 },
2228 .flags = DISPLAY_FLAGS_DE_HIGH,
2231 static const struct panel_desc koe_tx14d24vm1bpa = {
2232 .timings = &koe_tx14d24vm1bpa_timing,
2241 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2242 .pixelclock = { 151820000, 156720000, 159780000 },
2243 .hactive = { 1920, 1920, 1920 },
2244 .hfront_porch = { 105, 130, 142 },
2245 .hback_porch = { 45, 70, 82 },
2246 .hsync_len = { 30, 30, 30 },
2247 .vactive = { 1200, 1200, 1200},
2248 .vfront_porch = { 3, 5, 10 },
2249 .vback_porch = { 2, 5, 10 },
2250 .vsync_len = { 5, 5, 5 },
2253 static const struct panel_desc koe_tx26d202vm0bwa = {
2254 .timings = &koe_tx26d202vm0bwa_timing,
2267 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2268 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2269 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2272 static const struct display_timing koe_tx31d200vm0baa_timing = {
2273 .pixelclock = { 39600000, 43200000, 48000000 },
2274 .hactive = { 1280, 1280, 1280 },
2275 .hfront_porch = { 16, 36, 56 },
2276 .hback_porch = { 16, 36, 56 },
2277 .hsync_len = { 8, 8, 8 },
2278 .vactive = { 480, 480, 480 },
2279 .vfront_porch = { 6, 21, 33 },
2280 .vback_porch = { 6, 21, 33 },
2281 .vsync_len = { 8, 8, 8 },
2282 .flags = DISPLAY_FLAGS_DE_HIGH,
2285 static const struct panel_desc koe_tx31d200vm0baa = {
2286 .timings = &koe_tx31d200vm0baa_timing,
2293 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2294 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2297 static const struct display_timing kyo_tcg121xglp_timing = {
2298 .pixelclock = { 52000000, 65000000, 71000000 },
2299 .hactive = { 1024, 1024, 1024 },
2300 .hfront_porch = { 2, 2, 2 },
2301 .hback_porch = { 2, 2, 2 },
2302 .hsync_len = { 86, 124, 244 },
2303 .vactive = { 768, 768, 768 },
2304 .vfront_porch = { 2, 2, 2 },
2305 .vback_porch = { 2, 2, 2 },
2306 .vsync_len = { 6, 34, 73 },
2307 .flags = DISPLAY_FLAGS_DE_HIGH,
2310 static const struct panel_desc kyo_tcg121xglp = {
2311 .timings = &kyo_tcg121xglp_timing,
2318 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2319 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2322 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2325 .hsync_start = 320 + 20,
2326 .hsync_end = 320 + 20 + 30,
2327 .htotal = 320 + 20 + 30 + 38,
2329 .vsync_start = 240 + 4,
2330 .vsync_end = 240 + 4 + 3,
2331 .vtotal = 240 + 4 + 3 + 15,
2334 static const struct panel_desc lemaker_bl035_rgb_002 = {
2335 .modes = &lemaker_bl035_rgb_002_mode,
2341 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2342 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2345 static const struct drm_display_mode lg_lb070wv8_mode = {
2348 .hsync_start = 800 + 88,
2349 .hsync_end = 800 + 88 + 80,
2350 .htotal = 800 + 88 + 80 + 88,
2352 .vsync_start = 480 + 10,
2353 .vsync_end = 480 + 10 + 25,
2354 .vtotal = 480 + 10 + 25 + 10,
2357 static const struct panel_desc lg_lb070wv8 = {
2358 .modes = &lg_lb070wv8_mode,
2365 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2366 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2369 static const struct display_timing logictechno_lt161010_2nh_timing = {
2370 .pixelclock = { 26400000, 33300000, 46800000 },
2371 .hactive = { 800, 800, 800 },
2372 .hfront_porch = { 16, 210, 354 },
2373 .hback_porch = { 46, 46, 46 },
2374 .hsync_len = { 1, 20, 40 },
2375 .vactive = { 480, 480, 480 },
2376 .vfront_porch = { 7, 22, 147 },
2377 .vback_porch = { 23, 23, 23 },
2378 .vsync_len = { 1, 10, 20 },
2379 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2380 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2381 DISPLAY_FLAGS_SYNC_POSEDGE,
2384 static const struct panel_desc logictechno_lt161010_2nh = {
2385 .timings = &logictechno_lt161010_2nh_timing,
2391 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2392 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2393 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2394 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2395 .connector_type = DRM_MODE_CONNECTOR_DPI,
2398 static const struct display_timing logictechno_lt170410_2whc_timing = {
2399 .pixelclock = { 68900000, 71100000, 73400000 },
2400 .hactive = { 1280, 1280, 1280 },
2401 .hfront_porch = { 23, 60, 71 },
2402 .hback_porch = { 23, 60, 71 },
2403 .hsync_len = { 15, 40, 47 },
2404 .vactive = { 800, 800, 800 },
2405 .vfront_porch = { 5, 7, 10 },
2406 .vback_porch = { 5, 7, 10 },
2407 .vsync_len = { 6, 9, 12 },
2408 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2409 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2410 DISPLAY_FLAGS_SYNC_POSEDGE,
2413 static const struct panel_desc logictechno_lt170410_2whc = {
2414 .timings = &logictechno_lt170410_2whc_timing,
2420 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2421 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2422 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2425 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2428 .hsync_start = 800 + 112,
2429 .hsync_end = 800 + 112 + 3,
2430 .htotal = 800 + 112 + 3 + 85,
2432 .vsync_start = 480 + 38,
2433 .vsync_end = 480 + 38 + 3,
2434 .vtotal = 480 + 38 + 3 + 29,
2435 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2438 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2439 .modes = &logictechno_lttd800480070_l2rt_mode,
2452 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2453 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2454 .connector_type = DRM_MODE_CONNECTOR_DPI,
2457 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2460 .hsync_start = 800 + 154,
2461 .hsync_end = 800 + 154 + 3,
2462 .htotal = 800 + 154 + 3 + 43,
2464 .vsync_start = 480 + 47,
2465 .vsync_end = 480 + 47 + 3,
2466 .vtotal = 480 + 47 + 3 + 20,
2467 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2470 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2471 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2484 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2485 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2486 .connector_type = DRM_MODE_CONNECTOR_DPI,
2489 static const struct drm_display_mode logicpd_type_28_mode = {
2492 .hsync_start = 480 + 3,
2493 .hsync_end = 480 + 3 + 42,
2494 .htotal = 480 + 3 + 42 + 2,
2497 .vsync_start = 272 + 2,
2498 .vsync_end = 272 + 2 + 11,
2499 .vtotal = 272 + 2 + 11 + 3,
2500 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2503 static const struct panel_desc logicpd_type_28 = {
2504 .modes = &logicpd_type_28_mode,
2517 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2518 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2519 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2520 .connector_type = DRM_MODE_CONNECTOR_DPI,
2523 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2526 .hsync_start = 800 + 0,
2527 .hsync_end = 800 + 1,
2528 .htotal = 800 + 0 + 1 + 160,
2530 .vsync_start = 480 + 0,
2531 .vsync_end = 480 + 48 + 1,
2532 .vtotal = 480 + 48 + 1 + 0,
2533 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2536 static const struct panel_desc mitsubishi_aa070mc01 = {
2537 .modes = &mitsubishi_aa070mc01_mode,
2550 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2551 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2552 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2555 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2556 .pixelclock = { 29000000, 33000000, 38000000 },
2557 .hactive = { 800, 800, 800 },
2558 .hfront_porch = { 180, 210, 240 },
2559 .hback_porch = { 16, 16, 16 },
2560 .hsync_len = { 30, 30, 30 },
2561 .vactive = { 480, 480, 480 },
2562 .vfront_porch = { 12, 22, 32 },
2563 .vback_porch = { 10, 10, 10 },
2564 .vsync_len = { 13, 13, 13 },
2565 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2566 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2567 DISPLAY_FLAGS_SYNC_POSEDGE,
2570 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2571 .timings = &multi_inno_mi0700s4t_6_timing,
2578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2579 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2580 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2581 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2582 .connector_type = DRM_MODE_CONNECTOR_DPI,
2585 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2586 .pixelclock = { 68900000, 70000000, 73400000 },
2587 .hactive = { 1280, 1280, 1280 },
2588 .hfront_porch = { 30, 60, 71 },
2589 .hback_porch = { 30, 60, 71 },
2590 .hsync_len = { 10, 10, 48 },
2591 .vactive = { 800, 800, 800 },
2592 .vfront_porch = { 5, 10, 10 },
2593 .vback_porch = { 5, 10, 10 },
2594 .vsync_len = { 5, 6, 13 },
2595 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2596 DISPLAY_FLAGS_DE_HIGH,
2599 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2600 .timings = &multi_inno_mi1010ait_1cp_timing,
2611 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2612 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2613 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2616 static const struct display_timing nec_nl12880bc20_05_timing = {
2617 .pixelclock = { 67000000, 71000000, 75000000 },
2618 .hactive = { 1280, 1280, 1280 },
2619 .hfront_porch = { 2, 30, 30 },
2620 .hback_porch = { 6, 100, 100 },
2621 .hsync_len = { 2, 30, 30 },
2622 .vactive = { 800, 800, 800 },
2623 .vfront_porch = { 5, 5, 5 },
2624 .vback_porch = { 11, 11, 11 },
2625 .vsync_len = { 7, 7, 7 },
2628 static const struct panel_desc nec_nl12880bc20_05 = {
2629 .timings = &nec_nl12880bc20_05_timing,
2640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2641 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2644 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2647 .hsync_start = 480 + 2,
2648 .hsync_end = 480 + 2 + 41,
2649 .htotal = 480 + 2 + 41 + 2,
2651 .vsync_start = 272 + 2,
2652 .vsync_end = 272 + 2 + 4,
2653 .vtotal = 272 + 2 + 4 + 2,
2654 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2657 static const struct panel_desc nec_nl4827hc19_05b = {
2658 .modes = &nec_nl4827hc19_05b_mode,
2665 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2666 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2669 static const struct drm_display_mode netron_dy_e231732_mode = {
2672 .hsync_start = 1024 + 160,
2673 .hsync_end = 1024 + 160 + 70,
2674 .htotal = 1024 + 160 + 70 + 90,
2676 .vsync_start = 600 + 127,
2677 .vsync_end = 600 + 127 + 20,
2678 .vtotal = 600 + 127 + 20 + 3,
2681 static const struct panel_desc netron_dy_e231732 = {
2682 .modes = &netron_dy_e231732_mode,
2688 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2691 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2694 .hsync_start = 480 + 2,
2695 .hsync_end = 480 + 2 + 41,
2696 .htotal = 480 + 2 + 41 + 2,
2698 .vsync_start = 272 + 2,
2699 .vsync_end = 272 + 2 + 10,
2700 .vtotal = 272 + 2 + 10 + 2,
2701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2704 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2705 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2713 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2714 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2715 .connector_type = DRM_MODE_CONNECTOR_DPI,
2718 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2719 .pixelclock = { 130000000, 148350000, 163000000 },
2720 .hactive = { 1920, 1920, 1920 },
2721 .hfront_porch = { 80, 100, 100 },
2722 .hback_porch = { 100, 120, 120 },
2723 .hsync_len = { 50, 60, 60 },
2724 .vactive = { 1080, 1080, 1080 },
2725 .vfront_porch = { 12, 30, 30 },
2726 .vback_porch = { 4, 10, 10 },
2727 .vsync_len = { 4, 5, 5 },
2730 static const struct panel_desc nlt_nl192108ac18_02d = {
2731 .timings = &nlt_nl192108ac18_02d_timing,
2741 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2742 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2745 static const struct drm_display_mode nvd_9128_mode = {
2748 .hsync_start = 800 + 130,
2749 .hsync_end = 800 + 130 + 98,
2750 .htotal = 800 + 0 + 130 + 98,
2752 .vsync_start = 480 + 10,
2753 .vsync_end = 480 + 10 + 50,
2754 .vtotal = 480 + 0 + 10 + 50,
2757 static const struct panel_desc nvd_9128 = {
2758 .modes = &nvd_9128_mode,
2765 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2766 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2769 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2770 .pixelclock = { 30000000, 30000000, 40000000 },
2771 .hactive = { 800, 800, 800 },
2772 .hfront_porch = { 40, 40, 40 },
2773 .hback_porch = { 40, 40, 40 },
2774 .hsync_len = { 1, 48, 48 },
2775 .vactive = { 480, 480, 480 },
2776 .vfront_porch = { 13, 13, 13 },
2777 .vback_porch = { 29, 29, 29 },
2778 .vsync_len = { 3, 3, 3 },
2779 .flags = DISPLAY_FLAGS_DE_HIGH,
2782 static const struct panel_desc okaya_rs800480t_7x0gp = {
2783 .timings = &okaya_rs800480t_7x0gp_timing,
2796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2799 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2802 .hsync_start = 480 + 5,
2803 .hsync_end = 480 + 5 + 30,
2804 .htotal = 480 + 5 + 30 + 10,
2806 .vsync_start = 272 + 8,
2807 .vsync_end = 272 + 8 + 5,
2808 .vtotal = 272 + 8 + 5 + 3,
2811 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2812 .modes = &olimex_lcd_olinuxino_43ts_mode,
2818 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2822 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2823 * pixel clocks, but this is the timing that was being used in the Adafruit
2824 * installation instructions.
2826 static const struct drm_display_mode ontat_yx700wv03_mode = {
2836 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2841 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2843 static const struct panel_desc ontat_yx700wv03 = {
2844 .modes = &ontat_yx700wv03_mode,
2851 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2854 static const struct drm_display_mode ortustech_com37h3m_mode = {
2857 .hsync_start = 480 + 40,
2858 .hsync_end = 480 + 40 + 10,
2859 .htotal = 480 + 40 + 10 + 40,
2861 .vsync_start = 640 + 4,
2862 .vsync_end = 640 + 4 + 2,
2863 .vtotal = 640 + 4 + 2 + 4,
2864 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2867 static const struct panel_desc ortustech_com37h3m = {
2868 .modes = &ortustech_com37h3m_mode,
2872 .width = 56, /* 56.16mm */
2873 .height = 75, /* 74.88mm */
2875 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2876 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2877 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2880 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2883 .hsync_start = 480 + 10,
2884 .hsync_end = 480 + 10 + 10,
2885 .htotal = 480 + 10 + 10 + 15,
2887 .vsync_start = 800 + 3,
2888 .vsync_end = 800 + 3 + 3,
2889 .vtotal = 800 + 3 + 3 + 3,
2892 static const struct panel_desc ortustech_com43h4m85ulc = {
2893 .modes = &ortustech_com43h4m85ulc_mode,
2900 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2902 .connector_type = DRM_MODE_CONNECTOR_DPI,
2905 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2908 .hsync_start = 800 + 210,
2909 .hsync_end = 800 + 210 + 30,
2910 .htotal = 800 + 210 + 30 + 16,
2912 .vsync_start = 480 + 22,
2913 .vsync_end = 480 + 22 + 13,
2914 .vtotal = 480 + 22 + 13 + 10,
2915 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2918 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2919 .modes = &osddisplays_osd070t1718_19ts_mode,
2926 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2927 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2928 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2929 .connector_type = DRM_MODE_CONNECTOR_DPI,
2932 static const struct drm_display_mode pda_91_00156_a0_mode = {
2935 .hsync_start = 800 + 1,
2936 .hsync_end = 800 + 1 + 64,
2937 .htotal = 800 + 1 + 64 + 64,
2939 .vsync_start = 480 + 1,
2940 .vsync_end = 480 + 1 + 23,
2941 .vtotal = 480 + 1 + 23 + 22,
2944 static const struct panel_desc pda_91_00156_a0 = {
2945 .modes = &pda_91_00156_a0_mode,
2951 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2954 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
2957 .hsync_start = 800 + 54,
2958 .hsync_end = 800 + 54 + 2,
2959 .htotal = 800 + 54 + 2 + 44,
2961 .vsync_start = 480 + 49,
2962 .vsync_end = 480 + 49 + 2,
2963 .vtotal = 480 + 49 + 2 + 22,
2966 static const struct panel_desc powertip_ph800480t013_idf02 = {
2967 .modes = &powertip_ph800480t013_idf02_mode,
2973 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2974 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2975 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2976 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2977 .connector_type = DRM_MODE_CONNECTOR_DPI,
2980 static const struct drm_display_mode qd43003c0_40_mode = {
2983 .hsync_start = 480 + 8,
2984 .hsync_end = 480 + 8 + 4,
2985 .htotal = 480 + 8 + 4 + 39,
2987 .vsync_start = 272 + 4,
2988 .vsync_end = 272 + 4 + 10,
2989 .vtotal = 272 + 4 + 10 + 2,
2992 static const struct panel_desc qd43003c0_40 = {
2993 .modes = &qd43003c0_40_mode,
3000 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3003 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3007 .hsync_start = 480 + 77,
3008 .hsync_end = 480 + 77 + 41,
3009 .htotal = 480 + 77 + 41 + 2,
3011 .vsync_start = 272 + 16,
3012 .vsync_end = 272 + 16 + 10,
3013 .vtotal = 272 + 16 + 10 + 2,
3014 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3019 .hsync_start = 480 + 17,
3020 .hsync_end = 480 + 17 + 41,
3021 .htotal = 480 + 17 + 41 + 2,
3023 .vsync_start = 272 + 116,
3024 .vsync_end = 272 + 116 + 10,
3025 .vtotal = 272 + 116 + 10 + 2,
3026 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3030 static const struct panel_desc qishenglong_gopher2b_lcd = {
3031 .modes = qishenglong_gopher2b_lcd_modes,
3032 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3038 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3039 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3040 .connector_type = DRM_MODE_CONNECTOR_DPI,
3043 static const struct display_timing rocktech_rk070er9427_timing = {
3044 .pixelclock = { 26400000, 33300000, 46800000 },
3045 .hactive = { 800, 800, 800 },
3046 .hfront_porch = { 16, 210, 354 },
3047 .hback_porch = { 46, 46, 46 },
3048 .hsync_len = { 1, 1, 1 },
3049 .vactive = { 480, 480, 480 },
3050 .vfront_porch = { 7, 22, 147 },
3051 .vback_porch = { 23, 23, 23 },
3052 .vsync_len = { 1, 1, 1 },
3053 .flags = DISPLAY_FLAGS_DE_HIGH,
3056 static const struct panel_desc rocktech_rk070er9427 = {
3057 .timings = &rocktech_rk070er9427_timing,
3070 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3073 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3076 .hsync_start = 1280 + 48,
3077 .hsync_end = 1280 + 48 + 32,
3078 .htotal = 1280 + 48 + 32 + 80,
3080 .vsync_start = 800 + 2,
3081 .vsync_end = 800 + 2 + 5,
3082 .vtotal = 800 + 2 + 5 + 16,
3085 static const struct panel_desc rocktech_rk101ii01d_ct = {
3086 .modes = &rocktech_rk101ii01d_ct_mode,
3097 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3099 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3102 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3105 .hsync_start = 1024 + 24,
3106 .hsync_end = 1024 + 24 + 136,
3107 .htotal = 1024 + 24 + 136 + 160,
3109 .vsync_start = 600 + 3,
3110 .vsync_end = 600 + 3 + 6,
3111 .vtotal = 600 + 3 + 6 + 61,
3114 static const struct panel_desc samsung_ltn101nt05 = {
3115 .modes = &samsung_ltn101nt05_mode,
3122 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3123 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3124 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3127 static const struct display_timing satoz_sat050at40h12r2_timing = {
3128 .pixelclock = {33300000, 33300000, 50000000},
3129 .hactive = {800, 800, 800},
3130 .hfront_porch = {16, 210, 354},
3131 .hback_porch = {46, 46, 46},
3132 .hsync_len = {1, 1, 40},
3133 .vactive = {480, 480, 480},
3134 .vfront_porch = {7, 22, 147},
3135 .vback_porch = {23, 23, 23},
3136 .vsync_len = {1, 1, 20},
3139 static const struct panel_desc satoz_sat050at40h12r2 = {
3140 .timings = &satoz_sat050at40h12r2_timing,
3147 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3148 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3151 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3154 .hsync_start = 800 + 64,
3155 .hsync_end = 800 + 64 + 128,
3156 .htotal = 800 + 64 + 128 + 64,
3158 .vsync_start = 480 + 8,
3159 .vsync_end = 480 + 8 + 2,
3160 .vtotal = 480 + 8 + 2 + 35,
3161 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3164 static const struct panel_desc sharp_lq070y3dg3b = {
3165 .modes = &sharp_lq070y3dg3b_mode,
3169 .width = 152, /* 152.4mm */
3170 .height = 91, /* 91.4mm */
3172 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3173 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3174 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3177 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3180 .hsync_start = 240 + 16,
3181 .hsync_end = 240 + 16 + 7,
3182 .htotal = 240 + 16 + 7 + 5,
3184 .vsync_start = 320 + 9,
3185 .vsync_end = 320 + 9 + 1,
3186 .vtotal = 320 + 9 + 1 + 7,
3189 static const struct panel_desc sharp_lq035q7db03 = {
3190 .modes = &sharp_lq035q7db03_mode,
3197 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3200 static const struct display_timing sharp_lq101k1ly04_timing = {
3201 .pixelclock = { 60000000, 65000000, 80000000 },
3202 .hactive = { 1280, 1280, 1280 },
3203 .hfront_porch = { 20, 20, 20 },
3204 .hback_porch = { 20, 20, 20 },
3205 .hsync_len = { 10, 10, 10 },
3206 .vactive = { 800, 800, 800 },
3207 .vfront_porch = { 4, 4, 4 },
3208 .vback_porch = { 4, 4, 4 },
3209 .vsync_len = { 4, 4, 4 },
3210 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3213 static const struct panel_desc sharp_lq101k1ly04 = {
3214 .timings = &sharp_lq101k1ly04_timing,
3221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3222 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3225 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3229 .hsync_start = 240 + 58,
3230 .hsync_end = 240 + 58 + 1,
3231 .htotal = 240 + 58 + 1 + 1,
3233 .vsync_start = 160 + 24,
3234 .vsync_end = 160 + 24 + 10,
3235 .vtotal = 160 + 24 + 10 + 6,
3236 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3241 .hsync_start = 240 + 8,
3242 .hsync_end = 240 + 8 + 1,
3243 .htotal = 240 + 8 + 1 + 1,
3245 .vsync_start = 160 + 24,
3246 .vsync_end = 160 + 24 + 10,
3247 .vtotal = 160 + 24 + 10 + 6,
3248 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3252 static const struct panel_desc sharp_ls020b1dd01d = {
3253 .modes = sharp_ls020b1dd01d_modes,
3254 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3260 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3261 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3262 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3263 | DRM_BUS_FLAG_SHARP_SIGNALS,
3266 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3269 .hsync_start = 800 + 1,
3270 .hsync_end = 800 + 1 + 64,
3271 .htotal = 800 + 1 + 64 + 64,
3273 .vsync_start = 480 + 1,
3274 .vsync_end = 480 + 1 + 23,
3275 .vtotal = 480 + 1 + 23 + 22,
3278 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3279 .modes = &shelly_sca07010_bfn_lnn_mode,
3285 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3288 static const struct drm_display_mode starry_kr070pe2t_mode = {
3291 .hsync_start = 800 + 209,
3292 .hsync_end = 800 + 209 + 1,
3293 .htotal = 800 + 209 + 1 + 45,
3295 .vsync_start = 480 + 22,
3296 .vsync_end = 480 + 22 + 1,
3297 .vtotal = 480 + 22 + 1 + 22,
3300 static const struct panel_desc starry_kr070pe2t = {
3301 .modes = &starry_kr070pe2t_mode,
3308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3309 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3310 .connector_type = DRM_MODE_CONNECTOR_DPI,
3313 static const struct display_timing startek_kd070wvfpa_mode = {
3314 .pixelclock = { 25200000, 27200000, 30500000 },
3315 .hactive = { 800, 800, 800 },
3316 .hfront_porch = { 19, 44, 115 },
3317 .hback_porch = { 5, 16, 101 },
3318 .hsync_len = { 1, 2, 100 },
3319 .vactive = { 480, 480, 480 },
3320 .vfront_porch = { 5, 43, 67 },
3321 .vback_porch = { 5, 5, 67 },
3322 .vsync_len = { 1, 2, 66 },
3323 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3324 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3325 DISPLAY_FLAGS_SYNC_POSEDGE,
3328 static const struct panel_desc startek_kd070wvfpa = {
3329 .timings = &startek_kd070wvfpa_mode,
3341 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3342 .connector_type = DRM_MODE_CONNECTOR_DPI,
3343 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3344 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3345 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3348 static const struct display_timing tsd_tst043015cmhx_timing = {
3349 .pixelclock = { 5000000, 9000000, 12000000 },
3350 .hactive = { 480, 480, 480 },
3351 .hfront_porch = { 4, 5, 65 },
3352 .hback_porch = { 36, 40, 255 },
3353 .hsync_len = { 1, 1, 1 },
3354 .vactive = { 272, 272, 272 },
3355 .vfront_porch = { 2, 8, 97 },
3356 .vback_porch = { 3, 8, 31 },
3357 .vsync_len = { 1, 1, 1 },
3359 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3360 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3363 static const struct panel_desc tsd_tst043015cmhx = {
3364 .timings = &tsd_tst043015cmhx_timing,
3371 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3372 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3375 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3378 .hsync_start = 800 + 39,
3379 .hsync_end = 800 + 39 + 47,
3380 .htotal = 800 + 39 + 47 + 39,
3382 .vsync_start = 480 + 13,
3383 .vsync_end = 480 + 13 + 2,
3384 .vtotal = 480 + 13 + 2 + 29,
3387 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3388 .modes = &tfc_s9700rtwv43tr_01b_mode,
3395 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3396 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3399 static const struct display_timing tianma_tm070jdhg30_timing = {
3400 .pixelclock = { 62600000, 68200000, 78100000 },
3401 .hactive = { 1280, 1280, 1280 },
3402 .hfront_porch = { 15, 64, 159 },
3403 .hback_porch = { 5, 5, 5 },
3404 .hsync_len = { 1, 1, 256 },
3405 .vactive = { 800, 800, 800 },
3406 .vfront_porch = { 3, 40, 99 },
3407 .vback_porch = { 2, 2, 2 },
3408 .vsync_len = { 1, 1, 128 },
3409 .flags = DISPLAY_FLAGS_DE_HIGH,
3412 static const struct panel_desc tianma_tm070jdhg30 = {
3413 .timings = &tianma_tm070jdhg30_timing,
3420 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3421 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3424 static const struct panel_desc tianma_tm070jvhg33 = {
3425 .timings = &tianma_tm070jdhg30_timing,
3432 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3433 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3436 static const struct display_timing tianma_tm070rvhg71_timing = {
3437 .pixelclock = { 27700000, 29200000, 39600000 },
3438 .hactive = { 800, 800, 800 },
3439 .hfront_porch = { 12, 40, 212 },
3440 .hback_porch = { 88, 88, 88 },
3441 .hsync_len = { 1, 1, 40 },
3442 .vactive = { 480, 480, 480 },
3443 .vfront_porch = { 1, 13, 88 },
3444 .vback_porch = { 32, 32, 32 },
3445 .vsync_len = { 1, 1, 3 },
3446 .flags = DISPLAY_FLAGS_DE_HIGH,
3449 static const struct panel_desc tianma_tm070rvhg71 = {
3450 .timings = &tianma_tm070rvhg71_timing,
3457 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3458 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3461 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3465 .hsync_start = 320 + 50,
3466 .hsync_end = 320 + 50 + 6,
3467 .htotal = 320 + 50 + 6 + 38,
3469 .vsync_start = 240 + 3,
3470 .vsync_end = 240 + 3 + 1,
3471 .vtotal = 240 + 3 + 1 + 17,
3472 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3476 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3477 .modes = ti_nspire_cx_lcd_mode,
3484 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3485 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3488 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3492 .hsync_start = 320 + 6,
3493 .hsync_end = 320 + 6 + 6,
3494 .htotal = 320 + 6 + 6 + 6,
3496 .vsync_start = 240 + 0,
3497 .vsync_end = 240 + 0 + 1,
3498 .vtotal = 240 + 0 + 1 + 0,
3499 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3503 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3504 .modes = ti_nspire_classic_lcd_mode,
3506 /* The grayscale panel has 8 bit for the color .. Y (black) */
3512 /* This is the grayscale bus format */
3513 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3514 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3517 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3520 .hsync_start = 1280 + 192,
3521 .hsync_end = 1280 + 192 + 128,
3522 .htotal = 1280 + 192 + 128 + 64,
3524 .vsync_start = 768 + 20,
3525 .vsync_end = 768 + 20 + 7,
3526 .vtotal = 768 + 20 + 7 + 3,
3529 static const struct panel_desc toshiba_lt089ac29000 = {
3530 .modes = &toshiba_lt089ac29000_mode,
3536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3537 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3538 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3541 static const struct drm_display_mode tpk_f07a_0102_mode = {
3544 .hsync_start = 800 + 40,
3545 .hsync_end = 800 + 40 + 128,
3546 .htotal = 800 + 40 + 128 + 88,
3548 .vsync_start = 480 + 10,
3549 .vsync_end = 480 + 10 + 2,
3550 .vtotal = 480 + 10 + 2 + 33,
3553 static const struct panel_desc tpk_f07a_0102 = {
3554 .modes = &tpk_f07a_0102_mode,
3560 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3563 static const struct drm_display_mode tpk_f10a_0102_mode = {
3566 .hsync_start = 1024 + 176,
3567 .hsync_end = 1024 + 176 + 5,
3568 .htotal = 1024 + 176 + 5 + 88,
3570 .vsync_start = 600 + 20,
3571 .vsync_end = 600 + 20 + 5,
3572 .vtotal = 600 + 20 + 5 + 25,
3575 static const struct panel_desc tpk_f10a_0102 = {
3576 .modes = &tpk_f10a_0102_mode,
3584 static const struct display_timing urt_umsh_8596md_timing = {
3585 .pixelclock = { 33260000, 33260000, 33260000 },
3586 .hactive = { 800, 800, 800 },
3587 .hfront_porch = { 41, 41, 41 },
3588 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3589 .hsync_len = { 71, 128, 128 },
3590 .vactive = { 480, 480, 480 },
3591 .vfront_porch = { 10, 10, 10 },
3592 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3593 .vsync_len = { 2, 2, 2 },
3594 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3595 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3598 static const struct panel_desc urt_umsh_8596md_lvds = {
3599 .timings = &urt_umsh_8596md_timing,
3606 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3607 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3610 static const struct panel_desc urt_umsh_8596md_parallel = {
3611 .timings = &urt_umsh_8596md_timing,
3618 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3621 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3624 .hsync_start = 1024 + 160,
3625 .hsync_end = 1024 + 160 + 100,
3626 .htotal = 1024 + 160 + 100 + 60,
3628 .vsync_start = 600 + 12,
3629 .vsync_end = 600 + 12 + 10,
3630 .vtotal = 600 + 12 + 10 + 13,
3633 static const struct panel_desc vivax_tpc9150_panel = {
3634 .modes = &vivax_tpc9150_panel_mode,
3641 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3642 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3643 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3646 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3649 .hsync_start = 800 + 210,
3650 .hsync_end = 800 + 210 + 20,
3651 .htotal = 800 + 210 + 20 + 46,
3653 .vsync_start = 480 + 22,
3654 .vsync_end = 480 + 22 + 10,
3655 .vtotal = 480 + 22 + 10 + 23,
3656 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3659 static const struct panel_desc vl050_8048nt_c01 = {
3660 .modes = &vl050_8048nt_c01_mode,
3667 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3671 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3674 .hsync_start = 320 + 20,
3675 .hsync_end = 320 + 20 + 30,
3676 .htotal = 320 + 20 + 30 + 38,
3678 .vsync_start = 240 + 4,
3679 .vsync_end = 240 + 4 + 3,
3680 .vtotal = 240 + 4 + 3 + 15,
3681 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3684 static const struct panel_desc winstar_wf35ltiacd = {
3685 .modes = &winstar_wf35ltiacd_mode,
3692 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3695 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3698 .hsync_start = 1024 + 100,
3699 .hsync_end = 1024 + 100 + 100,
3700 .htotal = 1024 + 100 + 100 + 120,
3702 .vsync_start = 600 + 10,
3703 .vsync_end = 600 + 10 + 10,
3704 .vtotal = 600 + 10 + 10 + 15,
3705 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3708 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3709 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3716 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3718 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3721 static const struct drm_display_mode arm_rtsm_mode[] = {
3725 .hsync_start = 1024 + 24,
3726 .hsync_end = 1024 + 24 + 136,
3727 .htotal = 1024 + 24 + 136 + 160,
3729 .vsync_start = 768 + 3,
3730 .vsync_end = 768 + 3 + 6,
3731 .vtotal = 768 + 3 + 6 + 29,
3732 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3736 static const struct panel_desc arm_rtsm = {
3737 .modes = arm_rtsm_mode,
3744 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3747 static const struct of_device_id platform_of_match[] = {
3749 .compatible = "ampire,am-1280800n3tzqw-t00h",
3750 .data = &ire_am_1280800n3tzqw_t00h,
3752 .compatible = "ampire,am-480272h3tmqw-t01h",
3753 .data = &ire_am_480272h3tmqw_t01h,
3755 .compatible = "ampire,am800480r3tmqwa1h",
3756 .data = &ire_am800480r3tmqwa1h,
3758 .compatible = "arm,rtsm-display",
3761 .compatible = "armadeus,st0700-adapt",
3762 .data = &armadeus_st0700_adapt,
3764 .compatible = "auo,b101aw03",
3765 .data = &auo_b101aw03,
3767 .compatible = "auo,b101xtn01",
3768 .data = &auo_b101xtn01,
3770 .compatible = "auo,g070vvn01",
3771 .data = &auo_g070vvn01,
3773 .compatible = "auo,g101evn010",
3774 .data = &auo_g101evn010,
3776 .compatible = "auo,g104sn02",
3777 .data = &auo_g104sn02,
3779 .compatible = "auo,g121ean01",
3780 .data = &auo_g121ean01,
3782 .compatible = "auo,g133han01",
3783 .data = &auo_g133han01,
3785 .compatible = "auo,g156xtn01",
3786 .data = &auo_g156xtn01,
3788 .compatible = "auo,g185han01",
3789 .data = &auo_g185han01,
3791 .compatible = "auo,g190ean01",
3792 .data = &auo_g190ean01,
3794 .compatible = "auo,p320hvn03",
3795 .data = &auo_p320hvn03,
3797 .compatible = "auo,t215hvn01",
3798 .data = &auo_t215hvn01,
3800 .compatible = "avic,tm070ddh03",
3801 .data = &avic_tm070ddh03,
3803 .compatible = "bananapi,s070wv20-ct16",
3804 .data = &bananapi_s070wv20_ct16,
3806 .compatible = "boe,hv070wsa-100",
3807 .data = &boe_hv070wsa
3809 .compatible = "cdtech,s043wq26h-ct7",
3810 .data = &cdtech_s043wq26h_ct7,
3812 .compatible = "cdtech,s070pws19hp-fc21",
3813 .data = &cdtech_s070pws19hp_fc21,
3815 .compatible = "cdtech,s070swv29hg-dc44",
3816 .data = &cdtech_s070swv29hg_dc44,
3818 .compatible = "cdtech,s070wv95-ct16",
3819 .data = &cdtech_s070wv95_ct16,
3821 .compatible = "chefree,ch101olhlwh-002",
3822 .data = &chefree_ch101olhlwh_002,
3824 .compatible = "chunghwa,claa070wp03xg",
3825 .data = &chunghwa_claa070wp03xg,
3827 .compatible = "chunghwa,claa101wa01a",
3828 .data = &chunghwa_claa101wa01a
3830 .compatible = "chunghwa,claa101wb01",
3831 .data = &chunghwa_claa101wb01
3833 .compatible = "dataimage,fg040346dsswbg04",
3834 .data = &dataimage_fg040346dsswbg04,
3836 .compatible = "dataimage,scf0700c48ggu18",
3837 .data = &dataimage_scf0700c48ggu18,
3839 .compatible = "dlc,dlc0700yzg-1",
3840 .data = &dlc_dlc0700yzg_1,
3842 .compatible = "dlc,dlc1010gig",
3843 .data = &dlc_dlc1010gig,
3845 .compatible = "edt,et035012dm6",
3846 .data = &edt_et035012dm6,
3848 .compatible = "edt,etm0350g0dh6",
3849 .data = &edt_etm0350g0dh6,
3851 .compatible = "edt,etm043080dh6gp",
3852 .data = &edt_etm043080dh6gp,
3854 .compatible = "edt,etm0430g0dh6",
3855 .data = &edt_etm0430g0dh6,
3857 .compatible = "edt,et057090dhu",
3858 .data = &edt_et057090dhu,
3860 .compatible = "edt,et070080dh6",
3861 .data = &edt_etm0700g0dh6,
3863 .compatible = "edt,etm0700g0dh6",
3864 .data = &edt_etm0700g0dh6,
3866 .compatible = "edt,etm0700g0bdh6",
3867 .data = &edt_etm0700g0bdh6,
3869 .compatible = "edt,etm0700g0edh6",
3870 .data = &edt_etm0700g0bdh6,
3872 .compatible = "edt,etmv570g2dhu",
3873 .data = &edt_etmv570g2dhu,
3875 .compatible = "eink,vb3300-kca",
3876 .data = &eink_vb3300_kca,
3878 .compatible = "evervision,vgg804821",
3879 .data = &evervision_vgg804821,
3881 .compatible = "foxlink,fl500wvr00-a0t",
3882 .data = &foxlink_fl500wvr00_a0t,
3884 .compatible = "frida,frd350h54004",
3885 .data = &frida_frd350h54004,
3887 .compatible = "friendlyarm,hd702e",
3888 .data = &friendlyarm_hd702e,
3890 .compatible = "giantplus,gpg482739qs5",
3891 .data = &giantplus_gpg482739qs5
3893 .compatible = "giantplus,gpm940b0",
3894 .data = &giantplus_gpm940b0,
3896 .compatible = "hannstar,hsd070pww1",
3897 .data = &hannstar_hsd070pww1,
3899 .compatible = "hannstar,hsd100pxn1",
3900 .data = &hannstar_hsd100pxn1,
3902 .compatible = "hit,tx23d38vm0caa",
3903 .data = &hitachi_tx23d38vm0caa
3905 .compatible = "innolux,at043tn24",
3906 .data = &innolux_at043tn24,
3908 .compatible = "innolux,at070tn92",
3909 .data = &innolux_at070tn92,
3911 .compatible = "innolux,g070y2-l01",
3912 .data = &innolux_g070y2_l01,
3914 .compatible = "innolux,g070y2-t02",
3915 .data = &innolux_g070y2_t02,
3917 .compatible = "innolux,g101ice-l01",
3918 .data = &innolux_g101ice_l01
3920 .compatible = "innolux,g121i1-l01",
3921 .data = &innolux_g121i1_l01
3923 .compatible = "innolux,g121x1-l03",
3924 .data = &innolux_g121x1_l03,
3926 .compatible = "innolux,n156bge-l21",
3927 .data = &innolux_n156bge_l21,
3929 .compatible = "innolux,zj070na-01p",
3930 .data = &innolux_zj070na_01p,
3932 .compatible = "koe,tx14d24vm1bpa",
3933 .data = &koe_tx14d24vm1bpa,
3935 .compatible = "koe,tx26d202vm0bwa",
3936 .data = &koe_tx26d202vm0bwa,
3938 .compatible = "koe,tx31d200vm0baa",
3939 .data = &koe_tx31d200vm0baa,
3941 .compatible = "kyo,tcg121xglp",
3942 .data = &kyo_tcg121xglp,
3944 .compatible = "lemaker,bl035-rgb-002",
3945 .data = &lemaker_bl035_rgb_002,
3947 .compatible = "lg,lb070wv8",
3948 .data = &lg_lb070wv8,
3950 .compatible = "logicpd,type28",
3951 .data = &logicpd_type_28,
3953 .compatible = "logictechno,lt161010-2nhc",
3954 .data = &logictechno_lt161010_2nh,
3956 .compatible = "logictechno,lt161010-2nhr",
3957 .data = &logictechno_lt161010_2nh,
3959 .compatible = "logictechno,lt170410-2whc",
3960 .data = &logictechno_lt170410_2whc,
3962 .compatible = "logictechno,lttd800480070-l2rt",
3963 .data = &logictechno_lttd800480070_l2rt,
3965 .compatible = "logictechno,lttd800480070-l6wh-rt",
3966 .data = &logictechno_lttd800480070_l6wh_rt,
3968 .compatible = "mitsubishi,aa070mc01-ca1",
3969 .data = &mitsubishi_aa070mc01,
3971 .compatible = "multi-inno,mi0700s4t-6",
3972 .data = &multi_inno_mi0700s4t_6,
3974 .compatible = "multi-inno,mi1010ait-1cp",
3975 .data = &multi_inno_mi1010ait_1cp,
3977 .compatible = "nec,nl12880bc20-05",
3978 .data = &nec_nl12880bc20_05,
3980 .compatible = "nec,nl4827hc19-05b",
3981 .data = &nec_nl4827hc19_05b,
3983 .compatible = "netron-dy,e231732",
3984 .data = &netron_dy_e231732,
3986 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3987 .data = &newhaven_nhd_43_480272ef_atxl,
3989 .compatible = "nlt,nl192108ac18-02d",
3990 .data = &nlt_nl192108ac18_02d,
3992 .compatible = "nvd,9128",
3995 .compatible = "okaya,rs800480t-7x0gp",
3996 .data = &okaya_rs800480t_7x0gp,
3998 .compatible = "olimex,lcd-olinuxino-43-ts",
3999 .data = &olimex_lcd_olinuxino_43ts,
4001 .compatible = "ontat,yx700wv03",
4002 .data = &ontat_yx700wv03,
4004 .compatible = "ortustech,com37h3m05dtc",
4005 .data = &ortustech_com37h3m,
4007 .compatible = "ortustech,com37h3m99dtc",
4008 .data = &ortustech_com37h3m,
4010 .compatible = "ortustech,com43h4m85ulc",
4011 .data = &ortustech_com43h4m85ulc,
4013 .compatible = "osddisplays,osd070t1718-19ts",
4014 .data = &osddisplays_osd070t1718_19ts,
4016 .compatible = "pda,91-00156-a0",
4017 .data = &pda_91_00156_a0,
4019 .compatible = "powertip,ph800480t013-idf02",
4020 .data = &powertip_ph800480t013_idf02,
4022 .compatible = "qiaodian,qd43003c0-40",
4023 .data = &qd43003c0_40,
4025 .compatible = "qishenglong,gopher2b-lcd",
4026 .data = &qishenglong_gopher2b_lcd,
4028 .compatible = "rocktech,rk070er9427",
4029 .data = &rocktech_rk070er9427,
4031 .compatible = "rocktech,rk101ii01d-ct",
4032 .data = &rocktech_rk101ii01d_ct,
4034 .compatible = "samsung,ltn101nt05",
4035 .data = &samsung_ltn101nt05,
4037 .compatible = "satoz,sat050at40h12r2",
4038 .data = &satoz_sat050at40h12r2,
4040 .compatible = "sharp,lq035q7db03",
4041 .data = &sharp_lq035q7db03,
4043 .compatible = "sharp,lq070y3dg3b",
4044 .data = &sharp_lq070y3dg3b,
4046 .compatible = "sharp,lq101k1ly04",
4047 .data = &sharp_lq101k1ly04,
4049 .compatible = "sharp,ls020b1dd01d",
4050 .data = &sharp_ls020b1dd01d,
4052 .compatible = "shelly,sca07010-bfn-lnn",
4053 .data = &shelly_sca07010_bfn_lnn,
4055 .compatible = "starry,kr070pe2t",
4056 .data = &starry_kr070pe2t,
4058 .compatible = "startek,kd070wvfpa",
4059 .data = &startek_kd070wvfpa,
4061 .compatible = "team-source-display,tst043015cmhx",
4062 .data = &tsd_tst043015cmhx,
4064 .compatible = "tfc,s9700rtwv43tr-01b",
4065 .data = &tfc_s9700rtwv43tr_01b,
4067 .compatible = "tianma,tm070jdhg30",
4068 .data = &tianma_tm070jdhg30,
4070 .compatible = "tianma,tm070jvhg33",
4071 .data = &tianma_tm070jvhg33,
4073 .compatible = "tianma,tm070rvhg71",
4074 .data = &tianma_tm070rvhg71,
4076 .compatible = "ti,nspire-cx-lcd-panel",
4077 .data = &ti_nspire_cx_lcd_panel,
4079 .compatible = "ti,nspire-classic-lcd-panel",
4080 .data = &ti_nspire_classic_lcd_panel,
4082 .compatible = "toshiba,lt089ac29000",
4083 .data = &toshiba_lt089ac29000,
4085 .compatible = "tpk,f07a-0102",
4086 .data = &tpk_f07a_0102,
4088 .compatible = "tpk,f10a-0102",
4089 .data = &tpk_f10a_0102,
4091 .compatible = "urt,umsh-8596md-t",
4092 .data = &urt_umsh_8596md_parallel,
4094 .compatible = "urt,umsh-8596md-1t",
4095 .data = &urt_umsh_8596md_parallel,
4097 .compatible = "urt,umsh-8596md-7t",
4098 .data = &urt_umsh_8596md_parallel,
4100 .compatible = "urt,umsh-8596md-11t",
4101 .data = &urt_umsh_8596md_lvds,
4103 .compatible = "urt,umsh-8596md-19t",
4104 .data = &urt_umsh_8596md_lvds,
4106 .compatible = "urt,umsh-8596md-20t",
4107 .data = &urt_umsh_8596md_parallel,
4109 .compatible = "vivax,tpc9150-panel",
4110 .data = &vivax_tpc9150_panel,
4112 .compatible = "vxt,vl050-8048nt-c01",
4113 .data = &vl050_8048nt_c01,
4115 .compatible = "winstar,wf35ltiacd",
4116 .data = &winstar_wf35ltiacd,
4118 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4119 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4121 /* Must be the last entry */
4122 .compatible = "panel-dpi",
4128 MODULE_DEVICE_TABLE(of, platform_of_match);
4130 static int panel_simple_platform_probe(struct platform_device *pdev)
4132 const struct of_device_id *id;
4134 id = of_match_node(platform_of_match, pdev->dev.of_node);
4138 return panel_simple_probe(&pdev->dev, id->data);
4141 static int panel_simple_platform_remove(struct platform_device *pdev)
4143 return panel_simple_remove(&pdev->dev);
4146 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4148 panel_simple_shutdown(&pdev->dev);
4151 static const struct dev_pm_ops panel_simple_pm_ops = {
4152 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4153 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4154 pm_runtime_force_resume)
4157 static struct platform_driver panel_simple_platform_driver = {
4159 .name = "panel-simple",
4160 .of_match_table = platform_of_match,
4161 .pm = &panel_simple_pm_ops,
4163 .probe = panel_simple_platform_probe,
4164 .remove = panel_simple_platform_remove,
4165 .shutdown = panel_simple_platform_shutdown,
4168 struct panel_desc_dsi {
4169 struct panel_desc desc;
4171 unsigned long flags;
4172 enum mipi_dsi_pixel_format format;
4176 static const struct drm_display_mode auo_b080uan01_mode = {
4179 .hsync_start = 1200 + 62,
4180 .hsync_end = 1200 + 62 + 4,
4181 .htotal = 1200 + 62 + 4 + 62,
4183 .vsync_start = 1920 + 9,
4184 .vsync_end = 1920 + 9 + 2,
4185 .vtotal = 1920 + 9 + 2 + 8,
4188 static const struct panel_desc_dsi auo_b080uan01 = {
4190 .modes = &auo_b080uan01_mode,
4197 .connector_type = DRM_MODE_CONNECTOR_DSI,
4199 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4200 .format = MIPI_DSI_FMT_RGB888,
4204 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4207 .hsync_start = 1200 + 120,
4208 .hsync_end = 1200 + 120 + 20,
4209 .htotal = 1200 + 120 + 20 + 21,
4211 .vsync_start = 1920 + 21,
4212 .vsync_end = 1920 + 21 + 3,
4213 .vtotal = 1920 + 21 + 3 + 18,
4214 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4217 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4219 .modes = &boe_tv080wum_nl0_mode,
4225 .connector_type = DRM_MODE_CONNECTOR_DSI,
4227 .flags = MIPI_DSI_MODE_VIDEO |
4228 MIPI_DSI_MODE_VIDEO_BURST |
4229 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4230 .format = MIPI_DSI_FMT_RGB888,
4234 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4237 .hsync_start = 800 + 32,
4238 .hsync_end = 800 + 32 + 1,
4239 .htotal = 800 + 32 + 1 + 57,
4241 .vsync_start = 1280 + 28,
4242 .vsync_end = 1280 + 28 + 1,
4243 .vtotal = 1280 + 28 + 1 + 14,
4246 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4248 .modes = &lg_ld070wx3_sl01_mode,
4255 .connector_type = DRM_MODE_CONNECTOR_DSI,
4257 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4258 .format = MIPI_DSI_FMT_RGB888,
4262 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4265 .hsync_start = 720 + 12,
4266 .hsync_end = 720 + 12 + 4,
4267 .htotal = 720 + 12 + 4 + 112,
4269 .vsync_start = 1280 + 8,
4270 .vsync_end = 1280 + 8 + 4,
4271 .vtotal = 1280 + 8 + 4 + 12,
4274 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4276 .modes = &lg_lh500wx1_sd03_mode,
4283 .connector_type = DRM_MODE_CONNECTOR_DSI,
4285 .flags = MIPI_DSI_MODE_VIDEO,
4286 .format = MIPI_DSI_FMT_RGB888,
4290 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4293 .hsync_start = 1920 + 154,
4294 .hsync_end = 1920 + 154 + 16,
4295 .htotal = 1920 + 154 + 16 + 32,
4297 .vsync_start = 1200 + 17,
4298 .vsync_end = 1200 + 17 + 2,
4299 .vtotal = 1200 + 17 + 2 + 16,
4302 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4304 .modes = &panasonic_vvx10f004b00_mode,
4311 .connector_type = DRM_MODE_CONNECTOR_DSI,
4313 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4314 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4315 .format = MIPI_DSI_FMT_RGB888,
4319 static const struct drm_display_mode lg_acx467akm_7_mode = {
4322 .hsync_start = 1080 + 2,
4323 .hsync_end = 1080 + 2 + 2,
4324 .htotal = 1080 + 2 + 2 + 2,
4326 .vsync_start = 1920 + 2,
4327 .vsync_end = 1920 + 2 + 2,
4328 .vtotal = 1920 + 2 + 2 + 2,
4331 static const struct panel_desc_dsi lg_acx467akm_7 = {
4333 .modes = &lg_acx467akm_7_mode,
4340 .connector_type = DRM_MODE_CONNECTOR_DSI,
4343 .format = MIPI_DSI_FMT_RGB888,
4347 static const struct drm_display_mode osd101t2045_53ts_mode = {
4350 .hsync_start = 1920 + 112,
4351 .hsync_end = 1920 + 112 + 16,
4352 .htotal = 1920 + 112 + 16 + 32,
4354 .vsync_start = 1200 + 16,
4355 .vsync_end = 1200 + 16 + 2,
4356 .vtotal = 1200 + 16 + 2 + 16,
4357 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4360 static const struct panel_desc_dsi osd101t2045_53ts = {
4362 .modes = &osd101t2045_53ts_mode,
4369 .connector_type = DRM_MODE_CONNECTOR_DSI,
4371 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4372 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4373 MIPI_DSI_MODE_NO_EOT_PACKET,
4374 .format = MIPI_DSI_FMT_RGB888,
4378 static const struct of_device_id dsi_of_match[] = {
4380 .compatible = "auo,b080uan01",
4381 .data = &auo_b080uan01
4383 .compatible = "boe,tv080wum-nl0",
4384 .data = &boe_tv080wum_nl0
4386 .compatible = "lg,ld070wx3-sl01",
4387 .data = &lg_ld070wx3_sl01
4389 .compatible = "lg,lh500wx1-sd03",
4390 .data = &lg_lh500wx1_sd03
4392 .compatible = "panasonic,vvx10f004b00",
4393 .data = &panasonic_vvx10f004b00
4395 .compatible = "lg,acx467akm-7",
4396 .data = &lg_acx467akm_7
4398 .compatible = "osddisplays,osd101t2045-53ts",
4399 .data = &osd101t2045_53ts
4404 MODULE_DEVICE_TABLE(of, dsi_of_match);
4406 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4408 const struct panel_desc_dsi *desc;
4409 const struct of_device_id *id;
4412 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4418 err = panel_simple_probe(&dsi->dev, &desc->desc);
4422 dsi->mode_flags = desc->flags;
4423 dsi->format = desc->format;
4424 dsi->lanes = desc->lanes;
4426 err = mipi_dsi_attach(dsi);
4428 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4430 drm_panel_remove(&panel->base);
4436 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4440 err = mipi_dsi_detach(dsi);
4442 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4444 return panel_simple_remove(&dsi->dev);
4447 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4449 panel_simple_shutdown(&dsi->dev);
4452 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4454 .name = "panel-simple-dsi",
4455 .of_match_table = dsi_of_match,
4456 .pm = &panel_simple_pm_ops,
4458 .probe = panel_simple_dsi_probe,
4459 .remove = panel_simple_dsi_remove,
4460 .shutdown = panel_simple_dsi_shutdown,
4463 static int __init panel_simple_init(void)
4467 err = platform_driver_register(&panel_simple_platform_driver);
4471 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4472 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4474 goto err_did_platform_register;
4479 err_did_platform_register:
4480 platform_driver_unregister(&panel_simple_platform_driver);
4484 module_init(panel_simple_init);
4486 static void __exit panel_simple_exit(void)
4488 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4489 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4491 platform_driver_unregister(&panel_simple_platform_driver);
4493 module_exit(panel_simple_exit);
4495 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4496 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4497 MODULE_LICENSE("GPL and additional rights");