2 * DMM IOMMU driver support functions for TI OMAP processors.
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 * Author: Rob Clark <rob@ti.com>
6 * Andy Gross <andy.gross@ti.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/completion.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h> /* platform_device() */
28 #include <linux/sched.h>
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/time.h>
32 #include <linux/vmalloc.h>
33 #include <linux/wait.h>
35 #include "omap_dmm_tiler.h"
36 #include "omap_dmm_priv.h"
38 #define DMM_DRIVER_NAME "dmm"
40 /* mappings for associating views to luts */
41 static struct tcm *containers[TILFMT_NFORMATS];
42 static struct dmm *omap_dmm;
44 #if defined(CONFIG_OF)
45 static const struct of_device_id dmm_of_match[];
48 /* global spinlock for protecting lists */
49 static DEFINE_SPINLOCK(list_lock);
52 #define GEOM(xshift, yshift, bytes_per_pixel) { \
55 .cpp = (bytes_per_pixel), \
56 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
57 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
61 u32 x_shft; /* unused X-bits (as part of bpp) */
62 u32 y_shft; /* unused Y-bits (as part of bpp) */
63 u32 cpp; /* bytes/chars per pixel */
64 u32 slot_w; /* width of each slot (in pixels) */
65 u32 slot_h; /* height of each slot (in pixels) */
66 } geom[TILFMT_NFORMATS] = {
67 [TILFMT_8BIT] = GEOM(0, 0, 1),
68 [TILFMT_16BIT] = GEOM(0, 1, 2),
69 [TILFMT_32BIT] = GEOM(1, 1, 4),
70 [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
74 /* lookup table for registers w/ per-engine instances */
75 static const u32 reg[][4] = {
76 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
77 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
78 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
79 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
82 static u32 dmm_read(struct dmm *dmm, u32 reg)
84 return readl(dmm->base + reg);
87 static void dmm_write(struct dmm *dmm, u32 val, u32 reg)
89 writel(val, dmm->base + reg);
92 /* simple allocator to grab next 16 byte aligned memory from txn */
93 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
96 struct refill_engine *engine = txn->engine_handle;
98 /* dmm programming requires 16 byte aligned addresses */
99 txn->current_pa = round_up(txn->current_pa, 16);
100 txn->current_va = (void *)round_up((long)txn->current_va, 16);
102 ptr = txn->current_va;
103 *pa = txn->current_pa;
105 txn->current_pa += sz;
106 txn->current_va += sz;
108 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
113 /* check status and spin until wait_mask comes true */
114 static int wait_status(struct refill_engine *engine, u32 wait_mask)
116 struct dmm *dmm = engine->dmm;
119 i = DMM_FIXED_RETRY_COUNT;
121 r = dmm_read(dmm, reg[PAT_STATUS][engine->id]);
122 err = r & DMM_PATSTATUS_ERR;
125 "%s: error (engine%d). PAT_STATUS: 0x%08x\n",
126 __func__, engine->id, r);
130 if ((r & wait_mask) == wait_mask)
135 "%s: timeout (engine%d). PAT_STATUS: 0x%08x\n",
136 __func__, engine->id, r);
146 static void release_engine(struct refill_engine *engine)
150 spin_lock_irqsave(&list_lock, flags);
151 list_add(&engine->idle_node, &omap_dmm->idle_head);
152 spin_unlock_irqrestore(&list_lock, flags);
154 atomic_inc(&omap_dmm->engine_counter);
155 wake_up_interruptible(&omap_dmm->engine_queue);
158 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
160 struct dmm *dmm = arg;
161 u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS);
165 dmm_write(dmm, status, DMM_PAT_IRQSTATUS);
167 for (i = 0; i < dmm->num_engines; i++) {
168 if (status & DMM_IRQSTAT_ERR_MASK)
170 "irq error(engine%d): IRQSTAT 0x%02x\n",
173 if (status & DMM_IRQSTAT_LST) {
174 if (dmm->engines[i].async)
175 release_engine(&dmm->engines[i]);
177 complete(&dmm->engines[i].compl);
187 * Get a handle for a DMM transaction
189 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
191 struct dmm_txn *txn = NULL;
192 struct refill_engine *engine = NULL;
197 /* wait until an engine is available */
198 ret = wait_event_interruptible(omap_dmm->engine_queue,
199 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
203 /* grab an idle engine */
204 spin_lock_irqsave(&list_lock, flags);
205 if (!list_empty(&dmm->idle_head)) {
206 engine = list_entry(dmm->idle_head.next, struct refill_engine,
208 list_del(&engine->idle_node);
210 spin_unlock_irqrestore(&list_lock, flags);
216 txn->engine_handle = engine;
217 txn->last_pat = NULL;
218 txn->current_va = engine->refill_va;
219 txn->current_pa = engine->refill_pa;
225 * Add region to DMM transaction. If pages or pages[i] is NULL, then the
226 * corresponding slot is cleared (ie. dummy_pa is programmed)
228 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
229 struct page **pages, u32 npages, u32 roll)
231 dma_addr_t pat_pa = 0, data_pa = 0;
234 struct refill_engine *engine = txn->engine_handle;
235 int columns = (1 + area->x1 - area->x0);
236 int rows = (1 + area->y1 - area->y0);
237 int i = columns*rows;
239 pat = alloc_dma(txn, sizeof(*pat), &pat_pa);
242 txn->last_pat->next_pa = (u32)pat_pa;
246 /* adjust Y coordinates based off of container parameters */
247 pat->area.y0 += engine->tcm->y_offset;
248 pat->area.y1 += engine->tcm->y_offset;
250 pat->ctrl = (struct pat_ctrl){
252 .lut_id = engine->tcm->lut_id,
255 data = alloc_dma(txn, 4*i, &data_pa);
256 /* FIXME: what if data_pa is more than 32-bit ? */
257 pat->data_pa = data_pa;
263 data[i] = (pages && pages[n]) ?
264 page_to_phys(pages[n]) : engine->dmm->dummy_pa;
273 * Commit the DMM transaction.
275 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
278 struct refill_engine *engine = txn->engine_handle;
279 struct dmm *dmm = engine->dmm;
281 if (!txn->last_pat) {
282 dev_err(engine->dmm->dev, "need at least one txn\n");
287 txn->last_pat->next_pa = 0;
288 /* ensure that the written descriptors are visible to DMM */
292 * NOTE: the wmb() above should be enough, but there seems to be a bug
293 * in OMAP's memory barrier implementation, which in some rare cases may
294 * cause the writes not to be observable after wmb().
297 /* read back to ensure the data is in RAM */
298 readl(&txn->last_pat->next_pa);
300 /* write to PAT_DESCR to clear out any pending transaction */
301 dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);
303 /* wait for engine ready: */
304 ret = wait_status(engine, DMM_PATSTATUS_READY);
310 /* mark whether it is async to denote list management in IRQ handler */
311 engine->async = wait ? false : true;
312 reinit_completion(&engine->compl);
313 /* verify that the irq handler sees the 'async' and completion value */
317 dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);
320 if (!wait_for_completion_timeout(&engine->compl,
321 msecs_to_jiffies(100))) {
322 dev_err(dmm->dev, "timed out waiting for done\n");
327 /* Check the engine status before continue */
328 ret = wait_status(engine, DMM_PATSTATUS_READY |
329 DMM_PATSTATUS_VALID | DMM_PATSTATUS_DONE);
333 /* only place engine back on list if we are done with it */
335 release_engine(engine);
343 static int fill(struct tcm_area *area, struct page **pages,
344 u32 npages, u32 roll, bool wait)
347 struct tcm_area slice, area_s;
353 * Asynchronous fill does not work reliably, as the driver does not
354 * handle errors in the async code paths. The fill operation may
355 * silently fail, leading to leaking DMM engines, which may eventually
356 * lead to deadlock if we run out of DMM engines.
358 * For now, always set 'wait' so that we only use sync fills. Async
359 * fills should be fixed, or alternatively we could decide to only
360 * support sync fills and so the whole async code path could be removed.
365 txn = dmm_txn_init(omap_dmm, area->tcm);
366 if (IS_ERR_OR_NULL(txn))
369 tcm_for_each_slice(slice, *area, area_s) {
370 struct pat_area p_area = {
371 .x0 = slice.p0.x, .y0 = slice.p0.y,
372 .x1 = slice.p1.x, .y1 = slice.p1.y,
375 dmm_txn_append(txn, &p_area, pages, npages, roll);
377 roll += tcm_sizeof(slice);
380 ret = dmm_txn_commit(txn, wait);
389 /* note: slots for which pages[i] == NULL are filled w/ dummy page
391 int tiler_pin(struct tiler_block *block, struct page **pages,
392 u32 npages, u32 roll, bool wait)
396 ret = fill(&block->area, pages, npages, roll, wait);
404 int tiler_unpin(struct tiler_block *block)
406 return fill(&block->area, NULL, 0, 0, false);
412 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,
415 struct tiler_block *block;
421 block = kzalloc(sizeof(*block), GFP_KERNEL);
423 return ERR_PTR(-ENOMEM);
425 BUG_ON(!validfmt(fmt));
427 /* convert width/height to slots */
428 w = DIV_ROUND_UP(w, geom[fmt].slot_w);
429 h = DIV_ROUND_UP(h, geom[fmt].slot_h);
431 /* convert alignment to slots */
432 slot_bytes = geom[fmt].slot_w * geom[fmt].cpp;
433 min_align = max(min_align, slot_bytes);
434 align = (align > min_align) ? ALIGN(align, min_align) : min_align;
439 ret = tcm_reserve_2d(containers[fmt], w, h, align, -1, slot_bytes,
443 return ERR_PTR(-ENOMEM);
446 /* add to allocation list */
447 spin_lock_irqsave(&list_lock, flags);
448 list_add(&block->alloc_node, &omap_dmm->alloc_head);
449 spin_unlock_irqrestore(&list_lock, flags);
454 struct tiler_block *tiler_reserve_1d(size_t size)
456 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
457 int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
461 return ERR_PTR(-ENOMEM);
463 block->fmt = TILFMT_PAGE;
465 if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
468 return ERR_PTR(-ENOMEM);
471 spin_lock_irqsave(&list_lock, flags);
472 list_add(&block->alloc_node, &omap_dmm->alloc_head);
473 spin_unlock_irqrestore(&list_lock, flags);
478 /* note: if you have pin'd pages, you should have already unpin'd first! */
479 int tiler_release(struct tiler_block *block)
481 int ret = tcm_free(&block->area);
485 dev_err(omap_dmm->dev, "failed to release block\n");
487 spin_lock_irqsave(&list_lock, flags);
488 list_del(&block->alloc_node);
489 spin_unlock_irqrestore(&list_lock, flags);
499 /* calculate the tiler space address of a pixel in a view orientation...
500 * below description copied from the display subsystem section of TRM:
502 * When the TILER is addressed, the bits:
503 * [28:27] = 0x0 for 8-bit tiled
504 * 0x1 for 16-bit tiled
505 * 0x2 for 32-bit tiled
507 * [31:29] = 0x0 for 0-degree view
508 * 0x1 for 180-degree view + mirroring
509 * 0x2 for 0-degree view + mirroring
510 * 0x3 for 180-degree view
511 * 0x4 for 270-degree view + mirroring
512 * 0x5 for 270-degree view
513 * 0x6 for 90-degree view
514 * 0x7 for 90-degree view + mirroring
515 * Otherwise the bits indicated the corresponding bit address to access
518 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
520 u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
522 x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
523 y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
524 alignment = geom[fmt].x_shft + geom[fmt].y_shft;
526 /* validate coordinate */
527 x_mask = MASK(x_bits);
528 y_mask = MASK(y_bits);
530 if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
531 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
532 x, x, x_mask, y, y, y_mask);
536 /* account for mirroring */
537 if (orient & MASK_X_INVERT)
539 if (orient & MASK_Y_INVERT)
542 /* get coordinate address */
543 if (orient & MASK_XY_FLIP)
544 tmp = ((x << y_bits) + y);
546 tmp = ((y << x_bits) + x);
548 return TIL_ADDR((tmp << alignment), orient, fmt);
551 dma_addr_t tiler_ssptr(struct tiler_block *block)
553 BUG_ON(!validfmt(block->fmt));
555 return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
556 block->area.p0.x * geom[block->fmt].slot_w,
557 block->area.p0.y * geom[block->fmt].slot_h);
560 dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,
563 struct tcm_pt *p = &block->area.p0;
564 BUG_ON(!validfmt(block->fmt));
566 return tiler_get_address(block->fmt, orient,
567 (p->x * geom[block->fmt].slot_w) + x,
568 (p->y * geom[block->fmt].slot_h) + y);
571 void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h)
573 BUG_ON(!validfmt(fmt));
574 *w = round_up(*w, geom[fmt].slot_w);
575 *h = round_up(*h, geom[fmt].slot_h);
578 u32 tiler_stride(enum tiler_fmt fmt, u32 orient)
580 BUG_ON(!validfmt(fmt));
582 if (orient & MASK_XY_FLIP)
583 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
585 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
588 size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h)
590 tiler_align(fmt, &w, &h);
591 return geom[fmt].cpp * w * h;
594 size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h)
596 BUG_ON(!validfmt(fmt));
597 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
600 u32 tiler_get_cpu_cache_flags(void)
602 return omap_dmm->plat_data->cpu_cache_flags;
605 bool dmm_is_available(void)
607 return omap_dmm ? true : false;
610 static int omap_dmm_remove(struct platform_device *dev)
612 struct tiler_block *block, *_block;
617 /* free all area regions */
618 spin_lock_irqsave(&list_lock, flags);
619 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
621 list_del(&block->alloc_node);
624 spin_unlock_irqrestore(&list_lock, flags);
626 for (i = 0; i < omap_dmm->num_lut; i++)
627 if (omap_dmm->tcm && omap_dmm->tcm[i])
628 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
629 kfree(omap_dmm->tcm);
631 kfree(omap_dmm->engines);
632 if (omap_dmm->refill_va)
633 dma_free_wc(omap_dmm->dev,
634 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
635 omap_dmm->refill_va, omap_dmm->refill_pa);
636 if (omap_dmm->dummy_page)
637 __free_page(omap_dmm->dummy_page);
639 if (omap_dmm->irq > 0)
640 free_irq(omap_dmm->irq, omap_dmm);
642 iounmap(omap_dmm->base);
650 static int omap_dmm_probe(struct platform_device *dev)
652 int ret = -EFAULT, i;
653 struct tcm_area area = {0};
654 u32 hwinfo, pat_geom;
655 struct resource *mem;
657 omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
661 /* initialize lists */
662 INIT_LIST_HEAD(&omap_dmm->alloc_head);
663 INIT_LIST_HEAD(&omap_dmm->idle_head);
665 init_waitqueue_head(&omap_dmm->engine_queue);
667 if (dev->dev.of_node) {
668 const struct of_device_id *match;
670 match = of_match_node(dmm_of_match, dev->dev.of_node);
672 dev_err(&dev->dev, "failed to find matching device node\n");
677 omap_dmm->plat_data = match->data;
680 /* lookup hwmod data - base address and irq */
681 mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
683 dev_err(&dev->dev, "failed to get base address resource\n");
687 omap_dmm->base = ioremap(mem->start, SZ_2K);
689 if (!omap_dmm->base) {
690 dev_err(&dev->dev, "failed to get dmm base address\n");
694 omap_dmm->irq = platform_get_irq(dev, 0);
695 if (omap_dmm->irq < 0) {
696 dev_err(&dev->dev, "failed to get IRQ resource\n");
700 omap_dmm->dev = &dev->dev;
702 hwinfo = dmm_read(omap_dmm, DMM_PAT_HWINFO);
703 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
704 omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
705 omap_dmm->container_width = 256;
706 omap_dmm->container_height = 128;
708 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
710 /* read out actual LUT width and height */
711 pat_geom = dmm_read(omap_dmm, DMM_PAT_GEOMETRY);
712 omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
713 omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
715 /* increment LUT by one if on OMAP5 */
716 /* LUT has twice the height, and is split into a separate container */
717 if (omap_dmm->lut_height != omap_dmm->container_height)
720 /* initialize DMM registers */
721 dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__0);
722 dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__1);
723 dmm_write(omap_dmm, 0x80808080, DMM_PAT_VIEW_MAP__0);
724 dmm_write(omap_dmm, 0x80000000, DMM_PAT_VIEW_MAP_BASE);
725 dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__0);
726 dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__1);
728 ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
729 "omap_dmm_irq_handler", omap_dmm);
732 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
738 /* Enable all interrupts for each refill engine except
739 * ERR_LUT_MISS<n> (which is just advisory, and we don't care
740 * about because we want to be able to refill live scanout
741 * buffers for accelerated pan/scroll) and FILL_DSC<n> which
742 * we just generally don't care about.
744 dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_SET);
746 omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
747 if (!omap_dmm->dummy_page) {
748 dev_err(&dev->dev, "could not allocate dummy page\n");
753 /* set dma mask for device */
754 ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
758 omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
760 /* alloc refill memory */
761 omap_dmm->refill_va = dma_alloc_wc(&dev->dev,
762 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
763 &omap_dmm->refill_pa, GFP_KERNEL);
764 if (!omap_dmm->refill_va) {
765 dev_err(&dev->dev, "could not allocate refill memory\n");
771 omap_dmm->engines = kcalloc(omap_dmm->num_engines,
772 sizeof(*omap_dmm->engines), GFP_KERNEL);
773 if (!omap_dmm->engines) {
778 for (i = 0; i < omap_dmm->num_engines; i++) {
779 omap_dmm->engines[i].id = i;
780 omap_dmm->engines[i].dmm = omap_dmm;
781 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
782 (REFILL_BUFFER_SIZE * i);
783 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
784 (REFILL_BUFFER_SIZE * i);
785 init_completion(&omap_dmm->engines[i].compl);
787 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
790 omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm),
792 if (!omap_dmm->tcm) {
797 /* init containers */
798 /* Each LUT is associated with a TCM (container manager). We use the
799 lut_id to denote the lut_id used to identify the correct LUT for
800 programming during reill operations */
801 for (i = 0; i < omap_dmm->num_lut; i++) {
802 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
803 omap_dmm->container_height);
805 if (!omap_dmm->tcm[i]) {
806 dev_err(&dev->dev, "failed to allocate container\n");
811 omap_dmm->tcm[i]->lut_id = i;
814 /* assign access mode containers to applicable tcm container */
815 /* OMAP 4 has 1 container for all 4 views */
816 /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
817 containers[TILFMT_8BIT] = omap_dmm->tcm[0];
818 containers[TILFMT_16BIT] = omap_dmm->tcm[0];
819 containers[TILFMT_32BIT] = omap_dmm->tcm[0];
821 if (omap_dmm->container_height != omap_dmm->lut_height) {
822 /* second LUT is used for PAGE mode. Programming must use
823 y offset that is added to all y coordinates. LUT id is still
824 0, because it is the same LUT, just the upper 128 lines */
825 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
826 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
827 omap_dmm->tcm[1]->lut_id = 0;
829 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
832 area = (struct tcm_area) {
834 .p1.x = omap_dmm->container_width - 1,
835 .p1.y = omap_dmm->container_height - 1,
838 /* initialize all LUTs to dummy page entries */
839 for (i = 0; i < omap_dmm->num_lut; i++) {
840 area.tcm = omap_dmm->tcm[i];
841 if (fill(&area, NULL, 0, 0, true))
842 dev_err(omap_dmm->dev, "refill failed");
845 dev_info(omap_dmm->dev, "initialized all PAT entries\n");
850 if (omap_dmm_remove(dev))
851 dev_err(&dev->dev, "cleanup failed\n");
859 #ifdef CONFIG_DEBUG_FS
861 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
862 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
863 static const char *special = ".,:;'\"`~!^-+";
865 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
869 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
870 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
871 if (map[y][x] == ' ' || ovw)
875 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
878 map[p->y / ydiv][p->x / xdiv] = c;
881 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
883 return map[p->y / ydiv][p->x / xdiv];
886 static int map_width(int xdiv, int x0, int x1)
888 return (x1 / xdiv) - (x0 / xdiv) + 1;
891 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
893 char *p = map[yd] + (x0 / xdiv);
894 int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
902 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
905 sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
906 if (a->p0.y + 1 < a->p1.y) {
907 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
909 } else if (a->p0.y < a->p1.y) {
910 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
911 text_map(map, xdiv, nice, a->p0.y / ydiv,
912 a->p0.x + xdiv, 256 - 1);
913 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
914 text_map(map, xdiv, nice, a->p1.y / ydiv,
916 } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
917 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
921 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
924 sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
925 if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
926 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
930 int tiler_map_show(struct seq_file *s, void *arg)
932 int xdiv = 2, ydiv = 1;
933 char **map = NULL, *global_map;
934 struct tiler_block *block;
935 struct tcm_area a, p;
937 const char *m2d = alphabet;
938 const char *a2d = special;
939 const char *m2dp = m2d, *a2dp = a2d;
948 /* early return if dmm/tiler device is not initialized */
952 h_adj = omap_dmm->container_height / ydiv;
953 w_adj = omap_dmm->container_width / xdiv;
955 map = kmalloc_array(h_adj, sizeof(*map), GFP_KERNEL);
956 global_map = kmalloc_array(w_adj + 1, h_adj, GFP_KERNEL);
958 if (!map || !global_map)
961 for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
962 memset(map, 0, h_adj * sizeof(*map));
963 memset(global_map, ' ', (w_adj + 1) * h_adj);
965 for (i = 0; i < omap_dmm->container_height; i++) {
966 map[i] = global_map + i * (w_adj + 1);
970 spin_lock_irqsave(&list_lock, flags);
972 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
973 if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
974 if (block->fmt != TILFMT_PAGE) {
975 fill_map(map, xdiv, ydiv, &block->area,
981 map_2d_info(map, xdiv, ydiv, nice,
984 bool start = read_map_pt(map, xdiv,
985 ydiv, &block->area.p0) == ' ';
986 bool end = read_map_pt(map, xdiv, ydiv,
987 &block->area.p1) == ' ';
989 tcm_for_each_slice(a, block->area, p)
990 fill_map(map, xdiv, ydiv, &a,
992 fill_map_pt(map, xdiv, ydiv,
995 fill_map_pt(map, xdiv, ydiv,
998 map_1d_info(map, xdiv, ydiv, nice,
1004 spin_unlock_irqrestore(&list_lock, flags);
1007 seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
1008 for (i = 0; i < 128; i++)
1009 seq_printf(s, "%03d:%s\n", i, map[i]);
1010 seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
1012 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
1014 for (i = 0; i < 128; i++)
1015 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
1016 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
1029 #ifdef CONFIG_PM_SLEEP
1030 static int omap_dmm_resume(struct device *dev)
1032 struct tcm_area area;
1038 area = (struct tcm_area) {
1040 .p1.x = omap_dmm->container_width - 1,
1041 .p1.y = omap_dmm->container_height - 1,
1044 /* initialize all LUTs to dummy page entries */
1045 for (i = 0; i < omap_dmm->num_lut; i++) {
1046 area.tcm = omap_dmm->tcm[i];
1047 if (fill(&area, NULL, 0, 0, true))
1048 dev_err(dev, "refill failed");
1055 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
1057 #if defined(CONFIG_OF)
1058 static const struct dmm_platform_data dmm_omap4_platform_data = {
1059 .cpu_cache_flags = OMAP_BO_WC,
1062 static const struct dmm_platform_data dmm_omap5_platform_data = {
1063 .cpu_cache_flags = OMAP_BO_UNCACHED,
1066 static const struct of_device_id dmm_of_match[] = {
1068 .compatible = "ti,omap4-dmm",
1069 .data = &dmm_omap4_platform_data,
1072 .compatible = "ti,omap5-dmm",
1073 .data = &dmm_omap5_platform_data,
1079 struct platform_driver omap_dmm_driver = {
1080 .probe = omap_dmm_probe,
1081 .remove = omap_dmm_remove,
1083 .owner = THIS_MODULE,
1084 .name = DMM_DRIVER_NAME,
1085 .of_match_table = of_match_ptr(dmm_of_match),
1086 .pm = &omap_dmm_pm_ops,
1090 MODULE_LICENSE("GPL v2");
1091 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
1092 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");