drivers/gpu/drm/omapdrm/omap_crtc.c

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  * Author: Rob Clark <rob@ti.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_mode.h>
  23 #include <drm/drm_plane_helper.h>
  24 #include <linux/math64.h>
  25
  26 #include "omap_drv.h"
  27
  28 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
  29
  30 struct omap_crtc_state {
  31         /* Must be first. */
  32         struct drm_crtc_state base;
  33         /* Shadow values for legacy userspace support. */
  34         unsigned int rotation;
  35         unsigned int zpos;
  36 };
  37
  38 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  39
  40 struct omap_crtc {
  41         struct drm_crtc base;
  42
  43         const char *name;
  44         enum omap_channel channel;
  45
  46         struct videomode vm;
  47
  48         bool ignore_digit_sync_lost;
  49
  50         bool enabled;
  51         bool pending;
  52         wait_queue_head_t pending_wait;
  53         struct drm_pending_vblank_event *event;
  54 };
  55
  56 /* -----------------------------------------------------------------------------
  57  * Helper Functions
  58  */
  59
  60 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  61 {
  62         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  63         return &omap_crtc->vm;
  64 }
  65
  66 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  67 {
  68         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  69         return omap_crtc->channel;
  70 }
  71
  72 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  73 {
  74         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  75         unsigned long flags;
  76         bool pending;
  77
  78         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  79         pending = omap_crtc->pending;
  80         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  81
  82         return pending;
  83 }
  84
  85 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  86 {
  87         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  88
  89         /*
  90          * Timeout is set to a "sufficiently" high value, which should cover
  91          * a single frame refresh even on slower displays.
  92          */
  93         return wait_event_timeout(omap_crtc->pending_wait,
  94                                   !omap_crtc_is_pending(crtc),
  95                                   msecs_to_jiffies(250));
  96 }
  97
  98 /* -----------------------------------------------------------------------------
  99  * DSS Manager Functions
 100  */
 101
 102 /*
 103  * Manager-ops, callbacks from output when they need to configure
 104  * the upstream part of the video pipe.
 105  *
 106  * Most of these we can ignore until we add support for command-mode
 107  * panels.. for video-mode the crtc-helpers already do an adequate
 108  * job of sequencing the setup of the video pipe in the proper order
 109  */
 110
 111 /* ovl-mgr-id -> crtc */
 112 static struct omap_crtc *omap_crtcs[8];
 113 static struct omap_dss_device *omap_crtc_output[8];
 114
 115 /* we can probably ignore these until we support command-mode panels: */
 116 static int omap_crtc_dss_connect(struct omap_drm_private *priv,
 117                 enum omap_channel channel,
 118                 struct omap_dss_device *dst)
 119 {
 120         const struct dispc_ops *dispc_ops = priv->dispc_ops;
 121         struct dispc_device *dispc = priv->dispc;
 122
 123         if (omap_crtc_output[channel])
 124                 return -EINVAL;
 125
 126         if (!(dispc_ops->mgr_get_supported_outputs(dispc, channel) & dst->id))
 127                 return -EINVAL;
 128
 129         omap_crtc_output[channel] = dst;
 130         dst->dispc_channel_connected = true;
 131
 132         return 0;
 133 }
 134
 135 static void omap_crtc_dss_disconnect(struct omap_drm_private *priv,
 136                 enum omap_channel channel,
 137                 struct omap_dss_device *dst)
 138 {
 139         omap_crtc_output[channel] = NULL;
 140         dst->dispc_channel_connected = false;
 141 }
 142
 143 static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
 144                                        enum omap_channel channel)
 145 {
 146 }
 147
 148 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 149 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 150 {
 151         struct drm_device *dev = crtc->dev;
 152         struct omap_drm_private *priv = dev->dev_private;
 153         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 154         enum omap_channel channel = omap_crtc->channel;
 155         struct omap_irq_wait *wait;
 156         u32 framedone_irq, vsync_irq;
 157         int ret;
 158
 159         if (WARN_ON(omap_crtc->enabled == enable))
 160                 return;
 161
 162         if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
 163                 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 164                 omap_crtc->enabled = enable;
 165                 return;
 166         }
 167
 168         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 169                 /*
 170                  * Digit output produces some sync lost interrupts during the
 171                  * first frame when enabling, so we need to ignore those.
 172                  */
 173                 omap_crtc->ignore_digit_sync_lost = true;
 174         }
 175
 176         framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
 177                                                                channel);
 178         vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
 179
 180         if (enable) {
 181                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 182         } else {
 183                 /*
 184                  * When we disable the digit output, we need to wait for
 185                  * FRAMEDONE to know that DISPC has finished with the output.
 186                  *
 187                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 188                  * that case we need to use vsync interrupt, and wait for both
 189                  * even and odd frames.
 190                  */
 191
 192                 if (framedone_irq)
 193                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 194                 else
 195                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 196         }
 197
 198         priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 199         omap_crtc->enabled = enable;
 200
 201         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 202         if (ret) {
 203                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 204                                 omap_crtc->name, enable ? "enable" : "disable");
 205         }
 206
 207         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 208                 omap_crtc->ignore_digit_sync_lost = false;
 209                 /* make sure the irq handler sees the value above */
 210                 mb();
 211         }
 212 }
 213
 214
 215 static int omap_crtc_dss_enable(struct omap_drm_private *priv,
 216                                 enum omap_channel channel)
 217 {
 218         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 219
 220         priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
 221                                          &omap_crtc->vm);
 222         omap_crtc_set_enabled(&omap_crtc->base, true);
 223
 224         return 0;
 225 }
 226
 227 static void omap_crtc_dss_disable(struct omap_drm_private *priv,
 228                                   enum omap_channel channel)
 229 {
 230         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 231
 232         omap_crtc_set_enabled(&omap_crtc->base, false);
 233 }
 234
 235 static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
 236                 enum omap_channel channel,
 237                 const struct videomode *vm)
 238 {
 239         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 240         DBG("%s", omap_crtc->name);
 241         omap_crtc->vm = *vm;
 242 }
 243
 244 static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
 245                 enum omap_channel channel,
 246                 const struct dss_lcd_mgr_config *config)
 247 {
 248         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 249
 250         DBG("%s", omap_crtc->name);
 251         priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
 252                                             config);
 253 }
 254
 255 static int omap_crtc_dss_register_framedone(
 256                 struct omap_drm_private *priv, enum omap_channel channel,
 257                 void (*handler)(void *), void *data)
 258 {
 259         return 0;
 260 }
 261
 262 static void omap_crtc_dss_unregister_framedone(
 263                 struct omap_drm_private *priv, enum omap_channel channel,
 264                 void (*handler)(void *), void *data)
 265 {
 266 }
 267
 268 static const struct dss_mgr_ops mgr_ops = {
 269         .connect = omap_crtc_dss_connect,
 270         .disconnect = omap_crtc_dss_disconnect,
 271         .start_update = omap_crtc_dss_start_update,
 272         .enable = omap_crtc_dss_enable,
 273         .disable = omap_crtc_dss_disable,
 274         .set_timings = omap_crtc_dss_set_timings,
 275         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 276         .register_framedone_handler = omap_crtc_dss_register_framedone,
 277         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 278 };
 279
 280 /* -----------------------------------------------------------------------------
 281  * Setup, Flush and Page Flip
 282  */
 283
 284 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
 285 {
 286         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 287
 288         if (omap_crtc->ignore_digit_sync_lost) {
 289                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 290                 if (!irqstatus)
 291                         return;
 292         }
 293
 294         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 295 }
 296
 297 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
 298 {
 299         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 300         struct drm_device *dev = omap_crtc->base.dev;
 301         struct omap_drm_private *priv = dev->dev_private;
 302         bool pending;
 303
 304         spin_lock(&crtc->dev->event_lock);
 305         /*
 306          * If the dispc is busy we're racing the flush operation. Try again on
 307          * the next vblank interrupt.
 308          */
 309         if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
 310                 spin_unlock(&crtc->dev->event_lock);
 311                 return;
 312         }
 313
 314         /* Send the vblank event if one has been requested. */
 315         if (omap_crtc->event) {
 316                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 317                 omap_crtc->event = NULL;
 318         }
 319
 320         pending = omap_crtc->pending;
 321         omap_crtc->pending = false;
 322         spin_unlock(&crtc->dev->event_lock);
 323
 324         if (pending)
 325                 drm_crtc_vblank_put(crtc);
 326
 327         /* Wake up omap_atomic_complete. */
 328         wake_up(&omap_crtc->pending_wait);
 329
 330         DBG("%s: apply done", omap_crtc->name);
 331 }
 332
 333 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
 334 {
 335         struct omap_drm_private *priv = crtc->dev->dev_private;
 336         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 337         struct omap_overlay_manager_info info;
 338
 339         memset(&info, 0, sizeof(info));
 340
 341         info.default_color = 0x000000;
 342         info.trans_enabled = false;
 343         info.partial_alpha_enabled = false;
 344         info.cpr_enable = false;
 345
 346         priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
 347 }
 348
 349 /* -----------------------------------------------------------------------------
 350  * CRTC Functions
 351  */
 352
 353 static void omap_crtc_destroy(struct drm_crtc *crtc)
 354 {
 355         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 356
 357         DBG("%s", omap_crtc->name);
 358
 359         drm_crtc_cleanup(crtc);
 360
 361         kfree(omap_crtc);
 362 }
 363
 364 static void omap_crtc_arm_event(struct drm_crtc *crtc)
 365 {
 366         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 367
 368         WARN_ON(omap_crtc->pending);
 369         omap_crtc->pending = true;
 370
 371         if (crtc->state->event) {
 372                 omap_crtc->event = crtc->state->event;
 373                 crtc->state->event = NULL;
 374         }
 375 }
 376
 377 static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
 378                                     struct drm_crtc_state *old_state)
 379 {
 380         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 381         int ret;
 382
 383         DBG("%s", omap_crtc->name);
 384
 385         spin_lock_irq(&crtc->dev->event_lock);
 386         drm_crtc_vblank_on(crtc);
 387         ret = drm_crtc_vblank_get(crtc);
 388         WARN_ON(ret != 0);
 389
 390         omap_crtc_arm_event(crtc);
 391         spin_unlock_irq(&crtc->dev->event_lock);
 392 }
 393
 394 static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
 395                                      struct drm_crtc_state *old_state)
 396 {
 397         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 398
 399         DBG("%s", omap_crtc->name);
 400
 401         spin_lock_irq(&crtc->dev->event_lock);
 402         if (crtc->state->event) {
 403                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 404                 crtc->state->event = NULL;
 405         }
 406         spin_unlock_irq(&crtc->dev->event_lock);
 407
 408         drm_crtc_vblank_off(crtc);
 409 }
 410
 411 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
 412                                         const struct drm_display_mode *mode)
 413 {
 414         struct omap_drm_private *priv = crtc->dev->dev_private;
 415
 416         /* Check for bandwidth limit */
 417         if (priv->max_bandwidth) {
 418                 /*
 419                  * Estimation for the bandwidth need of a given mode with one
 420                  * full screen plane:
 421                  * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
 422                  *                                      ^^ Refresh rate ^^
 423                  *
 424                  * The interlaced mode is taken into account by using the
 425                  * pixelclock in the calculation.
 426                  *
 427                  * The equation is rearranged for 64bit arithmetic.
 428                  */
 429                 uint64_t bandwidth = mode->clock * 1000;
 430                 unsigned int bpp = 4;
 431
 432                 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
 433                 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
 434
 435                 /*
 436                  * Reject modes which would need more bandwidth if used with one
 437                  * full resolution plane (most common use case).
 438                  */
 439                 if (priv->max_bandwidth < bandwidth)
 440                         return MODE_BAD;
 441         }
 442
 443         return MODE_OK;
 444 }
 445
 446 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 447 {
 448         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 449         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 450         struct omap_drm_private *priv = crtc->dev->dev_private;
 451         const u32 flags_mask = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_DE_LOW |
 452                 DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
 453                 DISPLAY_FLAGS_SYNC_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE;
 454         unsigned int i;
 455
 456         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 457             omap_crtc->name, mode->base.id, mode->name,
 458             mode->vrefresh, mode->clock,
 459             mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
 460             mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
 461             mode->type, mode->flags);
 462
 463         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 464
 465         /*
 466          * HACK: This fixes the vm flags.
 467          * struct drm_display_mode does not contain the VSYNC/HSYNC/DE flags
 468          * and they get lost when converting back and forth between
 469          * struct drm_display_mode and struct videomode. The hack below
 470          * goes and fetches the missing flags from the panel drivers.
 471          *
 472          * Correct solution would be to use DRM's bus-flags, but that's not
 473          * easily possible before the omapdrm's panel/encoder driver model
 474          * has been changed to the DRM model.
 475          */
 476
 477         for (i = 0; i < priv->num_encoders; ++i) {
 478                 struct drm_encoder *encoder = priv->encoders[i];
 479
 480                 if (encoder->crtc == crtc) {
 481                         struct omap_dss_device *dssdev;
 482
 483                         dssdev = omap_encoder_get_dssdev(encoder);
 484
 485                         if (dssdev) {
 486                                 struct videomode vm = {0};
 487
 488                                 dssdev->driver->get_timings(dssdev, &vm);
 489
 490                                 omap_crtc->vm.flags |= vm.flags & flags_mask;
 491                         }
 492
 493                         break;
 494                 }
 495         }
 496 }
 497
 498 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 499                                 struct drm_crtc_state *state)
 500 {
 501         struct drm_plane_state *pri_state;
 502
 503         if (state->color_mgmt_changed && state->gamma_lut) {
 504                 unsigned int length = state->gamma_lut->length /
 505                         sizeof(struct drm_color_lut);
 506
 507                 if (length < 2)
 508                         return -EINVAL;
 509         }
 510
 511         pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
 512         if (pri_state) {
 513                 struct omap_crtc_state *omap_crtc_state =
 514                         to_omap_crtc_state(state);
 515
 516                 /* Mirror new values for zpos and rotation in omap_crtc_state */
 517                 omap_crtc_state->zpos = pri_state->zpos;
 518                 omap_crtc_state->rotation = pri_state->rotation;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 525                                    struct drm_crtc_state *old_crtc_state)
 526 {
 527 }
 528
 529 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 530                                    struct drm_crtc_state *old_crtc_state)
 531 {
 532         struct omap_drm_private *priv = crtc->dev->dev_private;
 533         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 534         int ret;
 535
 536         if (crtc->state->color_mgmt_changed) {
 537                 struct drm_color_lut *lut = NULL;
 538                 unsigned int length = 0;
 539
 540                 if (crtc->state->gamma_lut) {
 541                         lut = (struct drm_color_lut *)
 542                                 crtc->state->gamma_lut->data;
 543                         length = crtc->state->gamma_lut->length /
 544                                 sizeof(*lut);
 545                 }
 546                 priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
 547                                                lut, length);
 548         }
 549
 550         omap_crtc_write_crtc_properties(crtc);
 551
 552         /* Only flush the CRTC if it is currently enabled. */
 553         if (!omap_crtc->enabled)
 554                 return;
 555
 556         DBG("%s: GO", omap_crtc->name);
 557
 558         ret = drm_crtc_vblank_get(crtc);
 559         WARN_ON(ret != 0);
 560
 561         spin_lock_irq(&crtc->dev->event_lock);
 562         priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
 563         omap_crtc_arm_event(crtc);
 564         spin_unlock_irq(&crtc->dev->event_lock);
 565 }
 566
 567 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 568                                          struct drm_crtc_state *state,
 569                                          struct drm_property *property,
 570                                          u64 val)
 571 {
 572         struct omap_drm_private *priv = crtc->dev->dev_private;
 573         struct drm_plane_state *plane_state;
 574
 575         /*
 576          * Delegate property set to the primary plane. Get the plane state and
 577          * set the property directly, the shadow copy will be assigned in the
 578          * omap_crtc_atomic_check callback. This way updates to plane state will
 579          * always be mirrored in the crtc state correctly.
 580          */
 581         plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
 582         if (IS_ERR(plane_state))
 583                 return PTR_ERR(plane_state);
 584
 585         if (property == crtc->primary->rotation_property)
 586                 plane_state->rotation = val;
 587         else if (property == priv->zorder_prop)
 588                 plane_state->zpos = val;
 589         else
 590                 return -EINVAL;
 591
 592         return 0;
 593 }
 594
 595 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 596                                          const struct drm_crtc_state *state,
 597                                          struct drm_property *property,
 598                                          u64 *val)
 599 {
 600         struct omap_drm_private *priv = crtc->dev->dev_private;
 601         struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
 602
 603         if (property == crtc->primary->rotation_property)
 604                 *val = omap_state->rotation;
 605         else if (property == priv->zorder_prop)
 606                 *val = omap_state->zpos;
 607         else
 608                 return -EINVAL;
 609
 610         return 0;
 611 }
 612
 613 static void omap_crtc_reset(struct drm_crtc *crtc)
 614 {
 615         if (crtc->state)
 616                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 617
 618         kfree(crtc->state);
 619         crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
 620
 621         if (crtc->state)
 622                 crtc->state->crtc = crtc;
 623 }
 624
 625 static struct drm_crtc_state *
 626 omap_crtc_duplicate_state(struct drm_crtc *crtc)
 627 {
 628         struct omap_crtc_state *state, *current_state;
 629
 630         if (WARN_ON(!crtc->state))
 631                 return NULL;
 632
 633         current_state = to_omap_crtc_state(crtc->state);
 634
 635         state = kmalloc(sizeof(*state), GFP_KERNEL);
 636         if (!state)
 637                 return NULL;
 638
 639         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 640
 641         state->zpos = current_state->zpos;
 642         state->rotation = current_state->rotation;
 643
 644         return &state->base;
 645 }
 646
 647 static const struct drm_crtc_funcs omap_crtc_funcs = {
 648         .reset = omap_crtc_reset,
 649         .set_config = drm_atomic_helper_set_config,
 650         .destroy = omap_crtc_destroy,
 651         .page_flip = drm_atomic_helper_page_flip,
 652         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 653         .atomic_duplicate_state = omap_crtc_duplicate_state,
 654         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 655         .atomic_set_property = omap_crtc_atomic_set_property,
 656         .atomic_get_property = omap_crtc_atomic_get_property,
 657         .enable_vblank = omap_irq_enable_vblank,
 658         .disable_vblank = omap_irq_disable_vblank,
 659 };
 660
 661 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 662         .mode_set_nofb = omap_crtc_mode_set_nofb,
 663         .atomic_check = omap_crtc_atomic_check,
 664         .atomic_begin = omap_crtc_atomic_begin,
 665         .atomic_flush = omap_crtc_atomic_flush,
 666         .atomic_enable = omap_crtc_atomic_enable,
 667         .atomic_disable = omap_crtc_atomic_disable,
 668         .mode_valid = omap_crtc_mode_valid,
 669 };
 670
 671 /* -----------------------------------------------------------------------------
 672  * Init and Cleanup
 673  */
 674
 675 static const char *channel_names[] = {
 676         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 677         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 678         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 679         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 680 };
 681
 682 void omap_crtc_pre_init(struct omap_drm_private *priv)
 683 {
 684         memset(omap_crtcs, 0, sizeof(omap_crtcs));
 685
 686         dss_install_mgr_ops(&mgr_ops, priv);
 687 }
 688
 689 void omap_crtc_pre_uninit(void)
 690 {
 691         dss_uninstall_mgr_ops();
 692 }
 693
 694 /* initialize crtc */
 695 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 696                 struct drm_plane *plane, struct omap_dss_device *dssdev)
 697 {
 698         struct omap_drm_private *priv = dev->dev_private;
 699         struct drm_crtc *crtc = NULL;
 700         struct omap_crtc *omap_crtc;
 701         enum omap_channel channel;
 702         struct omap_dss_device *out;
 703         int ret;
 704
 705         out = omapdss_find_output_from_display(dssdev);
 706         channel = out->dispc_channel;
 707         omap_dss_put_device(out);
 708
 709         DBG("%s", channel_names[channel]);
 710
 711         /* Multiple displays on same channel is not allowed */
 712         if (WARN_ON(omap_crtcs[channel] != NULL))
 713                 return ERR_PTR(-EINVAL);
 714
 715         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 716         if (!omap_crtc)
 717                 return ERR_PTR(-ENOMEM);
 718
 719         crtc = &omap_crtc->base;
 720
 721         init_waitqueue_head(&omap_crtc->pending_wait);
 722
 723         omap_crtc->channel = channel;
 724         omap_crtc->name = channel_names[channel];
 725
 726         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 727                                         &omap_crtc_funcs, NULL);
 728         if (ret < 0) {
 729                 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
 730                         __func__, dssdev->name);
 731                 kfree(omap_crtc);
 732                 return ERR_PTR(ret);
 733         }
 734
 735         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 736
 737         /* The dispc API adapts to what ever size, but the HW supports
 738          * 256 element gamma table for LCDs and 1024 element table for
 739          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 740          * tables so lets use that. Size of HW gamma table can be
 741          * extracted with dispc_mgr_gamma_size(). If it returns 0
 742          * gamma table is not supprted.
 743          */
 744         if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
 745                 unsigned int gamma_lut_size = 256;
 746
 747                 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
 748                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 749         }
 750
 751         omap_plane_install_properties(crtc->primary, &crtc->base);
 752
 753         omap_crtcs[channel] = omap_crtc;
 754
 755         return crtc;
 756 }