2 * Copyright (C) 2014 Texas Instruments Ltd
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * You should have received a copy of the GNU General Public License along with
9 * this program. If not, see <http://www.gnu.org/licenses/>.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/sched.h>
22 #include "dss_features.h"
24 struct dss_video_pll {
29 void __iomem *clkctrl_base;
32 #define REG_MOD(reg, val, start, end) \
33 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
35 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
37 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
40 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
42 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
45 static void dss_dpll_power_enable(struct dss_video_pll *vpll)
47 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
50 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
51 * so we have to use fixed delay here.
56 static void dss_dpll_power_disable(struct dss_video_pll *vpll)
58 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
61 static int dss_video_pll_enable(struct dss_pll *pll)
63 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
66 r = dss_runtime_get();
70 dss_ctrl_pll_enable(pll->id, true);
72 dss_dpll_enable_scp_clk(vpll);
74 r = dss_pll_wait_reset_done(pll);
78 dss_dpll_power_enable(vpll);
83 dss_dpll_disable_scp_clk(vpll);
84 dss_ctrl_pll_enable(pll->id, false);
90 static void dss_video_pll_disable(struct dss_pll *pll)
92 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
94 dss_dpll_power_disable(vpll);
96 dss_dpll_disable_scp_clk(vpll);
98 dss_ctrl_pll_enable(pll->id, false);
103 static const struct dss_pll_ops dss_pll_ops = {
104 .enable = dss_video_pll_enable,
105 .disable = dss_video_pll_disable,
106 .set_config = dss_pll_write_config_type_a,
109 static const struct dss_pll_hw dss_dra7_video_pll_hw = {
110 .type = DSS_PLL_TYPE_A,
112 .n_max = (1 << 8) - 1,
113 .m_max = (1 << 12) - 1,
114 .mX_max = (1 << 5) - 1,
117 .clkdco_max = 1800000000,
136 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
137 struct regulator *regulator)
139 const char * const reg_name[] = { "pll1", "pll2" };
140 const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
141 const char * const clkin_name[] = { "video1_clk", "video2_clk" };
143 struct resource *res;
144 struct dss_video_pll *vpll;
145 void __iomem *pll_base, *clkctrl_base;
152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]);
155 "missing platform resource data for pll%d\n", id);
156 return ERR_PTR(-ENODEV);
159 pll_base = devm_ioremap_resource(&pdev->dev, res);
160 if (IS_ERR(pll_base)) {
161 dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id);
162 return ERR_CAST(pll_base);
167 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
171 "missing platform resource data for pll%d\n", id);
172 return ERR_PTR(-ENODEV);
175 clkctrl_base = devm_ioremap_resource(&pdev->dev, res);
176 if (IS_ERR(clkctrl_base)) {
177 dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id);
178 return ERR_CAST(clkctrl_base);
183 clk = devm_clk_get(&pdev->dev, clkin_name[id]);
185 DSSERR("can't get video pll clkin\n");
186 return ERR_CAST(clk);
189 vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
191 return ERR_PTR(-ENOMEM);
193 vpll->dev = &pdev->dev;
194 vpll->clkctrl_base = clkctrl_base;
198 pll->name = id == 0 ? "video0" : "video1";
199 pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
201 pll->regulator = regulator;
202 pll->base = pll_base;
203 pll->hw = &dss_dra7_video_pll_hw;
204 pll->ops = &dss_pll_ops;
206 r = dss_pll_register(pll);
213 void dss_video_pll_uninit(struct dss_pll *pll)
215 dss_pll_unregister(pll);