2 * Copyright (C) 2014 Texas Instruments Ltd
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * You should have received a copy of the GNU General Public License along with
9 * this program. If not, see <http://www.gnu.org/licenses/>.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/sched.h>
23 struct dss_video_pll {
28 void __iomem *clkctrl_base;
31 #define REG_MOD(reg, val, start, end) \
32 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
34 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
36 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
39 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
41 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
44 static void dss_dpll_power_enable(struct dss_video_pll *vpll)
46 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
49 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
50 * so we have to use fixed delay here.
55 static void dss_dpll_power_disable(struct dss_video_pll *vpll)
57 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
60 static int dss_video_pll_enable(struct dss_pll *pll)
62 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
65 r = dss_runtime_get();
69 dss_ctrl_pll_enable(pll->id, true);
71 dss_dpll_enable_scp_clk(vpll);
73 r = dss_pll_wait_reset_done(pll);
77 dss_dpll_power_enable(vpll);
82 dss_dpll_disable_scp_clk(vpll);
83 dss_ctrl_pll_enable(pll->id, false);
89 static void dss_video_pll_disable(struct dss_pll *pll)
91 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
93 dss_dpll_power_disable(vpll);
95 dss_dpll_disable_scp_clk(vpll);
97 dss_ctrl_pll_enable(pll->id, false);
102 static const struct dss_pll_ops dss_pll_ops = {
103 .enable = dss_video_pll_enable,
104 .disable = dss_video_pll_disable,
105 .set_config = dss_pll_write_config_type_a,
108 static const struct dss_pll_hw dss_dra7_video_pll_hw = {
109 .type = DSS_PLL_TYPE_A,
111 .n_max = (1 << 8) - 1,
112 .m_max = (1 << 12) - 1,
113 .mX_max = (1 << 5) - 1,
116 .clkdco_max = 1800000000,
137 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
138 struct regulator *regulator)
140 const char * const reg_name[] = { "pll1", "pll2" };
141 const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
142 const char * const clkin_name[] = { "video1_clk", "video2_clk" };
144 struct resource *res;
145 struct dss_video_pll *vpll;
146 void __iomem *pll_base, *clkctrl_base;
153 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]);
154 pll_base = devm_ioremap_resource(&pdev->dev, res);
155 if (IS_ERR(pll_base))
156 return ERR_CAST(pll_base);
160 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
162 clkctrl_base = devm_ioremap_resource(&pdev->dev, res);
163 if (IS_ERR(clkctrl_base))
164 return ERR_CAST(clkctrl_base);
168 clk = devm_clk_get(&pdev->dev, clkin_name[id]);
170 DSSERR("can't get video pll clkin\n");
171 return ERR_CAST(clk);
174 vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
176 return ERR_PTR(-ENOMEM);
178 vpll->dev = &pdev->dev;
179 vpll->clkctrl_base = clkctrl_base;
183 pll->name = id == 0 ? "video0" : "video1";
184 pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
186 pll->regulator = regulator;
187 pll->base = pll_base;
188 pll->hw = &dss_dra7_video_pll_hw;
189 pll->ops = &dss_pll_ops;
191 r = dss_pll_register(pll);
198 void dss_video_pll_uninit(struct dss_pll *pll)
200 dss_pll_unregister(pll);