2 * linux/drivers/video/omap2/dss/venc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * VENC settings from TI's DSS driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "VENC"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <linux/of_graph.h>
39 #include <linux/component.h>
40 #include <linux/sys_soc.h>
46 #define VENC_REV_ID 0x00
47 #define VENC_STATUS 0x04
48 #define VENC_F_CONTROL 0x08
49 #define VENC_VIDOUT_CTRL 0x10
50 #define VENC_SYNC_CTRL 0x14
51 #define VENC_LLEN 0x1C
52 #define VENC_FLENS 0x20
53 #define VENC_HFLTR_CTRL 0x24
54 #define VENC_CC_CARR_WSS_CARR 0x28
55 #define VENC_C_PHASE 0x2C
56 #define VENC_GAIN_U 0x30
57 #define VENC_GAIN_V 0x34
58 #define VENC_GAIN_Y 0x38
59 #define VENC_BLACK_LEVEL 0x3C
60 #define VENC_BLANK_LEVEL 0x40
61 #define VENC_X_COLOR 0x44
62 #define VENC_M_CONTROL 0x48
63 #define VENC_BSTAMP_WSS_DATA 0x4C
64 #define VENC_S_CARR 0x50
65 #define VENC_LINE21 0x54
66 #define VENC_LN_SEL 0x58
67 #define VENC_L21__WC_CTL 0x5C
68 #define VENC_HTRIGGER_VTRIGGER 0x60
69 #define VENC_SAVID__EAVID 0x64
70 #define VENC_FLEN__FAL 0x68
71 #define VENC_LAL__PHASE_RESET 0x6C
72 #define VENC_HS_INT_START_STOP_X 0x70
73 #define VENC_HS_EXT_START_STOP_X 0x74
74 #define VENC_VS_INT_START_X 0x78
75 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
76 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
77 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
78 #define VENC_VS_EXT_STOP_Y 0x88
79 #define VENC_AVID_START_STOP_X 0x90
80 #define VENC_AVID_START_STOP_Y 0x94
81 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
82 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
83 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
84 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
85 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
86 #define VENC_GEN_CTRL 0xB8
87 #define VENC_OUTPUT_CONTROL 0xC4
88 #define VENC_OUTPUT_TEST 0xC8
89 #define VENC_DAC_B__DAC_C 0xC8
112 u32 htrigger_vtrigger;
115 u32 lal__phase_reset;
116 u32 hs_int_start_stop_x;
117 u32 hs_ext_start_stop_x;
119 u32 vs_int_stop_x__vs_int_start_y;
120 u32 vs_int_stop_y__vs_ext_start_x;
121 u32 vs_ext_stop_x__vs_ext_start_y;
123 u32 avid_start_stop_x;
124 u32 avid_start_stop_y;
125 u32 fid_int_start_x__fid_int_start_y;
126 u32 fid_int_offset_y__fid_ext_start_x;
127 u32 fid_ext_start_y__fid_ext_offset_y;
128 u32 tvdetgp_int_start_stop_x;
129 u32 tvdetgp_int_start_stop_y;
134 static const struct venc_config venc_config_pal_trm = {
138 .llen = 0x35F, /* 863 */
139 .flens = 0x270, /* 624 */
141 .cc_carr_wss_carr = 0x2F7225ED,
150 .bstamp_wss_data = 0x3F,
151 .s_carr = 0x2A098ACB,
153 .ln_sel = 0x01290015,
154 .l21__wc_ctl = 0x0000F603,
155 .htrigger_vtrigger = 0,
157 .savid__eavid = 0x06A70108,
158 .flen__fal = 0x00180270,
159 .lal__phase_reset = 0x00040135,
160 .hs_int_start_stop_x = 0x00880358,
161 .hs_ext_start_stop_x = 0x000F035F,
162 .vs_int_start_x = 0x01A70000,
163 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
166 .vs_ext_stop_y = 0x00000025,
167 .avid_start_stop_x = 0x03530083,
168 .avid_start_stop_y = 0x026C002E,
169 .fid_int_start_x__fid_int_start_y = 0x0001008A,
170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
173 .tvdetgp_int_start_stop_x = 0x00140001,
174 .tvdetgp_int_start_stop_y = 0x00010001,
175 .gen_ctrl = 0x00FF0000,
179 static const struct venc_config venc_config_ntsc_trm = {
186 .cc_carr_wss_carr = 0x043F2631,
195 .bstamp_wss_data = 0x38,
196 .s_carr = 0x21F07C1F,
198 .ln_sel = 0x01310011,
199 .l21__wc_ctl = 0x0000F003,
200 .htrigger_vtrigger = 0,
202 .savid__eavid = 0x069300F4,
203 .flen__fal = 0x0016020C,
204 .lal__phase_reset = 0x00060107,
205 .hs_int_start_stop_x = 0x008E0350,
206 .hs_ext_start_stop_x = 0x000F0359,
207 .vs_int_start_x = 0x01A00000,
208 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
211 .vs_ext_stop_y = 0x00000006,
212 .avid_start_stop_x = 0x03480078,
213 .avid_start_stop_y = 0x02060024,
214 .fid_int_start_x__fid_int_start_y = 0x0001008A,
215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
218 .tvdetgp_int_start_stop_x = 0x00140001,
219 .tvdetgp_int_start_stop_y = 0x00010001,
220 .gen_ctrl = 0x00F90000,
223 static const struct venc_config venc_config_pal_bdghi = {
231 .htrigger_vtrigger = 0,
232 .tvdetgp_int_start_stop_x = 0x00140001,
233 .tvdetgp_int_start_stop_y = 0x00010001,
234 .gen_ctrl = 0x00FB0000,
238 .cc_carr_wss_carr = 0x2F7625ED,
245 .m_control = 0<<2 | 1<<1,
246 .bstamp_wss_data = 0x42,
247 .s_carr = 0x2a098acb,
248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
249 .savid__eavid = 0x06A70108,
250 .flen__fal = 23<<16 | 624<<0,
251 .lal__phase_reset = 2<<17 | 310<<0,
252 .hs_int_start_stop_x = 0x00920358,
253 .hs_ext_start_stop_x = 0x000F035F,
254 .vs_int_start_x = 0x1a7<<16,
255 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
258 .vs_ext_stop_y = 0x05,
259 .avid_start_stop_x = 0x03530082,
260 .avid_start_stop_y = 0x0270002E,
261 .fid_int_start_x__fid_int_start_y = 0x0005008A,
262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
266 enum venc_videomode {
272 static const struct videomode omap_dss_pal_vm = {
275 .pixelclock = 13500000,
283 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
284 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
285 DISPLAY_FLAGS_PIXDATA_POSEDGE |
286 DISPLAY_FLAGS_SYNC_NEGEDGE,
289 static const struct videomode omap_dss_ntsc_vm = {
292 .pixelclock = 13500000,
300 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
301 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
302 DISPLAY_FLAGS_PIXDATA_POSEDGE |
303 DISPLAY_FLAGS_SYNC_NEGEDGE,
306 static enum venc_videomode venc_get_videomode(const struct videomode *vm)
308 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED))
309 return VENC_MODE_UNKNOWN;
311 if (vm->pixelclock == omap_dss_pal_vm.pixelclock &&
312 vm->hactive == omap_dss_pal_vm.hactive &&
313 vm->vactive == omap_dss_pal_vm.vactive)
314 return VENC_MODE_PAL;
316 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock &&
317 vm->hactive == omap_dss_ntsc_vm.hactive &&
318 vm->vactive == omap_dss_ntsc_vm.vactive)
319 return VENC_MODE_NTSC;
321 return VENC_MODE_UNKNOWN;
325 struct platform_device *pdev;
327 struct mutex venc_lock;
329 struct regulator *vdda_dac_reg;
331 struct clk *tv_dac_clk;
334 enum omap_dss_venc_type type;
335 bool invert_polarity;
336 bool requires_tv_dac_clk;
338 struct omap_dss_device output;
341 static inline void venc_write_reg(int idx, u32 val)
343 __raw_writel(val, venc.base + idx);
346 static inline u32 venc_read_reg(int idx)
348 u32 l = __raw_readl(venc.base + idx);
352 static void venc_write_config(const struct venc_config *config)
354 DSSDBG("write venc conf\n");
356 venc_write_reg(VENC_LLEN, config->llen);
357 venc_write_reg(VENC_FLENS, config->flens);
358 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
359 venc_write_reg(VENC_C_PHASE, config->c_phase);
360 venc_write_reg(VENC_GAIN_U, config->gain_u);
361 venc_write_reg(VENC_GAIN_V, config->gain_v);
362 venc_write_reg(VENC_GAIN_Y, config->gain_y);
363 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
364 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
365 venc_write_reg(VENC_M_CONTROL, config->m_control);
366 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
368 venc_write_reg(VENC_S_CARR, config->s_carr);
369 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
370 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
371 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
372 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
373 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
374 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
375 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
376 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
377 config->vs_int_stop_x__vs_int_start_y);
378 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
379 config->vs_int_stop_y__vs_ext_start_x);
380 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
381 config->vs_ext_stop_x__vs_ext_start_y);
382 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
383 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
384 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
385 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
386 config->fid_int_start_x__fid_int_start_y);
387 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
388 config->fid_int_offset_y__fid_ext_start_x);
389 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
390 config->fid_ext_start_y__fid_ext_offset_y);
392 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
393 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
394 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
395 venc_write_reg(VENC_X_COLOR, config->x_color);
396 venc_write_reg(VENC_LINE21, config->line21);
397 venc_write_reg(VENC_LN_SEL, config->ln_sel);
398 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
399 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
400 config->tvdetgp_int_start_stop_x);
401 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
402 config->tvdetgp_int_start_stop_y);
403 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
404 venc_write_reg(VENC_F_CONTROL, config->f_control);
405 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
408 static void venc_reset(void)
412 venc_write_reg(VENC_F_CONTROL, 1<<8);
413 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
415 DSSERR("Failed to reset venc\n");
420 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
421 /* the magical sleep that makes things work */
422 /* XXX more info? What bug this circumvents? */
427 static int venc_runtime_get(void)
431 DSSDBG("venc_runtime_get\n");
433 r = pm_runtime_get_sync(&venc.pdev->dev);
435 return r < 0 ? r : 0;
438 static void venc_runtime_put(void)
442 DSSDBG("venc_runtime_put\n");
444 r = pm_runtime_put_sync(&venc.pdev->dev);
445 WARN_ON(r < 0 && r != -ENOSYS);
448 static const struct venc_config *venc_timings_to_config(struct videomode *vm)
450 switch (venc_get_videomode(vm)) {
454 return &venc_config_pal_trm;
456 return &venc_config_ntsc_trm;
460 static int venc_power_on(struct omap_dss_device *dssdev)
462 enum omap_channel channel = dssdev->dispc_channel;
466 r = venc_runtime_get();
471 venc_write_config(venc_timings_to_config(&venc.vm));
473 dss_set_venc_output(venc.type);
474 dss_set_dac_pwrdn_bgz(1);
478 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
481 l |= (1 << 0) | (1 << 2);
483 if (venc.invert_polarity == false)
486 venc_write_reg(VENC_OUTPUT_CONTROL, l);
488 dss_mgr_set_timings(channel, &venc.vm);
490 r = regulator_enable(venc.vdda_dac_reg);
494 r = dss_mgr_enable(channel);
501 regulator_disable(venc.vdda_dac_reg);
503 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
504 dss_set_dac_pwrdn_bgz(0);
511 static void venc_power_off(struct omap_dss_device *dssdev)
513 enum omap_channel channel = dssdev->dispc_channel;
515 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
516 dss_set_dac_pwrdn_bgz(0);
518 dss_mgr_disable(channel);
520 regulator_disable(venc.vdda_dac_reg);
525 static int venc_display_enable(struct omap_dss_device *dssdev)
527 struct omap_dss_device *out = &venc.output;
530 DSSDBG("venc_display_enable\n");
532 mutex_lock(&venc.venc_lock);
534 if (!out->dispc_channel_connected) {
535 DSSERR("Failed to enable display: no output/manager\n");
540 r = venc_power_on(dssdev);
546 mutex_unlock(&venc.venc_lock);
550 mutex_unlock(&venc.venc_lock);
554 static void venc_display_disable(struct omap_dss_device *dssdev)
556 DSSDBG("venc_display_disable\n");
558 mutex_lock(&venc.venc_lock);
560 venc_power_off(dssdev);
562 mutex_unlock(&venc.venc_lock);
565 static void venc_set_timings(struct omap_dss_device *dssdev,
566 struct videomode *vm)
568 struct videomode actual_vm;
570 DSSDBG("venc_set_timings\n");
572 mutex_lock(&venc.venc_lock);
574 switch (venc_get_videomode(vm)) {
578 actual_vm = omap_dss_pal_vm;
581 actual_vm = omap_dss_ntsc_vm;
585 /* Reset WSS data when the TV standard changes. */
586 if (memcmp(&venc.vm, &actual_vm, sizeof(actual_vm)))
591 dispc_set_tv_pclk(13500000);
593 mutex_unlock(&venc.venc_lock);
596 static int venc_check_timings(struct omap_dss_device *dssdev,
597 struct videomode *vm)
599 DSSDBG("venc_check_timings\n");
601 switch (venc_get_videomode(vm)) {
610 static void venc_get_timings(struct omap_dss_device *dssdev,
611 struct videomode *vm)
613 mutex_lock(&venc.venc_lock);
617 mutex_unlock(&venc.venc_lock);
620 static u32 venc_get_wss(struct omap_dss_device *dssdev)
622 /* Invert due to VENC_L21_WC_CTL:INV=1 */
623 return (venc.wss_data >> 8) ^ 0xfffff;
626 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
628 const struct venc_config *config;
631 DSSDBG("venc_set_wss\n");
633 mutex_lock(&venc.venc_lock);
635 config = venc_timings_to_config(&venc.vm);
637 /* Invert due to VENC_L21_WC_CTL:INV=1 */
638 venc.wss_data = (wss ^ 0xfffff) << 8;
640 r = venc_runtime_get();
644 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
650 mutex_unlock(&venc.venc_lock);
655 static int venc_init_regulator(void)
657 struct regulator *vdda_dac;
659 if (venc.vdda_dac_reg != NULL)
662 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
663 if (IS_ERR(vdda_dac)) {
664 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
665 DSSERR("can't get VDDA_DAC regulator\n");
666 return PTR_ERR(vdda_dac);
669 venc.vdda_dac_reg = vdda_dac;
674 static void venc_dump_regs(struct seq_file *s)
676 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
678 if (venc_runtime_get())
681 DUMPREG(VENC_F_CONTROL);
682 DUMPREG(VENC_VIDOUT_CTRL);
683 DUMPREG(VENC_SYNC_CTRL);
686 DUMPREG(VENC_HFLTR_CTRL);
687 DUMPREG(VENC_CC_CARR_WSS_CARR);
688 DUMPREG(VENC_C_PHASE);
689 DUMPREG(VENC_GAIN_U);
690 DUMPREG(VENC_GAIN_V);
691 DUMPREG(VENC_GAIN_Y);
692 DUMPREG(VENC_BLACK_LEVEL);
693 DUMPREG(VENC_BLANK_LEVEL);
694 DUMPREG(VENC_X_COLOR);
695 DUMPREG(VENC_M_CONTROL);
696 DUMPREG(VENC_BSTAMP_WSS_DATA);
697 DUMPREG(VENC_S_CARR);
698 DUMPREG(VENC_LINE21);
699 DUMPREG(VENC_LN_SEL);
700 DUMPREG(VENC_L21__WC_CTL);
701 DUMPREG(VENC_HTRIGGER_VTRIGGER);
702 DUMPREG(VENC_SAVID__EAVID);
703 DUMPREG(VENC_FLEN__FAL);
704 DUMPREG(VENC_LAL__PHASE_RESET);
705 DUMPREG(VENC_HS_INT_START_STOP_X);
706 DUMPREG(VENC_HS_EXT_START_STOP_X);
707 DUMPREG(VENC_VS_INT_START_X);
708 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
709 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
710 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
711 DUMPREG(VENC_VS_EXT_STOP_Y);
712 DUMPREG(VENC_AVID_START_STOP_X);
713 DUMPREG(VENC_AVID_START_STOP_Y);
714 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
715 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
716 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
717 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
718 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
719 DUMPREG(VENC_GEN_CTRL);
720 DUMPREG(VENC_OUTPUT_CONTROL);
721 DUMPREG(VENC_OUTPUT_TEST);
728 static int venc_get_clocks(struct platform_device *pdev)
732 if (venc.requires_tv_dac_clk) {
733 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
735 DSSERR("can't get tv_dac_clk\n");
742 venc.tv_dac_clk = clk;
747 static int venc_connect(struct omap_dss_device *dssdev,
748 struct omap_dss_device *dst)
750 enum omap_channel channel = dssdev->dispc_channel;
753 r = venc_init_regulator();
757 r = dss_mgr_connect(channel, dssdev);
761 r = omapdss_output_set_device(dssdev, dst);
763 DSSERR("failed to connect output to new device: %s\n",
765 dss_mgr_disconnect(channel, dssdev);
772 static void venc_disconnect(struct omap_dss_device *dssdev,
773 struct omap_dss_device *dst)
775 enum omap_channel channel = dssdev->dispc_channel;
777 WARN_ON(dst != dssdev->dst);
779 if (dst != dssdev->dst)
782 omapdss_output_unset_device(dssdev);
784 dss_mgr_disconnect(channel, dssdev);
787 static const struct omapdss_atv_ops venc_ops = {
788 .connect = venc_connect,
789 .disconnect = venc_disconnect,
791 .enable = venc_display_enable,
792 .disable = venc_display_disable,
794 .check_timings = venc_check_timings,
795 .set_timings = venc_set_timings,
796 .get_timings = venc_get_timings,
798 .set_wss = venc_set_wss,
799 .get_wss = venc_get_wss,
802 static void venc_init_output(struct platform_device *pdev)
804 struct omap_dss_device *out = &venc.output;
806 out->dev = &pdev->dev;
807 out->id = OMAP_DSS_OUTPUT_VENC;
808 out->output_type = OMAP_DISPLAY_TYPE_VENC;
809 out->name = "venc.0";
810 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
811 out->ops.atv = &venc_ops;
812 out->owner = THIS_MODULE;
814 omapdss_register_output(out);
817 static void venc_uninit_output(struct platform_device *pdev)
819 struct omap_dss_device *out = &venc.output;
821 omapdss_unregister_output(out);
824 static int venc_probe_of(struct platform_device *pdev)
826 struct device_node *node = pdev->dev.of_node;
827 struct device_node *ep;
831 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
835 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
837 r = of_property_read_u32(ep, "ti,channels", &channels);
840 "failed to read property 'ti,channels': %d\n", r);
846 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
849 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
852 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
866 /* VENC HW IP initialisation */
867 static const struct soc_device_attribute venc_soc_devices[] = {
868 { .machine = "OMAP3[45]*" },
869 { .machine = "AM35*" },
873 static int venc_bind(struct device *dev, struct device *master, void *data)
875 struct platform_device *pdev = to_platform_device(dev);
877 struct resource *venc_mem;
882 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
883 if (soc_device_match(venc_soc_devices))
884 venc.requires_tv_dac_clk = true;
886 mutex_init(&venc.venc_lock);
890 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
891 venc.base = devm_ioremap_resource(&pdev->dev, venc_mem);
892 if (IS_ERR(venc.base))
893 return PTR_ERR(venc.base);
895 r = venc_get_clocks(pdev);
899 pm_runtime_enable(&pdev->dev);
901 r = venc_runtime_get();
903 goto err_runtime_get;
905 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
906 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
910 r = venc_probe_of(pdev);
912 DSSERR("Invalid DT data\n");
916 dss_debugfs_create_file("venc", venc_dump_regs);
918 venc_init_output(pdev);
924 pm_runtime_disable(&pdev->dev);
928 static void venc_unbind(struct device *dev, struct device *master, void *data)
930 struct platform_device *pdev = to_platform_device(dev);
932 venc_uninit_output(pdev);
934 pm_runtime_disable(&pdev->dev);
937 static const struct component_ops venc_component_ops = {
939 .unbind = venc_unbind,
942 static int venc_probe(struct platform_device *pdev)
944 return component_add(&pdev->dev, &venc_component_ops);
947 static int venc_remove(struct platform_device *pdev)
949 component_del(&pdev->dev, &venc_component_ops);
953 static int venc_runtime_suspend(struct device *dev)
956 clk_disable_unprepare(venc.tv_dac_clk);
963 static int venc_runtime_resume(struct device *dev)
967 r = dispc_runtime_get();
972 clk_prepare_enable(venc.tv_dac_clk);
977 static const struct dev_pm_ops venc_pm_ops = {
978 .runtime_suspend = venc_runtime_suspend,
979 .runtime_resume = venc_runtime_resume,
982 static const struct of_device_id venc_of_match[] = {
983 { .compatible = "ti,omap2-venc", },
984 { .compatible = "ti,omap3-venc", },
985 { .compatible = "ti,omap4-venc", },
989 static struct platform_driver omap_venchw_driver = {
991 .remove = venc_remove,
993 .name = "omapdss_venc",
995 .of_match_table = venc_of_match,
996 .suppress_bind_attrs = true,
1000 int __init venc_init_platform_driver(void)
1002 return platform_driver_register(&omap_venchw_driver);
1005 void venc_uninit_platform_driver(void)
1007 platform_driver_unregister(&omap_venchw_driver);