2 * linux/drivers/video/omap2/dss/sdi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "SDI"
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/export.h>
27 #include <linux/platform_device.h>
28 #include <linux/string.h>
35 struct platform_device *pdev;
38 struct regulator *vdds_sdi_reg;
40 struct dss_lcd_mgr_config mgr_config;
44 struct omap_dss_device output;
46 bool port_initialized;
49 struct sdi_clk_calc_ctx {
50 unsigned long pck_min, pck_max;
53 struct dispc_clock_info dispc_cinfo;
56 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
57 unsigned long pck, void *data)
59 struct sdi_clk_calc_ctx *ctx = data;
61 ctx->dispc_cinfo.lck_div = lckd;
62 ctx->dispc_cinfo.pck_div = pckd;
63 ctx->dispc_cinfo.lck = lck;
64 ctx->dispc_cinfo.pck = pck;
69 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
71 struct sdi_clk_calc_ctx *ctx = data;
75 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
76 dpi_calc_dispc_cb, ctx);
79 static int sdi_calc_clock_div(unsigned long pclk,
81 struct dispc_clock_info *dispc_cinfo)
84 struct sdi_clk_calc_ctx ctx;
87 * DSS fclk gives us very few possibilities, so finding a good pixel
88 * clock may not be possible. We try multiple times to find the clock,
89 * each time widening the pixel clock range we look for, up to
93 for (i = 0; i < 10; ++i) {
96 memset(&ctx, 0, sizeof(ctx));
97 if (pclk > 1000 * i * i * i)
98 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
101 ctx.pck_max = pclk + 1000 * i * i * i;
103 ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
106 *dispc_cinfo = ctx.dispc_cinfo;
114 static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
116 enum omap_channel channel = dssdev->dispc_channel;
118 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
120 sdi.mgr_config.stallmode = false;
121 sdi.mgr_config.fifohandcheck = false;
123 sdi.mgr_config.video_port_width = 24;
124 sdi.mgr_config.lcden_sig_polarity = 1;
126 dss_mgr_set_lcd_config(channel, &sdi.mgr_config);
129 static int sdi_display_enable(struct omap_dss_device *dssdev)
131 struct omap_dss_device *out = &sdi.output;
132 enum omap_channel channel = dssdev->dispc_channel;
133 struct videomode *vm = &sdi.vm;
135 struct dispc_clock_info dispc_cinfo;
139 if (!out->dispc_channel_connected) {
140 DSSERR("failed to enable display: no output/manager\n");
144 r = regulator_enable(sdi.vdds_sdi_reg);
148 r = dispc_runtime_get();
153 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
155 r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo);
157 goto err_calc_clock_div;
159 sdi.mgr_config.clock_info = dispc_cinfo;
161 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
163 if (pck != vm->pixelclock) {
164 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
165 vm->pixelclock, pck);
167 vm->pixelclock = pck;
171 dss_mgr_set_timings(channel, vm);
173 r = dss_set_fck_rate(fck);
175 goto err_set_dss_clock_div;
177 sdi_config_lcd_manager(dssdev);
180 * LCLK and PCLK divisors are located in shadow registers, and we
181 * normally write them to DISPC registers when enabling the output.
182 * However, SDI uses pck-free as source clock for its PLL, and pck-free
183 * is affected by the divisors. And as we need the PLL before enabling
184 * the output, we need to write the divisors early.
186 * It seems just writing to the DISPC register is enough, and we don't
187 * need to care about the shadow register mechanism for pck-free. The
188 * exact reason for this is unknown.
190 dispc_mgr_set_clock_div(channel, &sdi.mgr_config.clock_info);
192 dss_sdi_init(sdi.datapairs);
193 r = dss_sdi_enable();
198 r = dss_mgr_enable(channel);
207 err_set_dss_clock_div:
211 regulator_disable(sdi.vdds_sdi_reg);
216 static void sdi_display_disable(struct omap_dss_device *dssdev)
218 enum omap_channel channel = dssdev->dispc_channel;
220 dss_mgr_disable(channel);
226 regulator_disable(sdi.vdds_sdi_reg);
229 static void sdi_set_timings(struct omap_dss_device *dssdev,
230 struct videomode *vm)
235 static void sdi_get_timings(struct omap_dss_device *dssdev,
236 struct videomode *vm)
241 static int sdi_check_timings(struct omap_dss_device *dssdev,
242 struct videomode *vm)
244 enum omap_channel channel = dssdev->dispc_channel;
246 if (!dispc_mgr_timings_ok(channel, vm))
249 if (vm->pixelclock == 0)
255 static int sdi_init_regulator(void)
257 struct regulator *vdds_sdi;
259 if (sdi.vdds_sdi_reg)
262 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
263 if (IS_ERR(vdds_sdi)) {
264 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
265 DSSERR("can't get VDDS_SDI regulator\n");
266 return PTR_ERR(vdds_sdi);
269 sdi.vdds_sdi_reg = vdds_sdi;
274 static int sdi_connect(struct omap_dss_device *dssdev,
275 struct omap_dss_device *dst)
277 enum omap_channel channel = dssdev->dispc_channel;
280 r = sdi_init_regulator();
284 r = dss_mgr_connect(channel, dssdev);
288 r = omapdss_output_set_device(dssdev, dst);
290 DSSERR("failed to connect output to new device: %s\n",
292 dss_mgr_disconnect(channel, dssdev);
299 static void sdi_disconnect(struct omap_dss_device *dssdev,
300 struct omap_dss_device *dst)
302 enum omap_channel channel = dssdev->dispc_channel;
304 WARN_ON(dst != dssdev->dst);
306 if (dst != dssdev->dst)
309 omapdss_output_unset_device(dssdev);
311 dss_mgr_disconnect(channel, dssdev);
314 static const struct omapdss_sdi_ops sdi_ops = {
315 .connect = sdi_connect,
316 .disconnect = sdi_disconnect,
318 .enable = sdi_display_enable,
319 .disable = sdi_display_disable,
321 .check_timings = sdi_check_timings,
322 .set_timings = sdi_set_timings,
323 .get_timings = sdi_get_timings,
326 static void sdi_init_output(struct platform_device *pdev)
328 struct omap_dss_device *out = &sdi.output;
330 out->dev = &pdev->dev;
331 out->id = OMAP_DSS_OUTPUT_SDI;
332 out->output_type = OMAP_DISPLAY_TYPE_SDI;
334 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
335 /* We have SDI only on OMAP3, where it's on port 1 */
337 out->ops.sdi = &sdi_ops;
338 out->owner = THIS_MODULE;
340 omapdss_register_output(out);
343 static void sdi_uninit_output(struct platform_device *pdev)
345 struct omap_dss_device *out = &sdi.output;
347 omapdss_unregister_output(out);
350 int sdi_init_port(struct platform_device *pdev, struct device_node *port)
352 struct device_node *ep;
356 ep = of_get_next_child(port, NULL);
360 r = of_property_read_u32(ep, "datapairs", &datapairs);
362 DSSERR("failed to parse datapairs\n");
366 sdi.datapairs = datapairs;
372 sdi_init_output(pdev);
374 sdi.port_initialized = true;
384 void sdi_uninit_port(struct device_node *port)
386 if (!sdi.port_initialized)
389 sdi_uninit_output(sdi.pdev);