2 * Copyright (C) 2014 Texas Instruments Incorporated
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #define DSS_SUBSYS_NAME "PLL"
19 #include <linux/clk.h>
21 #include <linux/kernel.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sched.h>
28 #define PLL_CONTROL 0x0000
29 #define PLL_STATUS 0x0004
31 #define PLL_CONFIGURATION1 0x000C
32 #define PLL_CONFIGURATION2 0x0010
33 #define PLL_CONFIGURATION3 0x0014
34 #define PLL_SSC_CONFIGURATION1 0x0018
35 #define PLL_SSC_CONFIGURATION2 0x001C
36 #define PLL_CONFIGURATION4 0x0020
38 static struct dss_pll *dss_plls[4];
40 int dss_pll_register(struct dss_pll *pll)
44 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
54 void dss_pll_unregister(struct dss_pll *pll)
58 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
59 if (dss_plls[i] == pll) {
66 struct dss_pll *dss_pll_find(const char *name)
70 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
71 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0)
78 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src)
87 case DSS_CLK_SRC_HDMI_PLL:
88 return dss_pll_find("hdmi");
90 case DSS_CLK_SRC_PLL1_1:
91 case DSS_CLK_SRC_PLL1_2:
92 case DSS_CLK_SRC_PLL1_3:
93 pll = dss_pll_find("dsi0");
95 pll = dss_pll_find("video0");
98 case DSS_CLK_SRC_PLL2_1:
99 case DSS_CLK_SRC_PLL2_2:
100 case DSS_CLK_SRC_PLL2_3:
101 pll = dss_pll_find("dsi1");
103 pll = dss_pll_find("video1");
108 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src)
111 case DSS_CLK_SRC_HDMI_PLL:
114 case DSS_CLK_SRC_PLL1_1:
115 case DSS_CLK_SRC_PLL2_1:
118 case DSS_CLK_SRC_PLL1_2:
119 case DSS_CLK_SRC_PLL2_2:
122 case DSS_CLK_SRC_PLL1_3:
123 case DSS_CLK_SRC_PLL2_3:
131 int dss_pll_enable(struct dss_pll *pll)
135 r = clk_prepare_enable(pll->clkin);
139 if (pll->regulator) {
140 r = regulator_enable(pll->regulator);
145 r = pll->ops->enable(pll);
153 regulator_disable(pll->regulator);
155 clk_disable_unprepare(pll->clkin);
159 void dss_pll_disable(struct dss_pll *pll)
161 pll->ops->disable(pll);
164 regulator_disable(pll->regulator);
166 clk_disable_unprepare(pll->clkin);
168 memset(&pll->cinfo, 0, sizeof(pll->cinfo));
171 int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
175 r = pll->ops->set_config(pll, cinfo);
184 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
185 unsigned long out_min, unsigned long out_max,
186 dss_hsdiv_calc_func func, void *data)
188 const struct dss_pll_hw *hw = pll->hw;
189 int m, m_start, m_stop;
192 out_min = out_min ? out_min : 1;
193 out_max = out_max ? out_max : ULONG_MAX;
195 m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);
197 m_stop = min((unsigned)(clkdco / out_min), hw->mX_max);
199 for (m = m_start; m <= m_stop; ++m) {
202 if (func(m, out, data))
210 * clkdco = clkin / n * m * 2
211 * clkoutX = clkdco / mX
213 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
214 unsigned long pll_min, unsigned long pll_max,
215 dss_pll_calc_func func, void *data)
217 const struct dss_pll_hw *hw = pll->hw;
218 int n, n_start, n_stop, n_inc;
219 int m, m_start, m_stop, m_inc;
220 unsigned long fint, clkdco;
221 unsigned long pll_hw_max;
222 unsigned long fint_hw_min, fint_hw_max;
224 pll_hw_max = hw->clkdco_max;
226 fint_hw_min = hw->fint_min;
227 fint_hw_max = hw->fint_max;
229 n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
230 n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max);
233 if (hw->errata_i886) {
234 swap(n_start, n_stop);
238 pll_max = pll_max ? pll_max : ULONG_MAX;
240 for (n = n_start; n != n_stop; n += n_inc) {
243 m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
245 m_stop = min3((unsigned)(pll_max / fint / 2),
246 (unsigned)(pll_hw_max / fint / 2),
250 if (hw->errata_i886) {
251 swap(m_start, m_stop);
255 for (m = m_start; m != m_stop; m += m_inc) {
256 clkdco = 2 * m * fint;
258 if (func(n, m, fint, clkdco, data))
267 * This calculates a PLL config that will provide the target_clkout rate
268 * for clkout. Additionally clkdco rate will be the same as clkout rate
269 * when clkout rate is >= min_clkdco.
271 * clkdco = clkin / n * m + clkin / n * mf / 262144
272 * clkout = clkdco / m2
274 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
275 unsigned long target_clkout, struct dss_pll_clock_info *cinfo)
277 unsigned long fint, clkdco, clkout;
278 unsigned long target_clkdco;
279 unsigned long min_dco;
280 unsigned n, m, mf, m2, sd;
281 const struct dss_pll_hw *hw = pll->hw;
283 DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);
286 n = DIV_ROUND_UP(clkin, hw->fint_max);
289 /* adjust m2 so that the clkdco will be high enough */
290 min_dco = roundup(hw->clkdco_min, fint);
291 m2 = DIV_ROUND_UP(min_dco, target_clkout);
295 target_clkdco = target_clkout * m2;
296 m = target_clkdco / fint;
300 /* adjust clkdco with fractional mf */
301 if (WARN_ON(target_clkdco - clkdco > fint))
304 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
307 clkdco += (u32)div_u64((u64)mf * fint, 262144);
309 clkout = clkdco / m2;
312 sd = DIV_ROUND_UP(fint * m, 250000000);
314 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
316 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
325 cinfo->clkdco = clkdco;
326 cinfo->clkout[0] = clkout;
331 static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
333 unsigned long timeout;
337 /* first busyloop to see if the bit changes right away */
340 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
344 /* then loop for 500ms, sleeping for 1ms in between */
345 timeout = jiffies + msecs_to_jiffies(500);
346 while (time_before(jiffies, timeout)) {
347 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
350 wait = ns_to_ktime(1000 * 1000);
351 set_current_state(TASK_UNINTERRUPTIBLE);
352 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
358 int dss_pll_wait_reset_done(struct dss_pll *pll)
360 void __iomem *base = pll->base;
362 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
368 static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
373 u32 v = readl_relaxed(pll->base + PLL_STATUS);
375 if (v == hsdiv_ack_mask)
382 int dss_pll_write_config_type_a(struct dss_pll *pll,
383 const struct dss_pll_clock_info *cinfo)
385 const struct dss_pll_hw *hw = pll->hw;
386 void __iomem *base = pll->base;
391 if (hw->has_stopmode)
392 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */
393 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */
394 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */
396 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,
397 hw->mX_msb[0], hw->mX_lsb[0]);
399 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,
400 hw->mX_msb[1], hw->mX_lsb[1]);
401 writel_relaxed(l, base + PLL_CONFIGURATION1);
405 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,
406 hw->mX_msb[2], hw->mX_lsb[2]);
408 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,
409 hw->mX_msb[3], hw->mX_lsb[3]);
410 writel_relaxed(l, base + PLL_CONFIGURATION3);
412 l = readl_relaxed(base + PLL_CONFIGURATION2);
413 if (hw->has_freqsel) {
414 u32 f = cinfo->fint < 1000000 ? 0x3 :
415 cinfo->fint < 1250000 ? 0x4 :
416 cinfo->fint < 1500000 ? 0x5 :
417 cinfo->fint < 1750000 ? 0x6 :
420 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */
421 } else if (hw->has_selfreqdco) {
422 u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;
424 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
426 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
427 l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */
428 l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */
429 l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */
430 l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
432 l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */
433 l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */
434 l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */
435 writel_relaxed(l, base + PLL_CONFIGURATION2);
437 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
439 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
440 DSSERR("DSS DPLL GO bit not going down.\n");
445 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
446 DSSERR("cannot lock DSS DPLL\n");
451 l = readl_relaxed(base + PLL_CONFIGURATION2);
452 l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
453 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */
454 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */
455 l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
456 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */
457 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */
458 writel_relaxed(l, base + PLL_CONFIGURATION2);
460 r = dss_wait_hsdiv_ack(pll,
461 (cinfo->mX[0] ? BIT(7) : 0) |
462 (cinfo->mX[1] ? BIT(8) : 0) |
463 (cinfo->mX[2] ? BIT(10) : 0) |
464 (cinfo->mX[3] ? BIT(11) : 0));
466 DSSERR("failed to enable HSDIV clocks\n");
474 int dss_pll_write_config_type_b(struct dss_pll *pll,
475 const struct dss_pll_clock_info *cinfo)
477 const struct dss_pll_hw *hw = pll->hw;
478 void __iomem *base = pll->base;
482 l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */
483 l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */
484 writel_relaxed(l, base + PLL_CONFIGURATION1);
486 l = readl_relaxed(base + PLL_CONFIGURATION2);
487 l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
488 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */
489 l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */
491 l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */
494 if (cinfo->clkdco > hw->clkdco_low)
495 l = FLD_MOD(l, 0x4, 3, 1);
497 l = FLD_MOD(l, 0x2, 3, 1);
498 writel_relaxed(l, base + PLL_CONFIGURATION2);
500 l = readl_relaxed(base + PLL_CONFIGURATION3);
501 l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */
502 writel_relaxed(l, base + PLL_CONFIGURATION3);
504 l = readl_relaxed(base + PLL_CONFIGURATION4);
505 l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */
506 l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */
507 writel_relaxed(l, base + PLL_CONFIGURATION4);
509 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
511 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
512 DSSERR("DSS DPLL GO bit not going down.\n");
516 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
517 DSSERR("cannot lock DSS DPLL\n");