2 * Copyright (C) 2014 Texas Instruments Incorporated
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #define DSS_SUBSYS_NAME "PLL"
19 #include <linux/clk.h>
21 #include <linux/kernel.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sched.h>
28 #define PLL_CONTROL 0x0000
29 #define PLL_STATUS 0x0004
31 #define PLL_CONFIGURATION1 0x000C
32 #define PLL_CONFIGURATION2 0x0010
33 #define PLL_CONFIGURATION3 0x0014
34 #define PLL_SSC_CONFIGURATION1 0x0018
35 #define PLL_SSC_CONFIGURATION2 0x001C
36 #define PLL_CONFIGURATION4 0x0020
38 static struct dss_pll *dss_plls[4];
40 int dss_pll_register(struct dss_pll *pll)
44 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
54 void dss_pll_unregister(struct dss_pll *pll)
58 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
59 if (dss_plls[i] == pll) {
66 struct dss_pll *dss_pll_find(const char *name)
70 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
71 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0)
78 struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src)
87 case DSS_CLK_SRC_HDMI_PLL:
88 return dss_pll_find("hdmi");
90 case DSS_CLK_SRC_PLL1_1:
91 case DSS_CLK_SRC_PLL1_2:
92 case DSS_CLK_SRC_PLL1_3:
93 pll = dss_pll_find("dsi0");
95 pll = dss_pll_find("video0");
98 case DSS_CLK_SRC_PLL2_1:
99 case DSS_CLK_SRC_PLL2_2:
100 case DSS_CLK_SRC_PLL2_3:
101 pll = dss_pll_find("dsi1");
103 pll = dss_pll_find("video1");
108 unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src)
111 case DSS_CLK_SRC_HDMI_PLL:
114 case DSS_CLK_SRC_PLL1_1:
115 case DSS_CLK_SRC_PLL2_1:
118 case DSS_CLK_SRC_PLL1_2:
119 case DSS_CLK_SRC_PLL2_2:
122 case DSS_CLK_SRC_PLL1_3:
123 case DSS_CLK_SRC_PLL2_3:
131 int dss_pll_enable(struct dss_pll *pll)
135 r = clk_prepare_enable(pll->clkin);
139 if (pll->regulator) {
140 r = regulator_enable(pll->regulator);
145 r = pll->ops->enable(pll);
153 regulator_disable(pll->regulator);
155 clk_disable_unprepare(pll->clkin);
159 void dss_pll_disable(struct dss_pll *pll)
161 pll->ops->disable(pll);
164 regulator_disable(pll->regulator);
166 clk_disable_unprepare(pll->clkin);
168 memset(&pll->cinfo, 0, sizeof(pll->cinfo));
171 int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
175 r = pll->ops->set_config(pll, cinfo);
184 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
185 unsigned long out_min, unsigned long out_max,
186 dss_hsdiv_calc_func func, void *data)
188 const struct dss_pll_hw *hw = pll->hw;
189 int m, m_start, m_stop;
192 out_min = out_min ? out_min : 1;
193 out_max = out_max ? out_max : ULONG_MAX;
195 m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);
197 m_stop = min((unsigned)(clkdco / out_min), hw->mX_max);
199 for (m = m_start; m <= m_stop; ++m) {
202 if (func(m, out, data))
210 * clkdco = clkin / n * m * 2
211 * clkoutX = clkdco / mX
213 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
214 unsigned long pll_min, unsigned long pll_max,
215 dss_pll_calc_func func, void *data)
217 const struct dss_pll_hw *hw = pll->hw;
218 int n, n_start, n_stop;
219 int m, m_start, m_stop;
220 unsigned long fint, clkdco;
221 unsigned long pll_hw_max;
222 unsigned long fint_hw_min, fint_hw_max;
224 pll_hw_max = hw->clkdco_max;
226 fint_hw_min = hw->fint_min;
227 fint_hw_max = hw->fint_max;
229 n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
230 n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max);
232 pll_max = pll_max ? pll_max : ULONG_MAX;
234 for (n = n_start; n <= n_stop; ++n) {
237 m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
239 m_stop = min3((unsigned)(pll_max / fint / 2),
240 (unsigned)(pll_hw_max / fint / 2),
243 for (m = m_start; m <= m_stop; ++m) {
244 clkdco = 2 * m * fint;
246 if (func(n, m, fint, clkdco, data))
255 * This calculates a PLL config that will provide the target_clkout rate
256 * for clkout. Additionally clkdco rate will be the same as clkout rate
257 * when clkout rate is >= min_clkdco.
259 * clkdco = clkin / n * m + clkin / n * mf / 262144
260 * clkout = clkdco / m2
262 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
263 unsigned long target_clkout, struct dss_pll_clock_info *cinfo)
265 unsigned long fint, clkdco, clkout;
266 unsigned long target_clkdco;
267 unsigned long min_dco;
268 unsigned n, m, mf, m2, sd;
269 const struct dss_pll_hw *hw = pll->hw;
271 DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);
274 n = DIV_ROUND_UP(clkin, hw->fint_max);
277 /* adjust m2 so that the clkdco will be high enough */
278 min_dco = roundup(hw->clkdco_min, fint);
279 m2 = DIV_ROUND_UP(min_dco, target_clkout);
283 target_clkdco = target_clkout * m2;
284 m = target_clkdco / fint;
288 /* adjust clkdco with fractional mf */
289 if (WARN_ON(target_clkdco - clkdco > fint))
292 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
295 clkdco += (u32)div_u64((u64)mf * fint, 262144);
297 clkout = clkdco / m2;
300 sd = DIV_ROUND_UP(fint * m, 250000000);
302 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
304 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
313 cinfo->clkdco = clkdco;
314 cinfo->clkout[0] = clkout;
319 static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
321 unsigned long timeout;
325 /* first busyloop to see if the bit changes right away */
328 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
332 /* then loop for 500ms, sleeping for 1ms in between */
333 timeout = jiffies + msecs_to_jiffies(500);
334 while (time_before(jiffies, timeout)) {
335 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
338 wait = ns_to_ktime(1000 * 1000);
339 set_current_state(TASK_UNINTERRUPTIBLE);
340 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
346 int dss_pll_wait_reset_done(struct dss_pll *pll)
348 void __iomem *base = pll->base;
350 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
356 static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
361 u32 v = readl_relaxed(pll->base + PLL_STATUS);
363 if (v == hsdiv_ack_mask)
370 int dss_pll_write_config_type_a(struct dss_pll *pll,
371 const struct dss_pll_clock_info *cinfo)
373 const struct dss_pll_hw *hw = pll->hw;
374 void __iomem *base = pll->base;
379 if (hw->has_stopmode)
380 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */
381 l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */
382 l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */
384 l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,
385 hw->mX_msb[0], hw->mX_lsb[0]);
387 l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,
388 hw->mX_msb[1], hw->mX_lsb[1]);
389 writel_relaxed(l, base + PLL_CONFIGURATION1);
393 l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,
394 hw->mX_msb[2], hw->mX_lsb[2]);
396 l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,
397 hw->mX_msb[3], hw->mX_lsb[3]);
398 writel_relaxed(l, base + PLL_CONFIGURATION3);
400 l = readl_relaxed(base + PLL_CONFIGURATION2);
401 if (hw->has_freqsel) {
402 u32 f = cinfo->fint < 1000000 ? 0x3 :
403 cinfo->fint < 1250000 ? 0x4 :
404 cinfo->fint < 1500000 ? 0x5 :
405 cinfo->fint < 1750000 ? 0x6 :
408 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */
409 } else if (hw->has_selfreqdco) {
410 u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;
412 l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
414 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
415 l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */
416 l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */
417 l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */
418 l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
420 l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */
421 l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */
422 l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */
423 writel_relaxed(l, base + PLL_CONFIGURATION2);
425 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
427 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
428 DSSERR("DSS DPLL GO bit not going down.\n");
433 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
434 DSSERR("cannot lock DSS DPLL\n");
439 l = readl_relaxed(base + PLL_CONFIGURATION2);
440 l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
441 l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */
442 l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */
443 l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
444 l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */
445 l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */
446 writel_relaxed(l, base + PLL_CONFIGURATION2);
448 r = dss_wait_hsdiv_ack(pll,
449 (cinfo->mX[0] ? BIT(7) : 0) |
450 (cinfo->mX[1] ? BIT(8) : 0) |
451 (cinfo->mX[2] ? BIT(10) : 0) |
452 (cinfo->mX[3] ? BIT(11) : 0));
454 DSSERR("failed to enable HSDIV clocks\n");
462 int dss_pll_write_config_type_b(struct dss_pll *pll,
463 const struct dss_pll_clock_info *cinfo)
465 const struct dss_pll_hw *hw = pll->hw;
466 void __iomem *base = pll->base;
470 l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */
471 l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */
472 writel_relaxed(l, base + PLL_CONFIGURATION1);
474 l = readl_relaxed(base + PLL_CONFIGURATION2);
475 l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
476 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */
477 l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */
479 l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */
482 if (cinfo->clkdco > hw->clkdco_low)
483 l = FLD_MOD(l, 0x4, 3, 1);
485 l = FLD_MOD(l, 0x2, 3, 1);
486 writel_relaxed(l, base + PLL_CONFIGURATION2);
488 l = readl_relaxed(base + PLL_CONFIGURATION3);
489 l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */
490 writel_relaxed(l, base + PLL_CONFIGURATION3);
492 l = readl_relaxed(base + PLL_CONFIGURATION4);
493 l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */
494 l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */
495 writel_relaxed(l, base + PLL_CONFIGURATION4);
497 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
499 if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
500 DSSERR("DSS DPLL GO bit not going down.\n");
504 if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
505 DSSERR("cannot lock DSS DPLL\n");